xref: /openbmc/linux/drivers/net/ethernet/intel/igb/e1000_phy.h (revision e33bbe69149b802c0c77bfb822685772f85388ca)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Intel(R) Gigabit Ethernet Linux driver
3  * Copyright(c) 2007-2014 Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, see <http://www.gnu.org/licenses/>.
16  *
17  * The full GNU General Public License is included in this distribution in
18  * the file called "COPYING".
19  *
20  * Contact Information:
21  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23  */
24 
25 #ifndef _E1000_PHY_H_
26 #define _E1000_PHY_H_
27 
28 enum e1000_ms_type {
29 	e1000_ms_hw_default = 0,
30 	e1000_ms_force_master,
31 	e1000_ms_force_slave,
32 	e1000_ms_auto
33 };
34 
35 enum e1000_smart_speed {
36 	e1000_smart_speed_default = 0,
37 	e1000_smart_speed_on,
38 	e1000_smart_speed_off
39 };
40 
41 s32  igb_check_downshift(struct e1000_hw *hw);
42 s32  igb_check_reset_block(struct e1000_hw *hw);
43 s32  igb_copper_link_setup_igp(struct e1000_hw *hw);
44 s32  igb_copper_link_setup_m88(struct e1000_hw *hw);
45 s32  igb_copper_link_setup_m88_gen2(struct e1000_hw *hw);
46 s32  igb_phy_force_speed_duplex_igp(struct e1000_hw *hw);
47 s32  igb_phy_force_speed_duplex_m88(struct e1000_hw *hw);
48 s32  igb_get_cable_length_m88(struct e1000_hw *hw);
49 s32  igb_get_cable_length_m88_gen2(struct e1000_hw *hw);
50 s32  igb_get_cable_length_igp_2(struct e1000_hw *hw);
51 s32  igb_get_phy_id(struct e1000_hw *hw);
52 s32  igb_get_phy_info_igp(struct e1000_hw *hw);
53 s32  igb_get_phy_info_m88(struct e1000_hw *hw);
54 s32  igb_phy_sw_reset(struct e1000_hw *hw);
55 s32  igb_phy_hw_reset(struct e1000_hw *hw);
56 s32  igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
57 s32  igb_set_d3_lplu_state(struct e1000_hw *hw, bool active);
58 s32  igb_setup_copper_link(struct e1000_hw *hw);
59 s32  igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
60 s32  igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
61 				u32 usec_interval, bool *success);
62 void igb_power_up_phy_copper(struct e1000_hw *hw);
63 void igb_power_down_phy_copper(struct e1000_hw *hw);
64 s32  igb_phy_init_script_igp3(struct e1000_hw *hw);
65 s32  igb_initialize_M88E1512_phy(struct e1000_hw *hw);
66 s32  igb_initialize_M88E1543_phy(struct e1000_hw *hw);
67 s32  igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
68 s32  igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
69 s32  igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
70 s32  igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
71 s32  igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);
72 s32  igb_copper_link_setup_82580(struct e1000_hw *hw);
73 s32  igb_get_phy_info_82580(struct e1000_hw *hw);
74 s32  igb_phy_force_speed_duplex_82580(struct e1000_hw *hw);
75 s32  igb_get_cable_length_82580(struct e1000_hw *hw);
76 s32  igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data);
77 s32  igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data);
78 s32  igb_check_polarity_m88(struct e1000_hw *hw);
79 
80 /* IGP01E1000 Specific Registers */
81 #define IGP01E1000_PHY_PORT_CONFIG        0x10 /* Port Config */
82 #define IGP01E1000_PHY_PORT_STATUS        0x11 /* Status */
83 #define IGP01E1000_PHY_PORT_CTRL          0x12 /* Control */
84 #define IGP01E1000_PHY_LINK_HEALTH        0x13 /* PHY Link Health */
85 #define IGP02E1000_PHY_POWER_MGMT         0x19 /* Power Management */
86 #define IGP01E1000_PHY_PAGE_SELECT        0x1F /* Page Select */
87 #define IGP01E1000_PHY_PCS_INIT_REG       0x00B4
88 #define IGP01E1000_PHY_POLARITY_MASK      0x0078
89 #define IGP01E1000_PSCR_AUTO_MDIX         0x1000
90 #define IGP01E1000_PSCR_FORCE_MDI_MDIX    0x2000 /* 0=MDI, 1=MDIX */
91 #define IGP01E1000_PSCFR_SMART_SPEED      0x0080
92 
93 #define I82580_ADDR_REG                   16
94 #define I82580_CFG_REG                    22
95 #define I82580_CFG_ASSERT_CRS_ON_TX       BIT(15)
96 #define I82580_CFG_ENABLE_DOWNSHIFT       (3u << 10) /* auto downshift 100/10 */
97 #define I82580_CTRL_REG                   23
98 #define I82580_CTRL_DOWNSHIFT_MASK        (7u << 10)
99 
100 /* 82580 specific PHY registers */
101 #define I82580_PHY_CTRL_2            18
102 #define I82580_PHY_LBK_CTRL          19
103 #define I82580_PHY_STATUS_2          26
104 #define I82580_PHY_DIAG_STATUS       31
105 
106 /* I82580 PHY Status 2 */
107 #define I82580_PHY_STATUS2_REV_POLARITY   0x0400
108 #define I82580_PHY_STATUS2_MDIX           0x0800
109 #define I82580_PHY_STATUS2_SPEED_MASK     0x0300
110 #define I82580_PHY_STATUS2_SPEED_1000MBPS 0x0200
111 #define I82580_PHY_STATUS2_SPEED_100MBPS  0x0100
112 
113 /* I82580 PHY Control 2 */
114 #define I82580_PHY_CTRL2_MANUAL_MDIX      0x0200
115 #define I82580_PHY_CTRL2_AUTO_MDI_MDIX    0x0400
116 #define I82580_PHY_CTRL2_MDIX_CFG_MASK    0x0600
117 
118 /* I82580 PHY Diagnostics Status */
119 #define I82580_DSTATUS_CABLE_LENGTH       0x03FC
120 #define I82580_DSTATUS_CABLE_LENGTH_SHIFT 2
121 
122 /* 82580 PHY Power Management */
123 #define E1000_82580_PHY_POWER_MGMT	0xE14
124 #define E1000_82580_PM_SPD		0x0001 /* Smart Power Down */
125 #define E1000_82580_PM_D0_LPLU		0x0002 /* For D0a states */
126 #define E1000_82580_PM_D3_LPLU		0x0004 /* For all other states */
127 #define E1000_82580_PM_GO_LINKD		0x0020 /* Go Link Disconnect */
128 
129 /* Enable flexible speed on link-up */
130 #define IGP02E1000_PM_D0_LPLU             0x0002 /* For D0a states */
131 #define IGP02E1000_PM_D3_LPLU             0x0004 /* For all other states */
132 #define IGP01E1000_PLHR_SS_DOWNGRADE      0x8000
133 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
134 #define IGP01E1000_PSSR_MDIX              0x0800
135 #define IGP01E1000_PSSR_SPEED_MASK        0xC000
136 #define IGP01E1000_PSSR_SPEED_1000MBPS    0xC000
137 #define IGP02E1000_PHY_CHANNEL_NUM        4
138 #define IGP02E1000_PHY_AGC_A              0x11B1
139 #define IGP02E1000_PHY_AGC_B              0x12B1
140 #define IGP02E1000_PHY_AGC_C              0x14B1
141 #define IGP02E1000_PHY_AGC_D              0x18B1
142 #define IGP02E1000_AGC_LENGTH_SHIFT       9   /* Course - 15:13, Fine - 12:9 */
143 #define IGP02E1000_AGC_LENGTH_MASK        0x7F
144 #define IGP02E1000_AGC_RANGE              15
145 
146 #define E1000_CABLE_LENGTH_UNDEFINED      0xFF
147 
148 /* SFP modules ID memory locations */
149 #define E1000_SFF_IDENTIFIER_OFFSET	0x00
150 #define E1000_SFF_IDENTIFIER_SFF	0x02
151 #define E1000_SFF_IDENTIFIER_SFP	0x03
152 
153 #define E1000_SFF_ETH_FLAGS_OFFSET	0x06
154 /* Flags for SFP modules compatible with ETH up to 1Gb */
155 struct e1000_sfp_flags {
156 	u8 e1000_base_sx:1;
157 	u8 e1000_base_lx:1;
158 	u8 e1000_base_cx:1;
159 	u8 e1000_base_t:1;
160 	u8 e100_base_lx:1;
161 	u8 e100_base_fx:1;
162 	u8 e10_base_bx10:1;
163 	u8 e10_base_px:1;
164 };
165 
166 #endif
167