1 /* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 #ifndef _E1000_PHY_H_ 25 #define _E1000_PHY_H_ 26 27 enum e1000_ms_type { 28 e1000_ms_hw_default = 0, 29 e1000_ms_force_master, 30 e1000_ms_force_slave, 31 e1000_ms_auto 32 }; 33 34 enum e1000_smart_speed { 35 e1000_smart_speed_default = 0, 36 e1000_smart_speed_on, 37 e1000_smart_speed_off 38 }; 39 40 s32 igb_check_downshift(struct e1000_hw *hw); 41 s32 igb_check_reset_block(struct e1000_hw *hw); 42 s32 igb_copper_link_setup_igp(struct e1000_hw *hw); 43 s32 igb_copper_link_setup_m88(struct e1000_hw *hw); 44 s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw); 45 s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw); 46 s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw); 47 s32 igb_get_cable_length_m88(struct e1000_hw *hw); 48 s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw); 49 s32 igb_get_cable_length_igp_2(struct e1000_hw *hw); 50 s32 igb_get_phy_id(struct e1000_hw *hw); 51 s32 igb_get_phy_info_igp(struct e1000_hw *hw); 52 s32 igb_get_phy_info_m88(struct e1000_hw *hw); 53 s32 igb_phy_sw_reset(struct e1000_hw *hw); 54 s32 igb_phy_hw_reset(struct e1000_hw *hw); 55 s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); 56 s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active); 57 s32 igb_setup_copper_link(struct e1000_hw *hw); 58 s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); 59 s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations, 60 u32 usec_interval, bool *success); 61 void igb_power_up_phy_copper(struct e1000_hw *hw); 62 void igb_power_down_phy_copper(struct e1000_hw *hw); 63 s32 igb_phy_init_script_igp3(struct e1000_hw *hw); 64 s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); 65 s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); 66 s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data); 67 s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data); 68 s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data); 69 s32 igb_copper_link_setup_82580(struct e1000_hw *hw); 70 s32 igb_get_phy_info_82580(struct e1000_hw *hw); 71 s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw); 72 s32 igb_get_cable_length_82580(struct e1000_hw *hw); 73 s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); 74 s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data); 75 s32 igb_check_polarity_m88(struct e1000_hw *hw); 76 77 /* IGP01E1000 Specific Registers */ 78 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ 79 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ 80 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ 81 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ 82 #define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ 83 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ 84 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 85 #define IGP01E1000_PHY_POLARITY_MASK 0x0078 86 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 87 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ 88 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 89 90 #define I82580_ADDR_REG 16 91 #define I82580_CFG_REG 22 92 #define I82580_CFG_ASSERT_CRS_ON_TX (1 << 15) 93 #define I82580_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */ 94 #define I82580_CTRL_REG 23 95 #define I82580_CTRL_DOWNSHIFT_MASK (7 << 10) 96 97 /* 82580 specific PHY registers */ 98 #define I82580_PHY_CTRL_2 18 99 #define I82580_PHY_LBK_CTRL 19 100 #define I82580_PHY_STATUS_2 26 101 #define I82580_PHY_DIAG_STATUS 31 102 103 /* I82580 PHY Status 2 */ 104 #define I82580_PHY_STATUS2_REV_POLARITY 0x0400 105 #define I82580_PHY_STATUS2_MDIX 0x0800 106 #define I82580_PHY_STATUS2_SPEED_MASK 0x0300 107 #define I82580_PHY_STATUS2_SPEED_1000MBPS 0x0200 108 #define I82580_PHY_STATUS2_SPEED_100MBPS 0x0100 109 110 /* I82580 PHY Control 2 */ 111 #define I82580_PHY_CTRL2_MANUAL_MDIX 0x0200 112 #define I82580_PHY_CTRL2_AUTO_MDI_MDIX 0x0400 113 #define I82580_PHY_CTRL2_MDIX_CFG_MASK 0x0600 114 115 /* I82580 PHY Diagnostics Status */ 116 #define I82580_DSTATUS_CABLE_LENGTH 0x03FC 117 #define I82580_DSTATUS_CABLE_LENGTH_SHIFT 2 118 119 /* 82580 PHY Power Management */ 120 #define E1000_82580_PHY_POWER_MGMT 0xE14 121 #define E1000_82580_PM_SPD 0x0001 /* Smart Power Down */ 122 #define E1000_82580_PM_D0_LPLU 0x0002 /* For D0a states */ 123 #define E1000_82580_PM_D3_LPLU 0x0004 /* For all other states */ 124 #define E1000_82580_PM_GO_LINKD 0x0020 /* Go Link Disconnect */ 125 126 /* Enable flexible speed on link-up */ 127 #define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ 128 #define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ 129 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 130 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 131 #define IGP01E1000_PSSR_MDIX 0x0800 132 #define IGP01E1000_PSSR_SPEED_MASK 0xC000 133 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 134 #define IGP02E1000_PHY_CHANNEL_NUM 4 135 #define IGP02E1000_PHY_AGC_A 0x11B1 136 #define IGP02E1000_PHY_AGC_B 0x12B1 137 #define IGP02E1000_PHY_AGC_C 0x14B1 138 #define IGP02E1000_PHY_AGC_D 0x18B1 139 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course - 15:13, Fine - 12:9 */ 140 #define IGP02E1000_AGC_LENGTH_MASK 0x7F 141 #define IGP02E1000_AGC_RANGE 15 142 143 #define E1000_CABLE_LENGTH_UNDEFINED 0xFF 144 145 /* GS40G - I210 PHY defines */ 146 #define GS40G_PAGE_SELECT 0x16 147 #define GS40G_PAGE_SHIFT 16 148 #define GS40G_OFFSET_MASK 0xFFFF 149 #define GS40G_PAGE_2 0x20000 150 #define GS40G_MAC_REG2 0x15 151 #define GS40G_MAC_LB 0x4140 152 #define GS40G_MAC_SPEED_1G 0X0006 153 #define GS40G_COPPER_SPEC 0x0010 154 #define GS40G_LINE_LB 0x4000 155 156 /* SFP modules ID memory locations */ 157 #define E1000_SFF_IDENTIFIER_OFFSET 0x00 158 #define E1000_SFF_IDENTIFIER_SFF 0x02 159 #define E1000_SFF_IDENTIFIER_SFP 0x03 160 161 #define E1000_SFF_ETH_FLAGS_OFFSET 0x06 162 /* Flags for SFP modules compatible with ETH up to 1Gb */ 163 struct e1000_sfp_flags { 164 u8 e1000_base_sx:1; 165 u8 e1000_base_lx:1; 166 u8 e1000_base_cx:1; 167 u8 e1000_base_t:1; 168 u8 e100_base_lx:1; 169 u8 e100_base_fx:1; 170 u8 e10_base_bx10:1; 171 u8 e10_base_px:1; 172 }; 173 174 #endif 175