1 /******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #include <linux/if_ether.h> 29 #include <linux/delay.h> 30 31 #include "e1000_mac.h" 32 #include "e1000_phy.h" 33 34 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw); 35 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, 36 u16 *phy_ctrl); 37 static s32 igb_wait_autoneg(struct e1000_hw *hw); 38 static s32 igb_set_master_slave_mode(struct e1000_hw *hw); 39 40 /* Cable length tables */ 41 static const u16 e1000_m88_cable_length_table[] = { 42 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 43 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 44 (sizeof(e1000_m88_cable_length_table) / \ 45 sizeof(e1000_m88_cable_length_table[0])) 46 47 static const u16 e1000_igp_2_cable_length_table[] = { 48 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 49 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 50 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 51 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 52 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 53 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 54 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 55 104, 109, 114, 118, 121, 124}; 56 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 57 (sizeof(e1000_igp_2_cable_length_table) / \ 58 sizeof(e1000_igp_2_cable_length_table[0])) 59 60 /** 61 * igb_check_reset_block - Check if PHY reset is blocked 62 * @hw: pointer to the HW structure 63 * 64 * Read the PHY management control register and check whether a PHY reset 65 * is blocked. If a reset is not blocked return 0, otherwise 66 * return E1000_BLK_PHY_RESET (12). 67 **/ 68 s32 igb_check_reset_block(struct e1000_hw *hw) 69 { 70 u32 manc; 71 72 manc = rd32(E1000_MANC); 73 74 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0; 75 } 76 77 /** 78 * igb_get_phy_id - Retrieve the PHY ID and revision 79 * @hw: pointer to the HW structure 80 * 81 * Reads the PHY registers and stores the PHY ID and possibly the PHY 82 * revision in the hardware structure. 83 **/ 84 s32 igb_get_phy_id(struct e1000_hw *hw) 85 { 86 struct e1000_phy_info *phy = &hw->phy; 87 s32 ret_val = 0; 88 u16 phy_id; 89 90 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 91 if (ret_val) 92 goto out; 93 94 phy->id = (u32)(phy_id << 16); 95 udelay(20); 96 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 97 if (ret_val) 98 goto out; 99 100 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 101 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 102 103 out: 104 return ret_val; 105 } 106 107 /** 108 * igb_phy_reset_dsp - Reset PHY DSP 109 * @hw: pointer to the HW structure 110 * 111 * Reset the digital signal processor. 112 **/ 113 static s32 igb_phy_reset_dsp(struct e1000_hw *hw) 114 { 115 s32 ret_val = 0; 116 117 if (!(hw->phy.ops.write_reg)) 118 goto out; 119 120 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 121 if (ret_val) 122 goto out; 123 124 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 125 126 out: 127 return ret_val; 128 } 129 130 /** 131 * igb_read_phy_reg_mdic - Read MDI control register 132 * @hw: pointer to the HW structure 133 * @offset: register offset to be read 134 * @data: pointer to the read data 135 * 136 * Reads the MDI control regsiter in the PHY at offset and stores the 137 * information read to data. 138 **/ 139 s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 140 { 141 struct e1000_phy_info *phy = &hw->phy; 142 u32 i, mdic = 0; 143 s32 ret_val = 0; 144 145 if (offset > MAX_PHY_REG_ADDRESS) { 146 hw_dbg("PHY Address %d is out of range\n", offset); 147 ret_val = -E1000_ERR_PARAM; 148 goto out; 149 } 150 151 /* Set up Op-code, Phy Address, and register offset in the MDI 152 * Control register. The MAC will take care of interfacing with the 153 * PHY to retrieve the desired data. 154 */ 155 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 156 (phy->addr << E1000_MDIC_PHY_SHIFT) | 157 (E1000_MDIC_OP_READ)); 158 159 wr32(E1000_MDIC, mdic); 160 161 /* Poll the ready bit to see if the MDI read completed 162 * Increasing the time out as testing showed failures with 163 * the lower time out 164 */ 165 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 166 udelay(50); 167 mdic = rd32(E1000_MDIC); 168 if (mdic & E1000_MDIC_READY) 169 break; 170 } 171 if (!(mdic & E1000_MDIC_READY)) { 172 hw_dbg("MDI Read did not complete\n"); 173 ret_val = -E1000_ERR_PHY; 174 goto out; 175 } 176 if (mdic & E1000_MDIC_ERROR) { 177 hw_dbg("MDI Error\n"); 178 ret_val = -E1000_ERR_PHY; 179 goto out; 180 } 181 *data = (u16) mdic; 182 183 out: 184 return ret_val; 185 } 186 187 /** 188 * igb_write_phy_reg_mdic - Write MDI control register 189 * @hw: pointer to the HW structure 190 * @offset: register offset to write to 191 * @data: data to write to register at offset 192 * 193 * Writes data to MDI control register in the PHY at offset. 194 **/ 195 s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 196 { 197 struct e1000_phy_info *phy = &hw->phy; 198 u32 i, mdic = 0; 199 s32 ret_val = 0; 200 201 if (offset > MAX_PHY_REG_ADDRESS) { 202 hw_dbg("PHY Address %d is out of range\n", offset); 203 ret_val = -E1000_ERR_PARAM; 204 goto out; 205 } 206 207 /* Set up Op-code, Phy Address, and register offset in the MDI 208 * Control register. The MAC will take care of interfacing with the 209 * PHY to retrieve the desired data. 210 */ 211 mdic = (((u32)data) | 212 (offset << E1000_MDIC_REG_SHIFT) | 213 (phy->addr << E1000_MDIC_PHY_SHIFT) | 214 (E1000_MDIC_OP_WRITE)); 215 216 wr32(E1000_MDIC, mdic); 217 218 /* Poll the ready bit to see if the MDI read completed 219 * Increasing the time out as testing showed failures with 220 * the lower time out 221 */ 222 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 223 udelay(50); 224 mdic = rd32(E1000_MDIC); 225 if (mdic & E1000_MDIC_READY) 226 break; 227 } 228 if (!(mdic & E1000_MDIC_READY)) { 229 hw_dbg("MDI Write did not complete\n"); 230 ret_val = -E1000_ERR_PHY; 231 goto out; 232 } 233 if (mdic & E1000_MDIC_ERROR) { 234 hw_dbg("MDI Error\n"); 235 ret_val = -E1000_ERR_PHY; 236 goto out; 237 } 238 239 out: 240 return ret_val; 241 } 242 243 /** 244 * igb_read_phy_reg_i2c - Read PHY register using i2c 245 * @hw: pointer to the HW structure 246 * @offset: register offset to be read 247 * @data: pointer to the read data 248 * 249 * Reads the PHY register at offset using the i2c interface and stores the 250 * retrieved information in data. 251 **/ 252 s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) 253 { 254 struct e1000_phy_info *phy = &hw->phy; 255 u32 i, i2ccmd = 0; 256 257 /* Set up Op-code, Phy Address, and register address in the I2CCMD 258 * register. The MAC will take care of interfacing with the 259 * PHY to retrieve the desired data. 260 */ 261 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 262 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 263 (E1000_I2CCMD_OPCODE_READ)); 264 265 wr32(E1000_I2CCMD, i2ccmd); 266 267 /* Poll the ready bit to see if the I2C read completed */ 268 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 269 udelay(50); 270 i2ccmd = rd32(E1000_I2CCMD); 271 if (i2ccmd & E1000_I2CCMD_READY) 272 break; 273 } 274 if (!(i2ccmd & E1000_I2CCMD_READY)) { 275 hw_dbg("I2CCMD Read did not complete\n"); 276 return -E1000_ERR_PHY; 277 } 278 if (i2ccmd & E1000_I2CCMD_ERROR) { 279 hw_dbg("I2CCMD Error bit set\n"); 280 return -E1000_ERR_PHY; 281 } 282 283 /* Need to byte-swap the 16-bit value. */ 284 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 285 286 return 0; 287 } 288 289 /** 290 * igb_write_phy_reg_i2c - Write PHY register using i2c 291 * @hw: pointer to the HW structure 292 * @offset: register offset to write to 293 * @data: data to write at register offset 294 * 295 * Writes the data to PHY register at the offset using the i2c interface. 296 **/ 297 s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) 298 { 299 struct e1000_phy_info *phy = &hw->phy; 300 u32 i, i2ccmd = 0; 301 u16 phy_data_swapped; 302 303 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/ 304 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) { 305 hw_dbg("PHY I2C Address %d is out of range.\n", 306 hw->phy.addr); 307 return -E1000_ERR_CONFIG; 308 } 309 310 /* Swap the data bytes for the I2C interface */ 311 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 312 313 /* Set up Op-code, Phy Address, and register address in the I2CCMD 314 * register. The MAC will take care of interfacing with the 315 * PHY to retrieve the desired data. 316 */ 317 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 318 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 319 E1000_I2CCMD_OPCODE_WRITE | 320 phy_data_swapped); 321 322 wr32(E1000_I2CCMD, i2ccmd); 323 324 /* Poll the ready bit to see if the I2C read completed */ 325 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 326 udelay(50); 327 i2ccmd = rd32(E1000_I2CCMD); 328 if (i2ccmd & E1000_I2CCMD_READY) 329 break; 330 } 331 if (!(i2ccmd & E1000_I2CCMD_READY)) { 332 hw_dbg("I2CCMD Write did not complete\n"); 333 return -E1000_ERR_PHY; 334 } 335 if (i2ccmd & E1000_I2CCMD_ERROR) { 336 hw_dbg("I2CCMD Error bit set\n"); 337 return -E1000_ERR_PHY; 338 } 339 340 return 0; 341 } 342 343 /** 344 * igb_read_sfp_data_byte - Reads SFP module data. 345 * @hw: pointer to the HW structure 346 * @offset: byte location offset to be read 347 * @data: read data buffer pointer 348 * 349 * Reads one byte from SFP module data stored 350 * in SFP resided EEPROM memory or SFP diagnostic area. 351 * Function should be called with 352 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 353 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 354 * access 355 **/ 356 s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data) 357 { 358 u32 i = 0; 359 u32 i2ccmd = 0; 360 u32 data_local = 0; 361 362 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 363 hw_dbg("I2CCMD command address exceeds upper limit\n"); 364 return -E1000_ERR_PHY; 365 } 366 367 /* Set up Op-code, EEPROM Address,in the I2CCMD 368 * register. The MAC will take care of interfacing with the 369 * EEPROM to retrieve the desired data. 370 */ 371 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 372 E1000_I2CCMD_OPCODE_READ); 373 374 wr32(E1000_I2CCMD, i2ccmd); 375 376 /* Poll the ready bit to see if the I2C read completed */ 377 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 378 udelay(50); 379 data_local = rd32(E1000_I2CCMD); 380 if (data_local & E1000_I2CCMD_READY) 381 break; 382 } 383 if (!(data_local & E1000_I2CCMD_READY)) { 384 hw_dbg("I2CCMD Read did not complete\n"); 385 return -E1000_ERR_PHY; 386 } 387 if (data_local & E1000_I2CCMD_ERROR) { 388 hw_dbg("I2CCMD Error bit set\n"); 389 return -E1000_ERR_PHY; 390 } 391 *data = (u8) data_local & 0xFF; 392 393 return 0; 394 } 395 396 /** 397 * e1000_write_sfp_data_byte - Writes SFP module data. 398 * @hw: pointer to the HW structure 399 * @offset: byte location offset to write to 400 * @data: data to write 401 * 402 * Writes one byte to SFP module data stored 403 * in SFP resided EEPROM memory or SFP diagnostic area. 404 * Function should be called with 405 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 406 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 407 * access 408 **/ 409 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data) 410 { 411 u32 i = 0; 412 u32 i2ccmd = 0; 413 u32 data_local = 0; 414 415 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 416 hw_dbg("I2CCMD command address exceeds upper limit\n"); 417 return -E1000_ERR_PHY; 418 } 419 /* The programming interface is 16 bits wide 420 * so we need to read the whole word first 421 * then update appropriate byte lane and write 422 * the updated word back. 423 */ 424 /* Set up Op-code, EEPROM Address,in the I2CCMD 425 * register. The MAC will take care of interfacing 426 * with an EEPROM to write the data given. 427 */ 428 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 429 E1000_I2CCMD_OPCODE_READ); 430 /* Set a command to read single word */ 431 wr32(E1000_I2CCMD, i2ccmd); 432 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 433 udelay(50); 434 /* Poll the ready bit to see if lastly 435 * launched I2C operation completed 436 */ 437 i2ccmd = rd32(E1000_I2CCMD); 438 if (i2ccmd & E1000_I2CCMD_READY) { 439 /* Check if this is READ or WRITE phase */ 440 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) == 441 E1000_I2CCMD_OPCODE_READ) { 442 /* Write the selected byte 443 * lane and update whole word 444 */ 445 data_local = i2ccmd & 0xFF00; 446 data_local |= data; 447 i2ccmd = ((offset << 448 E1000_I2CCMD_REG_ADDR_SHIFT) | 449 E1000_I2CCMD_OPCODE_WRITE | data_local); 450 wr32(E1000_I2CCMD, i2ccmd); 451 } else { 452 break; 453 } 454 } 455 } 456 if (!(i2ccmd & E1000_I2CCMD_READY)) { 457 hw_dbg("I2CCMD Write did not complete\n"); 458 return -E1000_ERR_PHY; 459 } 460 if (i2ccmd & E1000_I2CCMD_ERROR) { 461 hw_dbg("I2CCMD Error bit set\n"); 462 return -E1000_ERR_PHY; 463 } 464 return 0; 465 } 466 467 /** 468 * igb_read_phy_reg_igp - Read igp PHY register 469 * @hw: pointer to the HW structure 470 * @offset: register offset to be read 471 * @data: pointer to the read data 472 * 473 * Acquires semaphore, if necessary, then reads the PHY register at offset 474 * and storing the retrieved information in data. Release any acquired 475 * semaphores before exiting. 476 **/ 477 s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 478 { 479 s32 ret_val = 0; 480 481 if (!(hw->phy.ops.acquire)) 482 goto out; 483 484 ret_val = hw->phy.ops.acquire(hw); 485 if (ret_val) 486 goto out; 487 488 if (offset > MAX_PHY_MULTI_PAGE_REG) { 489 ret_val = igb_write_phy_reg_mdic(hw, 490 IGP01E1000_PHY_PAGE_SELECT, 491 (u16)offset); 492 if (ret_val) { 493 hw->phy.ops.release(hw); 494 goto out; 495 } 496 } 497 498 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 499 data); 500 501 hw->phy.ops.release(hw); 502 503 out: 504 return ret_val; 505 } 506 507 /** 508 * igb_write_phy_reg_igp - Write igp PHY register 509 * @hw: pointer to the HW structure 510 * @offset: register offset to write to 511 * @data: data to write at register offset 512 * 513 * Acquires semaphore, if necessary, then writes the data to PHY register 514 * at the offset. Release any acquired semaphores before exiting. 515 **/ 516 s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 517 { 518 s32 ret_val = 0; 519 520 if (!(hw->phy.ops.acquire)) 521 goto out; 522 523 ret_val = hw->phy.ops.acquire(hw); 524 if (ret_val) 525 goto out; 526 527 if (offset > MAX_PHY_MULTI_PAGE_REG) { 528 ret_val = igb_write_phy_reg_mdic(hw, 529 IGP01E1000_PHY_PAGE_SELECT, 530 (u16)offset); 531 if (ret_val) { 532 hw->phy.ops.release(hw); 533 goto out; 534 } 535 } 536 537 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 538 data); 539 540 hw->phy.ops.release(hw); 541 542 out: 543 return ret_val; 544 } 545 546 /** 547 * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link 548 * @hw: pointer to the HW structure 549 * 550 * Sets up Carrier-sense on Transmit and downshift values. 551 **/ 552 s32 igb_copper_link_setup_82580(struct e1000_hw *hw) 553 { 554 struct e1000_phy_info *phy = &hw->phy; 555 s32 ret_val; 556 u16 phy_data; 557 558 if (phy->reset_disable) { 559 ret_val = 0; 560 goto out; 561 } 562 563 if (phy->type == e1000_phy_82580) { 564 ret_val = hw->phy.ops.reset(hw); 565 if (ret_val) { 566 hw_dbg("Error resetting the PHY.\n"); 567 goto out; 568 } 569 } 570 571 /* Enable CRS on TX. This must be set for half-duplex operation. */ 572 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data); 573 if (ret_val) 574 goto out; 575 576 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX; 577 578 /* Enable downshift */ 579 phy_data |= I82580_CFG_ENABLE_DOWNSHIFT; 580 581 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data); 582 if (ret_val) 583 goto out; 584 585 /* Set MDI/MDIX mode */ 586 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); 587 if (ret_val) 588 goto out; 589 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK; 590 /* Options: 591 * 0 - Auto (default) 592 * 1 - MDI mode 593 * 2 - MDI-X mode 594 */ 595 switch (hw->phy.mdix) { 596 case 1: 597 break; 598 case 2: 599 phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX; 600 break; 601 case 0: 602 default: 603 phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX; 604 break; 605 } 606 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); 607 608 out: 609 return ret_val; 610 } 611 612 /** 613 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link 614 * @hw: pointer to the HW structure 615 * 616 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 617 * and downshift values are set also. 618 **/ 619 s32 igb_copper_link_setup_m88(struct e1000_hw *hw) 620 { 621 struct e1000_phy_info *phy = &hw->phy; 622 s32 ret_val; 623 u16 phy_data; 624 625 if (phy->reset_disable) { 626 ret_val = 0; 627 goto out; 628 } 629 630 /* Enable CRS on TX. This must be set for half-duplex operation. */ 631 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 632 if (ret_val) 633 goto out; 634 635 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 636 637 /* Options: 638 * MDI/MDI-X = 0 (default) 639 * 0 - Auto for all speeds 640 * 1 - MDI mode 641 * 2 - MDI-X mode 642 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 643 */ 644 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 645 646 switch (phy->mdix) { 647 case 1: 648 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 649 break; 650 case 2: 651 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 652 break; 653 case 3: 654 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 655 break; 656 case 0: 657 default: 658 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 659 break; 660 } 661 662 /* Options: 663 * disable_polarity_correction = 0 (default) 664 * Automatic Correction for Reversed Cable Polarity 665 * 0 - Disabled 666 * 1 - Enabled 667 */ 668 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 669 if (phy->disable_polarity_correction == 1) 670 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 671 672 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 673 if (ret_val) 674 goto out; 675 676 if (phy->revision < E1000_REVISION_4) { 677 /* Force TX_CLK in the Extended PHY Specific Control Register 678 * to 25MHz clock. 679 */ 680 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 681 &phy_data); 682 if (ret_val) 683 goto out; 684 685 phy_data |= M88E1000_EPSCR_TX_CLK_25; 686 687 if ((phy->revision == E1000_REVISION_2) && 688 (phy->id == M88E1111_I_PHY_ID)) { 689 /* 82573L PHY - set the downshift counter to 5x. */ 690 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 691 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 692 } else { 693 /* Configure Master and Slave downshift values */ 694 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 695 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 696 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 697 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 698 } 699 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 700 phy_data); 701 if (ret_val) 702 goto out; 703 } 704 705 /* Commit the changes. */ 706 ret_val = igb_phy_sw_reset(hw); 707 if (ret_val) { 708 hw_dbg("Error committing the PHY changes\n"); 709 goto out; 710 } 711 if (phy->type == e1000_phy_i210) { 712 ret_val = igb_set_master_slave_mode(hw); 713 if (ret_val) 714 return ret_val; 715 } 716 717 out: 718 return ret_val; 719 } 720 721 /** 722 * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link 723 * @hw: pointer to the HW structure 724 * 725 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's. 726 * Also enables and sets the downshift parameters. 727 **/ 728 s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw) 729 { 730 struct e1000_phy_info *phy = &hw->phy; 731 s32 ret_val; 732 u16 phy_data; 733 734 if (phy->reset_disable) { 735 ret_val = 0; 736 goto out; 737 } 738 739 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 740 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 741 if (ret_val) 742 goto out; 743 744 /* Options: 745 * MDI/MDI-X = 0 (default) 746 * 0 - Auto for all speeds 747 * 1 - MDI mode 748 * 2 - MDI-X mode 749 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 750 */ 751 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 752 753 switch (phy->mdix) { 754 case 1: 755 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 756 break; 757 case 2: 758 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 759 break; 760 case 3: 761 /* M88E1112 does not support this mode) */ 762 if (phy->id != M88E1112_E_PHY_ID) { 763 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 764 break; 765 } 766 case 0: 767 default: 768 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 769 break; 770 } 771 772 /* Options: 773 * disable_polarity_correction = 0 (default) 774 * Automatic Correction for Reversed Cable Polarity 775 * 0 - Disabled 776 * 1 - Enabled 777 */ 778 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 779 if (phy->disable_polarity_correction == 1) 780 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 781 782 /* Enable downshift and setting it to X6 */ 783 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK; 784 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X; 785 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE; 786 787 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 788 if (ret_val) 789 goto out; 790 791 /* Commit the changes. */ 792 ret_val = igb_phy_sw_reset(hw); 793 if (ret_val) { 794 hw_dbg("Error committing the PHY changes\n"); 795 goto out; 796 } 797 798 out: 799 return ret_val; 800 } 801 802 /** 803 * igb_copper_link_setup_igp - Setup igp PHY's for copper link 804 * @hw: pointer to the HW structure 805 * 806 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 807 * igp PHY's. 808 **/ 809 s32 igb_copper_link_setup_igp(struct e1000_hw *hw) 810 { 811 struct e1000_phy_info *phy = &hw->phy; 812 s32 ret_val; 813 u16 data; 814 815 if (phy->reset_disable) { 816 ret_val = 0; 817 goto out; 818 } 819 820 ret_val = phy->ops.reset(hw); 821 if (ret_val) { 822 hw_dbg("Error resetting the PHY.\n"); 823 goto out; 824 } 825 826 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid 827 * timeout issues when LFS is enabled. 828 */ 829 msleep(100); 830 831 /* The NVM settings will configure LPLU in D3 for 832 * non-IGP1 PHYs. 833 */ 834 if (phy->type == e1000_phy_igp) { 835 /* disable lplu d3 during driver init */ 836 if (phy->ops.set_d3_lplu_state) 837 ret_val = phy->ops.set_d3_lplu_state(hw, false); 838 if (ret_val) { 839 hw_dbg("Error Disabling LPLU D3\n"); 840 goto out; 841 } 842 } 843 844 /* disable lplu d0 during driver init */ 845 ret_val = phy->ops.set_d0_lplu_state(hw, false); 846 if (ret_val) { 847 hw_dbg("Error Disabling LPLU D0\n"); 848 goto out; 849 } 850 /* Configure mdi-mdix settings */ 851 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 852 if (ret_val) 853 goto out; 854 855 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 856 857 switch (phy->mdix) { 858 case 1: 859 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 860 break; 861 case 2: 862 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 863 break; 864 case 0: 865 default: 866 data |= IGP01E1000_PSCR_AUTO_MDIX; 867 break; 868 } 869 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 870 if (ret_val) 871 goto out; 872 873 /* set auto-master slave resolution settings */ 874 if (hw->mac.autoneg) { 875 /* when autonegotiation advertisement is only 1000Mbps then we 876 * should disable SmartSpeed and enable Auto MasterSlave 877 * resolution as hardware default. 878 */ 879 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 880 /* Disable SmartSpeed */ 881 ret_val = phy->ops.read_reg(hw, 882 IGP01E1000_PHY_PORT_CONFIG, 883 &data); 884 if (ret_val) 885 goto out; 886 887 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 888 ret_val = phy->ops.write_reg(hw, 889 IGP01E1000_PHY_PORT_CONFIG, 890 data); 891 if (ret_val) 892 goto out; 893 894 /* Set auto Master/Slave resolution process */ 895 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 896 if (ret_val) 897 goto out; 898 899 data &= ~CR_1000T_MS_ENABLE; 900 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 901 if (ret_val) 902 goto out; 903 } 904 905 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 906 if (ret_val) 907 goto out; 908 909 /* load defaults for future use */ 910 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 911 ((data & CR_1000T_MS_VALUE) ? 912 e1000_ms_force_master : 913 e1000_ms_force_slave) : 914 e1000_ms_auto; 915 916 switch (phy->ms_type) { 917 case e1000_ms_force_master: 918 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 919 break; 920 case e1000_ms_force_slave: 921 data |= CR_1000T_MS_ENABLE; 922 data &= ~(CR_1000T_MS_VALUE); 923 break; 924 case e1000_ms_auto: 925 data &= ~CR_1000T_MS_ENABLE; 926 default: 927 break; 928 } 929 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 930 if (ret_val) 931 goto out; 932 } 933 934 out: 935 return ret_val; 936 } 937 938 /** 939 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link 940 * @hw: pointer to the HW structure 941 * 942 * Performs initial bounds checking on autoneg advertisement parameter, then 943 * configure to advertise the full capability. Setup the PHY to autoneg 944 * and restart the negotiation process between the link partner. If 945 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 946 **/ 947 static s32 igb_copper_link_autoneg(struct e1000_hw *hw) 948 { 949 struct e1000_phy_info *phy = &hw->phy; 950 s32 ret_val; 951 u16 phy_ctrl; 952 953 /* Perform some bounds checking on the autoneg advertisement 954 * parameter. 955 */ 956 phy->autoneg_advertised &= phy->autoneg_mask; 957 958 /* If autoneg_advertised is zero, we assume it was not defaulted 959 * by the calling code so we set to advertise full capability. 960 */ 961 if (phy->autoneg_advertised == 0) 962 phy->autoneg_advertised = phy->autoneg_mask; 963 964 hw_dbg("Reconfiguring auto-neg advertisement params\n"); 965 ret_val = igb_phy_setup_autoneg(hw); 966 if (ret_val) { 967 hw_dbg("Error Setting up Auto-Negotiation\n"); 968 goto out; 969 } 970 hw_dbg("Restarting Auto-Neg\n"); 971 972 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 973 * the Auto Neg Restart bit in the PHY control register. 974 */ 975 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 976 if (ret_val) 977 goto out; 978 979 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 980 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 981 if (ret_val) 982 goto out; 983 984 /* Does the user want to wait for Auto-Neg to complete here, or 985 * check at a later time (for example, callback routine). 986 */ 987 if (phy->autoneg_wait_to_complete) { 988 ret_val = igb_wait_autoneg(hw); 989 if (ret_val) { 990 hw_dbg("Error while waiting for " 991 "autoneg to complete\n"); 992 goto out; 993 } 994 } 995 996 hw->mac.get_link_status = true; 997 998 out: 999 return ret_val; 1000 } 1001 1002 /** 1003 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation 1004 * @hw: pointer to the HW structure 1005 * 1006 * Reads the MII auto-neg advertisement register and/or the 1000T control 1007 * register and if the PHY is already setup for auto-negotiation, then 1008 * return successful. Otherwise, setup advertisement and flow control to 1009 * the appropriate values for the wanted auto-negotiation. 1010 **/ 1011 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw) 1012 { 1013 struct e1000_phy_info *phy = &hw->phy; 1014 s32 ret_val; 1015 u16 mii_autoneg_adv_reg; 1016 u16 mii_1000t_ctrl_reg = 0; 1017 1018 phy->autoneg_advertised &= phy->autoneg_mask; 1019 1020 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1021 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 1022 if (ret_val) 1023 goto out; 1024 1025 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1026 /* Read the MII 1000Base-T Control Register (Address 9). */ 1027 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 1028 &mii_1000t_ctrl_reg); 1029 if (ret_val) 1030 goto out; 1031 } 1032 1033 /* Need to parse both autoneg_advertised and fc and set up 1034 * the appropriate PHY registers. First we will parse for 1035 * autoneg_advertised software override. Since we can advertise 1036 * a plethora of combinations, we need to check each bit 1037 * individually. 1038 */ 1039 1040 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 1041 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1042 * the 1000Base-T Control Register (Address 9). 1043 */ 1044 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 1045 NWAY_AR_100TX_HD_CAPS | 1046 NWAY_AR_10T_FD_CAPS | 1047 NWAY_AR_10T_HD_CAPS); 1048 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 1049 1050 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); 1051 1052 /* Do we want to advertise 10 Mb Half Duplex? */ 1053 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 1054 hw_dbg("Advertise 10mb Half duplex\n"); 1055 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1056 } 1057 1058 /* Do we want to advertise 10 Mb Full Duplex? */ 1059 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 1060 hw_dbg("Advertise 10mb Full duplex\n"); 1061 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1062 } 1063 1064 /* Do we want to advertise 100 Mb Half Duplex? */ 1065 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 1066 hw_dbg("Advertise 100mb Half duplex\n"); 1067 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1068 } 1069 1070 /* Do we want to advertise 100 Mb Full Duplex? */ 1071 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 1072 hw_dbg("Advertise 100mb Full duplex\n"); 1073 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1074 } 1075 1076 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1077 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 1078 hw_dbg("Advertise 1000mb Half duplex request denied!\n"); 1079 1080 /* Do we want to advertise 1000 Mb Full Duplex? */ 1081 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 1082 hw_dbg("Advertise 1000mb Full duplex\n"); 1083 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1084 } 1085 1086 /* Check for a software override of the flow control settings, and 1087 * setup the PHY advertisement registers accordingly. If 1088 * auto-negotiation is enabled, then software will have to set the 1089 * "PAUSE" bits to the correct value in the Auto-Negotiation 1090 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 1091 * negotiation. 1092 * 1093 * The possible values of the "fc" parameter are: 1094 * 0: Flow control is completely disabled 1095 * 1: Rx flow control is enabled (we can receive pause frames 1096 * but not send pause frames). 1097 * 2: Tx flow control is enabled (we can send pause frames 1098 * but we do not support receiving pause frames). 1099 * 3: Both Rx and TX flow control (symmetric) are enabled. 1100 * other: No software override. The flow control configuration 1101 * in the EEPROM is used. 1102 */ 1103 switch (hw->fc.current_mode) { 1104 case e1000_fc_none: 1105 /* Flow control (RX & TX) is completely disabled by a 1106 * software over-ride. 1107 */ 1108 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1109 break; 1110 case e1000_fc_rx_pause: 1111 /* RX Flow control is enabled, and TX Flow control is 1112 * disabled, by a software over-ride. 1113 * 1114 * Since there really isn't a way to advertise that we are 1115 * capable of RX Pause ONLY, we will advertise that we 1116 * support both symmetric and asymmetric RX PAUSE. Later 1117 * (in e1000_config_fc_after_link_up) we will disable the 1118 * hw's ability to send PAUSE frames. 1119 */ 1120 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1121 break; 1122 case e1000_fc_tx_pause: 1123 /* TX Flow control is enabled, and RX Flow control is 1124 * disabled, by a software over-ride. 1125 */ 1126 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1127 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1128 break; 1129 case e1000_fc_full: 1130 /* Flow control (both RX and TX) is enabled by a software 1131 * over-ride. 1132 */ 1133 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1134 break; 1135 default: 1136 hw_dbg("Flow control param set incorrectly\n"); 1137 ret_val = -E1000_ERR_CONFIG; 1138 goto out; 1139 } 1140 1141 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1142 if (ret_val) 1143 goto out; 1144 1145 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1146 1147 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1148 ret_val = phy->ops.write_reg(hw, 1149 PHY_1000T_CTRL, 1150 mii_1000t_ctrl_reg); 1151 if (ret_val) 1152 goto out; 1153 } 1154 1155 out: 1156 return ret_val; 1157 } 1158 1159 /** 1160 * igb_setup_copper_link - Configure copper link settings 1161 * @hw: pointer to the HW structure 1162 * 1163 * Calls the appropriate function to configure the link for auto-neg or forced 1164 * speed and duplex. Then we check for link, once link is established calls 1165 * to configure collision distance and flow control are called. If link is 1166 * not established, we return -E1000_ERR_PHY (-2). 1167 **/ 1168 s32 igb_setup_copper_link(struct e1000_hw *hw) 1169 { 1170 s32 ret_val; 1171 bool link; 1172 1173 if (hw->mac.autoneg) { 1174 /* Setup autoneg and flow control advertisement and perform 1175 * autonegotiation. 1176 */ 1177 ret_val = igb_copper_link_autoneg(hw); 1178 if (ret_val) 1179 goto out; 1180 } else { 1181 /* PHY will be set to 10H, 10F, 100H or 100F 1182 * depending on user settings. 1183 */ 1184 hw_dbg("Forcing Speed and Duplex\n"); 1185 ret_val = hw->phy.ops.force_speed_duplex(hw); 1186 if (ret_val) { 1187 hw_dbg("Error Forcing Speed and Duplex\n"); 1188 goto out; 1189 } 1190 } 1191 1192 /* Check link status. Wait up to 100 microseconds for link to become 1193 * valid. 1194 */ 1195 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link); 1196 if (ret_val) 1197 goto out; 1198 1199 if (link) { 1200 hw_dbg("Valid link established!!!\n"); 1201 igb_config_collision_dist(hw); 1202 ret_val = igb_config_fc_after_link_up(hw); 1203 } else { 1204 hw_dbg("Unable to establish link!!!\n"); 1205 } 1206 1207 out: 1208 return ret_val; 1209 } 1210 1211 /** 1212 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1213 * @hw: pointer to the HW structure 1214 * 1215 * Calls the PHY setup function to force speed and duplex. Clears the 1216 * auto-crossover to force MDI manually. Waits for link and returns 1217 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1218 **/ 1219 s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1220 { 1221 struct e1000_phy_info *phy = &hw->phy; 1222 s32 ret_val; 1223 u16 phy_data; 1224 bool link; 1225 1226 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1227 if (ret_val) 1228 goto out; 1229 1230 igb_phy_force_speed_duplex_setup(hw, &phy_data); 1231 1232 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1233 if (ret_val) 1234 goto out; 1235 1236 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1237 * forced whenever speed and duplex are forced. 1238 */ 1239 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1240 if (ret_val) 1241 goto out; 1242 1243 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1244 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1245 1246 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1247 if (ret_val) 1248 goto out; 1249 1250 hw_dbg("IGP PSCR: %X\n", phy_data); 1251 1252 udelay(1); 1253 1254 if (phy->autoneg_wait_to_complete) { 1255 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); 1256 1257 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link); 1258 if (ret_val) 1259 goto out; 1260 1261 if (!link) 1262 hw_dbg("Link taking longer than expected.\n"); 1263 1264 /* Try once more */ 1265 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link); 1266 if (ret_val) 1267 goto out; 1268 } 1269 1270 out: 1271 return ret_val; 1272 } 1273 1274 /** 1275 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1276 * @hw: pointer to the HW structure 1277 * 1278 * Calls the PHY setup function to force speed and duplex. Clears the 1279 * auto-crossover to force MDI manually. Resets the PHY to commit the 1280 * changes. If time expires while waiting for link up, we reset the DSP. 1281 * After reset, TX_CLK and CRS on TX must be set. Return successful upon 1282 * successful completion, else return corresponding error code. 1283 **/ 1284 s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1285 { 1286 struct e1000_phy_info *phy = &hw->phy; 1287 s32 ret_val; 1288 u16 phy_data; 1289 bool link; 1290 1291 /* I210 and I211 devices support Auto-Crossover in forced operation. */ 1292 if (phy->type != e1000_phy_i210) { 1293 /* Clear Auto-Crossover to force MDI manually. M88E1000 1294 * requires MDI forced whenever speed and duplex are forced. 1295 */ 1296 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, 1297 &phy_data); 1298 if (ret_val) 1299 goto out; 1300 1301 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1302 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 1303 phy_data); 1304 if (ret_val) 1305 goto out; 1306 1307 hw_dbg("M88E1000 PSCR: %X\n", phy_data); 1308 } 1309 1310 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1311 if (ret_val) 1312 goto out; 1313 1314 igb_phy_force_speed_duplex_setup(hw, &phy_data); 1315 1316 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1317 if (ret_val) 1318 goto out; 1319 1320 /* Reset the phy to commit changes. */ 1321 ret_val = igb_phy_sw_reset(hw); 1322 if (ret_val) 1323 goto out; 1324 1325 if (phy->autoneg_wait_to_complete) { 1326 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); 1327 1328 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); 1329 if (ret_val) 1330 goto out; 1331 1332 if (!link) { 1333 bool reset_dsp = true; 1334 1335 switch (hw->phy.id) { 1336 case I347AT4_E_PHY_ID: 1337 case M88E1112_E_PHY_ID: 1338 case I210_I_PHY_ID: 1339 reset_dsp = false; 1340 break; 1341 default: 1342 if (hw->phy.type != e1000_phy_m88) 1343 reset_dsp = false; 1344 break; 1345 } 1346 if (!reset_dsp) 1347 hw_dbg("Link taking longer than expected.\n"); 1348 else { 1349 /* We didn't get link. 1350 * Reset the DSP and cross our fingers. 1351 */ 1352 ret_val = phy->ops.write_reg(hw, 1353 M88E1000_PHY_PAGE_SELECT, 1354 0x001d); 1355 if (ret_val) 1356 goto out; 1357 ret_val = igb_phy_reset_dsp(hw); 1358 if (ret_val) 1359 goto out; 1360 } 1361 } 1362 1363 /* Try once more */ 1364 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 1365 100000, &link); 1366 if (ret_val) 1367 goto out; 1368 } 1369 1370 if (hw->phy.type != e1000_phy_m88 || 1371 hw->phy.id == I347AT4_E_PHY_ID || 1372 hw->phy.id == M88E1112_E_PHY_ID || 1373 hw->phy.id == I210_I_PHY_ID) 1374 goto out; 1375 1376 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1377 if (ret_val) 1378 goto out; 1379 1380 /* Resetting the phy means we need to re-force TX_CLK in the 1381 * Extended PHY Specific Control Register to 25MHz clock from 1382 * the reset value of 2.5MHz. 1383 */ 1384 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1385 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1386 if (ret_val) 1387 goto out; 1388 1389 /* In addition, we must re-enable CRS on Tx for both half and full 1390 * duplex. 1391 */ 1392 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1393 if (ret_val) 1394 goto out; 1395 1396 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1397 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1398 1399 out: 1400 return ret_val; 1401 } 1402 1403 /** 1404 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1405 * @hw: pointer to the HW structure 1406 * @phy_ctrl: pointer to current value of PHY_CONTROL 1407 * 1408 * Forces speed and duplex on the PHY by doing the following: disable flow 1409 * control, force speed/duplex on the MAC, disable auto speed detection, 1410 * disable auto-negotiation, configure duplex, configure speed, configure 1411 * the collision distance, write configuration to CTRL register. The 1412 * caller must write to the PHY_CONTROL register for these settings to 1413 * take affect. 1414 **/ 1415 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, 1416 u16 *phy_ctrl) 1417 { 1418 struct e1000_mac_info *mac = &hw->mac; 1419 u32 ctrl; 1420 1421 /* Turn off flow control when forcing speed/duplex */ 1422 hw->fc.current_mode = e1000_fc_none; 1423 1424 /* Force speed/duplex on the mac */ 1425 ctrl = rd32(E1000_CTRL); 1426 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1427 ctrl &= ~E1000_CTRL_SPD_SEL; 1428 1429 /* Disable Auto Speed Detection */ 1430 ctrl &= ~E1000_CTRL_ASDE; 1431 1432 /* Disable autoneg on the phy */ 1433 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1434 1435 /* Forcing Full or Half Duplex? */ 1436 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1437 ctrl &= ~E1000_CTRL_FD; 1438 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1439 hw_dbg("Half Duplex\n"); 1440 } else { 1441 ctrl |= E1000_CTRL_FD; 1442 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1443 hw_dbg("Full Duplex\n"); 1444 } 1445 1446 /* Forcing 10mb or 100mb? */ 1447 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1448 ctrl |= E1000_CTRL_SPD_100; 1449 *phy_ctrl |= MII_CR_SPEED_100; 1450 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1451 hw_dbg("Forcing 100mb\n"); 1452 } else { 1453 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1454 *phy_ctrl |= MII_CR_SPEED_10; 1455 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1456 hw_dbg("Forcing 10mb\n"); 1457 } 1458 1459 igb_config_collision_dist(hw); 1460 1461 wr32(E1000_CTRL, ctrl); 1462 } 1463 1464 /** 1465 * igb_set_d3_lplu_state - Sets low power link up state for D3 1466 * @hw: pointer to the HW structure 1467 * @active: boolean used to enable/disable lplu 1468 * 1469 * Success returns 0, Failure returns 1 1470 * 1471 * The low power link up (lplu) state is set to the power management level D3 1472 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1473 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1474 * is used during Dx states where the power conservation is most important. 1475 * During driver activity, SmartSpeed should be enabled so performance is 1476 * maintained. 1477 **/ 1478 s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active) 1479 { 1480 struct e1000_phy_info *phy = &hw->phy; 1481 s32 ret_val = 0; 1482 u16 data; 1483 1484 if (!(hw->phy.ops.read_reg)) 1485 goto out; 1486 1487 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1488 if (ret_val) 1489 goto out; 1490 1491 if (!active) { 1492 data &= ~IGP02E1000_PM_D3_LPLU; 1493 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1494 data); 1495 if (ret_val) 1496 goto out; 1497 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1498 * during Dx states where the power conservation is most 1499 * important. During driver activity we should enable 1500 * SmartSpeed, so performance is maintained. 1501 */ 1502 if (phy->smart_speed == e1000_smart_speed_on) { 1503 ret_val = phy->ops.read_reg(hw, 1504 IGP01E1000_PHY_PORT_CONFIG, 1505 &data); 1506 if (ret_val) 1507 goto out; 1508 1509 data |= IGP01E1000_PSCFR_SMART_SPEED; 1510 ret_val = phy->ops.write_reg(hw, 1511 IGP01E1000_PHY_PORT_CONFIG, 1512 data); 1513 if (ret_val) 1514 goto out; 1515 } else if (phy->smart_speed == e1000_smart_speed_off) { 1516 ret_val = phy->ops.read_reg(hw, 1517 IGP01E1000_PHY_PORT_CONFIG, 1518 &data); 1519 if (ret_val) 1520 goto out; 1521 1522 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1523 ret_val = phy->ops.write_reg(hw, 1524 IGP01E1000_PHY_PORT_CONFIG, 1525 data); 1526 if (ret_val) 1527 goto out; 1528 } 1529 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1530 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1531 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1532 data |= IGP02E1000_PM_D3_LPLU; 1533 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1534 data); 1535 if (ret_val) 1536 goto out; 1537 1538 /* When LPLU is enabled, we should disable SmartSpeed */ 1539 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1540 &data); 1541 if (ret_val) 1542 goto out; 1543 1544 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1545 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1546 data); 1547 } 1548 1549 out: 1550 return ret_val; 1551 } 1552 1553 /** 1554 * igb_check_downshift - Checks whether a downshift in speed occurred 1555 * @hw: pointer to the HW structure 1556 * 1557 * Success returns 0, Failure returns 1 1558 * 1559 * A downshift is detected by querying the PHY link health. 1560 **/ 1561 s32 igb_check_downshift(struct e1000_hw *hw) 1562 { 1563 struct e1000_phy_info *phy = &hw->phy; 1564 s32 ret_val; 1565 u16 phy_data, offset, mask; 1566 1567 switch (phy->type) { 1568 case e1000_phy_i210: 1569 case e1000_phy_m88: 1570 case e1000_phy_gg82563: 1571 offset = M88E1000_PHY_SPEC_STATUS; 1572 mask = M88E1000_PSSR_DOWNSHIFT; 1573 break; 1574 case e1000_phy_igp_2: 1575 case e1000_phy_igp: 1576 case e1000_phy_igp_3: 1577 offset = IGP01E1000_PHY_LINK_HEALTH; 1578 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1579 break; 1580 default: 1581 /* speed downshift not supported */ 1582 phy->speed_downgraded = false; 1583 ret_val = 0; 1584 goto out; 1585 } 1586 1587 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 1588 1589 if (!ret_val) 1590 phy->speed_downgraded = (phy_data & mask) ? true : false; 1591 1592 out: 1593 return ret_val; 1594 } 1595 1596 /** 1597 * igb_check_polarity_m88 - Checks the polarity. 1598 * @hw: pointer to the HW structure 1599 * 1600 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1601 * 1602 * Polarity is determined based on the PHY specific status register. 1603 **/ 1604 s32 igb_check_polarity_m88(struct e1000_hw *hw) 1605 { 1606 struct e1000_phy_info *phy = &hw->phy; 1607 s32 ret_val; 1608 u16 data; 1609 1610 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 1611 1612 if (!ret_val) 1613 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 1614 ? e1000_rev_polarity_reversed 1615 : e1000_rev_polarity_normal; 1616 1617 return ret_val; 1618 } 1619 1620 /** 1621 * igb_check_polarity_igp - Checks the polarity. 1622 * @hw: pointer to the HW structure 1623 * 1624 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1625 * 1626 * Polarity is determined based on the PHY port status register, and the 1627 * current speed (since there is no polarity at 100Mbps). 1628 **/ 1629 static s32 igb_check_polarity_igp(struct e1000_hw *hw) 1630 { 1631 struct e1000_phy_info *phy = &hw->phy; 1632 s32 ret_val; 1633 u16 data, offset, mask; 1634 1635 /* Polarity is determined based on the speed of 1636 * our connection. 1637 */ 1638 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1639 if (ret_val) 1640 goto out; 1641 1642 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1643 IGP01E1000_PSSR_SPEED_1000MBPS) { 1644 offset = IGP01E1000_PHY_PCS_INIT_REG; 1645 mask = IGP01E1000_PHY_POLARITY_MASK; 1646 } else { 1647 /* This really only applies to 10Mbps since 1648 * there is no polarity for 100Mbps (always 0). 1649 */ 1650 offset = IGP01E1000_PHY_PORT_STATUS; 1651 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1652 } 1653 1654 ret_val = phy->ops.read_reg(hw, offset, &data); 1655 1656 if (!ret_val) 1657 phy->cable_polarity = (data & mask) 1658 ? e1000_rev_polarity_reversed 1659 : e1000_rev_polarity_normal; 1660 1661 out: 1662 return ret_val; 1663 } 1664 1665 /** 1666 * igb_wait_autoneg - Wait for auto-neg completion 1667 * @hw: pointer to the HW structure 1668 * 1669 * Waits for auto-negotiation to complete or for the auto-negotiation time 1670 * limit to expire, which ever happens first. 1671 **/ 1672 static s32 igb_wait_autoneg(struct e1000_hw *hw) 1673 { 1674 s32 ret_val = 0; 1675 u16 i, phy_status; 1676 1677 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 1678 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 1679 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1680 if (ret_val) 1681 break; 1682 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1683 if (ret_val) 1684 break; 1685 if (phy_status & MII_SR_AUTONEG_COMPLETE) 1686 break; 1687 msleep(100); 1688 } 1689 1690 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 1691 * has completed. 1692 */ 1693 return ret_val; 1694 } 1695 1696 /** 1697 * igb_phy_has_link - Polls PHY for link 1698 * @hw: pointer to the HW structure 1699 * @iterations: number of times to poll for link 1700 * @usec_interval: delay between polling attempts 1701 * @success: pointer to whether polling was successful or not 1702 * 1703 * Polls the PHY status register for link, 'iterations' number of times. 1704 **/ 1705 s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations, 1706 u32 usec_interval, bool *success) 1707 { 1708 s32 ret_val = 0; 1709 u16 i, phy_status; 1710 1711 for (i = 0; i < iterations; i++) { 1712 /* Some PHYs require the PHY_STATUS register to be read 1713 * twice due to the link bit being sticky. No harm doing 1714 * it across the board. 1715 */ 1716 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1717 if (ret_val && usec_interval > 0) { 1718 /* If the first read fails, another entity may have 1719 * ownership of the resources, wait and try again to 1720 * see if they have relinquished the resources yet. 1721 */ 1722 udelay(usec_interval); 1723 } 1724 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1725 if (ret_val) 1726 break; 1727 if (phy_status & MII_SR_LINK_STATUS) 1728 break; 1729 if (usec_interval >= 1000) 1730 mdelay(usec_interval/1000); 1731 else 1732 udelay(usec_interval); 1733 } 1734 1735 *success = (i < iterations) ? true : false; 1736 1737 return ret_val; 1738 } 1739 1740 /** 1741 * igb_get_cable_length_m88 - Determine cable length for m88 PHY 1742 * @hw: pointer to the HW structure 1743 * 1744 * Reads the PHY specific status register to retrieve the cable length 1745 * information. The cable length is determined by averaging the minimum and 1746 * maximum values to get the "average" cable length. The m88 PHY has four 1747 * possible cable length values, which are: 1748 * Register Value Cable Length 1749 * 0 < 50 meters 1750 * 1 50 - 80 meters 1751 * 2 80 - 110 meters 1752 * 3 110 - 140 meters 1753 * 4 > 140 meters 1754 **/ 1755 s32 igb_get_cable_length_m88(struct e1000_hw *hw) 1756 { 1757 struct e1000_phy_info *phy = &hw->phy; 1758 s32 ret_val; 1759 u16 phy_data, index; 1760 1761 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1762 if (ret_val) 1763 goto out; 1764 1765 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1766 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1767 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { 1768 ret_val = -E1000_ERR_PHY; 1769 goto out; 1770 } 1771 1772 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1773 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 1774 1775 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1776 1777 out: 1778 return ret_val; 1779 } 1780 1781 s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw) 1782 { 1783 struct e1000_phy_info *phy = &hw->phy; 1784 s32 ret_val; 1785 u16 phy_data, phy_data2, index, default_page, is_cm; 1786 1787 switch (hw->phy.id) { 1788 case I210_I_PHY_ID: 1789 /* Get cable length from PHY Cable Diagnostics Control Reg */ 1790 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + 1791 (I347AT4_PCDL + phy->addr), 1792 &phy_data); 1793 if (ret_val) 1794 return ret_val; 1795 1796 /* Check if the unit of cable length is meters or cm */ 1797 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + 1798 I347AT4_PCDC, &phy_data2); 1799 if (ret_val) 1800 return ret_val; 1801 1802 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 1803 1804 /* Populate the phy structure with cable length in meters */ 1805 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 1806 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 1807 phy->cable_length = phy_data / (is_cm ? 100 : 1); 1808 break; 1809 case M88E1545_E_PHY_ID: 1810 case I347AT4_E_PHY_ID: 1811 /* Remember the original page select and set it to 7 */ 1812 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 1813 &default_page); 1814 if (ret_val) 1815 goto out; 1816 1817 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07); 1818 if (ret_val) 1819 goto out; 1820 1821 /* Get cable length from PHY Cable Diagnostics Control Reg */ 1822 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr), 1823 &phy_data); 1824 if (ret_val) 1825 goto out; 1826 1827 /* Check if the unit of cable length is meters or cm */ 1828 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2); 1829 if (ret_val) 1830 goto out; 1831 1832 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 1833 1834 /* Populate the phy structure with cable length in meters */ 1835 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 1836 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 1837 phy->cable_length = phy_data / (is_cm ? 100 : 1); 1838 1839 /* Reset the page selec to its original value */ 1840 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 1841 default_page); 1842 if (ret_val) 1843 goto out; 1844 break; 1845 case M88E1112_E_PHY_ID: 1846 /* Remember the original page select and set it to 5 */ 1847 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 1848 &default_page); 1849 if (ret_val) 1850 goto out; 1851 1852 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05); 1853 if (ret_val) 1854 goto out; 1855 1856 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE, 1857 &phy_data); 1858 if (ret_val) 1859 goto out; 1860 1861 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1862 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1863 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { 1864 ret_val = -E1000_ERR_PHY; 1865 goto out; 1866 } 1867 1868 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1869 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 1870 1871 phy->cable_length = (phy->min_cable_length + 1872 phy->max_cable_length) / 2; 1873 1874 /* Reset the page select to its original value */ 1875 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 1876 default_page); 1877 if (ret_val) 1878 goto out; 1879 1880 break; 1881 default: 1882 ret_val = -E1000_ERR_PHY; 1883 goto out; 1884 } 1885 1886 out: 1887 return ret_val; 1888 } 1889 1890 /** 1891 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY 1892 * @hw: pointer to the HW structure 1893 * 1894 * The automatic gain control (agc) normalizes the amplitude of the 1895 * received signal, adjusting for the attenuation produced by the 1896 * cable. By reading the AGC registers, which represent the 1897 * combination of coarse and fine gain value, the value can be put 1898 * into a lookup table to obtain the approximate cable length 1899 * for each channel. 1900 **/ 1901 s32 igb_get_cable_length_igp_2(struct e1000_hw *hw) 1902 { 1903 struct e1000_phy_info *phy = &hw->phy; 1904 s32 ret_val = 0; 1905 u16 phy_data, i, agc_value = 0; 1906 u16 cur_agc_index, max_agc_index = 0; 1907 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 1908 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { 1909 IGP02E1000_PHY_AGC_A, 1910 IGP02E1000_PHY_AGC_B, 1911 IGP02E1000_PHY_AGC_C, 1912 IGP02E1000_PHY_AGC_D 1913 }; 1914 1915 /* Read the AGC registers for all channels */ 1916 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 1917 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 1918 if (ret_val) 1919 goto out; 1920 1921 /* Getting bits 15:9, which represent the combination of 1922 * coarse and fine gain values. The result is a number 1923 * that can be put into the lookup table to obtain the 1924 * approximate cable length. 1925 */ 1926 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 1927 IGP02E1000_AGC_LENGTH_MASK; 1928 1929 /* Array index bound check. */ 1930 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 1931 (cur_agc_index == 0)) { 1932 ret_val = -E1000_ERR_PHY; 1933 goto out; 1934 } 1935 1936 /* Remove min & max AGC values from calculation. */ 1937 if (e1000_igp_2_cable_length_table[min_agc_index] > 1938 e1000_igp_2_cable_length_table[cur_agc_index]) 1939 min_agc_index = cur_agc_index; 1940 if (e1000_igp_2_cable_length_table[max_agc_index] < 1941 e1000_igp_2_cable_length_table[cur_agc_index]) 1942 max_agc_index = cur_agc_index; 1943 1944 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 1945 } 1946 1947 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 1948 e1000_igp_2_cable_length_table[max_agc_index]); 1949 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 1950 1951 /* Calculate cable length with the error range of +/- 10 meters. */ 1952 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 1953 (agc_value - IGP02E1000_AGC_RANGE) : 0; 1954 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 1955 1956 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1957 1958 out: 1959 return ret_val; 1960 } 1961 1962 /** 1963 * igb_get_phy_info_m88 - Retrieve PHY information 1964 * @hw: pointer to the HW structure 1965 * 1966 * Valid for only copper links. Read the PHY status register (sticky read) 1967 * to verify that link is up. Read the PHY special control register to 1968 * determine the polarity and 10base-T extended distance. Read the PHY 1969 * special status register to determine MDI/MDIx and current speed. If 1970 * speed is 1000, then determine cable length, local and remote receiver. 1971 **/ 1972 s32 igb_get_phy_info_m88(struct e1000_hw *hw) 1973 { 1974 struct e1000_phy_info *phy = &hw->phy; 1975 s32 ret_val; 1976 u16 phy_data; 1977 bool link; 1978 1979 if (phy->media_type != e1000_media_type_copper) { 1980 hw_dbg("Phy info is only valid for copper media\n"); 1981 ret_val = -E1000_ERR_CONFIG; 1982 goto out; 1983 } 1984 1985 ret_val = igb_phy_has_link(hw, 1, 0, &link); 1986 if (ret_val) 1987 goto out; 1988 1989 if (!link) { 1990 hw_dbg("Phy info is only valid if link is up\n"); 1991 ret_val = -E1000_ERR_CONFIG; 1992 goto out; 1993 } 1994 1995 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1996 if (ret_val) 1997 goto out; 1998 1999 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 2000 ? true : false; 2001 2002 ret_val = igb_check_polarity_m88(hw); 2003 if (ret_val) 2004 goto out; 2005 2006 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2007 if (ret_val) 2008 goto out; 2009 2010 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false; 2011 2012 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 2013 ret_val = phy->ops.get_cable_length(hw); 2014 if (ret_val) 2015 goto out; 2016 2017 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 2018 if (ret_val) 2019 goto out; 2020 2021 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 2022 ? e1000_1000t_rx_status_ok 2023 : e1000_1000t_rx_status_not_ok; 2024 2025 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 2026 ? e1000_1000t_rx_status_ok 2027 : e1000_1000t_rx_status_not_ok; 2028 } else { 2029 /* Set values to "undefined" */ 2030 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2031 phy->local_rx = e1000_1000t_rx_status_undefined; 2032 phy->remote_rx = e1000_1000t_rx_status_undefined; 2033 } 2034 2035 out: 2036 return ret_val; 2037 } 2038 2039 /** 2040 * igb_get_phy_info_igp - Retrieve igp PHY information 2041 * @hw: pointer to the HW structure 2042 * 2043 * Read PHY status to determine if link is up. If link is up, then 2044 * set/determine 10base-T extended distance and polarity correction. Read 2045 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2046 * determine on the cable length, local and remote receiver. 2047 **/ 2048 s32 igb_get_phy_info_igp(struct e1000_hw *hw) 2049 { 2050 struct e1000_phy_info *phy = &hw->phy; 2051 s32 ret_val; 2052 u16 data; 2053 bool link; 2054 2055 ret_val = igb_phy_has_link(hw, 1, 0, &link); 2056 if (ret_val) 2057 goto out; 2058 2059 if (!link) { 2060 hw_dbg("Phy info is only valid if link is up\n"); 2061 ret_val = -E1000_ERR_CONFIG; 2062 goto out; 2063 } 2064 2065 phy->polarity_correction = true; 2066 2067 ret_val = igb_check_polarity_igp(hw); 2068 if (ret_val) 2069 goto out; 2070 2071 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2072 if (ret_val) 2073 goto out; 2074 2075 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false; 2076 2077 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2078 IGP01E1000_PSSR_SPEED_1000MBPS) { 2079 ret_val = phy->ops.get_cable_length(hw); 2080 if (ret_val) 2081 goto out; 2082 2083 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2084 if (ret_val) 2085 goto out; 2086 2087 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2088 ? e1000_1000t_rx_status_ok 2089 : e1000_1000t_rx_status_not_ok; 2090 2091 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2092 ? e1000_1000t_rx_status_ok 2093 : e1000_1000t_rx_status_not_ok; 2094 } else { 2095 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2096 phy->local_rx = e1000_1000t_rx_status_undefined; 2097 phy->remote_rx = e1000_1000t_rx_status_undefined; 2098 } 2099 2100 out: 2101 return ret_val; 2102 } 2103 2104 /** 2105 * igb_phy_sw_reset - PHY software reset 2106 * @hw: pointer to the HW structure 2107 * 2108 * Does a software reset of the PHY by reading the PHY control register and 2109 * setting/write the control register reset bit to the PHY. 2110 **/ 2111 s32 igb_phy_sw_reset(struct e1000_hw *hw) 2112 { 2113 s32 ret_val = 0; 2114 u16 phy_ctrl; 2115 2116 if (!(hw->phy.ops.read_reg)) 2117 goto out; 2118 2119 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 2120 if (ret_val) 2121 goto out; 2122 2123 phy_ctrl |= MII_CR_RESET; 2124 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 2125 if (ret_val) 2126 goto out; 2127 2128 udelay(1); 2129 2130 out: 2131 return ret_val; 2132 } 2133 2134 /** 2135 * igb_phy_hw_reset - PHY hardware reset 2136 * @hw: pointer to the HW structure 2137 * 2138 * Verify the reset block is not blocking us from resetting. Acquire 2139 * semaphore (if necessary) and read/set/write the device control reset 2140 * bit in the PHY. Wait the appropriate delay time for the device to 2141 * reset and release the semaphore (if necessary). 2142 **/ 2143 s32 igb_phy_hw_reset(struct e1000_hw *hw) 2144 { 2145 struct e1000_phy_info *phy = &hw->phy; 2146 s32 ret_val; 2147 u32 ctrl; 2148 2149 ret_val = igb_check_reset_block(hw); 2150 if (ret_val) { 2151 ret_val = 0; 2152 goto out; 2153 } 2154 2155 ret_val = phy->ops.acquire(hw); 2156 if (ret_val) 2157 goto out; 2158 2159 ctrl = rd32(E1000_CTRL); 2160 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2161 wrfl(); 2162 2163 udelay(phy->reset_delay_us); 2164 2165 wr32(E1000_CTRL, ctrl); 2166 wrfl(); 2167 2168 udelay(150); 2169 2170 phy->ops.release(hw); 2171 2172 ret_val = phy->ops.get_cfg_done(hw); 2173 2174 out: 2175 return ret_val; 2176 } 2177 2178 /** 2179 * igb_phy_init_script_igp3 - Inits the IGP3 PHY 2180 * @hw: pointer to the HW structure 2181 * 2182 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2183 **/ 2184 s32 igb_phy_init_script_igp3(struct e1000_hw *hw) 2185 { 2186 hw_dbg("Running IGP 3 PHY init script\n"); 2187 2188 /* PHY init IGP 3 */ 2189 /* Enable rise/fall, 10-mode work in class-A */ 2190 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2191 /* Remove all caps from Replica path filter */ 2192 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2193 /* Bias trimming for ADC, AFE and Driver (Default) */ 2194 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2195 /* Increase Hybrid poly bias */ 2196 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2197 /* Add 4% to TX amplitude in Giga mode */ 2198 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2199 /* Disable trimming (TTT) */ 2200 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2201 /* Poly DC correction to 94.6% + 2% for all channels */ 2202 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2203 /* ABS DC correction to 95.9% */ 2204 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2205 /* BG temp curve trim */ 2206 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2207 /* Increasing ADC OPAMP stage 1 currents to max */ 2208 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2209 /* Force 1000 ( required for enabling PHY regs configuration) */ 2210 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2211 /* Set upd_freq to 6 */ 2212 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2213 /* Disable NPDFE */ 2214 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2215 /* Disable adaptive fixed FFE (Default) */ 2216 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2217 /* Enable FFE hysteresis */ 2218 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2219 /* Fixed FFE for short cable lengths */ 2220 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2221 /* Fixed FFE for medium cable lengths */ 2222 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2223 /* Fixed FFE for long cable lengths */ 2224 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2225 /* Enable Adaptive Clip Threshold */ 2226 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2227 /* AHT reset limit to 1 */ 2228 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2229 /* Set AHT master delay to 127 msec */ 2230 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2231 /* Set scan bits for AHT */ 2232 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2233 /* Set AHT Preset bits */ 2234 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2235 /* Change integ_factor of channel A to 3 */ 2236 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2237 /* Change prop_factor of channels BCD to 8 */ 2238 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2239 /* Change cg_icount + enable integbp for channels BCD */ 2240 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2241 /* Change cg_icount + enable integbp + change prop_factor_master 2242 * to 8 for channel A 2243 */ 2244 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2245 /* Disable AHT in Slave mode on channel A */ 2246 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2247 /* Enable LPLU and disable AN to 1000 in non-D0a states, 2248 * Enable SPD+B2B 2249 */ 2250 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2251 /* Enable restart AN on an1000_dis change */ 2252 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2253 /* Enable wh_fifo read clock in 10/100 modes */ 2254 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2255 /* Restart AN, Speed selection is 1000 */ 2256 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2257 2258 return 0; 2259 } 2260 2261 /** 2262 * igb_power_up_phy_copper - Restore copper link in case of PHY power down 2263 * @hw: pointer to the HW structure 2264 * 2265 * In the case of a PHY power down to save power, or to turn off link during a 2266 * driver unload, restore the link to previous settings. 2267 **/ 2268 void igb_power_up_phy_copper(struct e1000_hw *hw) 2269 { 2270 u16 mii_reg = 0; 2271 u16 power_reg = 0; 2272 2273 /* The PHY will retain its settings across a power down/up cycle */ 2274 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2275 mii_reg &= ~MII_CR_POWER_DOWN; 2276 if (hw->phy.type == e1000_phy_i210) { 2277 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); 2278 power_reg &= ~GS40G_CS_POWER_DOWN; 2279 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); 2280 } 2281 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2282 } 2283 2284 /** 2285 * igb_power_down_phy_copper - Power down copper PHY 2286 * @hw: pointer to the HW structure 2287 * 2288 * Power down PHY to save power when interface is down and wake on lan 2289 * is not enabled. 2290 **/ 2291 void igb_power_down_phy_copper(struct e1000_hw *hw) 2292 { 2293 u16 mii_reg = 0; 2294 u16 power_reg = 0; 2295 2296 /* The PHY will retain its settings across a power down/up cycle */ 2297 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2298 mii_reg |= MII_CR_POWER_DOWN; 2299 2300 /* i210 Phy requires an additional bit for power up/down */ 2301 if (hw->phy.type == e1000_phy_i210) { 2302 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); 2303 power_reg |= GS40G_CS_POWER_DOWN; 2304 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); 2305 } 2306 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2307 msleep(1); 2308 } 2309 2310 /** 2311 * igb_check_polarity_82580 - Checks the polarity. 2312 * @hw: pointer to the HW structure 2313 * 2314 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2315 * 2316 * Polarity is determined based on the PHY specific status register. 2317 **/ 2318 static s32 igb_check_polarity_82580(struct e1000_hw *hw) 2319 { 2320 struct e1000_phy_info *phy = &hw->phy; 2321 s32 ret_val; 2322 u16 data; 2323 2324 2325 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); 2326 2327 if (!ret_val) 2328 phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY) 2329 ? e1000_rev_polarity_reversed 2330 : e1000_rev_polarity_normal; 2331 2332 return ret_val; 2333 } 2334 2335 /** 2336 * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY 2337 * @hw: pointer to the HW structure 2338 * 2339 * Calls the PHY setup function to force speed and duplex. Clears the 2340 * auto-crossover to force MDI manually. Waits for link and returns 2341 * successful if link up is successful, else -E1000_ERR_PHY (-2). 2342 **/ 2343 s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw) 2344 { 2345 struct e1000_phy_info *phy = &hw->phy; 2346 s32 ret_val; 2347 u16 phy_data; 2348 bool link; 2349 2350 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 2351 if (ret_val) 2352 goto out; 2353 2354 igb_phy_force_speed_duplex_setup(hw, &phy_data); 2355 2356 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 2357 if (ret_val) 2358 goto out; 2359 2360 /* Clear Auto-Crossover to force MDI manually. 82580 requires MDI 2361 * forced whenever speed and duplex are forced. 2362 */ 2363 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); 2364 if (ret_val) 2365 goto out; 2366 2367 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK; 2368 2369 ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); 2370 if (ret_val) 2371 goto out; 2372 2373 hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data); 2374 2375 udelay(1); 2376 2377 if (phy->autoneg_wait_to_complete) { 2378 hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n"); 2379 2380 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); 2381 if (ret_val) 2382 goto out; 2383 2384 if (!link) 2385 hw_dbg("Link taking longer than expected.\n"); 2386 2387 /* Try once more */ 2388 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); 2389 if (ret_val) 2390 goto out; 2391 } 2392 2393 out: 2394 return ret_val; 2395 } 2396 2397 /** 2398 * igb_get_phy_info_82580 - Retrieve I82580 PHY information 2399 * @hw: pointer to the HW structure 2400 * 2401 * Read PHY status to determine if link is up. If link is up, then 2402 * set/determine 10base-T extended distance and polarity correction. Read 2403 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2404 * determine on the cable length, local and remote receiver. 2405 **/ 2406 s32 igb_get_phy_info_82580(struct e1000_hw *hw) 2407 { 2408 struct e1000_phy_info *phy = &hw->phy; 2409 s32 ret_val; 2410 u16 data; 2411 bool link; 2412 2413 ret_val = igb_phy_has_link(hw, 1, 0, &link); 2414 if (ret_val) 2415 goto out; 2416 2417 if (!link) { 2418 hw_dbg("Phy info is only valid if link is up\n"); 2419 ret_val = -E1000_ERR_CONFIG; 2420 goto out; 2421 } 2422 2423 phy->polarity_correction = true; 2424 2425 ret_val = igb_check_polarity_82580(hw); 2426 if (ret_val) 2427 goto out; 2428 2429 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); 2430 if (ret_val) 2431 goto out; 2432 2433 phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false; 2434 2435 if ((data & I82580_PHY_STATUS2_SPEED_MASK) == 2436 I82580_PHY_STATUS2_SPEED_1000MBPS) { 2437 ret_val = hw->phy.ops.get_cable_length(hw); 2438 if (ret_val) 2439 goto out; 2440 2441 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2442 if (ret_val) 2443 goto out; 2444 2445 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2446 ? e1000_1000t_rx_status_ok 2447 : e1000_1000t_rx_status_not_ok; 2448 2449 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2450 ? e1000_1000t_rx_status_ok 2451 : e1000_1000t_rx_status_not_ok; 2452 } else { 2453 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2454 phy->local_rx = e1000_1000t_rx_status_undefined; 2455 phy->remote_rx = e1000_1000t_rx_status_undefined; 2456 } 2457 2458 out: 2459 return ret_val; 2460 } 2461 2462 /** 2463 * igb_get_cable_length_82580 - Determine cable length for 82580 PHY 2464 * @hw: pointer to the HW structure 2465 * 2466 * Reads the diagnostic status register and verifies result is valid before 2467 * placing it in the phy_cable_length field. 2468 **/ 2469 s32 igb_get_cable_length_82580(struct e1000_hw *hw) 2470 { 2471 struct e1000_phy_info *phy = &hw->phy; 2472 s32 ret_val; 2473 u16 phy_data, length; 2474 2475 ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data); 2476 if (ret_val) 2477 goto out; 2478 2479 length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >> 2480 I82580_DSTATUS_CABLE_LENGTH_SHIFT; 2481 2482 if (length == E1000_CABLE_LENGTH_UNDEFINED) 2483 ret_val = -E1000_ERR_PHY; 2484 2485 phy->cable_length = length; 2486 2487 out: 2488 return ret_val; 2489 } 2490 2491 /** 2492 * igb_write_phy_reg_gs40g - Write GS40G PHY register 2493 * @hw: pointer to the HW structure 2494 * @offset: lower half is register offset to write to 2495 * upper half is page to use. 2496 * @data: data to write at register offset 2497 * 2498 * Acquires semaphore, if necessary, then writes the data to PHY register 2499 * at the offset. Release any acquired semaphores before exiting. 2500 **/ 2501 s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) 2502 { 2503 s32 ret_val; 2504 u16 page = offset >> GS40G_PAGE_SHIFT; 2505 2506 offset = offset & GS40G_OFFSET_MASK; 2507 ret_val = hw->phy.ops.acquire(hw); 2508 if (ret_val) 2509 return ret_val; 2510 2511 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 2512 if (ret_val) 2513 goto release; 2514 ret_val = igb_write_phy_reg_mdic(hw, offset, data); 2515 2516 release: 2517 hw->phy.ops.release(hw); 2518 return ret_val; 2519 } 2520 2521 /** 2522 * igb_read_phy_reg_gs40g - Read GS40G PHY register 2523 * @hw: pointer to the HW structure 2524 * @offset: lower half is register offset to read to 2525 * upper half is page to use. 2526 * @data: data to read at register offset 2527 * 2528 * Acquires semaphore, if necessary, then reads the data in the PHY register 2529 * at the offset. Release any acquired semaphores before exiting. 2530 **/ 2531 s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) 2532 { 2533 s32 ret_val; 2534 u16 page = offset >> GS40G_PAGE_SHIFT; 2535 2536 offset = offset & GS40G_OFFSET_MASK; 2537 ret_val = hw->phy.ops.acquire(hw); 2538 if (ret_val) 2539 return ret_val; 2540 2541 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 2542 if (ret_val) 2543 goto release; 2544 ret_val = igb_read_phy_reg_mdic(hw, offset, data); 2545 2546 release: 2547 hw->phy.ops.release(hw); 2548 return ret_val; 2549 } 2550 2551 /** 2552 * igb_set_master_slave_mode - Setup PHY for Master/slave mode 2553 * @hw: pointer to the HW structure 2554 * 2555 * Sets up Master/slave mode 2556 **/ 2557 static s32 igb_set_master_slave_mode(struct e1000_hw *hw) 2558 { 2559 s32 ret_val; 2560 u16 phy_data; 2561 2562 /* Resolve Master/Slave mode */ 2563 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data); 2564 if (ret_val) 2565 return ret_val; 2566 2567 /* load defaults for future use */ 2568 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ? 2569 ((phy_data & CR_1000T_MS_VALUE) ? 2570 e1000_ms_force_master : 2571 e1000_ms_force_slave) : e1000_ms_auto; 2572 2573 switch (hw->phy.ms_type) { 2574 case e1000_ms_force_master: 2575 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2576 break; 2577 case e1000_ms_force_slave: 2578 phy_data |= CR_1000T_MS_ENABLE; 2579 phy_data &= ~(CR_1000T_MS_VALUE); 2580 break; 2581 case e1000_ms_auto: 2582 phy_data &= ~CR_1000T_MS_ENABLE; 2583 /* fall-through */ 2584 default: 2585 break; 2586 } 2587 2588 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data); 2589 } 2590