1 /******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #include <linux/if_ether.h> 29 #include <linux/delay.h> 30 31 #include "e1000_mac.h" 32 #include "e1000_phy.h" 33 34 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw); 35 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, 36 u16 *phy_ctrl); 37 static s32 igb_wait_autoneg(struct e1000_hw *hw); 38 static s32 igb_set_master_slave_mode(struct e1000_hw *hw); 39 40 /* Cable length tables */ 41 static const u16 e1000_m88_cable_length_table[] = { 42 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 43 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 44 (sizeof(e1000_m88_cable_length_table) / \ 45 sizeof(e1000_m88_cable_length_table[0])) 46 47 static const u16 e1000_igp_2_cable_length_table[] = { 48 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 49 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 50 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 51 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 52 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 53 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 54 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 55 104, 109, 114, 118, 121, 124}; 56 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 57 (sizeof(e1000_igp_2_cable_length_table) / \ 58 sizeof(e1000_igp_2_cable_length_table[0])) 59 60 /** 61 * igb_check_reset_block - Check if PHY reset is blocked 62 * @hw: pointer to the HW structure 63 * 64 * Read the PHY management control register and check whether a PHY reset 65 * is blocked. If a reset is not blocked return 0, otherwise 66 * return E1000_BLK_PHY_RESET (12). 67 **/ 68 s32 igb_check_reset_block(struct e1000_hw *hw) 69 { 70 u32 manc; 71 72 manc = rd32(E1000_MANC); 73 74 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0; 75 } 76 77 /** 78 * igb_get_phy_id - Retrieve the PHY ID and revision 79 * @hw: pointer to the HW structure 80 * 81 * Reads the PHY registers and stores the PHY ID and possibly the PHY 82 * revision in the hardware structure. 83 **/ 84 s32 igb_get_phy_id(struct e1000_hw *hw) 85 { 86 struct e1000_phy_info *phy = &hw->phy; 87 s32 ret_val = 0; 88 u16 phy_id; 89 90 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 91 if (ret_val) 92 goto out; 93 94 phy->id = (u32)(phy_id << 16); 95 udelay(20); 96 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 97 if (ret_val) 98 goto out; 99 100 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 101 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 102 103 out: 104 return ret_val; 105 } 106 107 /** 108 * igb_phy_reset_dsp - Reset PHY DSP 109 * @hw: pointer to the HW structure 110 * 111 * Reset the digital signal processor. 112 **/ 113 static s32 igb_phy_reset_dsp(struct e1000_hw *hw) 114 { 115 s32 ret_val = 0; 116 117 if (!(hw->phy.ops.write_reg)) 118 goto out; 119 120 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 121 if (ret_val) 122 goto out; 123 124 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 125 126 out: 127 return ret_val; 128 } 129 130 /** 131 * igb_read_phy_reg_mdic - Read MDI control register 132 * @hw: pointer to the HW structure 133 * @offset: register offset to be read 134 * @data: pointer to the read data 135 * 136 * Reads the MDI control regsiter in the PHY at offset and stores the 137 * information read to data. 138 **/ 139 s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 140 { 141 struct e1000_phy_info *phy = &hw->phy; 142 u32 i, mdic = 0; 143 s32 ret_val = 0; 144 145 if (offset > MAX_PHY_REG_ADDRESS) { 146 hw_dbg("PHY Address %d is out of range\n", offset); 147 ret_val = -E1000_ERR_PARAM; 148 goto out; 149 } 150 151 /* Set up Op-code, Phy Address, and register offset in the MDI 152 * Control register. The MAC will take care of interfacing with the 153 * PHY to retrieve the desired data. 154 */ 155 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 156 (phy->addr << E1000_MDIC_PHY_SHIFT) | 157 (E1000_MDIC_OP_READ)); 158 159 wr32(E1000_MDIC, mdic); 160 161 /* Poll the ready bit to see if the MDI read completed 162 * Increasing the time out as testing showed failures with 163 * the lower time out 164 */ 165 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 166 udelay(50); 167 mdic = rd32(E1000_MDIC); 168 if (mdic & E1000_MDIC_READY) 169 break; 170 } 171 if (!(mdic & E1000_MDIC_READY)) { 172 hw_dbg("MDI Read did not complete\n"); 173 ret_val = -E1000_ERR_PHY; 174 goto out; 175 } 176 if (mdic & E1000_MDIC_ERROR) { 177 hw_dbg("MDI Error\n"); 178 ret_val = -E1000_ERR_PHY; 179 goto out; 180 } 181 *data = (u16) mdic; 182 183 out: 184 return ret_val; 185 } 186 187 /** 188 * igb_write_phy_reg_mdic - Write MDI control register 189 * @hw: pointer to the HW structure 190 * @offset: register offset to write to 191 * @data: data to write to register at offset 192 * 193 * Writes data to MDI control register in the PHY at offset. 194 **/ 195 s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 196 { 197 struct e1000_phy_info *phy = &hw->phy; 198 u32 i, mdic = 0; 199 s32 ret_val = 0; 200 201 if (offset > MAX_PHY_REG_ADDRESS) { 202 hw_dbg("PHY Address %d is out of range\n", offset); 203 ret_val = -E1000_ERR_PARAM; 204 goto out; 205 } 206 207 /* Set up Op-code, Phy Address, and register offset in the MDI 208 * Control register. The MAC will take care of interfacing with the 209 * PHY to retrieve the desired data. 210 */ 211 mdic = (((u32)data) | 212 (offset << E1000_MDIC_REG_SHIFT) | 213 (phy->addr << E1000_MDIC_PHY_SHIFT) | 214 (E1000_MDIC_OP_WRITE)); 215 216 wr32(E1000_MDIC, mdic); 217 218 /* Poll the ready bit to see if the MDI read completed 219 * Increasing the time out as testing showed failures with 220 * the lower time out 221 */ 222 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 223 udelay(50); 224 mdic = rd32(E1000_MDIC); 225 if (mdic & E1000_MDIC_READY) 226 break; 227 } 228 if (!(mdic & E1000_MDIC_READY)) { 229 hw_dbg("MDI Write did not complete\n"); 230 ret_val = -E1000_ERR_PHY; 231 goto out; 232 } 233 if (mdic & E1000_MDIC_ERROR) { 234 hw_dbg("MDI Error\n"); 235 ret_val = -E1000_ERR_PHY; 236 goto out; 237 } 238 239 out: 240 return ret_val; 241 } 242 243 /** 244 * igb_read_phy_reg_i2c - Read PHY register using i2c 245 * @hw: pointer to the HW structure 246 * @offset: register offset to be read 247 * @data: pointer to the read data 248 * 249 * Reads the PHY register at offset using the i2c interface and stores the 250 * retrieved information in data. 251 **/ 252 s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) 253 { 254 struct e1000_phy_info *phy = &hw->phy; 255 u32 i, i2ccmd = 0; 256 257 /* Set up Op-code, Phy Address, and register address in the I2CCMD 258 * register. The MAC will take care of interfacing with the 259 * PHY to retrieve the desired data. 260 */ 261 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 262 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 263 (E1000_I2CCMD_OPCODE_READ)); 264 265 wr32(E1000_I2CCMD, i2ccmd); 266 267 /* Poll the ready bit to see if the I2C read completed */ 268 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 269 udelay(50); 270 i2ccmd = rd32(E1000_I2CCMD); 271 if (i2ccmd & E1000_I2CCMD_READY) 272 break; 273 } 274 if (!(i2ccmd & E1000_I2CCMD_READY)) { 275 hw_dbg("I2CCMD Read did not complete\n"); 276 return -E1000_ERR_PHY; 277 } 278 if (i2ccmd & E1000_I2CCMD_ERROR) { 279 hw_dbg("I2CCMD Error bit set\n"); 280 return -E1000_ERR_PHY; 281 } 282 283 /* Need to byte-swap the 16-bit value. */ 284 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 285 286 return 0; 287 } 288 289 /** 290 * igb_write_phy_reg_i2c - Write PHY register using i2c 291 * @hw: pointer to the HW structure 292 * @offset: register offset to write to 293 * @data: data to write at register offset 294 * 295 * Writes the data to PHY register at the offset using the i2c interface. 296 **/ 297 s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) 298 { 299 struct e1000_phy_info *phy = &hw->phy; 300 u32 i, i2ccmd = 0; 301 u16 phy_data_swapped; 302 303 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/ 304 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) { 305 hw_dbg("PHY I2C Address %d is out of range.\n", 306 hw->phy.addr); 307 return -E1000_ERR_CONFIG; 308 } 309 310 /* Swap the data bytes for the I2C interface */ 311 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 312 313 /* Set up Op-code, Phy Address, and register address in the I2CCMD 314 * register. The MAC will take care of interfacing with the 315 * PHY to retrieve the desired data. 316 */ 317 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 318 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 319 E1000_I2CCMD_OPCODE_WRITE | 320 phy_data_swapped); 321 322 wr32(E1000_I2CCMD, i2ccmd); 323 324 /* Poll the ready bit to see if the I2C read completed */ 325 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 326 udelay(50); 327 i2ccmd = rd32(E1000_I2CCMD); 328 if (i2ccmd & E1000_I2CCMD_READY) 329 break; 330 } 331 if (!(i2ccmd & E1000_I2CCMD_READY)) { 332 hw_dbg("I2CCMD Write did not complete\n"); 333 return -E1000_ERR_PHY; 334 } 335 if (i2ccmd & E1000_I2CCMD_ERROR) { 336 hw_dbg("I2CCMD Error bit set\n"); 337 return -E1000_ERR_PHY; 338 } 339 340 return 0; 341 } 342 343 /** 344 * igb_read_sfp_data_byte - Reads SFP module data. 345 * @hw: pointer to the HW structure 346 * @offset: byte location offset to be read 347 * @data: read data buffer pointer 348 * 349 * Reads one byte from SFP module data stored 350 * in SFP resided EEPROM memory or SFP diagnostic area. 351 * Function should be called with 352 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 353 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 354 * access 355 **/ 356 s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data) 357 { 358 u32 i = 0; 359 u32 i2ccmd = 0; 360 u32 data_local = 0; 361 362 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 363 hw_dbg("I2CCMD command address exceeds upper limit\n"); 364 return -E1000_ERR_PHY; 365 } 366 367 /* Set up Op-code, EEPROM Address,in the I2CCMD 368 * register. The MAC will take care of interfacing with the 369 * EEPROM to retrieve the desired data. 370 */ 371 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 372 E1000_I2CCMD_OPCODE_READ); 373 374 wr32(E1000_I2CCMD, i2ccmd); 375 376 /* Poll the ready bit to see if the I2C read completed */ 377 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 378 udelay(50); 379 data_local = rd32(E1000_I2CCMD); 380 if (data_local & E1000_I2CCMD_READY) 381 break; 382 } 383 if (!(data_local & E1000_I2CCMD_READY)) { 384 hw_dbg("I2CCMD Read did not complete\n"); 385 return -E1000_ERR_PHY; 386 } 387 if (data_local & E1000_I2CCMD_ERROR) { 388 hw_dbg("I2CCMD Error bit set\n"); 389 return -E1000_ERR_PHY; 390 } 391 *data = (u8) data_local & 0xFF; 392 393 return 0; 394 } 395 396 /** 397 * e1000_write_sfp_data_byte - Writes SFP module data. 398 * @hw: pointer to the HW structure 399 * @offset: byte location offset to write to 400 * @data: data to write 401 * 402 * Writes one byte to SFP module data stored 403 * in SFP resided EEPROM memory or SFP diagnostic area. 404 * Function should be called with 405 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 406 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 407 * access 408 **/ 409 s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data) 410 { 411 u32 i = 0; 412 u32 i2ccmd = 0; 413 u32 data_local = 0; 414 415 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 416 hw_dbg("I2CCMD command address exceeds upper limit\n"); 417 return -E1000_ERR_PHY; 418 } 419 /* The programming interface is 16 bits wide 420 * so we need to read the whole word first 421 * then update appropriate byte lane and write 422 * the updated word back. 423 */ 424 /* Set up Op-code, EEPROM Address,in the I2CCMD 425 * register. The MAC will take care of interfacing 426 * with an EEPROM to write the data given. 427 */ 428 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 429 E1000_I2CCMD_OPCODE_READ); 430 /* Set a command to read single word */ 431 wr32(E1000_I2CCMD, i2ccmd); 432 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 433 udelay(50); 434 /* Poll the ready bit to see if lastly 435 * launched I2C operation completed 436 */ 437 i2ccmd = rd32(E1000_I2CCMD); 438 if (i2ccmd & E1000_I2CCMD_READY) { 439 /* Check if this is READ or WRITE phase */ 440 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) == 441 E1000_I2CCMD_OPCODE_READ) { 442 /* Write the selected byte 443 * lane and update whole word 444 */ 445 data_local = i2ccmd & 0xFF00; 446 data_local |= data; 447 i2ccmd = ((offset << 448 E1000_I2CCMD_REG_ADDR_SHIFT) | 449 E1000_I2CCMD_OPCODE_WRITE | data_local); 450 wr32(E1000_I2CCMD, i2ccmd); 451 } else { 452 break; 453 } 454 } 455 } 456 if (!(i2ccmd & E1000_I2CCMD_READY)) { 457 hw_dbg("I2CCMD Write did not complete\n"); 458 return -E1000_ERR_PHY; 459 } 460 if (i2ccmd & E1000_I2CCMD_ERROR) { 461 hw_dbg("I2CCMD Error bit set\n"); 462 return -E1000_ERR_PHY; 463 } 464 return 0; 465 } 466 467 /** 468 * igb_read_phy_reg_igp - Read igp PHY register 469 * @hw: pointer to the HW structure 470 * @offset: register offset to be read 471 * @data: pointer to the read data 472 * 473 * Acquires semaphore, if necessary, then reads the PHY register at offset 474 * and storing the retrieved information in data. Release any acquired 475 * semaphores before exiting. 476 **/ 477 s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 478 { 479 s32 ret_val = 0; 480 481 if (!(hw->phy.ops.acquire)) 482 goto out; 483 484 ret_val = hw->phy.ops.acquire(hw); 485 if (ret_val) 486 goto out; 487 488 if (offset > MAX_PHY_MULTI_PAGE_REG) { 489 ret_val = igb_write_phy_reg_mdic(hw, 490 IGP01E1000_PHY_PAGE_SELECT, 491 (u16)offset); 492 if (ret_val) { 493 hw->phy.ops.release(hw); 494 goto out; 495 } 496 } 497 498 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 499 data); 500 501 hw->phy.ops.release(hw); 502 503 out: 504 return ret_val; 505 } 506 507 /** 508 * igb_write_phy_reg_igp - Write igp PHY register 509 * @hw: pointer to the HW structure 510 * @offset: register offset to write to 511 * @data: data to write at register offset 512 * 513 * Acquires semaphore, if necessary, then writes the data to PHY register 514 * at the offset. Release any acquired semaphores before exiting. 515 **/ 516 s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 517 { 518 s32 ret_val = 0; 519 520 if (!(hw->phy.ops.acquire)) 521 goto out; 522 523 ret_val = hw->phy.ops.acquire(hw); 524 if (ret_val) 525 goto out; 526 527 if (offset > MAX_PHY_MULTI_PAGE_REG) { 528 ret_val = igb_write_phy_reg_mdic(hw, 529 IGP01E1000_PHY_PAGE_SELECT, 530 (u16)offset); 531 if (ret_val) { 532 hw->phy.ops.release(hw); 533 goto out; 534 } 535 } 536 537 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 538 data); 539 540 hw->phy.ops.release(hw); 541 542 out: 543 return ret_val; 544 } 545 546 /** 547 * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link 548 * @hw: pointer to the HW structure 549 * 550 * Sets up Carrier-sense on Transmit and downshift values. 551 **/ 552 s32 igb_copper_link_setup_82580(struct e1000_hw *hw) 553 { 554 struct e1000_phy_info *phy = &hw->phy; 555 s32 ret_val; 556 u16 phy_data; 557 558 if (phy->reset_disable) { 559 ret_val = 0; 560 goto out; 561 } 562 563 if (phy->type == e1000_phy_82580) { 564 ret_val = hw->phy.ops.reset(hw); 565 if (ret_val) { 566 hw_dbg("Error resetting the PHY.\n"); 567 goto out; 568 } 569 } 570 571 /* Enable CRS on TX. This must be set for half-duplex operation. */ 572 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data); 573 if (ret_val) 574 goto out; 575 576 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX; 577 578 /* Enable downshift */ 579 phy_data |= I82580_CFG_ENABLE_DOWNSHIFT; 580 581 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data); 582 if (ret_val) 583 goto out; 584 585 /* Set MDI/MDIX mode */ 586 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); 587 if (ret_val) 588 goto out; 589 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK; 590 /* Options: 591 * 0 - Auto (default) 592 * 1 - MDI mode 593 * 2 - MDI-X mode 594 */ 595 switch (hw->phy.mdix) { 596 case 1: 597 break; 598 case 2: 599 phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX; 600 break; 601 case 0: 602 default: 603 phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX; 604 break; 605 } 606 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); 607 608 out: 609 return ret_val; 610 } 611 612 /** 613 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link 614 * @hw: pointer to the HW structure 615 * 616 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 617 * and downshift values are set also. 618 **/ 619 s32 igb_copper_link_setup_m88(struct e1000_hw *hw) 620 { 621 struct e1000_phy_info *phy = &hw->phy; 622 s32 ret_val; 623 u16 phy_data; 624 625 if (phy->reset_disable) { 626 ret_val = 0; 627 goto out; 628 } 629 630 /* Enable CRS on TX. This must be set for half-duplex operation. */ 631 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 632 if (ret_val) 633 goto out; 634 635 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 636 637 /* Options: 638 * MDI/MDI-X = 0 (default) 639 * 0 - Auto for all speeds 640 * 1 - MDI mode 641 * 2 - MDI-X mode 642 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 643 */ 644 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 645 646 switch (phy->mdix) { 647 case 1: 648 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 649 break; 650 case 2: 651 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 652 break; 653 case 3: 654 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 655 break; 656 case 0: 657 default: 658 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 659 break; 660 } 661 662 /* Options: 663 * disable_polarity_correction = 0 (default) 664 * Automatic Correction for Reversed Cable Polarity 665 * 0 - Disabled 666 * 1 - Enabled 667 */ 668 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 669 if (phy->disable_polarity_correction == 1) 670 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 671 672 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 673 if (ret_val) 674 goto out; 675 676 if (phy->revision < E1000_REVISION_4) { 677 /* Force TX_CLK in the Extended PHY Specific Control Register 678 * to 25MHz clock. 679 */ 680 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 681 &phy_data); 682 if (ret_val) 683 goto out; 684 685 phy_data |= M88E1000_EPSCR_TX_CLK_25; 686 687 if ((phy->revision == E1000_REVISION_2) && 688 (phy->id == M88E1111_I_PHY_ID)) { 689 /* 82573L PHY - set the downshift counter to 5x. */ 690 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 691 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 692 } else { 693 /* Configure Master and Slave downshift values */ 694 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 695 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 696 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 697 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 698 } 699 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 700 phy_data); 701 if (ret_val) 702 goto out; 703 } 704 705 /* Commit the changes. */ 706 ret_val = igb_phy_sw_reset(hw); 707 if (ret_val) { 708 hw_dbg("Error committing the PHY changes\n"); 709 goto out; 710 } 711 if (phy->type == e1000_phy_i210) { 712 ret_val = igb_set_master_slave_mode(hw); 713 if (ret_val) 714 return ret_val; 715 } 716 717 out: 718 return ret_val; 719 } 720 721 /** 722 * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link 723 * @hw: pointer to the HW structure 724 * 725 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's. 726 * Also enables and sets the downshift parameters. 727 **/ 728 s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw) 729 { 730 struct e1000_phy_info *phy = &hw->phy; 731 s32 ret_val; 732 u16 phy_data; 733 734 if (phy->reset_disable) 735 return 0; 736 737 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 738 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 739 if (ret_val) 740 return ret_val; 741 742 /* Options: 743 * MDI/MDI-X = 0 (default) 744 * 0 - Auto for all speeds 745 * 1 - MDI mode 746 * 2 - MDI-X mode 747 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 748 */ 749 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 750 751 switch (phy->mdix) { 752 case 1: 753 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 754 break; 755 case 2: 756 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 757 break; 758 case 3: 759 /* M88E1112 does not support this mode) */ 760 if (phy->id != M88E1112_E_PHY_ID) { 761 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 762 break; 763 } 764 case 0: 765 default: 766 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 767 break; 768 } 769 770 /* Options: 771 * disable_polarity_correction = 0 (default) 772 * Automatic Correction for Reversed Cable Polarity 773 * 0 - Disabled 774 * 1 - Enabled 775 */ 776 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 777 if (phy->disable_polarity_correction == 1) 778 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 779 780 /* Enable downshift and setting it to X6 */ 781 if (phy->id == M88E1543_E_PHY_ID) { 782 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE; 783 ret_val = 784 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 785 if (ret_val) 786 return ret_val; 787 788 ret_val = igb_phy_sw_reset(hw); 789 if (ret_val) { 790 hw_dbg("Error committing the PHY changes\n"); 791 return ret_val; 792 } 793 } 794 795 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK; 796 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X; 797 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE; 798 799 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 800 if (ret_val) 801 return ret_val; 802 803 /* Commit the changes. */ 804 ret_val = igb_phy_sw_reset(hw); 805 if (ret_val) { 806 hw_dbg("Error committing the PHY changes\n"); 807 return ret_val; 808 } 809 810 return 0; 811 } 812 813 /** 814 * igb_copper_link_setup_igp - Setup igp PHY's for copper link 815 * @hw: pointer to the HW structure 816 * 817 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 818 * igp PHY's. 819 **/ 820 s32 igb_copper_link_setup_igp(struct e1000_hw *hw) 821 { 822 struct e1000_phy_info *phy = &hw->phy; 823 s32 ret_val; 824 u16 data; 825 826 if (phy->reset_disable) { 827 ret_val = 0; 828 goto out; 829 } 830 831 ret_val = phy->ops.reset(hw); 832 if (ret_val) { 833 hw_dbg("Error resetting the PHY.\n"); 834 goto out; 835 } 836 837 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid 838 * timeout issues when LFS is enabled. 839 */ 840 msleep(100); 841 842 /* The NVM settings will configure LPLU in D3 for 843 * non-IGP1 PHYs. 844 */ 845 if (phy->type == e1000_phy_igp) { 846 /* disable lplu d3 during driver init */ 847 if (phy->ops.set_d3_lplu_state) 848 ret_val = phy->ops.set_d3_lplu_state(hw, false); 849 if (ret_val) { 850 hw_dbg("Error Disabling LPLU D3\n"); 851 goto out; 852 } 853 } 854 855 /* disable lplu d0 during driver init */ 856 ret_val = phy->ops.set_d0_lplu_state(hw, false); 857 if (ret_val) { 858 hw_dbg("Error Disabling LPLU D0\n"); 859 goto out; 860 } 861 /* Configure mdi-mdix settings */ 862 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 863 if (ret_val) 864 goto out; 865 866 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 867 868 switch (phy->mdix) { 869 case 1: 870 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 871 break; 872 case 2: 873 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 874 break; 875 case 0: 876 default: 877 data |= IGP01E1000_PSCR_AUTO_MDIX; 878 break; 879 } 880 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 881 if (ret_val) 882 goto out; 883 884 /* set auto-master slave resolution settings */ 885 if (hw->mac.autoneg) { 886 /* when autonegotiation advertisement is only 1000Mbps then we 887 * should disable SmartSpeed and enable Auto MasterSlave 888 * resolution as hardware default. 889 */ 890 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 891 /* Disable SmartSpeed */ 892 ret_val = phy->ops.read_reg(hw, 893 IGP01E1000_PHY_PORT_CONFIG, 894 &data); 895 if (ret_val) 896 goto out; 897 898 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 899 ret_val = phy->ops.write_reg(hw, 900 IGP01E1000_PHY_PORT_CONFIG, 901 data); 902 if (ret_val) 903 goto out; 904 905 /* Set auto Master/Slave resolution process */ 906 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 907 if (ret_val) 908 goto out; 909 910 data &= ~CR_1000T_MS_ENABLE; 911 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 912 if (ret_val) 913 goto out; 914 } 915 916 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 917 if (ret_val) 918 goto out; 919 920 /* load defaults for future use */ 921 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 922 ((data & CR_1000T_MS_VALUE) ? 923 e1000_ms_force_master : 924 e1000_ms_force_slave) : 925 e1000_ms_auto; 926 927 switch (phy->ms_type) { 928 case e1000_ms_force_master: 929 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 930 break; 931 case e1000_ms_force_slave: 932 data |= CR_1000T_MS_ENABLE; 933 data &= ~(CR_1000T_MS_VALUE); 934 break; 935 case e1000_ms_auto: 936 data &= ~CR_1000T_MS_ENABLE; 937 default: 938 break; 939 } 940 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 941 if (ret_val) 942 goto out; 943 } 944 945 out: 946 return ret_val; 947 } 948 949 /** 950 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link 951 * @hw: pointer to the HW structure 952 * 953 * Performs initial bounds checking on autoneg advertisement parameter, then 954 * configure to advertise the full capability. Setup the PHY to autoneg 955 * and restart the negotiation process between the link partner. If 956 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 957 **/ 958 static s32 igb_copper_link_autoneg(struct e1000_hw *hw) 959 { 960 struct e1000_phy_info *phy = &hw->phy; 961 s32 ret_val; 962 u16 phy_ctrl; 963 964 /* Perform some bounds checking on the autoneg advertisement 965 * parameter. 966 */ 967 phy->autoneg_advertised &= phy->autoneg_mask; 968 969 /* If autoneg_advertised is zero, we assume it was not defaulted 970 * by the calling code so we set to advertise full capability. 971 */ 972 if (phy->autoneg_advertised == 0) 973 phy->autoneg_advertised = phy->autoneg_mask; 974 975 hw_dbg("Reconfiguring auto-neg advertisement params\n"); 976 ret_val = igb_phy_setup_autoneg(hw); 977 if (ret_val) { 978 hw_dbg("Error Setting up Auto-Negotiation\n"); 979 goto out; 980 } 981 hw_dbg("Restarting Auto-Neg\n"); 982 983 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 984 * the Auto Neg Restart bit in the PHY control register. 985 */ 986 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 987 if (ret_val) 988 goto out; 989 990 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 991 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 992 if (ret_val) 993 goto out; 994 995 /* Does the user want to wait for Auto-Neg to complete here, or 996 * check at a later time (for example, callback routine). 997 */ 998 if (phy->autoneg_wait_to_complete) { 999 ret_val = igb_wait_autoneg(hw); 1000 if (ret_val) { 1001 hw_dbg("Error while waiting for " 1002 "autoneg to complete\n"); 1003 goto out; 1004 } 1005 } 1006 1007 hw->mac.get_link_status = true; 1008 1009 out: 1010 return ret_val; 1011 } 1012 1013 /** 1014 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation 1015 * @hw: pointer to the HW structure 1016 * 1017 * Reads the MII auto-neg advertisement register and/or the 1000T control 1018 * register and if the PHY is already setup for auto-negotiation, then 1019 * return successful. Otherwise, setup advertisement and flow control to 1020 * the appropriate values for the wanted auto-negotiation. 1021 **/ 1022 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw) 1023 { 1024 struct e1000_phy_info *phy = &hw->phy; 1025 s32 ret_val; 1026 u16 mii_autoneg_adv_reg; 1027 u16 mii_1000t_ctrl_reg = 0; 1028 1029 phy->autoneg_advertised &= phy->autoneg_mask; 1030 1031 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1032 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 1033 if (ret_val) 1034 goto out; 1035 1036 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1037 /* Read the MII 1000Base-T Control Register (Address 9). */ 1038 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 1039 &mii_1000t_ctrl_reg); 1040 if (ret_val) 1041 goto out; 1042 } 1043 1044 /* Need to parse both autoneg_advertised and fc and set up 1045 * the appropriate PHY registers. First we will parse for 1046 * autoneg_advertised software override. Since we can advertise 1047 * a plethora of combinations, we need to check each bit 1048 * individually. 1049 */ 1050 1051 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 1052 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1053 * the 1000Base-T Control Register (Address 9). 1054 */ 1055 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 1056 NWAY_AR_100TX_HD_CAPS | 1057 NWAY_AR_10T_FD_CAPS | 1058 NWAY_AR_10T_HD_CAPS); 1059 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 1060 1061 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); 1062 1063 /* Do we want to advertise 10 Mb Half Duplex? */ 1064 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 1065 hw_dbg("Advertise 10mb Half duplex\n"); 1066 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1067 } 1068 1069 /* Do we want to advertise 10 Mb Full Duplex? */ 1070 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 1071 hw_dbg("Advertise 10mb Full duplex\n"); 1072 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1073 } 1074 1075 /* Do we want to advertise 100 Mb Half Duplex? */ 1076 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 1077 hw_dbg("Advertise 100mb Half duplex\n"); 1078 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1079 } 1080 1081 /* Do we want to advertise 100 Mb Full Duplex? */ 1082 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 1083 hw_dbg("Advertise 100mb Full duplex\n"); 1084 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1085 } 1086 1087 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1088 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 1089 hw_dbg("Advertise 1000mb Half duplex request denied!\n"); 1090 1091 /* Do we want to advertise 1000 Mb Full Duplex? */ 1092 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 1093 hw_dbg("Advertise 1000mb Full duplex\n"); 1094 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1095 } 1096 1097 /* Check for a software override of the flow control settings, and 1098 * setup the PHY advertisement registers accordingly. If 1099 * auto-negotiation is enabled, then software will have to set the 1100 * "PAUSE" bits to the correct value in the Auto-Negotiation 1101 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 1102 * negotiation. 1103 * 1104 * The possible values of the "fc" parameter are: 1105 * 0: Flow control is completely disabled 1106 * 1: Rx flow control is enabled (we can receive pause frames 1107 * but not send pause frames). 1108 * 2: Tx flow control is enabled (we can send pause frames 1109 * but we do not support receiving pause frames). 1110 * 3: Both Rx and TX flow control (symmetric) are enabled. 1111 * other: No software override. The flow control configuration 1112 * in the EEPROM is used. 1113 */ 1114 switch (hw->fc.current_mode) { 1115 case e1000_fc_none: 1116 /* Flow control (RX & TX) is completely disabled by a 1117 * software over-ride. 1118 */ 1119 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1120 break; 1121 case e1000_fc_rx_pause: 1122 /* RX Flow control is enabled, and TX Flow control is 1123 * disabled, by a software over-ride. 1124 * 1125 * Since there really isn't a way to advertise that we are 1126 * capable of RX Pause ONLY, we will advertise that we 1127 * support both symmetric and asymmetric RX PAUSE. Later 1128 * (in e1000_config_fc_after_link_up) we will disable the 1129 * hw's ability to send PAUSE frames. 1130 */ 1131 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1132 break; 1133 case e1000_fc_tx_pause: 1134 /* TX Flow control is enabled, and RX Flow control is 1135 * disabled, by a software over-ride. 1136 */ 1137 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1138 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1139 break; 1140 case e1000_fc_full: 1141 /* Flow control (both RX and TX) is enabled by a software 1142 * over-ride. 1143 */ 1144 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1145 break; 1146 default: 1147 hw_dbg("Flow control param set incorrectly\n"); 1148 ret_val = -E1000_ERR_CONFIG; 1149 goto out; 1150 } 1151 1152 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1153 if (ret_val) 1154 goto out; 1155 1156 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1157 1158 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1159 ret_val = phy->ops.write_reg(hw, 1160 PHY_1000T_CTRL, 1161 mii_1000t_ctrl_reg); 1162 if (ret_val) 1163 goto out; 1164 } 1165 1166 out: 1167 return ret_val; 1168 } 1169 1170 /** 1171 * igb_setup_copper_link - Configure copper link settings 1172 * @hw: pointer to the HW structure 1173 * 1174 * Calls the appropriate function to configure the link for auto-neg or forced 1175 * speed and duplex. Then we check for link, once link is established calls 1176 * to configure collision distance and flow control are called. If link is 1177 * not established, we return -E1000_ERR_PHY (-2). 1178 **/ 1179 s32 igb_setup_copper_link(struct e1000_hw *hw) 1180 { 1181 s32 ret_val; 1182 bool link; 1183 1184 if (hw->mac.autoneg) { 1185 /* Setup autoneg and flow control advertisement and perform 1186 * autonegotiation. 1187 */ 1188 ret_val = igb_copper_link_autoneg(hw); 1189 if (ret_val) 1190 goto out; 1191 } else { 1192 /* PHY will be set to 10H, 10F, 100H or 100F 1193 * depending on user settings. 1194 */ 1195 hw_dbg("Forcing Speed and Duplex\n"); 1196 ret_val = hw->phy.ops.force_speed_duplex(hw); 1197 if (ret_val) { 1198 hw_dbg("Error Forcing Speed and Duplex\n"); 1199 goto out; 1200 } 1201 } 1202 1203 /* Check link status. Wait up to 100 microseconds for link to become 1204 * valid. 1205 */ 1206 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link); 1207 if (ret_val) 1208 goto out; 1209 1210 if (link) { 1211 hw_dbg("Valid link established!!!\n"); 1212 igb_config_collision_dist(hw); 1213 ret_val = igb_config_fc_after_link_up(hw); 1214 } else { 1215 hw_dbg("Unable to establish link!!!\n"); 1216 } 1217 1218 out: 1219 return ret_val; 1220 } 1221 1222 /** 1223 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1224 * @hw: pointer to the HW structure 1225 * 1226 * Calls the PHY setup function to force speed and duplex. Clears the 1227 * auto-crossover to force MDI manually. Waits for link and returns 1228 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1229 **/ 1230 s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1231 { 1232 struct e1000_phy_info *phy = &hw->phy; 1233 s32 ret_val; 1234 u16 phy_data; 1235 bool link; 1236 1237 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1238 if (ret_val) 1239 goto out; 1240 1241 igb_phy_force_speed_duplex_setup(hw, &phy_data); 1242 1243 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1244 if (ret_val) 1245 goto out; 1246 1247 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1248 * forced whenever speed and duplex are forced. 1249 */ 1250 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1251 if (ret_val) 1252 goto out; 1253 1254 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1255 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1256 1257 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1258 if (ret_val) 1259 goto out; 1260 1261 hw_dbg("IGP PSCR: %X\n", phy_data); 1262 1263 udelay(1); 1264 1265 if (phy->autoneg_wait_to_complete) { 1266 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); 1267 1268 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link); 1269 if (ret_val) 1270 goto out; 1271 1272 if (!link) 1273 hw_dbg("Link taking longer than expected.\n"); 1274 1275 /* Try once more */ 1276 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link); 1277 if (ret_val) 1278 goto out; 1279 } 1280 1281 out: 1282 return ret_val; 1283 } 1284 1285 /** 1286 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1287 * @hw: pointer to the HW structure 1288 * 1289 * Calls the PHY setup function to force speed and duplex. Clears the 1290 * auto-crossover to force MDI manually. Resets the PHY to commit the 1291 * changes. If time expires while waiting for link up, we reset the DSP. 1292 * After reset, TX_CLK and CRS on TX must be set. Return successful upon 1293 * successful completion, else return corresponding error code. 1294 **/ 1295 s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1296 { 1297 struct e1000_phy_info *phy = &hw->phy; 1298 s32 ret_val; 1299 u16 phy_data; 1300 bool link; 1301 1302 /* I210 and I211 devices support Auto-Crossover in forced operation. */ 1303 if (phy->type != e1000_phy_i210) { 1304 /* Clear Auto-Crossover to force MDI manually. M88E1000 1305 * requires MDI forced whenever speed and duplex are forced. 1306 */ 1307 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, 1308 &phy_data); 1309 if (ret_val) 1310 goto out; 1311 1312 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1313 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 1314 phy_data); 1315 if (ret_val) 1316 goto out; 1317 1318 hw_dbg("M88E1000 PSCR: %X\n", phy_data); 1319 } 1320 1321 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1322 if (ret_val) 1323 goto out; 1324 1325 igb_phy_force_speed_duplex_setup(hw, &phy_data); 1326 1327 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1328 if (ret_val) 1329 goto out; 1330 1331 /* Reset the phy to commit changes. */ 1332 ret_val = igb_phy_sw_reset(hw); 1333 if (ret_val) 1334 goto out; 1335 1336 if (phy->autoneg_wait_to_complete) { 1337 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); 1338 1339 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); 1340 if (ret_val) 1341 goto out; 1342 1343 if (!link) { 1344 bool reset_dsp = true; 1345 1346 switch (hw->phy.id) { 1347 case I347AT4_E_PHY_ID: 1348 case M88E1112_E_PHY_ID: 1349 case I210_I_PHY_ID: 1350 reset_dsp = false; 1351 break; 1352 default: 1353 if (hw->phy.type != e1000_phy_m88) 1354 reset_dsp = false; 1355 break; 1356 } 1357 if (!reset_dsp) 1358 hw_dbg("Link taking longer than expected.\n"); 1359 else { 1360 /* We didn't get link. 1361 * Reset the DSP and cross our fingers. 1362 */ 1363 ret_val = phy->ops.write_reg(hw, 1364 M88E1000_PHY_PAGE_SELECT, 1365 0x001d); 1366 if (ret_val) 1367 goto out; 1368 ret_val = igb_phy_reset_dsp(hw); 1369 if (ret_val) 1370 goto out; 1371 } 1372 } 1373 1374 /* Try once more */ 1375 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 1376 100000, &link); 1377 if (ret_val) 1378 goto out; 1379 } 1380 1381 if (hw->phy.type != e1000_phy_m88 || 1382 hw->phy.id == I347AT4_E_PHY_ID || 1383 hw->phy.id == M88E1112_E_PHY_ID || 1384 hw->phy.id == I210_I_PHY_ID) 1385 goto out; 1386 1387 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1388 if (ret_val) 1389 goto out; 1390 1391 /* Resetting the phy means we need to re-force TX_CLK in the 1392 * Extended PHY Specific Control Register to 25MHz clock from 1393 * the reset value of 2.5MHz. 1394 */ 1395 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1396 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1397 if (ret_val) 1398 goto out; 1399 1400 /* In addition, we must re-enable CRS on Tx for both half and full 1401 * duplex. 1402 */ 1403 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1404 if (ret_val) 1405 goto out; 1406 1407 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1408 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1409 1410 out: 1411 return ret_val; 1412 } 1413 1414 /** 1415 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1416 * @hw: pointer to the HW structure 1417 * @phy_ctrl: pointer to current value of PHY_CONTROL 1418 * 1419 * Forces speed and duplex on the PHY by doing the following: disable flow 1420 * control, force speed/duplex on the MAC, disable auto speed detection, 1421 * disable auto-negotiation, configure duplex, configure speed, configure 1422 * the collision distance, write configuration to CTRL register. The 1423 * caller must write to the PHY_CONTROL register for these settings to 1424 * take affect. 1425 **/ 1426 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, 1427 u16 *phy_ctrl) 1428 { 1429 struct e1000_mac_info *mac = &hw->mac; 1430 u32 ctrl; 1431 1432 /* Turn off flow control when forcing speed/duplex */ 1433 hw->fc.current_mode = e1000_fc_none; 1434 1435 /* Force speed/duplex on the mac */ 1436 ctrl = rd32(E1000_CTRL); 1437 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1438 ctrl &= ~E1000_CTRL_SPD_SEL; 1439 1440 /* Disable Auto Speed Detection */ 1441 ctrl &= ~E1000_CTRL_ASDE; 1442 1443 /* Disable autoneg on the phy */ 1444 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1445 1446 /* Forcing Full or Half Duplex? */ 1447 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1448 ctrl &= ~E1000_CTRL_FD; 1449 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1450 hw_dbg("Half Duplex\n"); 1451 } else { 1452 ctrl |= E1000_CTRL_FD; 1453 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1454 hw_dbg("Full Duplex\n"); 1455 } 1456 1457 /* Forcing 10mb or 100mb? */ 1458 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1459 ctrl |= E1000_CTRL_SPD_100; 1460 *phy_ctrl |= MII_CR_SPEED_100; 1461 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1462 hw_dbg("Forcing 100mb\n"); 1463 } else { 1464 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1465 *phy_ctrl |= MII_CR_SPEED_10; 1466 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1467 hw_dbg("Forcing 10mb\n"); 1468 } 1469 1470 igb_config_collision_dist(hw); 1471 1472 wr32(E1000_CTRL, ctrl); 1473 } 1474 1475 /** 1476 * igb_set_d3_lplu_state - Sets low power link up state for D3 1477 * @hw: pointer to the HW structure 1478 * @active: boolean used to enable/disable lplu 1479 * 1480 * Success returns 0, Failure returns 1 1481 * 1482 * The low power link up (lplu) state is set to the power management level D3 1483 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1484 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1485 * is used during Dx states where the power conservation is most important. 1486 * During driver activity, SmartSpeed should be enabled so performance is 1487 * maintained. 1488 **/ 1489 s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active) 1490 { 1491 struct e1000_phy_info *phy = &hw->phy; 1492 s32 ret_val = 0; 1493 u16 data; 1494 1495 if (!(hw->phy.ops.read_reg)) 1496 goto out; 1497 1498 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1499 if (ret_val) 1500 goto out; 1501 1502 if (!active) { 1503 data &= ~IGP02E1000_PM_D3_LPLU; 1504 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1505 data); 1506 if (ret_val) 1507 goto out; 1508 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1509 * during Dx states where the power conservation is most 1510 * important. During driver activity we should enable 1511 * SmartSpeed, so performance is maintained. 1512 */ 1513 if (phy->smart_speed == e1000_smart_speed_on) { 1514 ret_val = phy->ops.read_reg(hw, 1515 IGP01E1000_PHY_PORT_CONFIG, 1516 &data); 1517 if (ret_val) 1518 goto out; 1519 1520 data |= IGP01E1000_PSCFR_SMART_SPEED; 1521 ret_val = phy->ops.write_reg(hw, 1522 IGP01E1000_PHY_PORT_CONFIG, 1523 data); 1524 if (ret_val) 1525 goto out; 1526 } else if (phy->smart_speed == e1000_smart_speed_off) { 1527 ret_val = phy->ops.read_reg(hw, 1528 IGP01E1000_PHY_PORT_CONFIG, 1529 &data); 1530 if (ret_val) 1531 goto out; 1532 1533 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1534 ret_val = phy->ops.write_reg(hw, 1535 IGP01E1000_PHY_PORT_CONFIG, 1536 data); 1537 if (ret_val) 1538 goto out; 1539 } 1540 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1541 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1542 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1543 data |= IGP02E1000_PM_D3_LPLU; 1544 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1545 data); 1546 if (ret_val) 1547 goto out; 1548 1549 /* When LPLU is enabled, we should disable SmartSpeed */ 1550 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1551 &data); 1552 if (ret_val) 1553 goto out; 1554 1555 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1556 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1557 data); 1558 } 1559 1560 out: 1561 return ret_val; 1562 } 1563 1564 /** 1565 * igb_check_downshift - Checks whether a downshift in speed occurred 1566 * @hw: pointer to the HW structure 1567 * 1568 * Success returns 0, Failure returns 1 1569 * 1570 * A downshift is detected by querying the PHY link health. 1571 **/ 1572 s32 igb_check_downshift(struct e1000_hw *hw) 1573 { 1574 struct e1000_phy_info *phy = &hw->phy; 1575 s32 ret_val; 1576 u16 phy_data, offset, mask; 1577 1578 switch (phy->type) { 1579 case e1000_phy_i210: 1580 case e1000_phy_m88: 1581 case e1000_phy_gg82563: 1582 offset = M88E1000_PHY_SPEC_STATUS; 1583 mask = M88E1000_PSSR_DOWNSHIFT; 1584 break; 1585 case e1000_phy_igp_2: 1586 case e1000_phy_igp: 1587 case e1000_phy_igp_3: 1588 offset = IGP01E1000_PHY_LINK_HEALTH; 1589 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1590 break; 1591 default: 1592 /* speed downshift not supported */ 1593 phy->speed_downgraded = false; 1594 ret_val = 0; 1595 goto out; 1596 } 1597 1598 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 1599 1600 if (!ret_val) 1601 phy->speed_downgraded = (phy_data & mask) ? true : false; 1602 1603 out: 1604 return ret_val; 1605 } 1606 1607 /** 1608 * igb_check_polarity_m88 - Checks the polarity. 1609 * @hw: pointer to the HW structure 1610 * 1611 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1612 * 1613 * Polarity is determined based on the PHY specific status register. 1614 **/ 1615 s32 igb_check_polarity_m88(struct e1000_hw *hw) 1616 { 1617 struct e1000_phy_info *phy = &hw->phy; 1618 s32 ret_val; 1619 u16 data; 1620 1621 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 1622 1623 if (!ret_val) 1624 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 1625 ? e1000_rev_polarity_reversed 1626 : e1000_rev_polarity_normal; 1627 1628 return ret_val; 1629 } 1630 1631 /** 1632 * igb_check_polarity_igp - Checks the polarity. 1633 * @hw: pointer to the HW structure 1634 * 1635 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1636 * 1637 * Polarity is determined based on the PHY port status register, and the 1638 * current speed (since there is no polarity at 100Mbps). 1639 **/ 1640 static s32 igb_check_polarity_igp(struct e1000_hw *hw) 1641 { 1642 struct e1000_phy_info *phy = &hw->phy; 1643 s32 ret_val; 1644 u16 data, offset, mask; 1645 1646 /* Polarity is determined based on the speed of 1647 * our connection. 1648 */ 1649 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1650 if (ret_val) 1651 goto out; 1652 1653 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1654 IGP01E1000_PSSR_SPEED_1000MBPS) { 1655 offset = IGP01E1000_PHY_PCS_INIT_REG; 1656 mask = IGP01E1000_PHY_POLARITY_MASK; 1657 } else { 1658 /* This really only applies to 10Mbps since 1659 * there is no polarity for 100Mbps (always 0). 1660 */ 1661 offset = IGP01E1000_PHY_PORT_STATUS; 1662 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1663 } 1664 1665 ret_val = phy->ops.read_reg(hw, offset, &data); 1666 1667 if (!ret_val) 1668 phy->cable_polarity = (data & mask) 1669 ? e1000_rev_polarity_reversed 1670 : e1000_rev_polarity_normal; 1671 1672 out: 1673 return ret_val; 1674 } 1675 1676 /** 1677 * igb_wait_autoneg - Wait for auto-neg completion 1678 * @hw: pointer to the HW structure 1679 * 1680 * Waits for auto-negotiation to complete or for the auto-negotiation time 1681 * limit to expire, which ever happens first. 1682 **/ 1683 static s32 igb_wait_autoneg(struct e1000_hw *hw) 1684 { 1685 s32 ret_val = 0; 1686 u16 i, phy_status; 1687 1688 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 1689 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 1690 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1691 if (ret_val) 1692 break; 1693 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1694 if (ret_val) 1695 break; 1696 if (phy_status & MII_SR_AUTONEG_COMPLETE) 1697 break; 1698 msleep(100); 1699 } 1700 1701 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 1702 * has completed. 1703 */ 1704 return ret_val; 1705 } 1706 1707 /** 1708 * igb_phy_has_link - Polls PHY for link 1709 * @hw: pointer to the HW structure 1710 * @iterations: number of times to poll for link 1711 * @usec_interval: delay between polling attempts 1712 * @success: pointer to whether polling was successful or not 1713 * 1714 * Polls the PHY status register for link, 'iterations' number of times. 1715 **/ 1716 s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations, 1717 u32 usec_interval, bool *success) 1718 { 1719 s32 ret_val = 0; 1720 u16 i, phy_status; 1721 1722 for (i = 0; i < iterations; i++) { 1723 /* Some PHYs require the PHY_STATUS register to be read 1724 * twice due to the link bit being sticky. No harm doing 1725 * it across the board. 1726 */ 1727 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1728 if (ret_val && usec_interval > 0) { 1729 /* If the first read fails, another entity may have 1730 * ownership of the resources, wait and try again to 1731 * see if they have relinquished the resources yet. 1732 */ 1733 udelay(usec_interval); 1734 } 1735 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1736 if (ret_val) 1737 break; 1738 if (phy_status & MII_SR_LINK_STATUS) 1739 break; 1740 if (usec_interval >= 1000) 1741 mdelay(usec_interval/1000); 1742 else 1743 udelay(usec_interval); 1744 } 1745 1746 *success = (i < iterations) ? true : false; 1747 1748 return ret_val; 1749 } 1750 1751 /** 1752 * igb_get_cable_length_m88 - Determine cable length for m88 PHY 1753 * @hw: pointer to the HW structure 1754 * 1755 * Reads the PHY specific status register to retrieve the cable length 1756 * information. The cable length is determined by averaging the minimum and 1757 * maximum values to get the "average" cable length. The m88 PHY has four 1758 * possible cable length values, which are: 1759 * Register Value Cable Length 1760 * 0 < 50 meters 1761 * 1 50 - 80 meters 1762 * 2 80 - 110 meters 1763 * 3 110 - 140 meters 1764 * 4 > 140 meters 1765 **/ 1766 s32 igb_get_cable_length_m88(struct e1000_hw *hw) 1767 { 1768 struct e1000_phy_info *phy = &hw->phy; 1769 s32 ret_val; 1770 u16 phy_data, index; 1771 1772 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1773 if (ret_val) 1774 goto out; 1775 1776 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1777 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1778 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { 1779 ret_val = -E1000_ERR_PHY; 1780 goto out; 1781 } 1782 1783 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1784 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 1785 1786 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1787 1788 out: 1789 return ret_val; 1790 } 1791 1792 s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw) 1793 { 1794 struct e1000_phy_info *phy = &hw->phy; 1795 s32 ret_val; 1796 u16 phy_data, phy_data2, index, default_page, is_cm; 1797 1798 switch (hw->phy.id) { 1799 case I210_I_PHY_ID: 1800 /* Get cable length from PHY Cable Diagnostics Control Reg */ 1801 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + 1802 (I347AT4_PCDL + phy->addr), 1803 &phy_data); 1804 if (ret_val) 1805 return ret_val; 1806 1807 /* Check if the unit of cable length is meters or cm */ 1808 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + 1809 I347AT4_PCDC, &phy_data2); 1810 if (ret_val) 1811 return ret_val; 1812 1813 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 1814 1815 /* Populate the phy structure with cable length in meters */ 1816 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 1817 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 1818 phy->cable_length = phy_data / (is_cm ? 100 : 1); 1819 break; 1820 case M88E1543_E_PHY_ID: 1821 case I347AT4_E_PHY_ID: 1822 /* Remember the original page select and set it to 7 */ 1823 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 1824 &default_page); 1825 if (ret_val) 1826 goto out; 1827 1828 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07); 1829 if (ret_val) 1830 goto out; 1831 1832 /* Get cable length from PHY Cable Diagnostics Control Reg */ 1833 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr), 1834 &phy_data); 1835 if (ret_val) 1836 goto out; 1837 1838 /* Check if the unit of cable length is meters or cm */ 1839 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2); 1840 if (ret_val) 1841 goto out; 1842 1843 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 1844 1845 /* Populate the phy structure with cable length in meters */ 1846 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 1847 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 1848 phy->cable_length = phy_data / (is_cm ? 100 : 1); 1849 1850 /* Reset the page selec to its original value */ 1851 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 1852 default_page); 1853 if (ret_val) 1854 goto out; 1855 break; 1856 case M88E1112_E_PHY_ID: 1857 /* Remember the original page select and set it to 5 */ 1858 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 1859 &default_page); 1860 if (ret_val) 1861 goto out; 1862 1863 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05); 1864 if (ret_val) 1865 goto out; 1866 1867 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE, 1868 &phy_data); 1869 if (ret_val) 1870 goto out; 1871 1872 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1873 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1874 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { 1875 ret_val = -E1000_ERR_PHY; 1876 goto out; 1877 } 1878 1879 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1880 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 1881 1882 phy->cable_length = (phy->min_cable_length + 1883 phy->max_cable_length) / 2; 1884 1885 /* Reset the page select to its original value */ 1886 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 1887 default_page); 1888 if (ret_val) 1889 goto out; 1890 1891 break; 1892 default: 1893 ret_val = -E1000_ERR_PHY; 1894 goto out; 1895 } 1896 1897 out: 1898 return ret_val; 1899 } 1900 1901 /** 1902 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY 1903 * @hw: pointer to the HW structure 1904 * 1905 * The automatic gain control (agc) normalizes the amplitude of the 1906 * received signal, adjusting for the attenuation produced by the 1907 * cable. By reading the AGC registers, which represent the 1908 * combination of coarse and fine gain value, the value can be put 1909 * into a lookup table to obtain the approximate cable length 1910 * for each channel. 1911 **/ 1912 s32 igb_get_cable_length_igp_2(struct e1000_hw *hw) 1913 { 1914 struct e1000_phy_info *phy = &hw->phy; 1915 s32 ret_val = 0; 1916 u16 phy_data, i, agc_value = 0; 1917 u16 cur_agc_index, max_agc_index = 0; 1918 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 1919 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { 1920 IGP02E1000_PHY_AGC_A, 1921 IGP02E1000_PHY_AGC_B, 1922 IGP02E1000_PHY_AGC_C, 1923 IGP02E1000_PHY_AGC_D 1924 }; 1925 1926 /* Read the AGC registers for all channels */ 1927 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 1928 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 1929 if (ret_val) 1930 goto out; 1931 1932 /* Getting bits 15:9, which represent the combination of 1933 * coarse and fine gain values. The result is a number 1934 * that can be put into the lookup table to obtain the 1935 * approximate cable length. 1936 */ 1937 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 1938 IGP02E1000_AGC_LENGTH_MASK; 1939 1940 /* Array index bound check. */ 1941 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 1942 (cur_agc_index == 0)) { 1943 ret_val = -E1000_ERR_PHY; 1944 goto out; 1945 } 1946 1947 /* Remove min & max AGC values from calculation. */ 1948 if (e1000_igp_2_cable_length_table[min_agc_index] > 1949 e1000_igp_2_cable_length_table[cur_agc_index]) 1950 min_agc_index = cur_agc_index; 1951 if (e1000_igp_2_cable_length_table[max_agc_index] < 1952 e1000_igp_2_cable_length_table[cur_agc_index]) 1953 max_agc_index = cur_agc_index; 1954 1955 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 1956 } 1957 1958 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 1959 e1000_igp_2_cable_length_table[max_agc_index]); 1960 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 1961 1962 /* Calculate cable length with the error range of +/- 10 meters. */ 1963 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 1964 (agc_value - IGP02E1000_AGC_RANGE) : 0; 1965 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 1966 1967 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1968 1969 out: 1970 return ret_val; 1971 } 1972 1973 /** 1974 * igb_get_phy_info_m88 - Retrieve PHY information 1975 * @hw: pointer to the HW structure 1976 * 1977 * Valid for only copper links. Read the PHY status register (sticky read) 1978 * to verify that link is up. Read the PHY special control register to 1979 * determine the polarity and 10base-T extended distance. Read the PHY 1980 * special status register to determine MDI/MDIx and current speed. If 1981 * speed is 1000, then determine cable length, local and remote receiver. 1982 **/ 1983 s32 igb_get_phy_info_m88(struct e1000_hw *hw) 1984 { 1985 struct e1000_phy_info *phy = &hw->phy; 1986 s32 ret_val; 1987 u16 phy_data; 1988 bool link; 1989 1990 if (phy->media_type != e1000_media_type_copper) { 1991 hw_dbg("Phy info is only valid for copper media\n"); 1992 ret_val = -E1000_ERR_CONFIG; 1993 goto out; 1994 } 1995 1996 ret_val = igb_phy_has_link(hw, 1, 0, &link); 1997 if (ret_val) 1998 goto out; 1999 2000 if (!link) { 2001 hw_dbg("Phy info is only valid if link is up\n"); 2002 ret_val = -E1000_ERR_CONFIG; 2003 goto out; 2004 } 2005 2006 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2007 if (ret_val) 2008 goto out; 2009 2010 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 2011 ? true : false; 2012 2013 ret_val = igb_check_polarity_m88(hw); 2014 if (ret_val) 2015 goto out; 2016 2017 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2018 if (ret_val) 2019 goto out; 2020 2021 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false; 2022 2023 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 2024 ret_val = phy->ops.get_cable_length(hw); 2025 if (ret_val) 2026 goto out; 2027 2028 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 2029 if (ret_val) 2030 goto out; 2031 2032 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 2033 ? e1000_1000t_rx_status_ok 2034 : e1000_1000t_rx_status_not_ok; 2035 2036 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 2037 ? e1000_1000t_rx_status_ok 2038 : e1000_1000t_rx_status_not_ok; 2039 } else { 2040 /* Set values to "undefined" */ 2041 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2042 phy->local_rx = e1000_1000t_rx_status_undefined; 2043 phy->remote_rx = e1000_1000t_rx_status_undefined; 2044 } 2045 2046 out: 2047 return ret_val; 2048 } 2049 2050 /** 2051 * igb_get_phy_info_igp - Retrieve igp PHY information 2052 * @hw: pointer to the HW structure 2053 * 2054 * Read PHY status to determine if link is up. If link is up, then 2055 * set/determine 10base-T extended distance and polarity correction. Read 2056 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2057 * determine on the cable length, local and remote receiver. 2058 **/ 2059 s32 igb_get_phy_info_igp(struct e1000_hw *hw) 2060 { 2061 struct e1000_phy_info *phy = &hw->phy; 2062 s32 ret_val; 2063 u16 data; 2064 bool link; 2065 2066 ret_val = igb_phy_has_link(hw, 1, 0, &link); 2067 if (ret_val) 2068 goto out; 2069 2070 if (!link) { 2071 hw_dbg("Phy info is only valid if link is up\n"); 2072 ret_val = -E1000_ERR_CONFIG; 2073 goto out; 2074 } 2075 2076 phy->polarity_correction = true; 2077 2078 ret_val = igb_check_polarity_igp(hw); 2079 if (ret_val) 2080 goto out; 2081 2082 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2083 if (ret_val) 2084 goto out; 2085 2086 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false; 2087 2088 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2089 IGP01E1000_PSSR_SPEED_1000MBPS) { 2090 ret_val = phy->ops.get_cable_length(hw); 2091 if (ret_val) 2092 goto out; 2093 2094 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2095 if (ret_val) 2096 goto out; 2097 2098 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2099 ? e1000_1000t_rx_status_ok 2100 : e1000_1000t_rx_status_not_ok; 2101 2102 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2103 ? e1000_1000t_rx_status_ok 2104 : e1000_1000t_rx_status_not_ok; 2105 } else { 2106 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2107 phy->local_rx = e1000_1000t_rx_status_undefined; 2108 phy->remote_rx = e1000_1000t_rx_status_undefined; 2109 } 2110 2111 out: 2112 return ret_val; 2113 } 2114 2115 /** 2116 * igb_phy_sw_reset - PHY software reset 2117 * @hw: pointer to the HW structure 2118 * 2119 * Does a software reset of the PHY by reading the PHY control register and 2120 * setting/write the control register reset bit to the PHY. 2121 **/ 2122 s32 igb_phy_sw_reset(struct e1000_hw *hw) 2123 { 2124 s32 ret_val = 0; 2125 u16 phy_ctrl; 2126 2127 if (!(hw->phy.ops.read_reg)) 2128 goto out; 2129 2130 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 2131 if (ret_val) 2132 goto out; 2133 2134 phy_ctrl |= MII_CR_RESET; 2135 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 2136 if (ret_val) 2137 goto out; 2138 2139 udelay(1); 2140 2141 out: 2142 return ret_val; 2143 } 2144 2145 /** 2146 * igb_phy_hw_reset - PHY hardware reset 2147 * @hw: pointer to the HW structure 2148 * 2149 * Verify the reset block is not blocking us from resetting. Acquire 2150 * semaphore (if necessary) and read/set/write the device control reset 2151 * bit in the PHY. Wait the appropriate delay time for the device to 2152 * reset and release the semaphore (if necessary). 2153 **/ 2154 s32 igb_phy_hw_reset(struct e1000_hw *hw) 2155 { 2156 struct e1000_phy_info *phy = &hw->phy; 2157 s32 ret_val; 2158 u32 ctrl; 2159 2160 ret_val = igb_check_reset_block(hw); 2161 if (ret_val) { 2162 ret_val = 0; 2163 goto out; 2164 } 2165 2166 ret_val = phy->ops.acquire(hw); 2167 if (ret_val) 2168 goto out; 2169 2170 ctrl = rd32(E1000_CTRL); 2171 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2172 wrfl(); 2173 2174 udelay(phy->reset_delay_us); 2175 2176 wr32(E1000_CTRL, ctrl); 2177 wrfl(); 2178 2179 udelay(150); 2180 2181 phy->ops.release(hw); 2182 2183 ret_val = phy->ops.get_cfg_done(hw); 2184 2185 out: 2186 return ret_val; 2187 } 2188 2189 /** 2190 * igb_phy_init_script_igp3 - Inits the IGP3 PHY 2191 * @hw: pointer to the HW structure 2192 * 2193 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2194 **/ 2195 s32 igb_phy_init_script_igp3(struct e1000_hw *hw) 2196 { 2197 hw_dbg("Running IGP 3 PHY init script\n"); 2198 2199 /* PHY init IGP 3 */ 2200 /* Enable rise/fall, 10-mode work in class-A */ 2201 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2202 /* Remove all caps from Replica path filter */ 2203 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2204 /* Bias trimming for ADC, AFE and Driver (Default) */ 2205 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2206 /* Increase Hybrid poly bias */ 2207 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2208 /* Add 4% to TX amplitude in Giga mode */ 2209 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2210 /* Disable trimming (TTT) */ 2211 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2212 /* Poly DC correction to 94.6% + 2% for all channels */ 2213 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2214 /* ABS DC correction to 95.9% */ 2215 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2216 /* BG temp curve trim */ 2217 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2218 /* Increasing ADC OPAMP stage 1 currents to max */ 2219 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2220 /* Force 1000 ( required for enabling PHY regs configuration) */ 2221 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2222 /* Set upd_freq to 6 */ 2223 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2224 /* Disable NPDFE */ 2225 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2226 /* Disable adaptive fixed FFE (Default) */ 2227 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2228 /* Enable FFE hysteresis */ 2229 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2230 /* Fixed FFE for short cable lengths */ 2231 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2232 /* Fixed FFE for medium cable lengths */ 2233 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2234 /* Fixed FFE for long cable lengths */ 2235 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2236 /* Enable Adaptive Clip Threshold */ 2237 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2238 /* AHT reset limit to 1 */ 2239 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2240 /* Set AHT master delay to 127 msec */ 2241 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2242 /* Set scan bits for AHT */ 2243 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2244 /* Set AHT Preset bits */ 2245 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2246 /* Change integ_factor of channel A to 3 */ 2247 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2248 /* Change prop_factor of channels BCD to 8 */ 2249 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2250 /* Change cg_icount + enable integbp for channels BCD */ 2251 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2252 /* Change cg_icount + enable integbp + change prop_factor_master 2253 * to 8 for channel A 2254 */ 2255 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2256 /* Disable AHT in Slave mode on channel A */ 2257 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2258 /* Enable LPLU and disable AN to 1000 in non-D0a states, 2259 * Enable SPD+B2B 2260 */ 2261 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2262 /* Enable restart AN on an1000_dis change */ 2263 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2264 /* Enable wh_fifo read clock in 10/100 modes */ 2265 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2266 /* Restart AN, Speed selection is 1000 */ 2267 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2268 2269 return 0; 2270 } 2271 2272 /** 2273 * igb_power_up_phy_copper - Restore copper link in case of PHY power down 2274 * @hw: pointer to the HW structure 2275 * 2276 * In the case of a PHY power down to save power, or to turn off link during a 2277 * driver unload, restore the link to previous settings. 2278 **/ 2279 void igb_power_up_phy_copper(struct e1000_hw *hw) 2280 { 2281 u16 mii_reg = 0; 2282 u16 power_reg = 0; 2283 2284 /* The PHY will retain its settings across a power down/up cycle */ 2285 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2286 mii_reg &= ~MII_CR_POWER_DOWN; 2287 if (hw->phy.type == e1000_phy_i210) { 2288 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); 2289 power_reg &= ~GS40G_CS_POWER_DOWN; 2290 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); 2291 } 2292 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2293 } 2294 2295 /** 2296 * igb_power_down_phy_copper - Power down copper PHY 2297 * @hw: pointer to the HW structure 2298 * 2299 * Power down PHY to save power when interface is down and wake on lan 2300 * is not enabled. 2301 **/ 2302 void igb_power_down_phy_copper(struct e1000_hw *hw) 2303 { 2304 u16 mii_reg = 0; 2305 u16 power_reg = 0; 2306 2307 /* The PHY will retain its settings across a power down/up cycle */ 2308 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2309 mii_reg |= MII_CR_POWER_DOWN; 2310 2311 /* i210 Phy requires an additional bit for power up/down */ 2312 if (hw->phy.type == e1000_phy_i210) { 2313 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); 2314 power_reg |= GS40G_CS_POWER_DOWN; 2315 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); 2316 } 2317 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2318 msleep(1); 2319 } 2320 2321 /** 2322 * igb_check_polarity_82580 - Checks the polarity. 2323 * @hw: pointer to the HW structure 2324 * 2325 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2326 * 2327 * Polarity is determined based on the PHY specific status register. 2328 **/ 2329 static s32 igb_check_polarity_82580(struct e1000_hw *hw) 2330 { 2331 struct e1000_phy_info *phy = &hw->phy; 2332 s32 ret_val; 2333 u16 data; 2334 2335 2336 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); 2337 2338 if (!ret_val) 2339 phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY) 2340 ? e1000_rev_polarity_reversed 2341 : e1000_rev_polarity_normal; 2342 2343 return ret_val; 2344 } 2345 2346 /** 2347 * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY 2348 * @hw: pointer to the HW structure 2349 * 2350 * Calls the PHY setup function to force speed and duplex. Clears the 2351 * auto-crossover to force MDI manually. Waits for link and returns 2352 * successful if link up is successful, else -E1000_ERR_PHY (-2). 2353 **/ 2354 s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw) 2355 { 2356 struct e1000_phy_info *phy = &hw->phy; 2357 s32 ret_val; 2358 u16 phy_data; 2359 bool link; 2360 2361 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 2362 if (ret_val) 2363 goto out; 2364 2365 igb_phy_force_speed_duplex_setup(hw, &phy_data); 2366 2367 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 2368 if (ret_val) 2369 goto out; 2370 2371 /* Clear Auto-Crossover to force MDI manually. 82580 requires MDI 2372 * forced whenever speed and duplex are forced. 2373 */ 2374 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); 2375 if (ret_val) 2376 goto out; 2377 2378 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK; 2379 2380 ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); 2381 if (ret_val) 2382 goto out; 2383 2384 hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data); 2385 2386 udelay(1); 2387 2388 if (phy->autoneg_wait_to_complete) { 2389 hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n"); 2390 2391 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); 2392 if (ret_val) 2393 goto out; 2394 2395 if (!link) 2396 hw_dbg("Link taking longer than expected.\n"); 2397 2398 /* Try once more */ 2399 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); 2400 if (ret_val) 2401 goto out; 2402 } 2403 2404 out: 2405 return ret_val; 2406 } 2407 2408 /** 2409 * igb_get_phy_info_82580 - Retrieve I82580 PHY information 2410 * @hw: pointer to the HW structure 2411 * 2412 * Read PHY status to determine if link is up. If link is up, then 2413 * set/determine 10base-T extended distance and polarity correction. Read 2414 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2415 * determine on the cable length, local and remote receiver. 2416 **/ 2417 s32 igb_get_phy_info_82580(struct e1000_hw *hw) 2418 { 2419 struct e1000_phy_info *phy = &hw->phy; 2420 s32 ret_val; 2421 u16 data; 2422 bool link; 2423 2424 ret_val = igb_phy_has_link(hw, 1, 0, &link); 2425 if (ret_val) 2426 goto out; 2427 2428 if (!link) { 2429 hw_dbg("Phy info is only valid if link is up\n"); 2430 ret_val = -E1000_ERR_CONFIG; 2431 goto out; 2432 } 2433 2434 phy->polarity_correction = true; 2435 2436 ret_val = igb_check_polarity_82580(hw); 2437 if (ret_val) 2438 goto out; 2439 2440 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); 2441 if (ret_val) 2442 goto out; 2443 2444 phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false; 2445 2446 if ((data & I82580_PHY_STATUS2_SPEED_MASK) == 2447 I82580_PHY_STATUS2_SPEED_1000MBPS) { 2448 ret_val = hw->phy.ops.get_cable_length(hw); 2449 if (ret_val) 2450 goto out; 2451 2452 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2453 if (ret_val) 2454 goto out; 2455 2456 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2457 ? e1000_1000t_rx_status_ok 2458 : e1000_1000t_rx_status_not_ok; 2459 2460 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2461 ? e1000_1000t_rx_status_ok 2462 : e1000_1000t_rx_status_not_ok; 2463 } else { 2464 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2465 phy->local_rx = e1000_1000t_rx_status_undefined; 2466 phy->remote_rx = e1000_1000t_rx_status_undefined; 2467 } 2468 2469 out: 2470 return ret_val; 2471 } 2472 2473 /** 2474 * igb_get_cable_length_82580 - Determine cable length for 82580 PHY 2475 * @hw: pointer to the HW structure 2476 * 2477 * Reads the diagnostic status register and verifies result is valid before 2478 * placing it in the phy_cable_length field. 2479 **/ 2480 s32 igb_get_cable_length_82580(struct e1000_hw *hw) 2481 { 2482 struct e1000_phy_info *phy = &hw->phy; 2483 s32 ret_val; 2484 u16 phy_data, length; 2485 2486 ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data); 2487 if (ret_val) 2488 goto out; 2489 2490 length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >> 2491 I82580_DSTATUS_CABLE_LENGTH_SHIFT; 2492 2493 if (length == E1000_CABLE_LENGTH_UNDEFINED) 2494 ret_val = -E1000_ERR_PHY; 2495 2496 phy->cable_length = length; 2497 2498 out: 2499 return ret_val; 2500 } 2501 2502 /** 2503 * igb_write_phy_reg_gs40g - Write GS40G PHY register 2504 * @hw: pointer to the HW structure 2505 * @offset: lower half is register offset to write to 2506 * upper half is page to use. 2507 * @data: data to write at register offset 2508 * 2509 * Acquires semaphore, if necessary, then writes the data to PHY register 2510 * at the offset. Release any acquired semaphores before exiting. 2511 **/ 2512 s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) 2513 { 2514 s32 ret_val; 2515 u16 page = offset >> GS40G_PAGE_SHIFT; 2516 2517 offset = offset & GS40G_OFFSET_MASK; 2518 ret_val = hw->phy.ops.acquire(hw); 2519 if (ret_val) 2520 return ret_val; 2521 2522 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 2523 if (ret_val) 2524 goto release; 2525 ret_val = igb_write_phy_reg_mdic(hw, offset, data); 2526 2527 release: 2528 hw->phy.ops.release(hw); 2529 return ret_val; 2530 } 2531 2532 /** 2533 * igb_read_phy_reg_gs40g - Read GS40G PHY register 2534 * @hw: pointer to the HW structure 2535 * @offset: lower half is register offset to read to 2536 * upper half is page to use. 2537 * @data: data to read at register offset 2538 * 2539 * Acquires semaphore, if necessary, then reads the data in the PHY register 2540 * at the offset. Release any acquired semaphores before exiting. 2541 **/ 2542 s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) 2543 { 2544 s32 ret_val; 2545 u16 page = offset >> GS40G_PAGE_SHIFT; 2546 2547 offset = offset & GS40G_OFFSET_MASK; 2548 ret_val = hw->phy.ops.acquire(hw); 2549 if (ret_val) 2550 return ret_val; 2551 2552 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 2553 if (ret_val) 2554 goto release; 2555 ret_val = igb_read_phy_reg_mdic(hw, offset, data); 2556 2557 release: 2558 hw->phy.ops.release(hw); 2559 return ret_val; 2560 } 2561 2562 /** 2563 * igb_set_master_slave_mode - Setup PHY for Master/slave mode 2564 * @hw: pointer to the HW structure 2565 * 2566 * Sets up Master/slave mode 2567 **/ 2568 static s32 igb_set_master_slave_mode(struct e1000_hw *hw) 2569 { 2570 s32 ret_val; 2571 u16 phy_data; 2572 2573 /* Resolve Master/Slave mode */ 2574 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data); 2575 if (ret_val) 2576 return ret_val; 2577 2578 /* load defaults for future use */ 2579 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ? 2580 ((phy_data & CR_1000T_MS_VALUE) ? 2581 e1000_ms_force_master : 2582 e1000_ms_force_slave) : e1000_ms_auto; 2583 2584 switch (hw->phy.ms_type) { 2585 case e1000_ms_force_master: 2586 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2587 break; 2588 case e1000_ms_force_slave: 2589 phy_data |= CR_1000T_MS_ENABLE; 2590 phy_data &= ~(CR_1000T_MS_VALUE); 2591 break; 2592 case e1000_ms_auto: 2593 phy_data &= ~CR_1000T_MS_ENABLE; 2594 /* fall-through */ 2595 default: 2596 break; 2597 } 2598 2599 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data); 2600 } 2601