1 /******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #include <linux/if_ether.h> 29 #include <linux/delay.h> 30 31 #include "e1000_mac.h" 32 #include "e1000_phy.h" 33 34 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw); 35 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, 36 u16 *phy_ctrl); 37 static s32 igb_wait_autoneg(struct e1000_hw *hw); 38 static s32 igb_set_master_slave_mode(struct e1000_hw *hw); 39 40 /* Cable length tables */ 41 static const u16 e1000_m88_cable_length_table[] = 42 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 43 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 44 (sizeof(e1000_m88_cable_length_table) / \ 45 sizeof(e1000_m88_cable_length_table[0])) 46 47 static const u16 e1000_igp_2_cable_length_table[] = 48 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 49 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 50 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 51 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 52 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 53 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 54 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 55 104, 109, 114, 118, 121, 124}; 56 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 57 (sizeof(e1000_igp_2_cable_length_table) / \ 58 sizeof(e1000_igp_2_cable_length_table[0])) 59 60 /** 61 * igb_check_reset_block - Check if PHY reset is blocked 62 * @hw: pointer to the HW structure 63 * 64 * Read the PHY management control register and check whether a PHY reset 65 * is blocked. If a reset is not blocked return 0, otherwise 66 * return E1000_BLK_PHY_RESET (12). 67 **/ 68 s32 igb_check_reset_block(struct e1000_hw *hw) 69 { 70 u32 manc; 71 72 manc = rd32(E1000_MANC); 73 74 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 75 E1000_BLK_PHY_RESET : 0; 76 } 77 78 /** 79 * igb_get_phy_id - Retrieve the PHY ID and revision 80 * @hw: pointer to the HW structure 81 * 82 * Reads the PHY registers and stores the PHY ID and possibly the PHY 83 * revision in the hardware structure. 84 **/ 85 s32 igb_get_phy_id(struct e1000_hw *hw) 86 { 87 struct e1000_phy_info *phy = &hw->phy; 88 s32 ret_val = 0; 89 u16 phy_id; 90 91 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 92 if (ret_val) 93 goto out; 94 95 phy->id = (u32)(phy_id << 16); 96 udelay(20); 97 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 98 if (ret_val) 99 goto out; 100 101 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 102 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 103 104 out: 105 return ret_val; 106 } 107 108 /** 109 * igb_phy_reset_dsp - Reset PHY DSP 110 * @hw: pointer to the HW structure 111 * 112 * Reset the digital signal processor. 113 **/ 114 static s32 igb_phy_reset_dsp(struct e1000_hw *hw) 115 { 116 s32 ret_val = 0; 117 118 if (!(hw->phy.ops.write_reg)) 119 goto out; 120 121 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 122 if (ret_val) 123 goto out; 124 125 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 126 127 out: 128 return ret_val; 129 } 130 131 /** 132 * igb_read_phy_reg_mdic - Read MDI control register 133 * @hw: pointer to the HW structure 134 * @offset: register offset to be read 135 * @data: pointer to the read data 136 * 137 * Reads the MDI control regsiter in the PHY at offset and stores the 138 * information read to data. 139 **/ 140 s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 141 { 142 struct e1000_phy_info *phy = &hw->phy; 143 u32 i, mdic = 0; 144 s32 ret_val = 0; 145 146 if (offset > MAX_PHY_REG_ADDRESS) { 147 hw_dbg("PHY Address %d is out of range\n", offset); 148 ret_val = -E1000_ERR_PARAM; 149 goto out; 150 } 151 152 /* 153 * Set up Op-code, Phy Address, and register offset in the MDI 154 * Control register. The MAC will take care of interfacing with the 155 * PHY to retrieve the desired data. 156 */ 157 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 158 (phy->addr << E1000_MDIC_PHY_SHIFT) | 159 (E1000_MDIC_OP_READ)); 160 161 wr32(E1000_MDIC, mdic); 162 163 /* 164 * Poll the ready bit to see if the MDI read completed 165 * Increasing the time out as testing showed failures with 166 * the lower time out 167 */ 168 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 169 udelay(50); 170 mdic = rd32(E1000_MDIC); 171 if (mdic & E1000_MDIC_READY) 172 break; 173 } 174 if (!(mdic & E1000_MDIC_READY)) { 175 hw_dbg("MDI Read did not complete\n"); 176 ret_val = -E1000_ERR_PHY; 177 goto out; 178 } 179 if (mdic & E1000_MDIC_ERROR) { 180 hw_dbg("MDI Error\n"); 181 ret_val = -E1000_ERR_PHY; 182 goto out; 183 } 184 *data = (u16) mdic; 185 186 out: 187 return ret_val; 188 } 189 190 /** 191 * igb_write_phy_reg_mdic - Write MDI control register 192 * @hw: pointer to the HW structure 193 * @offset: register offset to write to 194 * @data: data to write to register at offset 195 * 196 * Writes data to MDI control register in the PHY at offset. 197 **/ 198 s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 199 { 200 struct e1000_phy_info *phy = &hw->phy; 201 u32 i, mdic = 0; 202 s32 ret_val = 0; 203 204 if (offset > MAX_PHY_REG_ADDRESS) { 205 hw_dbg("PHY Address %d is out of range\n", offset); 206 ret_val = -E1000_ERR_PARAM; 207 goto out; 208 } 209 210 /* 211 * Set up Op-code, Phy Address, and register offset in the MDI 212 * Control register. The MAC will take care of interfacing with the 213 * PHY to retrieve the desired data. 214 */ 215 mdic = (((u32)data) | 216 (offset << E1000_MDIC_REG_SHIFT) | 217 (phy->addr << E1000_MDIC_PHY_SHIFT) | 218 (E1000_MDIC_OP_WRITE)); 219 220 wr32(E1000_MDIC, mdic); 221 222 /* 223 * Poll the ready bit to see if the MDI read completed 224 * Increasing the time out as testing showed failures with 225 * the lower time out 226 */ 227 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 228 udelay(50); 229 mdic = rd32(E1000_MDIC); 230 if (mdic & E1000_MDIC_READY) 231 break; 232 } 233 if (!(mdic & E1000_MDIC_READY)) { 234 hw_dbg("MDI Write did not complete\n"); 235 ret_val = -E1000_ERR_PHY; 236 goto out; 237 } 238 if (mdic & E1000_MDIC_ERROR) { 239 hw_dbg("MDI Error\n"); 240 ret_val = -E1000_ERR_PHY; 241 goto out; 242 } 243 244 out: 245 return ret_val; 246 } 247 248 /** 249 * igb_read_phy_reg_i2c - Read PHY register using i2c 250 * @hw: pointer to the HW structure 251 * @offset: register offset to be read 252 * @data: pointer to the read data 253 * 254 * Reads the PHY register at offset using the i2c interface and stores the 255 * retrieved information in data. 256 **/ 257 s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) 258 { 259 struct e1000_phy_info *phy = &hw->phy; 260 u32 i, i2ccmd = 0; 261 262 263 /* 264 * Set up Op-code, Phy Address, and register address in the I2CCMD 265 * register. The MAC will take care of interfacing with the 266 * PHY to retrieve the desired data. 267 */ 268 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 269 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 270 (E1000_I2CCMD_OPCODE_READ)); 271 272 wr32(E1000_I2CCMD, i2ccmd); 273 274 /* Poll the ready bit to see if the I2C read completed */ 275 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 276 udelay(50); 277 i2ccmd = rd32(E1000_I2CCMD); 278 if (i2ccmd & E1000_I2CCMD_READY) 279 break; 280 } 281 if (!(i2ccmd & E1000_I2CCMD_READY)) { 282 hw_dbg("I2CCMD Read did not complete\n"); 283 return -E1000_ERR_PHY; 284 } 285 if (i2ccmd & E1000_I2CCMD_ERROR) { 286 hw_dbg("I2CCMD Error bit set\n"); 287 return -E1000_ERR_PHY; 288 } 289 290 /* Need to byte-swap the 16-bit value. */ 291 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 292 293 return 0; 294 } 295 296 /** 297 * igb_write_phy_reg_i2c - Write PHY register using i2c 298 * @hw: pointer to the HW structure 299 * @offset: register offset to write to 300 * @data: data to write at register offset 301 * 302 * Writes the data to PHY register at the offset using the i2c interface. 303 **/ 304 s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) 305 { 306 struct e1000_phy_info *phy = &hw->phy; 307 u32 i, i2ccmd = 0; 308 u16 phy_data_swapped; 309 310 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/ 311 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) { 312 hw_dbg("PHY I2C Address %d is out of range.\n", 313 hw->phy.addr); 314 return -E1000_ERR_CONFIG; 315 } 316 317 /* Swap the data bytes for the I2C interface */ 318 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 319 320 /* 321 * Set up Op-code, Phy Address, and register address in the I2CCMD 322 * register. The MAC will take care of interfacing with the 323 * PHY to retrieve the desired data. 324 */ 325 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 326 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 327 E1000_I2CCMD_OPCODE_WRITE | 328 phy_data_swapped); 329 330 wr32(E1000_I2CCMD, i2ccmd); 331 332 /* Poll the ready bit to see if the I2C read completed */ 333 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 334 udelay(50); 335 i2ccmd = rd32(E1000_I2CCMD); 336 if (i2ccmd & E1000_I2CCMD_READY) 337 break; 338 } 339 if (!(i2ccmd & E1000_I2CCMD_READY)) { 340 hw_dbg("I2CCMD Write did not complete\n"); 341 return -E1000_ERR_PHY; 342 } 343 if (i2ccmd & E1000_I2CCMD_ERROR) { 344 hw_dbg("I2CCMD Error bit set\n"); 345 return -E1000_ERR_PHY; 346 } 347 348 return 0; 349 } 350 351 /** 352 * igb_read_phy_reg_igp - Read igp PHY register 353 * @hw: pointer to the HW structure 354 * @offset: register offset to be read 355 * @data: pointer to the read data 356 * 357 * Acquires semaphore, if necessary, then reads the PHY register at offset 358 * and storing the retrieved information in data. Release any acquired 359 * semaphores before exiting. 360 **/ 361 s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 362 { 363 s32 ret_val = 0; 364 365 if (!(hw->phy.ops.acquire)) 366 goto out; 367 368 ret_val = hw->phy.ops.acquire(hw); 369 if (ret_val) 370 goto out; 371 372 if (offset > MAX_PHY_MULTI_PAGE_REG) { 373 ret_val = igb_write_phy_reg_mdic(hw, 374 IGP01E1000_PHY_PAGE_SELECT, 375 (u16)offset); 376 if (ret_val) { 377 hw->phy.ops.release(hw); 378 goto out; 379 } 380 } 381 382 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 383 data); 384 385 hw->phy.ops.release(hw); 386 387 out: 388 return ret_val; 389 } 390 391 /** 392 * igb_write_phy_reg_igp - Write igp PHY register 393 * @hw: pointer to the HW structure 394 * @offset: register offset to write to 395 * @data: data to write at register offset 396 * 397 * Acquires semaphore, if necessary, then writes the data to PHY register 398 * at the offset. Release any acquired semaphores before exiting. 399 **/ 400 s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 401 { 402 s32 ret_val = 0; 403 404 if (!(hw->phy.ops.acquire)) 405 goto out; 406 407 ret_val = hw->phy.ops.acquire(hw); 408 if (ret_val) 409 goto out; 410 411 if (offset > MAX_PHY_MULTI_PAGE_REG) { 412 ret_val = igb_write_phy_reg_mdic(hw, 413 IGP01E1000_PHY_PAGE_SELECT, 414 (u16)offset); 415 if (ret_val) { 416 hw->phy.ops.release(hw); 417 goto out; 418 } 419 } 420 421 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 422 data); 423 424 hw->phy.ops.release(hw); 425 426 out: 427 return ret_val; 428 } 429 430 /** 431 * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link 432 * @hw: pointer to the HW structure 433 * 434 * Sets up Carrier-sense on Transmit and downshift values. 435 **/ 436 s32 igb_copper_link_setup_82580(struct e1000_hw *hw) 437 { 438 struct e1000_phy_info *phy = &hw->phy; 439 s32 ret_val; 440 u16 phy_data; 441 442 443 if (phy->reset_disable) { 444 ret_val = 0; 445 goto out; 446 } 447 448 if (phy->type == e1000_phy_82580) { 449 ret_val = hw->phy.ops.reset(hw); 450 if (ret_val) { 451 hw_dbg("Error resetting the PHY.\n"); 452 goto out; 453 } 454 } 455 456 /* Enable CRS on TX. This must be set for half-duplex operation. */ 457 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data); 458 if (ret_val) 459 goto out; 460 461 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX; 462 463 /* Enable downshift */ 464 phy_data |= I82580_CFG_ENABLE_DOWNSHIFT; 465 466 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data); 467 468 out: 469 return ret_val; 470 } 471 472 /** 473 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link 474 * @hw: pointer to the HW structure 475 * 476 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 477 * and downshift values are set also. 478 **/ 479 s32 igb_copper_link_setup_m88(struct e1000_hw *hw) 480 { 481 struct e1000_phy_info *phy = &hw->phy; 482 s32 ret_val; 483 u16 phy_data; 484 485 if (phy->reset_disable) { 486 ret_val = 0; 487 goto out; 488 } 489 490 /* Enable CRS on TX. This must be set for half-duplex operation. */ 491 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 492 if (ret_val) 493 goto out; 494 495 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 496 497 /* 498 * Options: 499 * MDI/MDI-X = 0 (default) 500 * 0 - Auto for all speeds 501 * 1 - MDI mode 502 * 2 - MDI-X mode 503 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 504 */ 505 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 506 507 switch (phy->mdix) { 508 case 1: 509 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 510 break; 511 case 2: 512 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 513 break; 514 case 3: 515 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 516 break; 517 case 0: 518 default: 519 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 520 break; 521 } 522 523 /* 524 * Options: 525 * disable_polarity_correction = 0 (default) 526 * Automatic Correction for Reversed Cable Polarity 527 * 0 - Disabled 528 * 1 - Enabled 529 */ 530 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 531 if (phy->disable_polarity_correction == 1) 532 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 533 534 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 535 if (ret_val) 536 goto out; 537 538 if (phy->revision < E1000_REVISION_4) { 539 /* 540 * Force TX_CLK in the Extended PHY Specific Control Register 541 * to 25MHz clock. 542 */ 543 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 544 &phy_data); 545 if (ret_val) 546 goto out; 547 548 phy_data |= M88E1000_EPSCR_TX_CLK_25; 549 550 if ((phy->revision == E1000_REVISION_2) && 551 (phy->id == M88E1111_I_PHY_ID)) { 552 /* 82573L PHY - set the downshift counter to 5x. */ 553 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 554 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 555 } else { 556 /* Configure Master and Slave downshift values */ 557 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 558 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 559 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 560 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 561 } 562 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 563 phy_data); 564 if (ret_val) 565 goto out; 566 } 567 568 /* Commit the changes. */ 569 ret_val = igb_phy_sw_reset(hw); 570 if (ret_val) { 571 hw_dbg("Error committing the PHY changes\n"); 572 goto out; 573 } 574 if (phy->type == e1000_phy_i210) { 575 ret_val = igb_set_master_slave_mode(hw); 576 if (ret_val) 577 return ret_val; 578 } 579 580 out: 581 return ret_val; 582 } 583 584 /** 585 * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link 586 * @hw: pointer to the HW structure 587 * 588 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's. 589 * Also enables and sets the downshift parameters. 590 **/ 591 s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw) 592 { 593 struct e1000_phy_info *phy = &hw->phy; 594 s32 ret_val; 595 u16 phy_data; 596 597 if (phy->reset_disable) { 598 ret_val = 0; 599 goto out; 600 } 601 602 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 603 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 604 if (ret_val) 605 goto out; 606 607 /* 608 * Options: 609 * MDI/MDI-X = 0 (default) 610 * 0 - Auto for all speeds 611 * 1 - MDI mode 612 * 2 - MDI-X mode 613 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 614 */ 615 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 616 617 switch (phy->mdix) { 618 case 1: 619 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 620 break; 621 case 2: 622 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 623 break; 624 case 3: 625 /* M88E1112 does not support this mode) */ 626 if (phy->id != M88E1112_E_PHY_ID) { 627 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 628 break; 629 } 630 case 0: 631 default: 632 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 633 break; 634 } 635 636 /* 637 * Options: 638 * disable_polarity_correction = 0 (default) 639 * Automatic Correction for Reversed Cable Polarity 640 * 0 - Disabled 641 * 1 - Enabled 642 */ 643 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 644 if (phy->disable_polarity_correction == 1) 645 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 646 647 /* Enable downshift and setting it to X6 */ 648 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK; 649 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X; 650 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE; 651 652 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 653 if (ret_val) 654 goto out; 655 656 /* Commit the changes. */ 657 ret_val = igb_phy_sw_reset(hw); 658 if (ret_val) { 659 hw_dbg("Error committing the PHY changes\n"); 660 goto out; 661 } 662 663 out: 664 return ret_val; 665 } 666 667 /** 668 * igb_copper_link_setup_igp - Setup igp PHY's for copper link 669 * @hw: pointer to the HW structure 670 * 671 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 672 * igp PHY's. 673 **/ 674 s32 igb_copper_link_setup_igp(struct e1000_hw *hw) 675 { 676 struct e1000_phy_info *phy = &hw->phy; 677 s32 ret_val; 678 u16 data; 679 680 if (phy->reset_disable) { 681 ret_val = 0; 682 goto out; 683 } 684 685 ret_val = phy->ops.reset(hw); 686 if (ret_val) { 687 hw_dbg("Error resetting the PHY.\n"); 688 goto out; 689 } 690 691 /* 692 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid 693 * timeout issues when LFS is enabled. 694 */ 695 msleep(100); 696 697 /* 698 * The NVM settings will configure LPLU in D3 for 699 * non-IGP1 PHYs. 700 */ 701 if (phy->type == e1000_phy_igp) { 702 /* disable lplu d3 during driver init */ 703 if (phy->ops.set_d3_lplu_state) 704 ret_val = phy->ops.set_d3_lplu_state(hw, false); 705 if (ret_val) { 706 hw_dbg("Error Disabling LPLU D3\n"); 707 goto out; 708 } 709 } 710 711 /* disable lplu d0 during driver init */ 712 ret_val = phy->ops.set_d0_lplu_state(hw, false); 713 if (ret_val) { 714 hw_dbg("Error Disabling LPLU D0\n"); 715 goto out; 716 } 717 /* Configure mdi-mdix settings */ 718 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 719 if (ret_val) 720 goto out; 721 722 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 723 724 switch (phy->mdix) { 725 case 1: 726 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 727 break; 728 case 2: 729 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 730 break; 731 case 0: 732 default: 733 data |= IGP01E1000_PSCR_AUTO_MDIX; 734 break; 735 } 736 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 737 if (ret_val) 738 goto out; 739 740 /* set auto-master slave resolution settings */ 741 if (hw->mac.autoneg) { 742 /* 743 * when autonegotiation advertisement is only 1000Mbps then we 744 * should disable SmartSpeed and enable Auto MasterSlave 745 * resolution as hardware default. 746 */ 747 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 748 /* Disable SmartSpeed */ 749 ret_val = phy->ops.read_reg(hw, 750 IGP01E1000_PHY_PORT_CONFIG, 751 &data); 752 if (ret_val) 753 goto out; 754 755 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 756 ret_val = phy->ops.write_reg(hw, 757 IGP01E1000_PHY_PORT_CONFIG, 758 data); 759 if (ret_val) 760 goto out; 761 762 /* Set auto Master/Slave resolution process */ 763 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 764 if (ret_val) 765 goto out; 766 767 data &= ~CR_1000T_MS_ENABLE; 768 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 769 if (ret_val) 770 goto out; 771 } 772 773 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 774 if (ret_val) 775 goto out; 776 777 /* load defaults for future use */ 778 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 779 ((data & CR_1000T_MS_VALUE) ? 780 e1000_ms_force_master : 781 e1000_ms_force_slave) : 782 e1000_ms_auto; 783 784 switch (phy->ms_type) { 785 case e1000_ms_force_master: 786 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 787 break; 788 case e1000_ms_force_slave: 789 data |= CR_1000T_MS_ENABLE; 790 data &= ~(CR_1000T_MS_VALUE); 791 break; 792 case e1000_ms_auto: 793 data &= ~CR_1000T_MS_ENABLE; 794 default: 795 break; 796 } 797 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 798 if (ret_val) 799 goto out; 800 } 801 802 out: 803 return ret_val; 804 } 805 806 /** 807 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link 808 * @hw: pointer to the HW structure 809 * 810 * Performs initial bounds checking on autoneg advertisement parameter, then 811 * configure to advertise the full capability. Setup the PHY to autoneg 812 * and restart the negotiation process between the link partner. If 813 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 814 **/ 815 static s32 igb_copper_link_autoneg(struct e1000_hw *hw) 816 { 817 struct e1000_phy_info *phy = &hw->phy; 818 s32 ret_val; 819 u16 phy_ctrl; 820 821 /* 822 * Perform some bounds checking on the autoneg advertisement 823 * parameter. 824 */ 825 phy->autoneg_advertised &= phy->autoneg_mask; 826 827 /* 828 * If autoneg_advertised is zero, we assume it was not defaulted 829 * by the calling code so we set to advertise full capability. 830 */ 831 if (phy->autoneg_advertised == 0) 832 phy->autoneg_advertised = phy->autoneg_mask; 833 834 hw_dbg("Reconfiguring auto-neg advertisement params\n"); 835 ret_val = igb_phy_setup_autoneg(hw); 836 if (ret_val) { 837 hw_dbg("Error Setting up Auto-Negotiation\n"); 838 goto out; 839 } 840 hw_dbg("Restarting Auto-Neg\n"); 841 842 /* 843 * Restart auto-negotiation by setting the Auto Neg Enable bit and 844 * the Auto Neg Restart bit in the PHY control register. 845 */ 846 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 847 if (ret_val) 848 goto out; 849 850 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 851 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 852 if (ret_val) 853 goto out; 854 855 /* 856 * Does the user want to wait for Auto-Neg to complete here, or 857 * check at a later time (for example, callback routine). 858 */ 859 if (phy->autoneg_wait_to_complete) { 860 ret_val = igb_wait_autoneg(hw); 861 if (ret_val) { 862 hw_dbg("Error while waiting for " 863 "autoneg to complete\n"); 864 goto out; 865 } 866 } 867 868 hw->mac.get_link_status = true; 869 870 out: 871 return ret_val; 872 } 873 874 /** 875 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation 876 * @hw: pointer to the HW structure 877 * 878 * Reads the MII auto-neg advertisement register and/or the 1000T control 879 * register and if the PHY is already setup for auto-negotiation, then 880 * return successful. Otherwise, setup advertisement and flow control to 881 * the appropriate values for the wanted auto-negotiation. 882 **/ 883 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw) 884 { 885 struct e1000_phy_info *phy = &hw->phy; 886 s32 ret_val; 887 u16 mii_autoneg_adv_reg; 888 u16 mii_1000t_ctrl_reg = 0; 889 890 phy->autoneg_advertised &= phy->autoneg_mask; 891 892 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 893 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 894 if (ret_val) 895 goto out; 896 897 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 898 /* Read the MII 1000Base-T Control Register (Address 9). */ 899 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 900 &mii_1000t_ctrl_reg); 901 if (ret_val) 902 goto out; 903 } 904 905 /* 906 * Need to parse both autoneg_advertised and fc and set up 907 * the appropriate PHY registers. First we will parse for 908 * autoneg_advertised software override. Since we can advertise 909 * a plethora of combinations, we need to check each bit 910 * individually. 911 */ 912 913 /* 914 * First we clear all the 10/100 mb speed bits in the Auto-Neg 915 * Advertisement Register (Address 4) and the 1000 mb speed bits in 916 * the 1000Base-T Control Register (Address 9). 917 */ 918 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 919 NWAY_AR_100TX_HD_CAPS | 920 NWAY_AR_10T_FD_CAPS | 921 NWAY_AR_10T_HD_CAPS); 922 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 923 924 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); 925 926 /* Do we want to advertise 10 Mb Half Duplex? */ 927 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 928 hw_dbg("Advertise 10mb Half duplex\n"); 929 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 930 } 931 932 /* Do we want to advertise 10 Mb Full Duplex? */ 933 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 934 hw_dbg("Advertise 10mb Full duplex\n"); 935 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 936 } 937 938 /* Do we want to advertise 100 Mb Half Duplex? */ 939 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 940 hw_dbg("Advertise 100mb Half duplex\n"); 941 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 942 } 943 944 /* Do we want to advertise 100 Mb Full Duplex? */ 945 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 946 hw_dbg("Advertise 100mb Full duplex\n"); 947 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 948 } 949 950 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 951 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 952 hw_dbg("Advertise 1000mb Half duplex request denied!\n"); 953 954 /* Do we want to advertise 1000 Mb Full Duplex? */ 955 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 956 hw_dbg("Advertise 1000mb Full duplex\n"); 957 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 958 } 959 960 /* 961 * Check for a software override of the flow control settings, and 962 * setup the PHY advertisement registers accordingly. If 963 * auto-negotiation is enabled, then software will have to set the 964 * "PAUSE" bits to the correct value in the Auto-Negotiation 965 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 966 * negotiation. 967 * 968 * The possible values of the "fc" parameter are: 969 * 0: Flow control is completely disabled 970 * 1: Rx flow control is enabled (we can receive pause frames 971 * but not send pause frames). 972 * 2: Tx flow control is enabled (we can send pause frames 973 * but we do not support receiving pause frames). 974 * 3: Both Rx and TX flow control (symmetric) are enabled. 975 * other: No software override. The flow control configuration 976 * in the EEPROM is used. 977 */ 978 switch (hw->fc.current_mode) { 979 case e1000_fc_none: 980 /* 981 * Flow control (RX & TX) is completely disabled by a 982 * software over-ride. 983 */ 984 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 985 break; 986 case e1000_fc_rx_pause: 987 /* 988 * RX Flow control is enabled, and TX Flow control is 989 * disabled, by a software over-ride. 990 * 991 * Since there really isn't a way to advertise that we are 992 * capable of RX Pause ONLY, we will advertise that we 993 * support both symmetric and asymmetric RX PAUSE. Later 994 * (in e1000_config_fc_after_link_up) we will disable the 995 * hw's ability to send PAUSE frames. 996 */ 997 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 998 break; 999 case e1000_fc_tx_pause: 1000 /* 1001 * TX Flow control is enabled, and RX Flow control is 1002 * disabled, by a software over-ride. 1003 */ 1004 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1005 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1006 break; 1007 case e1000_fc_full: 1008 /* 1009 * Flow control (both RX and TX) is enabled by a software 1010 * over-ride. 1011 */ 1012 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1013 break; 1014 default: 1015 hw_dbg("Flow control param set incorrectly\n"); 1016 ret_val = -E1000_ERR_CONFIG; 1017 goto out; 1018 } 1019 1020 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1021 if (ret_val) 1022 goto out; 1023 1024 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1025 1026 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1027 ret_val = phy->ops.write_reg(hw, 1028 PHY_1000T_CTRL, 1029 mii_1000t_ctrl_reg); 1030 if (ret_val) 1031 goto out; 1032 } 1033 1034 out: 1035 return ret_val; 1036 } 1037 1038 /** 1039 * igb_setup_copper_link - Configure copper link settings 1040 * @hw: pointer to the HW structure 1041 * 1042 * Calls the appropriate function to configure the link for auto-neg or forced 1043 * speed and duplex. Then we check for link, once link is established calls 1044 * to configure collision distance and flow control are called. If link is 1045 * not established, we return -E1000_ERR_PHY (-2). 1046 **/ 1047 s32 igb_setup_copper_link(struct e1000_hw *hw) 1048 { 1049 s32 ret_val; 1050 bool link; 1051 1052 1053 if (hw->mac.autoneg) { 1054 /* 1055 * Setup autoneg and flow control advertisement and perform 1056 * autonegotiation. 1057 */ 1058 ret_val = igb_copper_link_autoneg(hw); 1059 if (ret_val) 1060 goto out; 1061 } else { 1062 /* 1063 * PHY will be set to 10H, 10F, 100H or 100F 1064 * depending on user settings. 1065 */ 1066 hw_dbg("Forcing Speed and Duplex\n"); 1067 ret_val = hw->phy.ops.force_speed_duplex(hw); 1068 if (ret_val) { 1069 hw_dbg("Error Forcing Speed and Duplex\n"); 1070 goto out; 1071 } 1072 } 1073 1074 /* 1075 * Check link status. Wait up to 100 microseconds for link to become 1076 * valid. 1077 */ 1078 ret_val = igb_phy_has_link(hw, 1079 COPPER_LINK_UP_LIMIT, 1080 10, 1081 &link); 1082 if (ret_val) 1083 goto out; 1084 1085 if (link) { 1086 hw_dbg("Valid link established!!!\n"); 1087 igb_config_collision_dist(hw); 1088 ret_val = igb_config_fc_after_link_up(hw); 1089 } else { 1090 hw_dbg("Unable to establish link!!!\n"); 1091 } 1092 1093 out: 1094 return ret_val; 1095 } 1096 1097 /** 1098 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1099 * @hw: pointer to the HW structure 1100 * 1101 * Calls the PHY setup function to force speed and duplex. Clears the 1102 * auto-crossover to force MDI manually. Waits for link and returns 1103 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1104 **/ 1105 s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1106 { 1107 struct e1000_phy_info *phy = &hw->phy; 1108 s32 ret_val; 1109 u16 phy_data; 1110 bool link; 1111 1112 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1113 if (ret_val) 1114 goto out; 1115 1116 igb_phy_force_speed_duplex_setup(hw, &phy_data); 1117 1118 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1119 if (ret_val) 1120 goto out; 1121 1122 /* 1123 * Clear Auto-Crossover to force MDI manually. IGP requires MDI 1124 * forced whenever speed and duplex are forced. 1125 */ 1126 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1127 if (ret_val) 1128 goto out; 1129 1130 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1131 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1132 1133 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1134 if (ret_val) 1135 goto out; 1136 1137 hw_dbg("IGP PSCR: %X\n", phy_data); 1138 1139 udelay(1); 1140 1141 if (phy->autoneg_wait_to_complete) { 1142 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); 1143 1144 ret_val = igb_phy_has_link(hw, 1145 PHY_FORCE_LIMIT, 1146 100000, 1147 &link); 1148 if (ret_val) 1149 goto out; 1150 1151 if (!link) 1152 hw_dbg("Link taking longer than expected.\n"); 1153 1154 /* Try once more */ 1155 ret_val = igb_phy_has_link(hw, 1156 PHY_FORCE_LIMIT, 1157 100000, 1158 &link); 1159 if (ret_val) 1160 goto out; 1161 } 1162 1163 out: 1164 return ret_val; 1165 } 1166 1167 /** 1168 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1169 * @hw: pointer to the HW structure 1170 * 1171 * Calls the PHY setup function to force speed and duplex. Clears the 1172 * auto-crossover to force MDI manually. Resets the PHY to commit the 1173 * changes. If time expires while waiting for link up, we reset the DSP. 1174 * After reset, TX_CLK and CRS on TX must be set. Return successful upon 1175 * successful completion, else return corresponding error code. 1176 **/ 1177 s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1178 { 1179 struct e1000_phy_info *phy = &hw->phy; 1180 s32 ret_val; 1181 u16 phy_data; 1182 bool link; 1183 1184 /* 1185 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 1186 * forced whenever speed and duplex are forced. 1187 */ 1188 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1189 if (ret_val) 1190 goto out; 1191 1192 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1193 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1194 if (ret_val) 1195 goto out; 1196 1197 hw_dbg("M88E1000 PSCR: %X\n", phy_data); 1198 1199 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1200 if (ret_val) 1201 goto out; 1202 1203 igb_phy_force_speed_duplex_setup(hw, &phy_data); 1204 1205 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1206 if (ret_val) 1207 goto out; 1208 1209 /* Reset the phy to commit changes. */ 1210 ret_val = igb_phy_sw_reset(hw); 1211 if (ret_val) 1212 goto out; 1213 1214 if (phy->autoneg_wait_to_complete) { 1215 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); 1216 1217 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); 1218 if (ret_val) 1219 goto out; 1220 1221 if (!link) { 1222 bool reset_dsp = true; 1223 1224 switch (hw->phy.id) { 1225 case I347AT4_E_PHY_ID: 1226 case M88E1112_E_PHY_ID: 1227 case I210_I_PHY_ID: 1228 reset_dsp = false; 1229 break; 1230 default: 1231 if (hw->phy.type != e1000_phy_m88) 1232 reset_dsp = false; 1233 break; 1234 } 1235 if (!reset_dsp) 1236 hw_dbg("Link taking longer than expected.\n"); 1237 else { 1238 /* 1239 * We didn't get link. 1240 * Reset the DSP and cross our fingers. 1241 */ 1242 ret_val = phy->ops.write_reg(hw, 1243 M88E1000_PHY_PAGE_SELECT, 1244 0x001d); 1245 if (ret_val) 1246 goto out; 1247 ret_val = igb_phy_reset_dsp(hw); 1248 if (ret_val) 1249 goto out; 1250 } 1251 } 1252 1253 /* Try once more */ 1254 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 1255 100000, &link); 1256 if (ret_val) 1257 goto out; 1258 } 1259 1260 if (hw->phy.type != e1000_phy_m88 || 1261 hw->phy.id == I347AT4_E_PHY_ID || 1262 hw->phy.id == M88E1112_E_PHY_ID || 1263 hw->phy.id == I210_I_PHY_ID) 1264 goto out; 1265 1266 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1267 if (ret_val) 1268 goto out; 1269 1270 /* 1271 * Resetting the phy means we need to re-force TX_CLK in the 1272 * Extended PHY Specific Control Register to 25MHz clock from 1273 * the reset value of 2.5MHz. 1274 */ 1275 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1276 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1277 if (ret_val) 1278 goto out; 1279 1280 /* 1281 * In addition, we must re-enable CRS on Tx for both half and full 1282 * duplex. 1283 */ 1284 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1285 if (ret_val) 1286 goto out; 1287 1288 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1289 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1290 1291 out: 1292 return ret_val; 1293 } 1294 1295 /** 1296 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1297 * @hw: pointer to the HW structure 1298 * @phy_ctrl: pointer to current value of PHY_CONTROL 1299 * 1300 * Forces speed and duplex on the PHY by doing the following: disable flow 1301 * control, force speed/duplex on the MAC, disable auto speed detection, 1302 * disable auto-negotiation, configure duplex, configure speed, configure 1303 * the collision distance, write configuration to CTRL register. The 1304 * caller must write to the PHY_CONTROL register for these settings to 1305 * take affect. 1306 **/ 1307 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, 1308 u16 *phy_ctrl) 1309 { 1310 struct e1000_mac_info *mac = &hw->mac; 1311 u32 ctrl; 1312 1313 /* Turn off flow control when forcing speed/duplex */ 1314 hw->fc.current_mode = e1000_fc_none; 1315 1316 /* Force speed/duplex on the mac */ 1317 ctrl = rd32(E1000_CTRL); 1318 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1319 ctrl &= ~E1000_CTRL_SPD_SEL; 1320 1321 /* Disable Auto Speed Detection */ 1322 ctrl &= ~E1000_CTRL_ASDE; 1323 1324 /* Disable autoneg on the phy */ 1325 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1326 1327 /* Forcing Full or Half Duplex? */ 1328 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1329 ctrl &= ~E1000_CTRL_FD; 1330 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1331 hw_dbg("Half Duplex\n"); 1332 } else { 1333 ctrl |= E1000_CTRL_FD; 1334 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1335 hw_dbg("Full Duplex\n"); 1336 } 1337 1338 /* Forcing 10mb or 100mb? */ 1339 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1340 ctrl |= E1000_CTRL_SPD_100; 1341 *phy_ctrl |= MII_CR_SPEED_100; 1342 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1343 hw_dbg("Forcing 100mb\n"); 1344 } else { 1345 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1346 *phy_ctrl |= MII_CR_SPEED_10; 1347 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1348 hw_dbg("Forcing 10mb\n"); 1349 } 1350 1351 igb_config_collision_dist(hw); 1352 1353 wr32(E1000_CTRL, ctrl); 1354 } 1355 1356 /** 1357 * igb_set_d3_lplu_state - Sets low power link up state for D3 1358 * @hw: pointer to the HW structure 1359 * @active: boolean used to enable/disable lplu 1360 * 1361 * Success returns 0, Failure returns 1 1362 * 1363 * The low power link up (lplu) state is set to the power management level D3 1364 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1365 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1366 * is used during Dx states where the power conservation is most important. 1367 * During driver activity, SmartSpeed should be enabled so performance is 1368 * maintained. 1369 **/ 1370 s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active) 1371 { 1372 struct e1000_phy_info *phy = &hw->phy; 1373 s32 ret_val = 0; 1374 u16 data; 1375 1376 if (!(hw->phy.ops.read_reg)) 1377 goto out; 1378 1379 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1380 if (ret_val) 1381 goto out; 1382 1383 if (!active) { 1384 data &= ~IGP02E1000_PM_D3_LPLU; 1385 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1386 data); 1387 if (ret_val) 1388 goto out; 1389 /* 1390 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 1391 * during Dx states where the power conservation is most 1392 * important. During driver activity we should enable 1393 * SmartSpeed, so performance is maintained. 1394 */ 1395 if (phy->smart_speed == e1000_smart_speed_on) { 1396 ret_val = phy->ops.read_reg(hw, 1397 IGP01E1000_PHY_PORT_CONFIG, 1398 &data); 1399 if (ret_val) 1400 goto out; 1401 1402 data |= IGP01E1000_PSCFR_SMART_SPEED; 1403 ret_val = phy->ops.write_reg(hw, 1404 IGP01E1000_PHY_PORT_CONFIG, 1405 data); 1406 if (ret_val) 1407 goto out; 1408 } else if (phy->smart_speed == e1000_smart_speed_off) { 1409 ret_val = phy->ops.read_reg(hw, 1410 IGP01E1000_PHY_PORT_CONFIG, 1411 &data); 1412 if (ret_val) 1413 goto out; 1414 1415 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1416 ret_val = phy->ops.write_reg(hw, 1417 IGP01E1000_PHY_PORT_CONFIG, 1418 data); 1419 if (ret_val) 1420 goto out; 1421 } 1422 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1423 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1424 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1425 data |= IGP02E1000_PM_D3_LPLU; 1426 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1427 data); 1428 if (ret_val) 1429 goto out; 1430 1431 /* When LPLU is enabled, we should disable SmartSpeed */ 1432 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1433 &data); 1434 if (ret_val) 1435 goto out; 1436 1437 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1438 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1439 data); 1440 } 1441 1442 out: 1443 return ret_val; 1444 } 1445 1446 /** 1447 * igb_check_downshift - Checks whether a downshift in speed occurred 1448 * @hw: pointer to the HW structure 1449 * 1450 * Success returns 0, Failure returns 1 1451 * 1452 * A downshift is detected by querying the PHY link health. 1453 **/ 1454 s32 igb_check_downshift(struct e1000_hw *hw) 1455 { 1456 struct e1000_phy_info *phy = &hw->phy; 1457 s32 ret_val; 1458 u16 phy_data, offset, mask; 1459 1460 switch (phy->type) { 1461 case e1000_phy_i210: 1462 case e1000_phy_m88: 1463 case e1000_phy_gg82563: 1464 offset = M88E1000_PHY_SPEC_STATUS; 1465 mask = M88E1000_PSSR_DOWNSHIFT; 1466 break; 1467 case e1000_phy_igp_2: 1468 case e1000_phy_igp: 1469 case e1000_phy_igp_3: 1470 offset = IGP01E1000_PHY_LINK_HEALTH; 1471 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1472 break; 1473 default: 1474 /* speed downshift not supported */ 1475 phy->speed_downgraded = false; 1476 ret_val = 0; 1477 goto out; 1478 } 1479 1480 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 1481 1482 if (!ret_val) 1483 phy->speed_downgraded = (phy_data & mask) ? true : false; 1484 1485 out: 1486 return ret_val; 1487 } 1488 1489 /** 1490 * igb_check_polarity_m88 - Checks the polarity. 1491 * @hw: pointer to the HW structure 1492 * 1493 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1494 * 1495 * Polarity is determined based on the PHY specific status register. 1496 **/ 1497 s32 igb_check_polarity_m88(struct e1000_hw *hw) 1498 { 1499 struct e1000_phy_info *phy = &hw->phy; 1500 s32 ret_val; 1501 u16 data; 1502 1503 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 1504 1505 if (!ret_val) 1506 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 1507 ? e1000_rev_polarity_reversed 1508 : e1000_rev_polarity_normal; 1509 1510 return ret_val; 1511 } 1512 1513 /** 1514 * igb_check_polarity_igp - Checks the polarity. 1515 * @hw: pointer to the HW structure 1516 * 1517 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1518 * 1519 * Polarity is determined based on the PHY port status register, and the 1520 * current speed (since there is no polarity at 100Mbps). 1521 **/ 1522 static s32 igb_check_polarity_igp(struct e1000_hw *hw) 1523 { 1524 struct e1000_phy_info *phy = &hw->phy; 1525 s32 ret_val; 1526 u16 data, offset, mask; 1527 1528 /* 1529 * Polarity is determined based on the speed of 1530 * our connection. 1531 */ 1532 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1533 if (ret_val) 1534 goto out; 1535 1536 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1537 IGP01E1000_PSSR_SPEED_1000MBPS) { 1538 offset = IGP01E1000_PHY_PCS_INIT_REG; 1539 mask = IGP01E1000_PHY_POLARITY_MASK; 1540 } else { 1541 /* 1542 * This really only applies to 10Mbps since 1543 * there is no polarity for 100Mbps (always 0). 1544 */ 1545 offset = IGP01E1000_PHY_PORT_STATUS; 1546 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1547 } 1548 1549 ret_val = phy->ops.read_reg(hw, offset, &data); 1550 1551 if (!ret_val) 1552 phy->cable_polarity = (data & mask) 1553 ? e1000_rev_polarity_reversed 1554 : e1000_rev_polarity_normal; 1555 1556 out: 1557 return ret_val; 1558 } 1559 1560 /** 1561 * igb_wait_autoneg - Wait for auto-neg compeletion 1562 * @hw: pointer to the HW structure 1563 * 1564 * Waits for auto-negotiation to complete or for the auto-negotiation time 1565 * limit to expire, which ever happens first. 1566 **/ 1567 static s32 igb_wait_autoneg(struct e1000_hw *hw) 1568 { 1569 s32 ret_val = 0; 1570 u16 i, phy_status; 1571 1572 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 1573 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 1574 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1575 if (ret_val) 1576 break; 1577 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1578 if (ret_val) 1579 break; 1580 if (phy_status & MII_SR_AUTONEG_COMPLETE) 1581 break; 1582 msleep(100); 1583 } 1584 1585 /* 1586 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 1587 * has completed. 1588 */ 1589 return ret_val; 1590 } 1591 1592 /** 1593 * igb_phy_has_link - Polls PHY for link 1594 * @hw: pointer to the HW structure 1595 * @iterations: number of times to poll for link 1596 * @usec_interval: delay between polling attempts 1597 * @success: pointer to whether polling was successful or not 1598 * 1599 * Polls the PHY status register for link, 'iterations' number of times. 1600 **/ 1601 s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations, 1602 u32 usec_interval, bool *success) 1603 { 1604 s32 ret_val = 0; 1605 u16 i, phy_status; 1606 1607 for (i = 0; i < iterations; i++) { 1608 /* 1609 * Some PHYs require the PHY_STATUS register to be read 1610 * twice due to the link bit being sticky. No harm doing 1611 * it across the board. 1612 */ 1613 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1614 if (ret_val) { 1615 /* 1616 * If the first read fails, another entity may have 1617 * ownership of the resources, wait and try again to 1618 * see if they have relinquished the resources yet. 1619 */ 1620 udelay(usec_interval); 1621 } 1622 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1623 if (ret_val) 1624 break; 1625 if (phy_status & MII_SR_LINK_STATUS) 1626 break; 1627 if (usec_interval >= 1000) 1628 mdelay(usec_interval/1000); 1629 else 1630 udelay(usec_interval); 1631 } 1632 1633 *success = (i < iterations) ? true : false; 1634 1635 return ret_val; 1636 } 1637 1638 /** 1639 * igb_get_cable_length_m88 - Determine cable length for m88 PHY 1640 * @hw: pointer to the HW structure 1641 * 1642 * Reads the PHY specific status register to retrieve the cable length 1643 * information. The cable length is determined by averaging the minimum and 1644 * maximum values to get the "average" cable length. The m88 PHY has four 1645 * possible cable length values, which are: 1646 * Register Value Cable Length 1647 * 0 < 50 meters 1648 * 1 50 - 80 meters 1649 * 2 80 - 110 meters 1650 * 3 110 - 140 meters 1651 * 4 > 140 meters 1652 **/ 1653 s32 igb_get_cable_length_m88(struct e1000_hw *hw) 1654 { 1655 struct e1000_phy_info *phy = &hw->phy; 1656 s32 ret_val; 1657 u16 phy_data, index; 1658 1659 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1660 if (ret_val) 1661 goto out; 1662 1663 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1664 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1665 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { 1666 ret_val = -E1000_ERR_PHY; 1667 goto out; 1668 } 1669 1670 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1671 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 1672 1673 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1674 1675 out: 1676 return ret_val; 1677 } 1678 1679 s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw) 1680 { 1681 struct e1000_phy_info *phy = &hw->phy; 1682 s32 ret_val; 1683 u16 phy_data, phy_data2, index, default_page, is_cm; 1684 1685 switch (hw->phy.id) { 1686 case I210_I_PHY_ID: 1687 case I347AT4_E_PHY_ID: 1688 /* Remember the original page select and set it to 7 */ 1689 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 1690 &default_page); 1691 if (ret_val) 1692 goto out; 1693 1694 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07); 1695 if (ret_val) 1696 goto out; 1697 1698 /* Get cable length from PHY Cable Diagnostics Control Reg */ 1699 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr), 1700 &phy_data); 1701 if (ret_val) 1702 goto out; 1703 1704 /* Check if the unit of cable length is meters or cm */ 1705 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2); 1706 if (ret_val) 1707 goto out; 1708 1709 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 1710 1711 /* Populate the phy structure with cable length in meters */ 1712 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 1713 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 1714 phy->cable_length = phy_data / (is_cm ? 100 : 1); 1715 1716 /* Reset the page selec to its original value */ 1717 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 1718 default_page); 1719 if (ret_val) 1720 goto out; 1721 break; 1722 case M88E1112_E_PHY_ID: 1723 /* Remember the original page select and set it to 5 */ 1724 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 1725 &default_page); 1726 if (ret_val) 1727 goto out; 1728 1729 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05); 1730 if (ret_val) 1731 goto out; 1732 1733 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE, 1734 &phy_data); 1735 if (ret_val) 1736 goto out; 1737 1738 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1739 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1740 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) { 1741 ret_val = -E1000_ERR_PHY; 1742 goto out; 1743 } 1744 1745 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1746 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 1747 1748 phy->cable_length = (phy->min_cable_length + 1749 phy->max_cable_length) / 2; 1750 1751 /* Reset the page select to its original value */ 1752 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 1753 default_page); 1754 if (ret_val) 1755 goto out; 1756 1757 break; 1758 default: 1759 ret_val = -E1000_ERR_PHY; 1760 goto out; 1761 } 1762 1763 out: 1764 return ret_val; 1765 } 1766 1767 /** 1768 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY 1769 * @hw: pointer to the HW structure 1770 * 1771 * The automatic gain control (agc) normalizes the amplitude of the 1772 * received signal, adjusting for the attenuation produced by the 1773 * cable. By reading the AGC registers, which represent the 1774 * combination of coarse and fine gain value, the value can be put 1775 * into a lookup table to obtain the approximate cable length 1776 * for each channel. 1777 **/ 1778 s32 igb_get_cable_length_igp_2(struct e1000_hw *hw) 1779 { 1780 struct e1000_phy_info *phy = &hw->phy; 1781 s32 ret_val = 0; 1782 u16 phy_data, i, agc_value = 0; 1783 u16 cur_agc_index, max_agc_index = 0; 1784 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 1785 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { 1786 IGP02E1000_PHY_AGC_A, 1787 IGP02E1000_PHY_AGC_B, 1788 IGP02E1000_PHY_AGC_C, 1789 IGP02E1000_PHY_AGC_D 1790 }; 1791 1792 /* Read the AGC registers for all channels */ 1793 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 1794 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 1795 if (ret_val) 1796 goto out; 1797 1798 /* 1799 * Getting bits 15:9, which represent the combination of 1800 * coarse and fine gain values. The result is a number 1801 * that can be put into the lookup table to obtain the 1802 * approximate cable length. 1803 */ 1804 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 1805 IGP02E1000_AGC_LENGTH_MASK; 1806 1807 /* Array index bound check. */ 1808 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 1809 (cur_agc_index == 0)) { 1810 ret_val = -E1000_ERR_PHY; 1811 goto out; 1812 } 1813 1814 /* Remove min & max AGC values from calculation. */ 1815 if (e1000_igp_2_cable_length_table[min_agc_index] > 1816 e1000_igp_2_cable_length_table[cur_agc_index]) 1817 min_agc_index = cur_agc_index; 1818 if (e1000_igp_2_cable_length_table[max_agc_index] < 1819 e1000_igp_2_cable_length_table[cur_agc_index]) 1820 max_agc_index = cur_agc_index; 1821 1822 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 1823 } 1824 1825 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 1826 e1000_igp_2_cable_length_table[max_agc_index]); 1827 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 1828 1829 /* Calculate cable length with the error range of +/- 10 meters. */ 1830 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 1831 (agc_value - IGP02E1000_AGC_RANGE) : 0; 1832 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 1833 1834 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1835 1836 out: 1837 return ret_val; 1838 } 1839 1840 /** 1841 * igb_get_phy_info_m88 - Retrieve PHY information 1842 * @hw: pointer to the HW structure 1843 * 1844 * Valid for only copper links. Read the PHY status register (sticky read) 1845 * to verify that link is up. Read the PHY special control register to 1846 * determine the polarity and 10base-T extended distance. Read the PHY 1847 * special status register to determine MDI/MDIx and current speed. If 1848 * speed is 1000, then determine cable length, local and remote receiver. 1849 **/ 1850 s32 igb_get_phy_info_m88(struct e1000_hw *hw) 1851 { 1852 struct e1000_phy_info *phy = &hw->phy; 1853 s32 ret_val; 1854 u16 phy_data; 1855 bool link; 1856 1857 if (phy->media_type != e1000_media_type_copper) { 1858 hw_dbg("Phy info is only valid for copper media\n"); 1859 ret_val = -E1000_ERR_CONFIG; 1860 goto out; 1861 } 1862 1863 ret_val = igb_phy_has_link(hw, 1, 0, &link); 1864 if (ret_val) 1865 goto out; 1866 1867 if (!link) { 1868 hw_dbg("Phy info is only valid if link is up\n"); 1869 ret_val = -E1000_ERR_CONFIG; 1870 goto out; 1871 } 1872 1873 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1874 if (ret_val) 1875 goto out; 1876 1877 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 1878 ? true : false; 1879 1880 ret_val = igb_check_polarity_m88(hw); 1881 if (ret_val) 1882 goto out; 1883 1884 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1885 if (ret_val) 1886 goto out; 1887 1888 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false; 1889 1890 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 1891 ret_val = phy->ops.get_cable_length(hw); 1892 if (ret_val) 1893 goto out; 1894 1895 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 1896 if (ret_val) 1897 goto out; 1898 1899 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 1900 ? e1000_1000t_rx_status_ok 1901 : e1000_1000t_rx_status_not_ok; 1902 1903 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 1904 ? e1000_1000t_rx_status_ok 1905 : e1000_1000t_rx_status_not_ok; 1906 } else { 1907 /* Set values to "undefined" */ 1908 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1909 phy->local_rx = e1000_1000t_rx_status_undefined; 1910 phy->remote_rx = e1000_1000t_rx_status_undefined; 1911 } 1912 1913 out: 1914 return ret_val; 1915 } 1916 1917 /** 1918 * igb_get_phy_info_igp - Retrieve igp PHY information 1919 * @hw: pointer to the HW structure 1920 * 1921 * Read PHY status to determine if link is up. If link is up, then 1922 * set/determine 10base-T extended distance and polarity correction. Read 1923 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 1924 * determine on the cable length, local and remote receiver. 1925 **/ 1926 s32 igb_get_phy_info_igp(struct e1000_hw *hw) 1927 { 1928 struct e1000_phy_info *phy = &hw->phy; 1929 s32 ret_val; 1930 u16 data; 1931 bool link; 1932 1933 ret_val = igb_phy_has_link(hw, 1, 0, &link); 1934 if (ret_val) 1935 goto out; 1936 1937 if (!link) { 1938 hw_dbg("Phy info is only valid if link is up\n"); 1939 ret_val = -E1000_ERR_CONFIG; 1940 goto out; 1941 } 1942 1943 phy->polarity_correction = true; 1944 1945 ret_val = igb_check_polarity_igp(hw); 1946 if (ret_val) 1947 goto out; 1948 1949 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1950 if (ret_val) 1951 goto out; 1952 1953 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false; 1954 1955 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1956 IGP01E1000_PSSR_SPEED_1000MBPS) { 1957 ret_val = phy->ops.get_cable_length(hw); 1958 if (ret_val) 1959 goto out; 1960 1961 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 1962 if (ret_val) 1963 goto out; 1964 1965 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 1966 ? e1000_1000t_rx_status_ok 1967 : e1000_1000t_rx_status_not_ok; 1968 1969 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 1970 ? e1000_1000t_rx_status_ok 1971 : e1000_1000t_rx_status_not_ok; 1972 } else { 1973 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1974 phy->local_rx = e1000_1000t_rx_status_undefined; 1975 phy->remote_rx = e1000_1000t_rx_status_undefined; 1976 } 1977 1978 out: 1979 return ret_val; 1980 } 1981 1982 /** 1983 * igb_phy_sw_reset - PHY software reset 1984 * @hw: pointer to the HW structure 1985 * 1986 * Does a software reset of the PHY by reading the PHY control register and 1987 * setting/write the control register reset bit to the PHY. 1988 **/ 1989 s32 igb_phy_sw_reset(struct e1000_hw *hw) 1990 { 1991 s32 ret_val = 0; 1992 u16 phy_ctrl; 1993 1994 if (!(hw->phy.ops.read_reg)) 1995 goto out; 1996 1997 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 1998 if (ret_val) 1999 goto out; 2000 2001 phy_ctrl |= MII_CR_RESET; 2002 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 2003 if (ret_val) 2004 goto out; 2005 2006 udelay(1); 2007 2008 out: 2009 return ret_val; 2010 } 2011 2012 /** 2013 * igb_phy_hw_reset - PHY hardware reset 2014 * @hw: pointer to the HW structure 2015 * 2016 * Verify the reset block is not blocking us from resetting. Acquire 2017 * semaphore (if necessary) and read/set/write the device control reset 2018 * bit in the PHY. Wait the appropriate delay time for the device to 2019 * reset and relase the semaphore (if necessary). 2020 **/ 2021 s32 igb_phy_hw_reset(struct e1000_hw *hw) 2022 { 2023 struct e1000_phy_info *phy = &hw->phy; 2024 s32 ret_val; 2025 u32 ctrl; 2026 2027 ret_val = igb_check_reset_block(hw); 2028 if (ret_val) { 2029 ret_val = 0; 2030 goto out; 2031 } 2032 2033 ret_val = phy->ops.acquire(hw); 2034 if (ret_val) 2035 goto out; 2036 2037 ctrl = rd32(E1000_CTRL); 2038 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2039 wrfl(); 2040 2041 udelay(phy->reset_delay_us); 2042 2043 wr32(E1000_CTRL, ctrl); 2044 wrfl(); 2045 2046 udelay(150); 2047 2048 phy->ops.release(hw); 2049 2050 ret_val = phy->ops.get_cfg_done(hw); 2051 2052 out: 2053 return ret_val; 2054 } 2055 2056 /** 2057 * igb_phy_init_script_igp3 - Inits the IGP3 PHY 2058 * @hw: pointer to the HW structure 2059 * 2060 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2061 **/ 2062 s32 igb_phy_init_script_igp3(struct e1000_hw *hw) 2063 { 2064 hw_dbg("Running IGP 3 PHY init script\n"); 2065 2066 /* PHY init IGP 3 */ 2067 /* Enable rise/fall, 10-mode work in class-A */ 2068 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2069 /* Remove all caps from Replica path filter */ 2070 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2071 /* Bias trimming for ADC, AFE and Driver (Default) */ 2072 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2073 /* Increase Hybrid poly bias */ 2074 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2075 /* Add 4% to TX amplitude in Giga mode */ 2076 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2077 /* Disable trimming (TTT) */ 2078 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2079 /* Poly DC correction to 94.6% + 2% for all channels */ 2080 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2081 /* ABS DC correction to 95.9% */ 2082 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2083 /* BG temp curve trim */ 2084 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2085 /* Increasing ADC OPAMP stage 1 currents to max */ 2086 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2087 /* Force 1000 ( required for enabling PHY regs configuration) */ 2088 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2089 /* Set upd_freq to 6 */ 2090 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2091 /* Disable NPDFE */ 2092 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2093 /* Disable adaptive fixed FFE (Default) */ 2094 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2095 /* Enable FFE hysteresis */ 2096 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2097 /* Fixed FFE for short cable lengths */ 2098 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2099 /* Fixed FFE for medium cable lengths */ 2100 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2101 /* Fixed FFE for long cable lengths */ 2102 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2103 /* Enable Adaptive Clip Threshold */ 2104 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2105 /* AHT reset limit to 1 */ 2106 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2107 /* Set AHT master delay to 127 msec */ 2108 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2109 /* Set scan bits for AHT */ 2110 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2111 /* Set AHT Preset bits */ 2112 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2113 /* Change integ_factor of channel A to 3 */ 2114 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2115 /* Change prop_factor of channels BCD to 8 */ 2116 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2117 /* Change cg_icount + enable integbp for channels BCD */ 2118 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2119 /* 2120 * Change cg_icount + enable integbp + change prop_factor_master 2121 * to 8 for channel A 2122 */ 2123 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2124 /* Disable AHT in Slave mode on channel A */ 2125 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2126 /* 2127 * Enable LPLU and disable AN to 1000 in non-D0a states, 2128 * Enable SPD+B2B 2129 */ 2130 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2131 /* Enable restart AN on an1000_dis change */ 2132 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2133 /* Enable wh_fifo read clock in 10/100 modes */ 2134 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2135 /* Restart AN, Speed selection is 1000 */ 2136 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2137 2138 return 0; 2139 } 2140 2141 /** 2142 * igb_power_up_phy_copper - Restore copper link in case of PHY power down 2143 * @hw: pointer to the HW structure 2144 * 2145 * In the case of a PHY power down to save power, or to turn off link during a 2146 * driver unload, restore the link to previous settings. 2147 **/ 2148 void igb_power_up_phy_copper(struct e1000_hw *hw) 2149 { 2150 u16 mii_reg = 0; 2151 u16 power_reg = 0; 2152 2153 /* The PHY will retain its settings across a power down/up cycle */ 2154 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2155 mii_reg &= ~MII_CR_POWER_DOWN; 2156 if (hw->phy.type == e1000_phy_i210) { 2157 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); 2158 power_reg &= ~GS40G_CS_POWER_DOWN; 2159 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); 2160 } 2161 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2162 } 2163 2164 /** 2165 * igb_power_down_phy_copper - Power down copper PHY 2166 * @hw: pointer to the HW structure 2167 * 2168 * Power down PHY to save power when interface is down and wake on lan 2169 * is not enabled. 2170 **/ 2171 void igb_power_down_phy_copper(struct e1000_hw *hw) 2172 { 2173 u16 mii_reg = 0; 2174 u16 power_reg = 0; 2175 2176 /* The PHY will retain its settings across a power down/up cycle */ 2177 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2178 mii_reg |= MII_CR_POWER_DOWN; 2179 2180 /* i210 Phy requires an additional bit for power up/down */ 2181 if (hw->phy.type == e1000_phy_i210) { 2182 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); 2183 power_reg |= GS40G_CS_POWER_DOWN; 2184 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); 2185 } 2186 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2187 msleep(1); 2188 } 2189 2190 /** 2191 * igb_check_polarity_82580 - Checks the polarity. 2192 * @hw: pointer to the HW structure 2193 * 2194 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2195 * 2196 * Polarity is determined based on the PHY specific status register. 2197 **/ 2198 static s32 igb_check_polarity_82580(struct e1000_hw *hw) 2199 { 2200 struct e1000_phy_info *phy = &hw->phy; 2201 s32 ret_val; 2202 u16 data; 2203 2204 2205 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); 2206 2207 if (!ret_val) 2208 phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY) 2209 ? e1000_rev_polarity_reversed 2210 : e1000_rev_polarity_normal; 2211 2212 return ret_val; 2213 } 2214 2215 /** 2216 * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY 2217 * @hw: pointer to the HW structure 2218 * 2219 * Calls the PHY setup function to force speed and duplex. Clears the 2220 * auto-crossover to force MDI manually. Waits for link and returns 2221 * successful if link up is successful, else -E1000_ERR_PHY (-2). 2222 **/ 2223 s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw) 2224 { 2225 struct e1000_phy_info *phy = &hw->phy; 2226 s32 ret_val; 2227 u16 phy_data; 2228 bool link; 2229 2230 2231 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 2232 if (ret_val) 2233 goto out; 2234 2235 igb_phy_force_speed_duplex_setup(hw, &phy_data); 2236 2237 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 2238 if (ret_val) 2239 goto out; 2240 2241 /* 2242 * Clear Auto-Crossover to force MDI manually. 82580 requires MDI 2243 * forced whenever speed and duplex are forced. 2244 */ 2245 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); 2246 if (ret_val) 2247 goto out; 2248 2249 phy_data &= ~I82580_PHY_CTRL2_AUTO_MDIX; 2250 phy_data &= ~I82580_PHY_CTRL2_FORCE_MDI_MDIX; 2251 2252 ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); 2253 if (ret_val) 2254 goto out; 2255 2256 hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data); 2257 2258 udelay(1); 2259 2260 if (phy->autoneg_wait_to_complete) { 2261 hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n"); 2262 2263 ret_val = igb_phy_has_link(hw, 2264 PHY_FORCE_LIMIT, 2265 100000, 2266 &link); 2267 if (ret_val) 2268 goto out; 2269 2270 if (!link) 2271 hw_dbg("Link taking longer than expected.\n"); 2272 2273 /* Try once more */ 2274 ret_val = igb_phy_has_link(hw, 2275 PHY_FORCE_LIMIT, 2276 100000, 2277 &link); 2278 if (ret_val) 2279 goto out; 2280 } 2281 2282 out: 2283 return ret_val; 2284 } 2285 2286 /** 2287 * igb_get_phy_info_82580 - Retrieve I82580 PHY information 2288 * @hw: pointer to the HW structure 2289 * 2290 * Read PHY status to determine if link is up. If link is up, then 2291 * set/determine 10base-T extended distance and polarity correction. Read 2292 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2293 * determine on the cable length, local and remote receiver. 2294 **/ 2295 s32 igb_get_phy_info_82580(struct e1000_hw *hw) 2296 { 2297 struct e1000_phy_info *phy = &hw->phy; 2298 s32 ret_val; 2299 u16 data; 2300 bool link; 2301 2302 2303 ret_val = igb_phy_has_link(hw, 1, 0, &link); 2304 if (ret_val) 2305 goto out; 2306 2307 if (!link) { 2308 hw_dbg("Phy info is only valid if link is up\n"); 2309 ret_val = -E1000_ERR_CONFIG; 2310 goto out; 2311 } 2312 2313 phy->polarity_correction = true; 2314 2315 ret_val = igb_check_polarity_82580(hw); 2316 if (ret_val) 2317 goto out; 2318 2319 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); 2320 if (ret_val) 2321 goto out; 2322 2323 phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false; 2324 2325 if ((data & I82580_PHY_STATUS2_SPEED_MASK) == 2326 I82580_PHY_STATUS2_SPEED_1000MBPS) { 2327 ret_val = hw->phy.ops.get_cable_length(hw); 2328 if (ret_val) 2329 goto out; 2330 2331 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2332 if (ret_val) 2333 goto out; 2334 2335 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2336 ? e1000_1000t_rx_status_ok 2337 : e1000_1000t_rx_status_not_ok; 2338 2339 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2340 ? e1000_1000t_rx_status_ok 2341 : e1000_1000t_rx_status_not_ok; 2342 } else { 2343 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2344 phy->local_rx = e1000_1000t_rx_status_undefined; 2345 phy->remote_rx = e1000_1000t_rx_status_undefined; 2346 } 2347 2348 out: 2349 return ret_val; 2350 } 2351 2352 /** 2353 * igb_get_cable_length_82580 - Determine cable length for 82580 PHY 2354 * @hw: pointer to the HW structure 2355 * 2356 * Reads the diagnostic status register and verifies result is valid before 2357 * placing it in the phy_cable_length field. 2358 **/ 2359 s32 igb_get_cable_length_82580(struct e1000_hw *hw) 2360 { 2361 struct e1000_phy_info *phy = &hw->phy; 2362 s32 ret_val; 2363 u16 phy_data, length; 2364 2365 2366 ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data); 2367 if (ret_val) 2368 goto out; 2369 2370 length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >> 2371 I82580_DSTATUS_CABLE_LENGTH_SHIFT; 2372 2373 if (length == E1000_CABLE_LENGTH_UNDEFINED) 2374 ret_val = -E1000_ERR_PHY; 2375 2376 phy->cable_length = length; 2377 2378 out: 2379 return ret_val; 2380 } 2381 2382 /** 2383 * igb_write_phy_reg_gs40g - Write GS40G PHY register 2384 * @hw: pointer to the HW structure 2385 * @offset: lower half is register offset to write to 2386 * upper half is page to use. 2387 * @data: data to write at register offset 2388 * 2389 * Acquires semaphore, if necessary, then writes the data to PHY register 2390 * at the offset. Release any acquired semaphores before exiting. 2391 **/ 2392 s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) 2393 { 2394 s32 ret_val; 2395 u16 page = offset >> GS40G_PAGE_SHIFT; 2396 2397 offset = offset & GS40G_OFFSET_MASK; 2398 ret_val = hw->phy.ops.acquire(hw); 2399 if (ret_val) 2400 return ret_val; 2401 2402 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 2403 if (ret_val) 2404 goto release; 2405 ret_val = igb_write_phy_reg_mdic(hw, offset, data); 2406 2407 release: 2408 hw->phy.ops.release(hw); 2409 return ret_val; 2410 } 2411 2412 /** 2413 * igb_read_phy_reg_gs40g - Read GS40G PHY register 2414 * @hw: pointer to the HW structure 2415 * @offset: lower half is register offset to read to 2416 * upper half is page to use. 2417 * @data: data to read at register offset 2418 * 2419 * Acquires semaphore, if necessary, then reads the data in the PHY register 2420 * at the offset. Release any acquired semaphores before exiting. 2421 **/ 2422 s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) 2423 { 2424 s32 ret_val; 2425 u16 page = offset >> GS40G_PAGE_SHIFT; 2426 2427 offset = offset & GS40G_OFFSET_MASK; 2428 ret_val = hw->phy.ops.acquire(hw); 2429 if (ret_val) 2430 return ret_val; 2431 2432 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 2433 if (ret_val) 2434 goto release; 2435 ret_val = igb_read_phy_reg_mdic(hw, offset, data); 2436 2437 release: 2438 hw->phy.ops.release(hw); 2439 return ret_val; 2440 } 2441 2442 /** 2443 * igb_set_master_slave_mode - Setup PHY for Master/slave mode 2444 * @hw: pointer to the HW structure 2445 * 2446 * Sets up Master/slave mode 2447 **/ 2448 static s32 igb_set_master_slave_mode(struct e1000_hw *hw) 2449 { 2450 s32 ret_val; 2451 u16 phy_data; 2452 2453 /* Resolve Master/Slave mode */ 2454 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data); 2455 if (ret_val) 2456 return ret_val; 2457 2458 /* load defaults for future use */ 2459 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ? 2460 ((phy_data & CR_1000T_MS_VALUE) ? 2461 e1000_ms_force_master : 2462 e1000_ms_force_slave) : e1000_ms_auto; 2463 2464 switch (hw->phy.ms_type) { 2465 case e1000_ms_force_master: 2466 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2467 break; 2468 case e1000_ms_force_slave: 2469 phy_data |= CR_1000T_MS_ENABLE; 2470 phy_data &= ~(CR_1000T_MS_VALUE); 2471 break; 2472 case e1000_ms_auto: 2473 phy_data &= ~CR_1000T_MS_ENABLE; 2474 /* fall-through */ 2475 default: 2476 break; 2477 } 2478 2479 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data); 2480 } 2481