1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
3 
4 #include <linux/if_ether.h>
5 #include <linux/delay.h>
6 
7 #include "e1000_mac.h"
8 #include "e1000_phy.h"
9 
10 static s32  igb_phy_setup_autoneg(struct e1000_hw *hw);
11 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
12 					     u16 *phy_ctrl);
13 static s32  igb_wait_autoneg(struct e1000_hw *hw);
14 static s32  igb_set_master_slave_mode(struct e1000_hw *hw);
15 
16 /* Cable length tables */
17 static const u16 e1000_m88_cable_length_table[] = {
18 	0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
19 
20 static const u16 e1000_igp_2_cable_length_table[] = {
21 	0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
22 	0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
23 	6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
24 	21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
25 	40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
26 	60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
27 	83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
28 	104, 109, 114, 118, 121, 124};
29 
30 /**
31  *  igb_check_reset_block - Check if PHY reset is blocked
32  *  @hw: pointer to the HW structure
33  *
34  *  Read the PHY management control register and check whether a PHY reset
35  *  is blocked.  If a reset is not blocked return 0, otherwise
36  *  return E1000_BLK_PHY_RESET (12).
37  **/
38 s32 igb_check_reset_block(struct e1000_hw *hw)
39 {
40 	u32 manc;
41 
42 	manc = rd32(E1000_MANC);
43 
44 	return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
45 }
46 
47 /**
48  *  igb_get_phy_id - Retrieve the PHY ID and revision
49  *  @hw: pointer to the HW structure
50  *
51  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
52  *  revision in the hardware structure.
53  **/
54 s32 igb_get_phy_id(struct e1000_hw *hw)
55 {
56 	struct e1000_phy_info *phy = &hw->phy;
57 	s32 ret_val = 0;
58 	u16 phy_id;
59 
60 	/* ensure PHY page selection to fix misconfigured i210 */
61 	if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
62 		phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0);
63 
64 	ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
65 	if (ret_val)
66 		goto out;
67 
68 	phy->id = (u32)(phy_id << 16);
69 	udelay(20);
70 	ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
71 	if (ret_val)
72 		goto out;
73 
74 	phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
75 	phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
76 
77 out:
78 	return ret_val;
79 }
80 
81 /**
82  *  igb_phy_reset_dsp - Reset PHY DSP
83  *  @hw: pointer to the HW structure
84  *
85  *  Reset the digital signal processor.
86  **/
87 static s32 igb_phy_reset_dsp(struct e1000_hw *hw)
88 {
89 	s32 ret_val = 0;
90 
91 	if (!(hw->phy.ops.write_reg))
92 		goto out;
93 
94 	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
95 	if (ret_val)
96 		goto out;
97 
98 	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
99 
100 out:
101 	return ret_val;
102 }
103 
104 /**
105  *  igb_read_phy_reg_mdic - Read MDI control register
106  *  @hw: pointer to the HW structure
107  *  @offset: register offset to be read
108  *  @data: pointer to the read data
109  *
110  *  Reads the MDI control register in the PHY at offset and stores the
111  *  information read to data.
112  **/
113 s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
114 {
115 	struct e1000_phy_info *phy = &hw->phy;
116 	u32 i, mdic = 0;
117 	s32 ret_val = 0;
118 
119 	if (offset > MAX_PHY_REG_ADDRESS) {
120 		hw_dbg("PHY Address %d is out of range\n", offset);
121 		ret_val = -E1000_ERR_PARAM;
122 		goto out;
123 	}
124 
125 	/* Set up Op-code, Phy Address, and register offset in the MDI
126 	 * Control register.  The MAC will take care of interfacing with the
127 	 * PHY to retrieve the desired data.
128 	 */
129 	mdic = ((offset << E1000_MDIC_REG_SHIFT) |
130 		(phy->addr << E1000_MDIC_PHY_SHIFT) |
131 		(E1000_MDIC_OP_READ));
132 
133 	wr32(E1000_MDIC, mdic);
134 
135 	/* Poll the ready bit to see if the MDI read completed
136 	 * Increasing the time out as testing showed failures with
137 	 * the lower time out
138 	 */
139 	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
140 		udelay(50);
141 		mdic = rd32(E1000_MDIC);
142 		if (mdic & E1000_MDIC_READY)
143 			break;
144 	}
145 	if (!(mdic & E1000_MDIC_READY)) {
146 		hw_dbg("MDI Read did not complete\n");
147 		ret_val = -E1000_ERR_PHY;
148 		goto out;
149 	}
150 	if (mdic & E1000_MDIC_ERROR) {
151 		hw_dbg("MDI Error\n");
152 		ret_val = -E1000_ERR_PHY;
153 		goto out;
154 	}
155 	*data = (u16) mdic;
156 
157 out:
158 	return ret_val;
159 }
160 
161 /**
162  *  igb_write_phy_reg_mdic - Write MDI control register
163  *  @hw: pointer to the HW structure
164  *  @offset: register offset to write to
165  *  @data: data to write to register at offset
166  *
167  *  Writes data to MDI control register in the PHY at offset.
168  **/
169 s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
170 {
171 	struct e1000_phy_info *phy = &hw->phy;
172 	u32 i, mdic = 0;
173 	s32 ret_val = 0;
174 
175 	if (offset > MAX_PHY_REG_ADDRESS) {
176 		hw_dbg("PHY Address %d is out of range\n", offset);
177 		ret_val = -E1000_ERR_PARAM;
178 		goto out;
179 	}
180 
181 	/* Set up Op-code, Phy Address, and register offset in the MDI
182 	 * Control register.  The MAC will take care of interfacing with the
183 	 * PHY to retrieve the desired data.
184 	 */
185 	mdic = (((u32)data) |
186 		(offset << E1000_MDIC_REG_SHIFT) |
187 		(phy->addr << E1000_MDIC_PHY_SHIFT) |
188 		(E1000_MDIC_OP_WRITE));
189 
190 	wr32(E1000_MDIC, mdic);
191 
192 	/* Poll the ready bit to see if the MDI read completed
193 	 * Increasing the time out as testing showed failures with
194 	 * the lower time out
195 	 */
196 	for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
197 		udelay(50);
198 		mdic = rd32(E1000_MDIC);
199 		if (mdic & E1000_MDIC_READY)
200 			break;
201 	}
202 	if (!(mdic & E1000_MDIC_READY)) {
203 		hw_dbg("MDI Write did not complete\n");
204 		ret_val = -E1000_ERR_PHY;
205 		goto out;
206 	}
207 	if (mdic & E1000_MDIC_ERROR) {
208 		hw_dbg("MDI Error\n");
209 		ret_val = -E1000_ERR_PHY;
210 		goto out;
211 	}
212 
213 out:
214 	return ret_val;
215 }
216 
217 /**
218  *  igb_read_phy_reg_i2c - Read PHY register using i2c
219  *  @hw: pointer to the HW structure
220  *  @offset: register offset to be read
221  *  @data: pointer to the read data
222  *
223  *  Reads the PHY register at offset using the i2c interface and stores the
224  *  retrieved information in data.
225  **/
226 s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
227 {
228 	struct e1000_phy_info *phy = &hw->phy;
229 	u32 i, i2ccmd = 0;
230 
231 	/* Set up Op-code, Phy Address, and register address in the I2CCMD
232 	 * register.  The MAC will take care of interfacing with the
233 	 * PHY to retrieve the desired data.
234 	 */
235 	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
236 		  (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
237 		  (E1000_I2CCMD_OPCODE_READ));
238 
239 	wr32(E1000_I2CCMD, i2ccmd);
240 
241 	/* Poll the ready bit to see if the I2C read completed */
242 	for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
243 		udelay(50);
244 		i2ccmd = rd32(E1000_I2CCMD);
245 		if (i2ccmd & E1000_I2CCMD_READY)
246 			break;
247 	}
248 	if (!(i2ccmd & E1000_I2CCMD_READY)) {
249 		hw_dbg("I2CCMD Read did not complete\n");
250 		return -E1000_ERR_PHY;
251 	}
252 	if (i2ccmd & E1000_I2CCMD_ERROR) {
253 		hw_dbg("I2CCMD Error bit set\n");
254 		return -E1000_ERR_PHY;
255 	}
256 
257 	/* Need to byte-swap the 16-bit value. */
258 	*data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
259 
260 	return 0;
261 }
262 
263 /**
264  *  igb_write_phy_reg_i2c - Write PHY register using i2c
265  *  @hw: pointer to the HW structure
266  *  @offset: register offset to write to
267  *  @data: data to write at register offset
268  *
269  *  Writes the data to PHY register at the offset using the i2c interface.
270  **/
271 s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
272 {
273 	struct e1000_phy_info *phy = &hw->phy;
274 	u32 i, i2ccmd = 0;
275 	u16 phy_data_swapped;
276 
277 	/* Prevent overwriting SFP I2C EEPROM which is at A0 address.*/
278 	if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
279 		hw_dbg("PHY I2C Address %d is out of range.\n",
280 			  hw->phy.addr);
281 		return -E1000_ERR_CONFIG;
282 	}
283 
284 	/* Swap the data bytes for the I2C interface */
285 	phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
286 
287 	/* Set up Op-code, Phy Address, and register address in the I2CCMD
288 	 * register.  The MAC will take care of interfacing with the
289 	 * PHY to retrieve the desired data.
290 	 */
291 	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
292 		  (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
293 		  E1000_I2CCMD_OPCODE_WRITE |
294 		  phy_data_swapped);
295 
296 	wr32(E1000_I2CCMD, i2ccmd);
297 
298 	/* Poll the ready bit to see if the I2C read completed */
299 	for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
300 		udelay(50);
301 		i2ccmd = rd32(E1000_I2CCMD);
302 		if (i2ccmd & E1000_I2CCMD_READY)
303 			break;
304 	}
305 	if (!(i2ccmd & E1000_I2CCMD_READY)) {
306 		hw_dbg("I2CCMD Write did not complete\n");
307 		return -E1000_ERR_PHY;
308 	}
309 	if (i2ccmd & E1000_I2CCMD_ERROR) {
310 		hw_dbg("I2CCMD Error bit set\n");
311 		return -E1000_ERR_PHY;
312 	}
313 
314 	return 0;
315 }
316 
317 /**
318  *  igb_read_sfp_data_byte - Reads SFP module data.
319  *  @hw: pointer to the HW structure
320  *  @offset: byte location offset to be read
321  *  @data: read data buffer pointer
322  *
323  *  Reads one byte from SFP module data stored
324  *  in SFP resided EEPROM memory or SFP diagnostic area.
325  *  Function should be called with
326  *  E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
327  *  E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
328  *  access
329  **/
330 s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data)
331 {
332 	u32 i = 0;
333 	u32 i2ccmd = 0;
334 	u32 data_local = 0;
335 
336 	if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) {
337 		hw_dbg("I2CCMD command address exceeds upper limit\n");
338 		return -E1000_ERR_PHY;
339 	}
340 
341 	/* Set up Op-code, EEPROM Address,in the I2CCMD
342 	 * register. The MAC will take care of interfacing with the
343 	 * EEPROM to retrieve the desired data.
344 	 */
345 	i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
346 		  E1000_I2CCMD_OPCODE_READ);
347 
348 	wr32(E1000_I2CCMD, i2ccmd);
349 
350 	/* Poll the ready bit to see if the I2C read completed */
351 	for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
352 		udelay(50);
353 		data_local = rd32(E1000_I2CCMD);
354 		if (data_local & E1000_I2CCMD_READY)
355 			break;
356 	}
357 	if (!(data_local & E1000_I2CCMD_READY)) {
358 		hw_dbg("I2CCMD Read did not complete\n");
359 		return -E1000_ERR_PHY;
360 	}
361 	if (data_local & E1000_I2CCMD_ERROR) {
362 		hw_dbg("I2CCMD Error bit set\n");
363 		return -E1000_ERR_PHY;
364 	}
365 	*data = (u8) data_local & 0xFF;
366 
367 	return 0;
368 }
369 
370 /**
371  *  igb_read_phy_reg_igp - Read igp PHY register
372  *  @hw: pointer to the HW structure
373  *  @offset: register offset to be read
374  *  @data: pointer to the read data
375  *
376  *  Acquires semaphore, if necessary, then reads the PHY register at offset
377  *  and storing the retrieved information in data.  Release any acquired
378  *  semaphores before exiting.
379  **/
380 s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
381 {
382 	s32 ret_val = 0;
383 
384 	if (!(hw->phy.ops.acquire))
385 		goto out;
386 
387 	ret_val = hw->phy.ops.acquire(hw);
388 	if (ret_val)
389 		goto out;
390 
391 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
392 		ret_val = igb_write_phy_reg_mdic(hw,
393 						 IGP01E1000_PHY_PAGE_SELECT,
394 						 (u16)offset);
395 		if (ret_val) {
396 			hw->phy.ops.release(hw);
397 			goto out;
398 		}
399 	}
400 
401 	ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
402 					data);
403 
404 	hw->phy.ops.release(hw);
405 
406 out:
407 	return ret_val;
408 }
409 
410 /**
411  *  igb_write_phy_reg_igp - Write igp PHY register
412  *  @hw: pointer to the HW structure
413  *  @offset: register offset to write to
414  *  @data: data to write at register offset
415  *
416  *  Acquires semaphore, if necessary, then writes the data to PHY register
417  *  at the offset.  Release any acquired semaphores before exiting.
418  **/
419 s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
420 {
421 	s32 ret_val = 0;
422 
423 	if (!(hw->phy.ops.acquire))
424 		goto out;
425 
426 	ret_val = hw->phy.ops.acquire(hw);
427 	if (ret_val)
428 		goto out;
429 
430 	if (offset > MAX_PHY_MULTI_PAGE_REG) {
431 		ret_val = igb_write_phy_reg_mdic(hw,
432 						 IGP01E1000_PHY_PAGE_SELECT,
433 						 (u16)offset);
434 		if (ret_val) {
435 			hw->phy.ops.release(hw);
436 			goto out;
437 		}
438 	}
439 
440 	ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
441 					 data);
442 
443 	hw->phy.ops.release(hw);
444 
445 out:
446 	return ret_val;
447 }
448 
449 /**
450  *  igb_copper_link_setup_82580 - Setup 82580 PHY for copper link
451  *  @hw: pointer to the HW structure
452  *
453  *  Sets up Carrier-sense on Transmit and downshift values.
454  **/
455 s32 igb_copper_link_setup_82580(struct e1000_hw *hw)
456 {
457 	struct e1000_phy_info *phy = &hw->phy;
458 	s32 ret_val;
459 	u16 phy_data;
460 
461 	if (phy->reset_disable) {
462 		ret_val = 0;
463 		goto out;
464 	}
465 
466 	if (phy->type == e1000_phy_82580) {
467 		ret_val = hw->phy.ops.reset(hw);
468 		if (ret_val) {
469 			hw_dbg("Error resetting the PHY.\n");
470 			goto out;
471 		}
472 	}
473 
474 	/* Enable CRS on TX. This must be set for half-duplex operation. */
475 	ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data);
476 	if (ret_val)
477 		goto out;
478 
479 	phy_data |= I82580_CFG_ASSERT_CRS_ON_TX;
480 
481 	/* Enable downshift */
482 	phy_data |= I82580_CFG_ENABLE_DOWNSHIFT;
483 
484 	ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data);
485 	if (ret_val)
486 		goto out;
487 
488 	/* Set MDI/MDIX mode */
489 	ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
490 	if (ret_val)
491 		goto out;
492 	phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
493 	/* Options:
494 	 *   0 - Auto (default)
495 	 *   1 - MDI mode
496 	 *   2 - MDI-X mode
497 	 */
498 	switch (hw->phy.mdix) {
499 	case 1:
500 		break;
501 	case 2:
502 		phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX;
503 		break;
504 	case 0:
505 	default:
506 		phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX;
507 		break;
508 	}
509 	ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
510 
511 out:
512 	return ret_val;
513 }
514 
515 /**
516  *  igb_copper_link_setup_m88 - Setup m88 PHY's for copper link
517  *  @hw: pointer to the HW structure
518  *
519  *  Sets up MDI/MDI-X and polarity for m88 PHY's.  If necessary, transmit clock
520  *  and downshift values are set also.
521  **/
522 s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
523 {
524 	struct e1000_phy_info *phy = &hw->phy;
525 	s32 ret_val;
526 	u16 phy_data;
527 
528 	if (phy->reset_disable) {
529 		ret_val = 0;
530 		goto out;
531 	}
532 
533 	/* Enable CRS on TX. This must be set for half-duplex operation. */
534 	ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
535 	if (ret_val)
536 		goto out;
537 
538 	phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
539 
540 	/* Options:
541 	 *   MDI/MDI-X = 0 (default)
542 	 *   0 - Auto for all speeds
543 	 *   1 - MDI mode
544 	 *   2 - MDI-X mode
545 	 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
546 	 */
547 	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
548 
549 	switch (phy->mdix) {
550 	case 1:
551 		phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
552 		break;
553 	case 2:
554 		phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
555 		break;
556 	case 3:
557 		phy_data |= M88E1000_PSCR_AUTO_X_1000T;
558 		break;
559 	case 0:
560 	default:
561 		phy_data |= M88E1000_PSCR_AUTO_X_MODE;
562 		break;
563 	}
564 
565 	/* Options:
566 	 *   disable_polarity_correction = 0 (default)
567 	 *       Automatic Correction for Reversed Cable Polarity
568 	 *   0 - Disabled
569 	 *   1 - Enabled
570 	 */
571 	phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
572 	if (phy->disable_polarity_correction == 1)
573 		phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
574 
575 	ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
576 	if (ret_val)
577 		goto out;
578 
579 	if (phy->revision < E1000_REVISION_4) {
580 		/* Force TX_CLK in the Extended PHY Specific Control Register
581 		 * to 25MHz clock.
582 		 */
583 		ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
584 					    &phy_data);
585 		if (ret_val)
586 			goto out;
587 
588 		phy_data |= M88E1000_EPSCR_TX_CLK_25;
589 
590 		if ((phy->revision == E1000_REVISION_2) &&
591 		    (phy->id == M88E1111_I_PHY_ID)) {
592 			/* 82573L PHY - set the downshift counter to 5x. */
593 			phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
594 			phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
595 		} else {
596 			/* Configure Master and Slave downshift values */
597 			phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
598 				      M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
599 			phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
600 				     M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
601 		}
602 		ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
603 					     phy_data);
604 		if (ret_val)
605 			goto out;
606 	}
607 
608 	/* Commit the changes. */
609 	ret_val = igb_phy_sw_reset(hw);
610 	if (ret_val) {
611 		hw_dbg("Error committing the PHY changes\n");
612 		goto out;
613 	}
614 
615 out:
616 	return ret_val;
617 }
618 
619 /**
620  *  igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
621  *  @hw: pointer to the HW structure
622  *
623  *  Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
624  *  Also enables and sets the downshift parameters.
625  **/
626 s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw)
627 {
628 	struct e1000_phy_info *phy = &hw->phy;
629 	s32 ret_val;
630 	u16 phy_data;
631 
632 	if (phy->reset_disable)
633 		return 0;
634 
635 	/* Enable CRS on Tx. This must be set for half-duplex operation. */
636 	ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
637 	if (ret_val)
638 		return ret_val;
639 
640 	/* Options:
641 	 *   MDI/MDI-X = 0 (default)
642 	 *   0 - Auto for all speeds
643 	 *   1 - MDI mode
644 	 *   2 - MDI-X mode
645 	 *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
646 	 */
647 	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
648 
649 	switch (phy->mdix) {
650 	case 1:
651 		phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
652 		break;
653 	case 2:
654 		phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
655 		break;
656 	case 3:
657 		/* M88E1112 does not support this mode) */
658 		if (phy->id != M88E1112_E_PHY_ID) {
659 			phy_data |= M88E1000_PSCR_AUTO_X_1000T;
660 			break;
661 		}
662 		/* fall through */
663 	case 0:
664 	default:
665 		phy_data |= M88E1000_PSCR_AUTO_X_MODE;
666 		break;
667 	}
668 
669 	/* Options:
670 	 *   disable_polarity_correction = 0 (default)
671 	 *       Automatic Correction for Reversed Cable Polarity
672 	 *   0 - Disabled
673 	 *   1 - Enabled
674 	 */
675 	phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
676 	if (phy->disable_polarity_correction == 1)
677 		phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
678 
679 	/* Enable downshift and setting it to X6 */
680 	if (phy->id == M88E1543_E_PHY_ID) {
681 		phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
682 		ret_val =
683 		    phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
684 		if (ret_val)
685 			return ret_val;
686 
687 		ret_val = igb_phy_sw_reset(hw);
688 		if (ret_val) {
689 			hw_dbg("Error committing the PHY changes\n");
690 			return ret_val;
691 		}
692 	}
693 
694 	phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
695 	phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
696 	phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
697 
698 	ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
699 	if (ret_val)
700 		return ret_val;
701 
702 	/* Commit the changes. */
703 	ret_val = igb_phy_sw_reset(hw);
704 	if (ret_val) {
705 		hw_dbg("Error committing the PHY changes\n");
706 		return ret_val;
707 	}
708 	ret_val = igb_set_master_slave_mode(hw);
709 	if (ret_val)
710 		return ret_val;
711 
712 	return 0;
713 }
714 
715 /**
716  *  igb_copper_link_setup_igp - Setup igp PHY's for copper link
717  *  @hw: pointer to the HW structure
718  *
719  *  Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
720  *  igp PHY's.
721  **/
722 s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
723 {
724 	struct e1000_phy_info *phy = &hw->phy;
725 	s32 ret_val;
726 	u16 data;
727 
728 	if (phy->reset_disable) {
729 		ret_val = 0;
730 		goto out;
731 	}
732 
733 	ret_val = phy->ops.reset(hw);
734 	if (ret_val) {
735 		hw_dbg("Error resetting the PHY.\n");
736 		goto out;
737 	}
738 
739 	/* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
740 	 * timeout issues when LFS is enabled.
741 	 */
742 	msleep(100);
743 
744 	/* The NVM settings will configure LPLU in D3 for
745 	 * non-IGP1 PHYs.
746 	 */
747 	if (phy->type == e1000_phy_igp) {
748 		/* disable lplu d3 during driver init */
749 		if (phy->ops.set_d3_lplu_state)
750 			ret_val = phy->ops.set_d3_lplu_state(hw, false);
751 		if (ret_val) {
752 			hw_dbg("Error Disabling LPLU D3\n");
753 			goto out;
754 		}
755 	}
756 
757 	/* disable lplu d0 during driver init */
758 	ret_val = phy->ops.set_d0_lplu_state(hw, false);
759 	if (ret_val) {
760 		hw_dbg("Error Disabling LPLU D0\n");
761 		goto out;
762 	}
763 	/* Configure mdi-mdix settings */
764 	ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
765 	if (ret_val)
766 		goto out;
767 
768 	data &= ~IGP01E1000_PSCR_AUTO_MDIX;
769 
770 	switch (phy->mdix) {
771 	case 1:
772 		data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
773 		break;
774 	case 2:
775 		data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
776 		break;
777 	case 0:
778 	default:
779 		data |= IGP01E1000_PSCR_AUTO_MDIX;
780 		break;
781 	}
782 	ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
783 	if (ret_val)
784 		goto out;
785 
786 	/* set auto-master slave resolution settings */
787 	if (hw->mac.autoneg) {
788 		/* when autonegotiation advertisement is only 1000Mbps then we
789 		 * should disable SmartSpeed and enable Auto MasterSlave
790 		 * resolution as hardware default.
791 		 */
792 		if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
793 			/* Disable SmartSpeed */
794 			ret_val = phy->ops.read_reg(hw,
795 						    IGP01E1000_PHY_PORT_CONFIG,
796 						    &data);
797 			if (ret_val)
798 				goto out;
799 
800 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
801 			ret_val = phy->ops.write_reg(hw,
802 						     IGP01E1000_PHY_PORT_CONFIG,
803 						     data);
804 			if (ret_val)
805 				goto out;
806 
807 			/* Set auto Master/Slave resolution process */
808 			ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
809 			if (ret_val)
810 				goto out;
811 
812 			data &= ~CR_1000T_MS_ENABLE;
813 			ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
814 			if (ret_val)
815 				goto out;
816 		}
817 
818 		ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
819 		if (ret_val)
820 			goto out;
821 
822 		/* load defaults for future use */
823 		phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
824 			((data & CR_1000T_MS_VALUE) ?
825 			e1000_ms_force_master :
826 			e1000_ms_force_slave) :
827 			e1000_ms_auto;
828 
829 		switch (phy->ms_type) {
830 		case e1000_ms_force_master:
831 			data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
832 			break;
833 		case e1000_ms_force_slave:
834 			data |= CR_1000T_MS_ENABLE;
835 			data &= ~(CR_1000T_MS_VALUE);
836 			break;
837 		case e1000_ms_auto:
838 			data &= ~CR_1000T_MS_ENABLE;
839 		default:
840 			break;
841 		}
842 		ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
843 		if (ret_val)
844 			goto out;
845 	}
846 
847 out:
848 	return ret_val;
849 }
850 
851 /**
852  *  igb_copper_link_autoneg - Setup/Enable autoneg for copper link
853  *  @hw: pointer to the HW structure
854  *
855  *  Performs initial bounds checking on autoneg advertisement parameter, then
856  *  configure to advertise the full capability.  Setup the PHY to autoneg
857  *  and restart the negotiation process between the link partner.  If
858  *  autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
859  **/
860 static s32 igb_copper_link_autoneg(struct e1000_hw *hw)
861 {
862 	struct e1000_phy_info *phy = &hw->phy;
863 	s32 ret_val;
864 	u16 phy_ctrl;
865 
866 	/* Perform some bounds checking on the autoneg advertisement
867 	 * parameter.
868 	 */
869 	phy->autoneg_advertised &= phy->autoneg_mask;
870 
871 	/* If autoneg_advertised is zero, we assume it was not defaulted
872 	 * by the calling code so we set to advertise full capability.
873 	 */
874 	if (phy->autoneg_advertised == 0)
875 		phy->autoneg_advertised = phy->autoneg_mask;
876 
877 	hw_dbg("Reconfiguring auto-neg advertisement params\n");
878 	ret_val = igb_phy_setup_autoneg(hw);
879 	if (ret_val) {
880 		hw_dbg("Error Setting up Auto-Negotiation\n");
881 		goto out;
882 	}
883 	hw_dbg("Restarting Auto-Neg\n");
884 
885 	/* Restart auto-negotiation by setting the Auto Neg Enable bit and
886 	 * the Auto Neg Restart bit in the PHY control register.
887 	 */
888 	ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
889 	if (ret_val)
890 		goto out;
891 
892 	phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
893 	ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
894 	if (ret_val)
895 		goto out;
896 
897 	/* Does the user want to wait for Auto-Neg to complete here, or
898 	 * check at a later time (for example, callback routine).
899 	 */
900 	if (phy->autoneg_wait_to_complete) {
901 		ret_val = igb_wait_autoneg(hw);
902 		if (ret_val) {
903 			hw_dbg("Error while waiting for autoneg to complete\n");
904 			goto out;
905 		}
906 	}
907 
908 	hw->mac.get_link_status = true;
909 
910 out:
911 	return ret_val;
912 }
913 
914 /**
915  *  igb_phy_setup_autoneg - Configure PHY for auto-negotiation
916  *  @hw: pointer to the HW structure
917  *
918  *  Reads the MII auto-neg advertisement register and/or the 1000T control
919  *  register and if the PHY is already setup for auto-negotiation, then
920  *  return successful.  Otherwise, setup advertisement and flow control to
921  *  the appropriate values for the wanted auto-negotiation.
922  **/
923 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
924 {
925 	struct e1000_phy_info *phy = &hw->phy;
926 	s32 ret_val;
927 	u16 mii_autoneg_adv_reg;
928 	u16 mii_1000t_ctrl_reg = 0;
929 
930 	phy->autoneg_advertised &= phy->autoneg_mask;
931 
932 	/* Read the MII Auto-Neg Advertisement Register (Address 4). */
933 	ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
934 	if (ret_val)
935 		goto out;
936 
937 	if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
938 		/* Read the MII 1000Base-T Control Register (Address 9). */
939 		ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
940 					    &mii_1000t_ctrl_reg);
941 		if (ret_val)
942 			goto out;
943 	}
944 
945 	/* Need to parse both autoneg_advertised and fc and set up
946 	 * the appropriate PHY registers.  First we will parse for
947 	 * autoneg_advertised software override.  Since we can advertise
948 	 * a plethora of combinations, we need to check each bit
949 	 * individually.
950 	 */
951 
952 	/* First we clear all the 10/100 mb speed bits in the Auto-Neg
953 	 * Advertisement Register (Address 4) and the 1000 mb speed bits in
954 	 * the  1000Base-T Control Register (Address 9).
955 	 */
956 	mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
957 				 NWAY_AR_100TX_HD_CAPS |
958 				 NWAY_AR_10T_FD_CAPS   |
959 				 NWAY_AR_10T_HD_CAPS);
960 	mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
961 
962 	hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
963 
964 	/* Do we want to advertise 10 Mb Half Duplex? */
965 	if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
966 		hw_dbg("Advertise 10mb Half duplex\n");
967 		mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
968 	}
969 
970 	/* Do we want to advertise 10 Mb Full Duplex? */
971 	if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
972 		hw_dbg("Advertise 10mb Full duplex\n");
973 		mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
974 	}
975 
976 	/* Do we want to advertise 100 Mb Half Duplex? */
977 	if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
978 		hw_dbg("Advertise 100mb Half duplex\n");
979 		mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
980 	}
981 
982 	/* Do we want to advertise 100 Mb Full Duplex? */
983 	if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
984 		hw_dbg("Advertise 100mb Full duplex\n");
985 		mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
986 	}
987 
988 	/* We do not allow the Phy to advertise 1000 Mb Half Duplex */
989 	if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
990 		hw_dbg("Advertise 1000mb Half duplex request denied!\n");
991 
992 	/* Do we want to advertise 1000 Mb Full Duplex? */
993 	if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
994 		hw_dbg("Advertise 1000mb Full duplex\n");
995 		mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
996 	}
997 
998 	/* Check for a software override of the flow control settings, and
999 	 * setup the PHY advertisement registers accordingly.  If
1000 	 * auto-negotiation is enabled, then software will have to set the
1001 	 * "PAUSE" bits to the correct value in the Auto-Negotiation
1002 	 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1003 	 * negotiation.
1004 	 *
1005 	 * The possible values of the "fc" parameter are:
1006 	 *      0:  Flow control is completely disabled
1007 	 *      1:  Rx flow control is enabled (we can receive pause frames
1008 	 *          but not send pause frames).
1009 	 *      2:  Tx flow control is enabled (we can send pause frames
1010 	 *          but we do not support receiving pause frames).
1011 	 *      3:  Both Rx and TX flow control (symmetric) are enabled.
1012 	 *  other:  No software override.  The flow control configuration
1013 	 *          in the EEPROM is used.
1014 	 */
1015 	switch (hw->fc.current_mode) {
1016 	case e1000_fc_none:
1017 		/* Flow control (RX & TX) is completely disabled by a
1018 		 * software over-ride.
1019 		 */
1020 		mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1021 		break;
1022 	case e1000_fc_rx_pause:
1023 		/* RX Flow control is enabled, and TX Flow control is
1024 		 * disabled, by a software over-ride.
1025 		 *
1026 		 * Since there really isn't a way to advertise that we are
1027 		 * capable of RX Pause ONLY, we will advertise that we
1028 		 * support both symmetric and asymmetric RX PAUSE.  Later
1029 		 * (in e1000_config_fc_after_link_up) we will disable the
1030 		 * hw's ability to send PAUSE frames.
1031 		 */
1032 		mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1033 		break;
1034 	case e1000_fc_tx_pause:
1035 		/* TX Flow control is enabled, and RX Flow control is
1036 		 * disabled, by a software over-ride.
1037 		 */
1038 		mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1039 		mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1040 		break;
1041 	case e1000_fc_full:
1042 		/* Flow control (both RX and TX) is enabled by a software
1043 		 * over-ride.
1044 		 */
1045 		mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1046 		break;
1047 	default:
1048 		hw_dbg("Flow control param set incorrectly\n");
1049 		ret_val = -E1000_ERR_CONFIG;
1050 		goto out;
1051 	}
1052 
1053 	ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1054 	if (ret_val)
1055 		goto out;
1056 
1057 	hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1058 
1059 	if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1060 		ret_val = phy->ops.write_reg(hw,
1061 					     PHY_1000T_CTRL,
1062 					     mii_1000t_ctrl_reg);
1063 		if (ret_val)
1064 			goto out;
1065 	}
1066 
1067 out:
1068 	return ret_val;
1069 }
1070 
1071 /**
1072  *  igb_setup_copper_link - Configure copper link settings
1073  *  @hw: pointer to the HW structure
1074  *
1075  *  Calls the appropriate function to configure the link for auto-neg or forced
1076  *  speed and duplex.  Then we check for link, once link is established calls
1077  *  to configure collision distance and flow control are called.  If link is
1078  *  not established, we return -E1000_ERR_PHY (-2).
1079  **/
1080 s32 igb_setup_copper_link(struct e1000_hw *hw)
1081 {
1082 	s32 ret_val;
1083 	bool link;
1084 
1085 	if (hw->mac.autoneg) {
1086 		/* Setup autoneg and flow control advertisement and perform
1087 		 * autonegotiation.
1088 		 */
1089 		ret_val = igb_copper_link_autoneg(hw);
1090 		if (ret_val)
1091 			goto out;
1092 	} else {
1093 		/* PHY will be set to 10H, 10F, 100H or 100F
1094 		 * depending on user settings.
1095 		 */
1096 		hw_dbg("Forcing Speed and Duplex\n");
1097 		ret_val = hw->phy.ops.force_speed_duplex(hw);
1098 		if (ret_val) {
1099 			hw_dbg("Error Forcing Speed and Duplex\n");
1100 			goto out;
1101 		}
1102 	}
1103 
1104 	/* Check link status. Wait up to 100 microseconds for link to become
1105 	 * valid.
1106 	 */
1107 	ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link);
1108 	if (ret_val)
1109 		goto out;
1110 
1111 	if (link) {
1112 		hw_dbg("Valid link established!!!\n");
1113 		igb_config_collision_dist(hw);
1114 		ret_val = igb_config_fc_after_link_up(hw);
1115 	} else {
1116 		hw_dbg("Unable to establish link!!!\n");
1117 	}
1118 
1119 out:
1120 	return ret_val;
1121 }
1122 
1123 /**
1124  *  igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1125  *  @hw: pointer to the HW structure
1126  *
1127  *  Calls the PHY setup function to force speed and duplex.  Clears the
1128  *  auto-crossover to force MDI manually.  Waits for link and returns
1129  *  successful if link up is successful, else -E1000_ERR_PHY (-2).
1130  **/
1131 s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1132 {
1133 	struct e1000_phy_info *phy = &hw->phy;
1134 	s32 ret_val;
1135 	u16 phy_data;
1136 	bool link;
1137 
1138 	ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1139 	if (ret_val)
1140 		goto out;
1141 
1142 	igb_phy_force_speed_duplex_setup(hw, &phy_data);
1143 
1144 	ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1145 	if (ret_val)
1146 		goto out;
1147 
1148 	/* Clear Auto-Crossover to force MDI manually.  IGP requires MDI
1149 	 * forced whenever speed and duplex are forced.
1150 	 */
1151 	ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1152 	if (ret_val)
1153 		goto out;
1154 
1155 	phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1156 	phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1157 
1158 	ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1159 	if (ret_val)
1160 		goto out;
1161 
1162 	hw_dbg("IGP PSCR: %X\n", phy_data);
1163 
1164 	udelay(1);
1165 
1166 	if (phy->autoneg_wait_to_complete) {
1167 		hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1168 
1169 		ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
1170 		if (ret_val)
1171 			goto out;
1172 
1173 		if (!link)
1174 			hw_dbg("Link taking longer than expected.\n");
1175 
1176 		/* Try once more */
1177 		ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
1178 		if (ret_val)
1179 			goto out;
1180 	}
1181 
1182 out:
1183 	return ret_val;
1184 }
1185 
1186 /**
1187  *  igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1188  *  @hw: pointer to the HW structure
1189  *
1190  *  Calls the PHY setup function to force speed and duplex.  Clears the
1191  *  auto-crossover to force MDI manually.  Resets the PHY to commit the
1192  *  changes.  If time expires while waiting for link up, we reset the DSP.
1193  *  After reset, TX_CLK and CRS on TX must be set.  Return successful upon
1194  *  successful completion, else return corresponding error code.
1195  **/
1196 s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1197 {
1198 	struct e1000_phy_info *phy = &hw->phy;
1199 	s32 ret_val;
1200 	u16 phy_data;
1201 	bool link;
1202 
1203 	/* I210 and I211 devices support Auto-Crossover in forced operation. */
1204 	if (phy->type != e1000_phy_i210) {
1205 		/* Clear Auto-Crossover to force MDI manually.  M88E1000
1206 		 * requires MDI forced whenever speed and duplex are forced.
1207 		 */
1208 		ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1209 					    &phy_data);
1210 		if (ret_val)
1211 			goto out;
1212 
1213 		phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1214 		ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1215 					     phy_data);
1216 		if (ret_val)
1217 			goto out;
1218 
1219 		hw_dbg("M88E1000 PSCR: %X\n", phy_data);
1220 	}
1221 
1222 	ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1223 	if (ret_val)
1224 		goto out;
1225 
1226 	igb_phy_force_speed_duplex_setup(hw, &phy_data);
1227 
1228 	ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1229 	if (ret_val)
1230 		goto out;
1231 
1232 	/* Reset the phy to commit changes. */
1233 	ret_val = igb_phy_sw_reset(hw);
1234 	if (ret_val)
1235 		goto out;
1236 
1237 	if (phy->autoneg_wait_to_complete) {
1238 		hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1239 
1240 		ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
1241 		if (ret_val)
1242 			goto out;
1243 
1244 		if (!link) {
1245 			bool reset_dsp = true;
1246 
1247 			switch (hw->phy.id) {
1248 			case I347AT4_E_PHY_ID:
1249 			case M88E1112_E_PHY_ID:
1250 			case M88E1543_E_PHY_ID:
1251 			case M88E1512_E_PHY_ID:
1252 			case I210_I_PHY_ID:
1253 				reset_dsp = false;
1254 				break;
1255 			default:
1256 				if (hw->phy.type != e1000_phy_m88)
1257 					reset_dsp = false;
1258 				break;
1259 			}
1260 			if (!reset_dsp) {
1261 				hw_dbg("Link taking longer than expected.\n");
1262 			} else {
1263 				/* We didn't get link.
1264 				 * Reset the DSP and cross our fingers.
1265 				 */
1266 				ret_val = phy->ops.write_reg(hw,
1267 						M88E1000_PHY_PAGE_SELECT,
1268 						0x001d);
1269 				if (ret_val)
1270 					goto out;
1271 				ret_val = igb_phy_reset_dsp(hw);
1272 				if (ret_val)
1273 					goto out;
1274 			}
1275 		}
1276 
1277 		/* Try once more */
1278 		ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT,
1279 					   100000, &link);
1280 		if (ret_val)
1281 			goto out;
1282 	}
1283 
1284 	if (hw->phy.type != e1000_phy_m88 ||
1285 	    hw->phy.id == I347AT4_E_PHY_ID ||
1286 	    hw->phy.id == M88E1112_E_PHY_ID ||
1287 	    hw->phy.id == M88E1543_E_PHY_ID ||
1288 	    hw->phy.id == M88E1512_E_PHY_ID ||
1289 	    hw->phy.id == I210_I_PHY_ID)
1290 		goto out;
1291 
1292 	ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1293 	if (ret_val)
1294 		goto out;
1295 
1296 	/* Resetting the phy means we need to re-force TX_CLK in the
1297 	 * Extended PHY Specific Control Register to 25MHz clock from
1298 	 * the reset value of 2.5MHz.
1299 	 */
1300 	phy_data |= M88E1000_EPSCR_TX_CLK_25;
1301 	ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1302 	if (ret_val)
1303 		goto out;
1304 
1305 	/* In addition, we must re-enable CRS on Tx for both half and full
1306 	 * duplex.
1307 	 */
1308 	ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1309 	if (ret_val)
1310 		goto out;
1311 
1312 	phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1313 	ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1314 
1315 out:
1316 	return ret_val;
1317 }
1318 
1319 /**
1320  *  igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1321  *  @hw: pointer to the HW structure
1322  *  @phy_ctrl: pointer to current value of PHY_CONTROL
1323  *
1324  *  Forces speed and duplex on the PHY by doing the following: disable flow
1325  *  control, force speed/duplex on the MAC, disable auto speed detection,
1326  *  disable auto-negotiation, configure duplex, configure speed, configure
1327  *  the collision distance, write configuration to CTRL register.  The
1328  *  caller must write to the PHY_CONTROL register for these settings to
1329  *  take affect.
1330  **/
1331 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
1332 					     u16 *phy_ctrl)
1333 {
1334 	struct e1000_mac_info *mac = &hw->mac;
1335 	u32 ctrl;
1336 
1337 	/* Turn off flow control when forcing speed/duplex */
1338 	hw->fc.current_mode = e1000_fc_none;
1339 
1340 	/* Force speed/duplex on the mac */
1341 	ctrl = rd32(E1000_CTRL);
1342 	ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1343 	ctrl &= ~E1000_CTRL_SPD_SEL;
1344 
1345 	/* Disable Auto Speed Detection */
1346 	ctrl &= ~E1000_CTRL_ASDE;
1347 
1348 	/* Disable autoneg on the phy */
1349 	*phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1350 
1351 	/* Forcing Full or Half Duplex? */
1352 	if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1353 		ctrl &= ~E1000_CTRL_FD;
1354 		*phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1355 		hw_dbg("Half Duplex\n");
1356 	} else {
1357 		ctrl |= E1000_CTRL_FD;
1358 		*phy_ctrl |= MII_CR_FULL_DUPLEX;
1359 		hw_dbg("Full Duplex\n");
1360 	}
1361 
1362 	/* Forcing 10mb or 100mb? */
1363 	if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1364 		ctrl |= E1000_CTRL_SPD_100;
1365 		*phy_ctrl |= MII_CR_SPEED_100;
1366 		*phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1367 		hw_dbg("Forcing 100mb\n");
1368 	} else {
1369 		ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1370 		*phy_ctrl |= MII_CR_SPEED_10;
1371 		*phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1372 		hw_dbg("Forcing 10mb\n");
1373 	}
1374 
1375 	igb_config_collision_dist(hw);
1376 
1377 	wr32(E1000_CTRL, ctrl);
1378 }
1379 
1380 /**
1381  *  igb_set_d3_lplu_state - Sets low power link up state for D3
1382  *  @hw: pointer to the HW structure
1383  *  @active: boolean used to enable/disable lplu
1384  *
1385  *  Success returns 0, Failure returns 1
1386  *
1387  *  The low power link up (lplu) state is set to the power management level D3
1388  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
1389  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
1390  *  is used during Dx states where the power conservation is most important.
1391  *  During driver activity, SmartSpeed should be enabled so performance is
1392  *  maintained.
1393  **/
1394 s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1395 {
1396 	struct e1000_phy_info *phy = &hw->phy;
1397 	s32 ret_val = 0;
1398 	u16 data;
1399 
1400 	if (!(hw->phy.ops.read_reg))
1401 		goto out;
1402 
1403 	ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1404 	if (ret_val)
1405 		goto out;
1406 
1407 	if (!active) {
1408 		data &= ~IGP02E1000_PM_D3_LPLU;
1409 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1410 					     data);
1411 		if (ret_val)
1412 			goto out;
1413 		/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1414 		 * during Dx states where the power conservation is most
1415 		 * important.  During driver activity we should enable
1416 		 * SmartSpeed, so performance is maintained.
1417 		 */
1418 		if (phy->smart_speed == e1000_smart_speed_on) {
1419 			ret_val = phy->ops.read_reg(hw,
1420 						    IGP01E1000_PHY_PORT_CONFIG,
1421 						    &data);
1422 			if (ret_val)
1423 				goto out;
1424 
1425 			data |= IGP01E1000_PSCFR_SMART_SPEED;
1426 			ret_val = phy->ops.write_reg(hw,
1427 						     IGP01E1000_PHY_PORT_CONFIG,
1428 						     data);
1429 			if (ret_val)
1430 				goto out;
1431 		} else if (phy->smart_speed == e1000_smart_speed_off) {
1432 			ret_val = phy->ops.read_reg(hw,
1433 						     IGP01E1000_PHY_PORT_CONFIG,
1434 						     &data);
1435 			if (ret_val)
1436 				goto out;
1437 
1438 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1439 			ret_val = phy->ops.write_reg(hw,
1440 						     IGP01E1000_PHY_PORT_CONFIG,
1441 						     data);
1442 			if (ret_val)
1443 				goto out;
1444 		}
1445 	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1446 		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1447 		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1448 		data |= IGP02E1000_PM_D3_LPLU;
1449 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1450 					      data);
1451 		if (ret_val)
1452 			goto out;
1453 
1454 		/* When LPLU is enabled, we should disable SmartSpeed */
1455 		ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1456 					    &data);
1457 		if (ret_val)
1458 			goto out;
1459 
1460 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1461 		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1462 					     data);
1463 	}
1464 
1465 out:
1466 	return ret_val;
1467 }
1468 
1469 /**
1470  *  igb_check_downshift - Checks whether a downshift in speed occurred
1471  *  @hw: pointer to the HW structure
1472  *
1473  *  Success returns 0, Failure returns 1
1474  *
1475  *  A downshift is detected by querying the PHY link health.
1476  **/
1477 s32 igb_check_downshift(struct e1000_hw *hw)
1478 {
1479 	struct e1000_phy_info *phy = &hw->phy;
1480 	s32 ret_val;
1481 	u16 phy_data, offset, mask;
1482 
1483 	switch (phy->type) {
1484 	case e1000_phy_i210:
1485 	case e1000_phy_m88:
1486 	case e1000_phy_gg82563:
1487 		offset	= M88E1000_PHY_SPEC_STATUS;
1488 		mask	= M88E1000_PSSR_DOWNSHIFT;
1489 		break;
1490 	case e1000_phy_igp_2:
1491 	case e1000_phy_igp:
1492 	case e1000_phy_igp_3:
1493 		offset	= IGP01E1000_PHY_LINK_HEALTH;
1494 		mask	= IGP01E1000_PLHR_SS_DOWNGRADE;
1495 		break;
1496 	default:
1497 		/* speed downshift not supported */
1498 		phy->speed_downgraded = false;
1499 		ret_val = 0;
1500 		goto out;
1501 	}
1502 
1503 	ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1504 
1505 	if (!ret_val)
1506 		phy->speed_downgraded = (phy_data & mask) ? true : false;
1507 
1508 out:
1509 	return ret_val;
1510 }
1511 
1512 /**
1513  *  igb_check_polarity_m88 - Checks the polarity.
1514  *  @hw: pointer to the HW structure
1515  *
1516  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1517  *
1518  *  Polarity is determined based on the PHY specific status register.
1519  **/
1520 s32 igb_check_polarity_m88(struct e1000_hw *hw)
1521 {
1522 	struct e1000_phy_info *phy = &hw->phy;
1523 	s32 ret_val;
1524 	u16 data;
1525 
1526 	ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1527 
1528 	if (!ret_val)
1529 		phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1530 				      ? e1000_rev_polarity_reversed
1531 				      : e1000_rev_polarity_normal;
1532 
1533 	return ret_val;
1534 }
1535 
1536 /**
1537  *  igb_check_polarity_igp - Checks the polarity.
1538  *  @hw: pointer to the HW structure
1539  *
1540  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1541  *
1542  *  Polarity is determined based on the PHY port status register, and the
1543  *  current speed (since there is no polarity at 100Mbps).
1544  **/
1545 static s32 igb_check_polarity_igp(struct e1000_hw *hw)
1546 {
1547 	struct e1000_phy_info *phy = &hw->phy;
1548 	s32 ret_val;
1549 	u16 data, offset, mask;
1550 
1551 	/* Polarity is determined based on the speed of
1552 	 * our connection.
1553 	 */
1554 	ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1555 	if (ret_val)
1556 		goto out;
1557 
1558 	if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1559 	    IGP01E1000_PSSR_SPEED_1000MBPS) {
1560 		offset	= IGP01E1000_PHY_PCS_INIT_REG;
1561 		mask	= IGP01E1000_PHY_POLARITY_MASK;
1562 	} else {
1563 		/* This really only applies to 10Mbps since
1564 		 * there is no polarity for 100Mbps (always 0).
1565 		 */
1566 		offset	= IGP01E1000_PHY_PORT_STATUS;
1567 		mask	= IGP01E1000_PSSR_POLARITY_REVERSED;
1568 	}
1569 
1570 	ret_val = phy->ops.read_reg(hw, offset, &data);
1571 
1572 	if (!ret_val)
1573 		phy->cable_polarity = (data & mask)
1574 				      ? e1000_rev_polarity_reversed
1575 				      : e1000_rev_polarity_normal;
1576 
1577 out:
1578 	return ret_val;
1579 }
1580 
1581 /**
1582  *  igb_wait_autoneg - Wait for auto-neg completion
1583  *  @hw: pointer to the HW structure
1584  *
1585  *  Waits for auto-negotiation to complete or for the auto-negotiation time
1586  *  limit to expire, which ever happens first.
1587  **/
1588 static s32 igb_wait_autoneg(struct e1000_hw *hw)
1589 {
1590 	s32 ret_val = 0;
1591 	u16 i, phy_status;
1592 
1593 	/* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1594 	for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1595 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1596 		if (ret_val)
1597 			break;
1598 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1599 		if (ret_val)
1600 			break;
1601 		if (phy_status & MII_SR_AUTONEG_COMPLETE)
1602 			break;
1603 		msleep(100);
1604 	}
1605 
1606 	/* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1607 	 * has completed.
1608 	 */
1609 	return ret_val;
1610 }
1611 
1612 /**
1613  *  igb_phy_has_link - Polls PHY for link
1614  *  @hw: pointer to the HW structure
1615  *  @iterations: number of times to poll for link
1616  *  @usec_interval: delay between polling attempts
1617  *  @success: pointer to whether polling was successful or not
1618  *
1619  *  Polls the PHY status register for link, 'iterations' number of times.
1620  **/
1621 s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
1622 		     u32 usec_interval, bool *success)
1623 {
1624 	s32 ret_val = 0;
1625 	u16 i, phy_status;
1626 
1627 	for (i = 0; i < iterations; i++) {
1628 		/* Some PHYs require the PHY_STATUS register to be read
1629 		 * twice due to the link bit being sticky.  No harm doing
1630 		 * it across the board.
1631 		 */
1632 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1633 		if (ret_val && usec_interval > 0) {
1634 			/* If the first read fails, another entity may have
1635 			 * ownership of the resources, wait and try again to
1636 			 * see if they have relinquished the resources yet.
1637 			 */
1638 			if (usec_interval >= 1000)
1639 				mdelay(usec_interval/1000);
1640 			else
1641 				udelay(usec_interval);
1642 		}
1643 		ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1644 		if (ret_val)
1645 			break;
1646 		if (phy_status & MII_SR_LINK_STATUS)
1647 			break;
1648 		if (usec_interval >= 1000)
1649 			mdelay(usec_interval/1000);
1650 		else
1651 			udelay(usec_interval);
1652 	}
1653 
1654 	*success = (i < iterations) ? true : false;
1655 
1656 	return ret_val;
1657 }
1658 
1659 /**
1660  *  igb_get_cable_length_m88 - Determine cable length for m88 PHY
1661  *  @hw: pointer to the HW structure
1662  *
1663  *  Reads the PHY specific status register to retrieve the cable length
1664  *  information.  The cable length is determined by averaging the minimum and
1665  *  maximum values to get the "average" cable length.  The m88 PHY has four
1666  *  possible cable length values, which are:
1667  *	Register Value		Cable Length
1668  *	0			< 50 meters
1669  *	1			50 - 80 meters
1670  *	2			80 - 110 meters
1671  *	3			110 - 140 meters
1672  *	4			> 140 meters
1673  **/
1674 s32 igb_get_cable_length_m88(struct e1000_hw *hw)
1675 {
1676 	struct e1000_phy_info *phy = &hw->phy;
1677 	s32 ret_val;
1678 	u16 phy_data, index;
1679 
1680 	ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1681 	if (ret_val)
1682 		goto out;
1683 
1684 	index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1685 		M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1686 	if (index >= ARRAY_SIZE(e1000_m88_cable_length_table) - 1) {
1687 		ret_val = -E1000_ERR_PHY;
1688 		goto out;
1689 	}
1690 
1691 	phy->min_cable_length = e1000_m88_cable_length_table[index];
1692 	phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1693 
1694 	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1695 
1696 out:
1697 	return ret_val;
1698 }
1699 
1700 s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw)
1701 {
1702 	struct e1000_phy_info *phy = &hw->phy;
1703 	s32 ret_val;
1704 	u16 phy_data, phy_data2, index, default_page, is_cm;
1705 	int len_tot = 0;
1706 	u16 len_min;
1707 	u16 len_max;
1708 
1709 	switch (hw->phy.id) {
1710 	case M88E1543_E_PHY_ID:
1711 	case M88E1512_E_PHY_ID:
1712 	case I347AT4_E_PHY_ID:
1713 	case I210_I_PHY_ID:
1714 		/* Remember the original page select and set it to 7 */
1715 		ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1716 					    &default_page);
1717 		if (ret_val)
1718 			goto out;
1719 
1720 		ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
1721 		if (ret_val)
1722 			goto out;
1723 
1724 		/* Check if the unit of cable length is meters or cm */
1725 		ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
1726 		if (ret_val)
1727 			goto out;
1728 
1729 		is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
1730 
1731 		/* Get cable length from Pair 0 length Regs */
1732 		ret_val = phy->ops.read_reg(hw, I347AT4_PCDL0, &phy_data);
1733 		if (ret_val)
1734 			goto out;
1735 
1736 		phy->pair_length[0] = phy_data / (is_cm ? 100 : 1);
1737 		len_tot = phy->pair_length[0];
1738 		len_min = phy->pair_length[0];
1739 		len_max = phy->pair_length[0];
1740 
1741 		/* Get cable length from Pair 1 length Regs */
1742 		ret_val = phy->ops.read_reg(hw, I347AT4_PCDL1, &phy_data);
1743 		if (ret_val)
1744 			goto out;
1745 
1746 		phy->pair_length[1] = phy_data / (is_cm ? 100 : 1);
1747 		len_tot += phy->pair_length[1];
1748 		len_min = min(len_min, phy->pair_length[1]);
1749 		len_max = max(len_max, phy->pair_length[1]);
1750 
1751 		/* Get cable length from Pair 2 length Regs */
1752 		ret_val = phy->ops.read_reg(hw, I347AT4_PCDL2, &phy_data);
1753 		if (ret_val)
1754 			goto out;
1755 
1756 		phy->pair_length[2] = phy_data / (is_cm ? 100 : 1);
1757 		len_tot += phy->pair_length[2];
1758 		len_min = min(len_min, phy->pair_length[2]);
1759 		len_max = max(len_max, phy->pair_length[2]);
1760 
1761 		/* Get cable length from Pair 3 length Regs */
1762 		ret_val = phy->ops.read_reg(hw, I347AT4_PCDL3, &phy_data);
1763 		if (ret_val)
1764 			goto out;
1765 
1766 		phy->pair_length[3] = phy_data / (is_cm ? 100 : 1);
1767 		len_tot += phy->pair_length[3];
1768 		len_min = min(len_min, phy->pair_length[3]);
1769 		len_max = max(len_max, phy->pair_length[3]);
1770 
1771 		/* Populate the phy structure with cable length in meters */
1772 		phy->min_cable_length = len_min;
1773 		phy->max_cable_length = len_max;
1774 		phy->cable_length = len_tot / 4;
1775 
1776 		/* Reset the page selec to its original value */
1777 		ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1778 					     default_page);
1779 		if (ret_val)
1780 			goto out;
1781 		break;
1782 	case M88E1112_E_PHY_ID:
1783 		/* Remember the original page select and set it to 5 */
1784 		ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1785 					    &default_page);
1786 		if (ret_val)
1787 			goto out;
1788 
1789 		ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
1790 		if (ret_val)
1791 			goto out;
1792 
1793 		ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
1794 					    &phy_data);
1795 		if (ret_val)
1796 			goto out;
1797 
1798 		index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1799 			M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1800 		if (index >= ARRAY_SIZE(e1000_m88_cable_length_table) - 1) {
1801 			ret_val = -E1000_ERR_PHY;
1802 			goto out;
1803 		}
1804 
1805 		phy->min_cable_length = e1000_m88_cable_length_table[index];
1806 		phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1807 
1808 		phy->cable_length = (phy->min_cable_length +
1809 				     phy->max_cable_length) / 2;
1810 
1811 		/* Reset the page select to its original value */
1812 		ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1813 					     default_page);
1814 		if (ret_val)
1815 			goto out;
1816 
1817 		break;
1818 	default:
1819 		ret_val = -E1000_ERR_PHY;
1820 		goto out;
1821 	}
1822 
1823 out:
1824 	return ret_val;
1825 }
1826 
1827 /**
1828  *  igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1829  *  @hw: pointer to the HW structure
1830  *
1831  *  The automatic gain control (agc) normalizes the amplitude of the
1832  *  received signal, adjusting for the attenuation produced by the
1833  *  cable.  By reading the AGC registers, which represent the
1834  *  combination of coarse and fine gain value, the value can be put
1835  *  into a lookup table to obtain the approximate cable length
1836  *  for each channel.
1837  **/
1838 s32 igb_get_cable_length_igp_2(struct e1000_hw *hw)
1839 {
1840 	struct e1000_phy_info *phy = &hw->phy;
1841 	s32 ret_val = 0;
1842 	u16 phy_data, i, agc_value = 0;
1843 	u16 cur_agc_index, max_agc_index = 0;
1844 	u16 min_agc_index = ARRAY_SIZE(e1000_igp_2_cable_length_table) - 1;
1845 	static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1846 		IGP02E1000_PHY_AGC_A,
1847 		IGP02E1000_PHY_AGC_B,
1848 		IGP02E1000_PHY_AGC_C,
1849 		IGP02E1000_PHY_AGC_D
1850 	};
1851 
1852 	/* Read the AGC registers for all channels */
1853 	for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1854 		ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
1855 		if (ret_val)
1856 			goto out;
1857 
1858 		/* Getting bits 15:9, which represent the combination of
1859 		 * coarse and fine gain values.  The result is a number
1860 		 * that can be put into the lookup table to obtain the
1861 		 * approximate cable length.
1862 		 */
1863 		cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1864 				IGP02E1000_AGC_LENGTH_MASK;
1865 
1866 		/* Array index bound check. */
1867 		if ((cur_agc_index >= ARRAY_SIZE(e1000_igp_2_cable_length_table)) ||
1868 		    (cur_agc_index == 0)) {
1869 			ret_val = -E1000_ERR_PHY;
1870 			goto out;
1871 		}
1872 
1873 		/* Remove min & max AGC values from calculation. */
1874 		if (e1000_igp_2_cable_length_table[min_agc_index] >
1875 		    e1000_igp_2_cable_length_table[cur_agc_index])
1876 			min_agc_index = cur_agc_index;
1877 		if (e1000_igp_2_cable_length_table[max_agc_index] <
1878 		    e1000_igp_2_cable_length_table[cur_agc_index])
1879 			max_agc_index = cur_agc_index;
1880 
1881 		agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1882 	}
1883 
1884 	agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1885 		      e1000_igp_2_cable_length_table[max_agc_index]);
1886 	agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1887 
1888 	/* Calculate cable length with the error range of +/- 10 meters. */
1889 	phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1890 				 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1891 	phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1892 
1893 	phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1894 
1895 out:
1896 	return ret_val;
1897 }
1898 
1899 /**
1900  *  igb_get_phy_info_m88 - Retrieve PHY information
1901  *  @hw: pointer to the HW structure
1902  *
1903  *  Valid for only copper links.  Read the PHY status register (sticky read)
1904  *  to verify that link is up.  Read the PHY special control register to
1905  *  determine the polarity and 10base-T extended distance.  Read the PHY
1906  *  special status register to determine MDI/MDIx and current speed.  If
1907  *  speed is 1000, then determine cable length, local and remote receiver.
1908  **/
1909 s32 igb_get_phy_info_m88(struct e1000_hw *hw)
1910 {
1911 	struct e1000_phy_info *phy = &hw->phy;
1912 	s32  ret_val;
1913 	u16 phy_data;
1914 	bool link;
1915 
1916 	if (phy->media_type != e1000_media_type_copper) {
1917 		hw_dbg("Phy info is only valid for copper media\n");
1918 		ret_val = -E1000_ERR_CONFIG;
1919 		goto out;
1920 	}
1921 
1922 	ret_val = igb_phy_has_link(hw, 1, 0, &link);
1923 	if (ret_val)
1924 		goto out;
1925 
1926 	if (!link) {
1927 		hw_dbg("Phy info is only valid if link is up\n");
1928 		ret_val = -E1000_ERR_CONFIG;
1929 		goto out;
1930 	}
1931 
1932 	ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1933 	if (ret_val)
1934 		goto out;
1935 
1936 	phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
1937 				   ? true : false;
1938 
1939 	ret_val = igb_check_polarity_m88(hw);
1940 	if (ret_val)
1941 		goto out;
1942 
1943 	ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1944 	if (ret_val)
1945 		goto out;
1946 
1947 	phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
1948 
1949 	if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1950 		ret_val = phy->ops.get_cable_length(hw);
1951 		if (ret_val)
1952 			goto out;
1953 
1954 		ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
1955 		if (ret_val)
1956 			goto out;
1957 
1958 		phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1959 				? e1000_1000t_rx_status_ok
1960 				: e1000_1000t_rx_status_not_ok;
1961 
1962 		phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1963 				 ? e1000_1000t_rx_status_ok
1964 				 : e1000_1000t_rx_status_not_ok;
1965 	} else {
1966 		/* Set values to "undefined" */
1967 		phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1968 		phy->local_rx = e1000_1000t_rx_status_undefined;
1969 		phy->remote_rx = e1000_1000t_rx_status_undefined;
1970 	}
1971 
1972 out:
1973 	return ret_val;
1974 }
1975 
1976 /**
1977  *  igb_get_phy_info_igp - Retrieve igp PHY information
1978  *  @hw: pointer to the HW structure
1979  *
1980  *  Read PHY status to determine if link is up.  If link is up, then
1981  *  set/determine 10base-T extended distance and polarity correction.  Read
1982  *  PHY port status to determine MDI/MDIx and speed.  Based on the speed,
1983  *  determine on the cable length, local and remote receiver.
1984  **/
1985 s32 igb_get_phy_info_igp(struct e1000_hw *hw)
1986 {
1987 	struct e1000_phy_info *phy = &hw->phy;
1988 	s32 ret_val;
1989 	u16 data;
1990 	bool link;
1991 
1992 	ret_val = igb_phy_has_link(hw, 1, 0, &link);
1993 	if (ret_val)
1994 		goto out;
1995 
1996 	if (!link) {
1997 		hw_dbg("Phy info is only valid if link is up\n");
1998 		ret_val = -E1000_ERR_CONFIG;
1999 		goto out;
2000 	}
2001 
2002 	phy->polarity_correction = true;
2003 
2004 	ret_val = igb_check_polarity_igp(hw);
2005 	if (ret_val)
2006 		goto out;
2007 
2008 	ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2009 	if (ret_val)
2010 		goto out;
2011 
2012 	phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
2013 
2014 	if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2015 	    IGP01E1000_PSSR_SPEED_1000MBPS) {
2016 		ret_val = phy->ops.get_cable_length(hw);
2017 		if (ret_val)
2018 			goto out;
2019 
2020 		ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2021 		if (ret_val)
2022 			goto out;
2023 
2024 		phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2025 				? e1000_1000t_rx_status_ok
2026 				: e1000_1000t_rx_status_not_ok;
2027 
2028 		phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2029 				 ? e1000_1000t_rx_status_ok
2030 				 : e1000_1000t_rx_status_not_ok;
2031 	} else {
2032 		phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2033 		phy->local_rx = e1000_1000t_rx_status_undefined;
2034 		phy->remote_rx = e1000_1000t_rx_status_undefined;
2035 	}
2036 
2037 out:
2038 	return ret_val;
2039 }
2040 
2041 /**
2042  *  igb_phy_sw_reset - PHY software reset
2043  *  @hw: pointer to the HW structure
2044  *
2045  *  Does a software reset of the PHY by reading the PHY control register and
2046  *  setting/write the control register reset bit to the PHY.
2047  **/
2048 s32 igb_phy_sw_reset(struct e1000_hw *hw)
2049 {
2050 	s32 ret_val = 0;
2051 	u16 phy_ctrl;
2052 
2053 	if (!(hw->phy.ops.read_reg))
2054 		goto out;
2055 
2056 	ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2057 	if (ret_val)
2058 		goto out;
2059 
2060 	phy_ctrl |= MII_CR_RESET;
2061 	ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2062 	if (ret_val)
2063 		goto out;
2064 
2065 	udelay(1);
2066 
2067 out:
2068 	return ret_val;
2069 }
2070 
2071 /**
2072  *  igb_phy_hw_reset - PHY hardware reset
2073  *  @hw: pointer to the HW structure
2074  *
2075  *  Verify the reset block is not blocking us from resetting.  Acquire
2076  *  semaphore (if necessary) and read/set/write the device control reset
2077  *  bit in the PHY.  Wait the appropriate delay time for the device to
2078  *  reset and release the semaphore (if necessary).
2079  **/
2080 s32 igb_phy_hw_reset(struct e1000_hw *hw)
2081 {
2082 	struct e1000_phy_info *phy = &hw->phy;
2083 	s32  ret_val;
2084 	u32 ctrl;
2085 
2086 	ret_val = igb_check_reset_block(hw);
2087 	if (ret_val) {
2088 		ret_val = 0;
2089 		goto out;
2090 	}
2091 
2092 	ret_val = phy->ops.acquire(hw);
2093 	if (ret_val)
2094 		goto out;
2095 
2096 	ctrl = rd32(E1000_CTRL);
2097 	wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2098 	wrfl();
2099 
2100 	udelay(phy->reset_delay_us);
2101 
2102 	wr32(E1000_CTRL, ctrl);
2103 	wrfl();
2104 
2105 	udelay(150);
2106 
2107 	phy->ops.release(hw);
2108 
2109 	ret_val = phy->ops.get_cfg_done(hw);
2110 
2111 out:
2112 	return ret_val;
2113 }
2114 
2115 /**
2116  *  igb_phy_init_script_igp3 - Inits the IGP3 PHY
2117  *  @hw: pointer to the HW structure
2118  *
2119  *  Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2120  **/
2121 s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
2122 {
2123 	hw_dbg("Running IGP 3 PHY init script\n");
2124 
2125 	/* PHY init IGP 3 */
2126 	/* Enable rise/fall, 10-mode work in class-A */
2127 	hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2128 	/* Remove all caps from Replica path filter */
2129 	hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2130 	/* Bias trimming for ADC, AFE and Driver (Default) */
2131 	hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2132 	/* Increase Hybrid poly bias */
2133 	hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2134 	/* Add 4% to TX amplitude in Giga mode */
2135 	hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2136 	/* Disable trimming (TTT) */
2137 	hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2138 	/* Poly DC correction to 94.6% + 2% for all channels */
2139 	hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2140 	/* ABS DC correction to 95.9% */
2141 	hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2142 	/* BG temp curve trim */
2143 	hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2144 	/* Increasing ADC OPAMP stage 1 currents to max */
2145 	hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2146 	/* Force 1000 ( required for enabling PHY regs configuration) */
2147 	hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2148 	/* Set upd_freq to 6 */
2149 	hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2150 	/* Disable NPDFE */
2151 	hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2152 	/* Disable adaptive fixed FFE (Default) */
2153 	hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2154 	/* Enable FFE hysteresis */
2155 	hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2156 	/* Fixed FFE for short cable lengths */
2157 	hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2158 	/* Fixed FFE for medium cable lengths */
2159 	hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2160 	/* Fixed FFE for long cable lengths */
2161 	hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2162 	/* Enable Adaptive Clip Threshold */
2163 	hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2164 	/* AHT reset limit to 1 */
2165 	hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2166 	/* Set AHT master delay to 127 msec */
2167 	hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2168 	/* Set scan bits for AHT */
2169 	hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2170 	/* Set AHT Preset bits */
2171 	hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2172 	/* Change integ_factor of channel A to 3 */
2173 	hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2174 	/* Change prop_factor of channels BCD to 8 */
2175 	hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2176 	/* Change cg_icount + enable integbp for channels BCD */
2177 	hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2178 	/* Change cg_icount + enable integbp + change prop_factor_master
2179 	 * to 8 for channel A
2180 	 */
2181 	hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2182 	/* Disable AHT in Slave mode on channel A */
2183 	hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2184 	/* Enable LPLU and disable AN to 1000 in non-D0a states,
2185 	 * Enable SPD+B2B
2186 	 */
2187 	hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2188 	/* Enable restart AN on an1000_dis change */
2189 	hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2190 	/* Enable wh_fifo read clock in 10/100 modes */
2191 	hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2192 	/* Restart AN, Speed selection is 1000 */
2193 	hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2194 
2195 	return 0;
2196 }
2197 
2198 /**
2199  *  igb_initialize_M88E1512_phy - Initialize M88E1512 PHY
2200  *  @hw: pointer to the HW structure
2201  *
2202  *  Initialize Marvel 1512 to work correctly with Avoton.
2203  **/
2204 s32 igb_initialize_M88E1512_phy(struct e1000_hw *hw)
2205 {
2206 	struct e1000_phy_info *phy = &hw->phy;
2207 	s32 ret_val = 0;
2208 
2209 	/* Switch to PHY page 0xFF. */
2210 	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2211 	if (ret_val)
2212 		goto out;
2213 
2214 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2215 	if (ret_val)
2216 		goto out;
2217 
2218 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2219 	if (ret_val)
2220 		goto out;
2221 
2222 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2223 	if (ret_val)
2224 		goto out;
2225 
2226 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2227 	if (ret_val)
2228 		goto out;
2229 
2230 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2231 	if (ret_val)
2232 		goto out;
2233 
2234 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2235 	if (ret_val)
2236 		goto out;
2237 
2238 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C);
2239 	if (ret_val)
2240 		goto out;
2241 
2242 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2243 	if (ret_val)
2244 		goto out;
2245 
2246 	/* Switch to PHY page 0xFB. */
2247 	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2248 	if (ret_val)
2249 		goto out;
2250 
2251 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D);
2252 	if (ret_val)
2253 		goto out;
2254 
2255 	/* Switch to PHY page 0x12. */
2256 	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2257 	if (ret_val)
2258 		goto out;
2259 
2260 	/* Change mode to SGMII-to-Copper */
2261 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2262 	if (ret_val)
2263 		goto out;
2264 
2265 	/* Return the PHY to page 0. */
2266 	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2267 	if (ret_val)
2268 		goto out;
2269 
2270 	ret_val = igb_phy_sw_reset(hw);
2271 	if (ret_val) {
2272 		hw_dbg("Error committing the PHY changes\n");
2273 		return ret_val;
2274 	}
2275 
2276 	/* msec_delay(1000); */
2277 	usleep_range(1000, 2000);
2278 out:
2279 	return ret_val;
2280 }
2281 
2282 /**
2283  *  igb_initialize_M88E1543_phy - Initialize M88E1512 PHY
2284  *  @hw: pointer to the HW structure
2285  *
2286  *  Initialize Marvell 1543 to work correctly with Avoton.
2287  **/
2288 s32 igb_initialize_M88E1543_phy(struct e1000_hw *hw)
2289 {
2290 	struct e1000_phy_info *phy = &hw->phy;
2291 	s32 ret_val = 0;
2292 
2293 	/* Switch to PHY page 0xFF. */
2294 	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF);
2295 	if (ret_val)
2296 		goto out;
2297 
2298 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B);
2299 	if (ret_val)
2300 		goto out;
2301 
2302 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144);
2303 	if (ret_val)
2304 		goto out;
2305 
2306 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28);
2307 	if (ret_val)
2308 		goto out;
2309 
2310 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146);
2311 	if (ret_val)
2312 		goto out;
2313 
2314 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233);
2315 	if (ret_val)
2316 		goto out;
2317 
2318 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D);
2319 	if (ret_val)
2320 		goto out;
2321 
2322 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C);
2323 	if (ret_val)
2324 		goto out;
2325 
2326 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159);
2327 	if (ret_val)
2328 		goto out;
2329 
2330 	/* Switch to PHY page 0xFB. */
2331 	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB);
2332 	if (ret_val)
2333 		goto out;
2334 
2335 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x0C0D);
2336 	if (ret_val)
2337 		goto out;
2338 
2339 	/* Switch to PHY page 0x12. */
2340 	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12);
2341 	if (ret_val)
2342 		goto out;
2343 
2344 	/* Change mode to SGMII-to-Copper */
2345 	ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001);
2346 	if (ret_val)
2347 		goto out;
2348 
2349 	/* Switch to PHY page 1. */
2350 	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1);
2351 	if (ret_val)
2352 		goto out;
2353 
2354 	/* Change mode to 1000BASE-X/SGMII and autoneg enable */
2355 	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140);
2356 	if (ret_val)
2357 		goto out;
2358 
2359 	/* Return the PHY to page 0. */
2360 	ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2361 	if (ret_val)
2362 		goto out;
2363 
2364 	ret_val = igb_phy_sw_reset(hw);
2365 	if (ret_val) {
2366 		hw_dbg("Error committing the PHY changes\n");
2367 		return ret_val;
2368 	}
2369 
2370 	/* msec_delay(1000); */
2371 	usleep_range(1000, 2000);
2372 out:
2373 	return ret_val;
2374 }
2375 
2376 /**
2377  * igb_power_up_phy_copper - Restore copper link in case of PHY power down
2378  * @hw: pointer to the HW structure
2379  *
2380  * In the case of a PHY power down to save power, or to turn off link during a
2381  * driver unload, restore the link to previous settings.
2382  **/
2383 void igb_power_up_phy_copper(struct e1000_hw *hw)
2384 {
2385 	u16 mii_reg = 0;
2386 
2387 	/* The PHY will retain its settings across a power down/up cycle */
2388 	hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2389 	mii_reg &= ~MII_CR_POWER_DOWN;
2390 	hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2391 }
2392 
2393 /**
2394  * igb_power_down_phy_copper - Power down copper PHY
2395  * @hw: pointer to the HW structure
2396  *
2397  * Power down PHY to save power when interface is down and wake on lan
2398  * is not enabled.
2399  **/
2400 void igb_power_down_phy_copper(struct e1000_hw *hw)
2401 {
2402 	u16 mii_reg = 0;
2403 
2404 	/* The PHY will retain its settings across a power down/up cycle */
2405 	hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2406 	mii_reg |= MII_CR_POWER_DOWN;
2407 	hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2408 	usleep_range(1000, 2000);
2409 }
2410 
2411 /**
2412  *  igb_check_polarity_82580 - Checks the polarity.
2413  *  @hw: pointer to the HW structure
2414  *
2415  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2416  *
2417  *  Polarity is determined based on the PHY specific status register.
2418  **/
2419 static s32 igb_check_polarity_82580(struct e1000_hw *hw)
2420 {
2421 	struct e1000_phy_info *phy = &hw->phy;
2422 	s32 ret_val;
2423 	u16 data;
2424 
2425 
2426 	ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2427 
2428 	if (!ret_val)
2429 		phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY)
2430 				      ? e1000_rev_polarity_reversed
2431 				      : e1000_rev_polarity_normal;
2432 
2433 	return ret_val;
2434 }
2435 
2436 /**
2437  *  igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY
2438  *  @hw: pointer to the HW structure
2439  *
2440  *  Calls the PHY setup function to force speed and duplex.  Clears the
2441  *  auto-crossover to force MDI manually.  Waits for link and returns
2442  *  successful if link up is successful, else -E1000_ERR_PHY (-2).
2443  **/
2444 s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw)
2445 {
2446 	struct e1000_phy_info *phy = &hw->phy;
2447 	s32 ret_val;
2448 	u16 phy_data;
2449 	bool link;
2450 
2451 	ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
2452 	if (ret_val)
2453 		goto out;
2454 
2455 	igb_phy_force_speed_duplex_setup(hw, &phy_data);
2456 
2457 	ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
2458 	if (ret_val)
2459 		goto out;
2460 
2461 	/* Clear Auto-Crossover to force MDI manually.  82580 requires MDI
2462 	 * forced whenever speed and duplex are forced.
2463 	 */
2464 	ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
2465 	if (ret_val)
2466 		goto out;
2467 
2468 	phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
2469 
2470 	ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
2471 	if (ret_val)
2472 		goto out;
2473 
2474 	hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data);
2475 
2476 	udelay(1);
2477 
2478 	if (phy->autoneg_wait_to_complete) {
2479 		hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n");
2480 
2481 		ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2482 		if (ret_val)
2483 			goto out;
2484 
2485 		if (!link)
2486 			hw_dbg("Link taking longer than expected.\n");
2487 
2488 		/* Try once more */
2489 		ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
2490 		if (ret_val)
2491 			goto out;
2492 	}
2493 
2494 out:
2495 	return ret_val;
2496 }
2497 
2498 /**
2499  *  igb_get_phy_info_82580 - Retrieve I82580 PHY information
2500  *  @hw: pointer to the HW structure
2501  *
2502  *  Read PHY status to determine if link is up.  If link is up, then
2503  *  set/determine 10base-T extended distance and polarity correction.  Read
2504  *  PHY port status to determine MDI/MDIx and speed.  Based on the speed,
2505  *  determine on the cable length, local and remote receiver.
2506  **/
2507 s32 igb_get_phy_info_82580(struct e1000_hw *hw)
2508 {
2509 	struct e1000_phy_info *phy = &hw->phy;
2510 	s32 ret_val;
2511 	u16 data;
2512 	bool link;
2513 
2514 	ret_val = igb_phy_has_link(hw, 1, 0, &link);
2515 	if (ret_val)
2516 		goto out;
2517 
2518 	if (!link) {
2519 		hw_dbg("Phy info is only valid if link is up\n");
2520 		ret_val = -E1000_ERR_CONFIG;
2521 		goto out;
2522 	}
2523 
2524 	phy->polarity_correction = true;
2525 
2526 	ret_val = igb_check_polarity_82580(hw);
2527 	if (ret_val)
2528 		goto out;
2529 
2530 	ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2531 	if (ret_val)
2532 		goto out;
2533 
2534 	phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false;
2535 
2536 	if ((data & I82580_PHY_STATUS2_SPEED_MASK) ==
2537 	    I82580_PHY_STATUS2_SPEED_1000MBPS) {
2538 		ret_val = hw->phy.ops.get_cable_length(hw);
2539 		if (ret_val)
2540 			goto out;
2541 
2542 		ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2543 		if (ret_val)
2544 			goto out;
2545 
2546 		phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2547 				? e1000_1000t_rx_status_ok
2548 				: e1000_1000t_rx_status_not_ok;
2549 
2550 		phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2551 				 ? e1000_1000t_rx_status_ok
2552 				 : e1000_1000t_rx_status_not_ok;
2553 	} else {
2554 		phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2555 		phy->local_rx = e1000_1000t_rx_status_undefined;
2556 		phy->remote_rx = e1000_1000t_rx_status_undefined;
2557 	}
2558 
2559 out:
2560 	return ret_val;
2561 }
2562 
2563 /**
2564  *  igb_get_cable_length_82580 - Determine cable length for 82580 PHY
2565  *  @hw: pointer to the HW structure
2566  *
2567  * Reads the diagnostic status register and verifies result is valid before
2568  * placing it in the phy_cable_length field.
2569  **/
2570 s32 igb_get_cable_length_82580(struct e1000_hw *hw)
2571 {
2572 	struct e1000_phy_info *phy = &hw->phy;
2573 	s32 ret_val;
2574 	u16 phy_data, length;
2575 
2576 	ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data);
2577 	if (ret_val)
2578 		goto out;
2579 
2580 	length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >>
2581 		 I82580_DSTATUS_CABLE_LENGTH_SHIFT;
2582 
2583 	if (length == E1000_CABLE_LENGTH_UNDEFINED)
2584 		ret_val = -E1000_ERR_PHY;
2585 
2586 	phy->cable_length = length;
2587 
2588 out:
2589 	return ret_val;
2590 }
2591 
2592 /**
2593  *  igb_set_master_slave_mode - Setup PHY for Master/slave mode
2594  *  @hw: pointer to the HW structure
2595  *
2596  *  Sets up Master/slave mode
2597  **/
2598 static s32 igb_set_master_slave_mode(struct e1000_hw *hw)
2599 {
2600 	s32 ret_val;
2601 	u16 phy_data;
2602 
2603 	/* Resolve Master/Slave mode */
2604 	ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
2605 	if (ret_val)
2606 		return ret_val;
2607 
2608 	/* load defaults for future use */
2609 	hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
2610 				   ((phy_data & CR_1000T_MS_VALUE) ?
2611 				    e1000_ms_force_master :
2612 				    e1000_ms_force_slave) : e1000_ms_auto;
2613 
2614 	switch (hw->phy.ms_type) {
2615 	case e1000_ms_force_master:
2616 		phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2617 		break;
2618 	case e1000_ms_force_slave:
2619 		phy_data |= CR_1000T_MS_ENABLE;
2620 		phy_data &= ~(CR_1000T_MS_VALUE);
2621 		break;
2622 	case e1000_ms_auto:
2623 		phy_data &= ~CR_1000T_MS_ENABLE;
2624 		/* fall-through */
2625 	default:
2626 		break;
2627 	}
2628 
2629 	return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
2630 }
2631