1 /* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2015 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 #include <linux/if_ether.h> 25 #include <linux/delay.h> 26 27 #include "e1000_mac.h" 28 #include "e1000_phy.h" 29 30 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw); 31 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, 32 u16 *phy_ctrl); 33 static s32 igb_wait_autoneg(struct e1000_hw *hw); 34 static s32 igb_set_master_slave_mode(struct e1000_hw *hw); 35 36 /* Cable length tables */ 37 static const u16 e1000_m88_cable_length_table[] = { 38 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 39 40 static const u16 e1000_igp_2_cable_length_table[] = { 41 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 42 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 43 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 44 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 45 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 46 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 47 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, 48 104, 109, 114, 118, 121, 124}; 49 50 /** 51 * igb_check_reset_block - Check if PHY reset is blocked 52 * @hw: pointer to the HW structure 53 * 54 * Read the PHY management control register and check whether a PHY reset 55 * is blocked. If a reset is not blocked return 0, otherwise 56 * return E1000_BLK_PHY_RESET (12). 57 **/ 58 s32 igb_check_reset_block(struct e1000_hw *hw) 59 { 60 u32 manc; 61 62 manc = rd32(E1000_MANC); 63 64 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0; 65 } 66 67 /** 68 * igb_get_phy_id - Retrieve the PHY ID and revision 69 * @hw: pointer to the HW structure 70 * 71 * Reads the PHY registers and stores the PHY ID and possibly the PHY 72 * revision in the hardware structure. 73 **/ 74 s32 igb_get_phy_id(struct e1000_hw *hw) 75 { 76 struct e1000_phy_info *phy = &hw->phy; 77 s32 ret_val = 0; 78 u16 phy_id; 79 80 /* ensure PHY page selection to fix misconfigured i210 */ 81 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 82 phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0); 83 84 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 85 if (ret_val) 86 goto out; 87 88 phy->id = (u32)(phy_id << 16); 89 udelay(20); 90 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 91 if (ret_val) 92 goto out; 93 94 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 95 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 96 97 out: 98 return ret_val; 99 } 100 101 /** 102 * igb_phy_reset_dsp - Reset PHY DSP 103 * @hw: pointer to the HW structure 104 * 105 * Reset the digital signal processor. 106 **/ 107 static s32 igb_phy_reset_dsp(struct e1000_hw *hw) 108 { 109 s32 ret_val = 0; 110 111 if (!(hw->phy.ops.write_reg)) 112 goto out; 113 114 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 115 if (ret_val) 116 goto out; 117 118 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 119 120 out: 121 return ret_val; 122 } 123 124 /** 125 * igb_read_phy_reg_mdic - Read MDI control register 126 * @hw: pointer to the HW structure 127 * @offset: register offset to be read 128 * @data: pointer to the read data 129 * 130 * Reads the MDI control register in the PHY at offset and stores the 131 * information read to data. 132 **/ 133 s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 134 { 135 struct e1000_phy_info *phy = &hw->phy; 136 u32 i, mdic = 0; 137 s32 ret_val = 0; 138 139 if (offset > MAX_PHY_REG_ADDRESS) { 140 hw_dbg("PHY Address %d is out of range\n", offset); 141 ret_val = -E1000_ERR_PARAM; 142 goto out; 143 } 144 145 /* Set up Op-code, Phy Address, and register offset in the MDI 146 * Control register. The MAC will take care of interfacing with the 147 * PHY to retrieve the desired data. 148 */ 149 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 150 (phy->addr << E1000_MDIC_PHY_SHIFT) | 151 (E1000_MDIC_OP_READ)); 152 153 wr32(E1000_MDIC, mdic); 154 155 /* Poll the ready bit to see if the MDI read completed 156 * Increasing the time out as testing showed failures with 157 * the lower time out 158 */ 159 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 160 udelay(50); 161 mdic = rd32(E1000_MDIC); 162 if (mdic & E1000_MDIC_READY) 163 break; 164 } 165 if (!(mdic & E1000_MDIC_READY)) { 166 hw_dbg("MDI Read did not complete\n"); 167 ret_val = -E1000_ERR_PHY; 168 goto out; 169 } 170 if (mdic & E1000_MDIC_ERROR) { 171 hw_dbg("MDI Error\n"); 172 ret_val = -E1000_ERR_PHY; 173 goto out; 174 } 175 *data = (u16) mdic; 176 177 out: 178 return ret_val; 179 } 180 181 /** 182 * igb_write_phy_reg_mdic - Write MDI control register 183 * @hw: pointer to the HW structure 184 * @offset: register offset to write to 185 * @data: data to write to register at offset 186 * 187 * Writes data to MDI control register in the PHY at offset. 188 **/ 189 s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 190 { 191 struct e1000_phy_info *phy = &hw->phy; 192 u32 i, mdic = 0; 193 s32 ret_val = 0; 194 195 if (offset > MAX_PHY_REG_ADDRESS) { 196 hw_dbg("PHY Address %d is out of range\n", offset); 197 ret_val = -E1000_ERR_PARAM; 198 goto out; 199 } 200 201 /* Set up Op-code, Phy Address, and register offset in the MDI 202 * Control register. The MAC will take care of interfacing with the 203 * PHY to retrieve the desired data. 204 */ 205 mdic = (((u32)data) | 206 (offset << E1000_MDIC_REG_SHIFT) | 207 (phy->addr << E1000_MDIC_PHY_SHIFT) | 208 (E1000_MDIC_OP_WRITE)); 209 210 wr32(E1000_MDIC, mdic); 211 212 /* Poll the ready bit to see if the MDI read completed 213 * Increasing the time out as testing showed failures with 214 * the lower time out 215 */ 216 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 217 udelay(50); 218 mdic = rd32(E1000_MDIC); 219 if (mdic & E1000_MDIC_READY) 220 break; 221 } 222 if (!(mdic & E1000_MDIC_READY)) { 223 hw_dbg("MDI Write did not complete\n"); 224 ret_val = -E1000_ERR_PHY; 225 goto out; 226 } 227 if (mdic & E1000_MDIC_ERROR) { 228 hw_dbg("MDI Error\n"); 229 ret_val = -E1000_ERR_PHY; 230 goto out; 231 } 232 233 out: 234 return ret_val; 235 } 236 237 /** 238 * igb_read_phy_reg_i2c - Read PHY register using i2c 239 * @hw: pointer to the HW structure 240 * @offset: register offset to be read 241 * @data: pointer to the read data 242 * 243 * Reads the PHY register at offset using the i2c interface and stores the 244 * retrieved information in data. 245 **/ 246 s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) 247 { 248 struct e1000_phy_info *phy = &hw->phy; 249 u32 i, i2ccmd = 0; 250 251 /* Set up Op-code, Phy Address, and register address in the I2CCMD 252 * register. The MAC will take care of interfacing with the 253 * PHY to retrieve the desired data. 254 */ 255 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 256 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 257 (E1000_I2CCMD_OPCODE_READ)); 258 259 wr32(E1000_I2CCMD, i2ccmd); 260 261 /* Poll the ready bit to see if the I2C read completed */ 262 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 263 udelay(50); 264 i2ccmd = rd32(E1000_I2CCMD); 265 if (i2ccmd & E1000_I2CCMD_READY) 266 break; 267 } 268 if (!(i2ccmd & E1000_I2CCMD_READY)) { 269 hw_dbg("I2CCMD Read did not complete\n"); 270 return -E1000_ERR_PHY; 271 } 272 if (i2ccmd & E1000_I2CCMD_ERROR) { 273 hw_dbg("I2CCMD Error bit set\n"); 274 return -E1000_ERR_PHY; 275 } 276 277 /* Need to byte-swap the 16-bit value. */ 278 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 279 280 return 0; 281 } 282 283 /** 284 * igb_write_phy_reg_i2c - Write PHY register using i2c 285 * @hw: pointer to the HW structure 286 * @offset: register offset to write to 287 * @data: data to write at register offset 288 * 289 * Writes the data to PHY register at the offset using the i2c interface. 290 **/ 291 s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) 292 { 293 struct e1000_phy_info *phy = &hw->phy; 294 u32 i, i2ccmd = 0; 295 u16 phy_data_swapped; 296 297 /* Prevent overwriting SFP I2C EEPROM which is at A0 address.*/ 298 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) { 299 hw_dbg("PHY I2C Address %d is out of range.\n", 300 hw->phy.addr); 301 return -E1000_ERR_CONFIG; 302 } 303 304 /* Swap the data bytes for the I2C interface */ 305 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 306 307 /* Set up Op-code, Phy Address, and register address in the I2CCMD 308 * register. The MAC will take care of interfacing with the 309 * PHY to retrieve the desired data. 310 */ 311 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 312 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 313 E1000_I2CCMD_OPCODE_WRITE | 314 phy_data_swapped); 315 316 wr32(E1000_I2CCMD, i2ccmd); 317 318 /* Poll the ready bit to see if the I2C read completed */ 319 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 320 udelay(50); 321 i2ccmd = rd32(E1000_I2CCMD); 322 if (i2ccmd & E1000_I2CCMD_READY) 323 break; 324 } 325 if (!(i2ccmd & E1000_I2CCMD_READY)) { 326 hw_dbg("I2CCMD Write did not complete\n"); 327 return -E1000_ERR_PHY; 328 } 329 if (i2ccmd & E1000_I2CCMD_ERROR) { 330 hw_dbg("I2CCMD Error bit set\n"); 331 return -E1000_ERR_PHY; 332 } 333 334 return 0; 335 } 336 337 /** 338 * igb_read_sfp_data_byte - Reads SFP module data. 339 * @hw: pointer to the HW structure 340 * @offset: byte location offset to be read 341 * @data: read data buffer pointer 342 * 343 * Reads one byte from SFP module data stored 344 * in SFP resided EEPROM memory or SFP diagnostic area. 345 * Function should be called with 346 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 347 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 348 * access 349 **/ 350 s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data) 351 { 352 u32 i = 0; 353 u32 i2ccmd = 0; 354 u32 data_local = 0; 355 356 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 357 hw_dbg("I2CCMD command address exceeds upper limit\n"); 358 return -E1000_ERR_PHY; 359 } 360 361 /* Set up Op-code, EEPROM Address,in the I2CCMD 362 * register. The MAC will take care of interfacing with the 363 * EEPROM to retrieve the desired data. 364 */ 365 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 366 E1000_I2CCMD_OPCODE_READ); 367 368 wr32(E1000_I2CCMD, i2ccmd); 369 370 /* Poll the ready bit to see if the I2C read completed */ 371 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 372 udelay(50); 373 data_local = rd32(E1000_I2CCMD); 374 if (data_local & E1000_I2CCMD_READY) 375 break; 376 } 377 if (!(data_local & E1000_I2CCMD_READY)) { 378 hw_dbg("I2CCMD Read did not complete\n"); 379 return -E1000_ERR_PHY; 380 } 381 if (data_local & E1000_I2CCMD_ERROR) { 382 hw_dbg("I2CCMD Error bit set\n"); 383 return -E1000_ERR_PHY; 384 } 385 *data = (u8) data_local & 0xFF; 386 387 return 0; 388 } 389 390 /** 391 * igb_read_phy_reg_igp - Read igp PHY register 392 * @hw: pointer to the HW structure 393 * @offset: register offset to be read 394 * @data: pointer to the read data 395 * 396 * Acquires semaphore, if necessary, then reads the PHY register at offset 397 * and storing the retrieved information in data. Release any acquired 398 * semaphores before exiting. 399 **/ 400 s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 401 { 402 s32 ret_val = 0; 403 404 if (!(hw->phy.ops.acquire)) 405 goto out; 406 407 ret_val = hw->phy.ops.acquire(hw); 408 if (ret_val) 409 goto out; 410 411 if (offset > MAX_PHY_MULTI_PAGE_REG) { 412 ret_val = igb_write_phy_reg_mdic(hw, 413 IGP01E1000_PHY_PAGE_SELECT, 414 (u16)offset); 415 if (ret_val) { 416 hw->phy.ops.release(hw); 417 goto out; 418 } 419 } 420 421 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 422 data); 423 424 hw->phy.ops.release(hw); 425 426 out: 427 return ret_val; 428 } 429 430 /** 431 * igb_write_phy_reg_igp - Write igp PHY register 432 * @hw: pointer to the HW structure 433 * @offset: register offset to write to 434 * @data: data to write at register offset 435 * 436 * Acquires semaphore, if necessary, then writes the data to PHY register 437 * at the offset. Release any acquired semaphores before exiting. 438 **/ 439 s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 440 { 441 s32 ret_val = 0; 442 443 if (!(hw->phy.ops.acquire)) 444 goto out; 445 446 ret_val = hw->phy.ops.acquire(hw); 447 if (ret_val) 448 goto out; 449 450 if (offset > MAX_PHY_MULTI_PAGE_REG) { 451 ret_val = igb_write_phy_reg_mdic(hw, 452 IGP01E1000_PHY_PAGE_SELECT, 453 (u16)offset); 454 if (ret_val) { 455 hw->phy.ops.release(hw); 456 goto out; 457 } 458 } 459 460 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 461 data); 462 463 hw->phy.ops.release(hw); 464 465 out: 466 return ret_val; 467 } 468 469 /** 470 * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link 471 * @hw: pointer to the HW structure 472 * 473 * Sets up Carrier-sense on Transmit and downshift values. 474 **/ 475 s32 igb_copper_link_setup_82580(struct e1000_hw *hw) 476 { 477 struct e1000_phy_info *phy = &hw->phy; 478 s32 ret_val; 479 u16 phy_data; 480 481 if (phy->reset_disable) { 482 ret_val = 0; 483 goto out; 484 } 485 486 if (phy->type == e1000_phy_82580) { 487 ret_val = hw->phy.ops.reset(hw); 488 if (ret_val) { 489 hw_dbg("Error resetting the PHY.\n"); 490 goto out; 491 } 492 } 493 494 /* Enable CRS on TX. This must be set for half-duplex operation. */ 495 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data); 496 if (ret_val) 497 goto out; 498 499 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX; 500 501 /* Enable downshift */ 502 phy_data |= I82580_CFG_ENABLE_DOWNSHIFT; 503 504 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data); 505 if (ret_val) 506 goto out; 507 508 /* Set MDI/MDIX mode */ 509 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); 510 if (ret_val) 511 goto out; 512 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK; 513 /* Options: 514 * 0 - Auto (default) 515 * 1 - MDI mode 516 * 2 - MDI-X mode 517 */ 518 switch (hw->phy.mdix) { 519 case 1: 520 break; 521 case 2: 522 phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX; 523 break; 524 case 0: 525 default: 526 phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX; 527 break; 528 } 529 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); 530 531 out: 532 return ret_val; 533 } 534 535 /** 536 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link 537 * @hw: pointer to the HW structure 538 * 539 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 540 * and downshift values are set also. 541 **/ 542 s32 igb_copper_link_setup_m88(struct e1000_hw *hw) 543 { 544 struct e1000_phy_info *phy = &hw->phy; 545 s32 ret_val; 546 u16 phy_data; 547 548 if (phy->reset_disable) { 549 ret_val = 0; 550 goto out; 551 } 552 553 /* Enable CRS on TX. This must be set for half-duplex operation. */ 554 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 555 if (ret_val) 556 goto out; 557 558 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 559 560 /* Options: 561 * MDI/MDI-X = 0 (default) 562 * 0 - Auto for all speeds 563 * 1 - MDI mode 564 * 2 - MDI-X mode 565 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 566 */ 567 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 568 569 switch (phy->mdix) { 570 case 1: 571 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 572 break; 573 case 2: 574 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 575 break; 576 case 3: 577 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 578 break; 579 case 0: 580 default: 581 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 582 break; 583 } 584 585 /* Options: 586 * disable_polarity_correction = 0 (default) 587 * Automatic Correction for Reversed Cable Polarity 588 * 0 - Disabled 589 * 1 - Enabled 590 */ 591 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 592 if (phy->disable_polarity_correction == 1) 593 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 594 595 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 596 if (ret_val) 597 goto out; 598 599 if (phy->revision < E1000_REVISION_4) { 600 /* Force TX_CLK in the Extended PHY Specific Control Register 601 * to 25MHz clock. 602 */ 603 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 604 &phy_data); 605 if (ret_val) 606 goto out; 607 608 phy_data |= M88E1000_EPSCR_TX_CLK_25; 609 610 if ((phy->revision == E1000_REVISION_2) && 611 (phy->id == M88E1111_I_PHY_ID)) { 612 /* 82573L PHY - set the downshift counter to 5x. */ 613 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 614 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 615 } else { 616 /* Configure Master and Slave downshift values */ 617 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 618 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 619 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 620 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 621 } 622 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 623 phy_data); 624 if (ret_val) 625 goto out; 626 } 627 628 /* Commit the changes. */ 629 ret_val = igb_phy_sw_reset(hw); 630 if (ret_val) { 631 hw_dbg("Error committing the PHY changes\n"); 632 goto out; 633 } 634 635 out: 636 return ret_val; 637 } 638 639 /** 640 * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link 641 * @hw: pointer to the HW structure 642 * 643 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's. 644 * Also enables and sets the downshift parameters. 645 **/ 646 s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw) 647 { 648 struct e1000_phy_info *phy = &hw->phy; 649 s32 ret_val; 650 u16 phy_data; 651 652 if (phy->reset_disable) 653 return 0; 654 655 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 656 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 657 if (ret_val) 658 return ret_val; 659 660 /* Options: 661 * MDI/MDI-X = 0 (default) 662 * 0 - Auto for all speeds 663 * 1 - MDI mode 664 * 2 - MDI-X mode 665 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 666 */ 667 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 668 669 switch (phy->mdix) { 670 case 1: 671 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 672 break; 673 case 2: 674 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 675 break; 676 case 3: 677 /* M88E1112 does not support this mode) */ 678 if (phy->id != M88E1112_E_PHY_ID) { 679 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 680 break; 681 } 682 case 0: 683 default: 684 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 685 break; 686 } 687 688 /* Options: 689 * disable_polarity_correction = 0 (default) 690 * Automatic Correction for Reversed Cable Polarity 691 * 0 - Disabled 692 * 1 - Enabled 693 */ 694 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 695 if (phy->disable_polarity_correction == 1) 696 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 697 698 /* Enable downshift and setting it to X6 */ 699 if (phy->id == M88E1543_E_PHY_ID) { 700 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE; 701 ret_val = 702 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 703 if (ret_val) 704 return ret_val; 705 706 ret_val = igb_phy_sw_reset(hw); 707 if (ret_val) { 708 hw_dbg("Error committing the PHY changes\n"); 709 return ret_val; 710 } 711 } 712 713 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK; 714 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X; 715 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE; 716 717 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 718 if (ret_val) 719 return ret_val; 720 721 /* Commit the changes. */ 722 ret_val = igb_phy_sw_reset(hw); 723 if (ret_val) { 724 hw_dbg("Error committing the PHY changes\n"); 725 return ret_val; 726 } 727 ret_val = igb_set_master_slave_mode(hw); 728 if (ret_val) 729 return ret_val; 730 731 return 0; 732 } 733 734 /** 735 * igb_copper_link_setup_igp - Setup igp PHY's for copper link 736 * @hw: pointer to the HW structure 737 * 738 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 739 * igp PHY's. 740 **/ 741 s32 igb_copper_link_setup_igp(struct e1000_hw *hw) 742 { 743 struct e1000_phy_info *phy = &hw->phy; 744 s32 ret_val; 745 u16 data; 746 747 if (phy->reset_disable) { 748 ret_val = 0; 749 goto out; 750 } 751 752 ret_val = phy->ops.reset(hw); 753 if (ret_val) { 754 hw_dbg("Error resetting the PHY.\n"); 755 goto out; 756 } 757 758 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid 759 * timeout issues when LFS is enabled. 760 */ 761 msleep(100); 762 763 /* The NVM settings will configure LPLU in D3 for 764 * non-IGP1 PHYs. 765 */ 766 if (phy->type == e1000_phy_igp) { 767 /* disable lplu d3 during driver init */ 768 if (phy->ops.set_d3_lplu_state) 769 ret_val = phy->ops.set_d3_lplu_state(hw, false); 770 if (ret_val) { 771 hw_dbg("Error Disabling LPLU D3\n"); 772 goto out; 773 } 774 } 775 776 /* disable lplu d0 during driver init */ 777 ret_val = phy->ops.set_d0_lplu_state(hw, false); 778 if (ret_val) { 779 hw_dbg("Error Disabling LPLU D0\n"); 780 goto out; 781 } 782 /* Configure mdi-mdix settings */ 783 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 784 if (ret_val) 785 goto out; 786 787 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 788 789 switch (phy->mdix) { 790 case 1: 791 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 792 break; 793 case 2: 794 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 795 break; 796 case 0: 797 default: 798 data |= IGP01E1000_PSCR_AUTO_MDIX; 799 break; 800 } 801 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 802 if (ret_val) 803 goto out; 804 805 /* set auto-master slave resolution settings */ 806 if (hw->mac.autoneg) { 807 /* when autonegotiation advertisement is only 1000Mbps then we 808 * should disable SmartSpeed and enable Auto MasterSlave 809 * resolution as hardware default. 810 */ 811 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 812 /* Disable SmartSpeed */ 813 ret_val = phy->ops.read_reg(hw, 814 IGP01E1000_PHY_PORT_CONFIG, 815 &data); 816 if (ret_val) 817 goto out; 818 819 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 820 ret_val = phy->ops.write_reg(hw, 821 IGP01E1000_PHY_PORT_CONFIG, 822 data); 823 if (ret_val) 824 goto out; 825 826 /* Set auto Master/Slave resolution process */ 827 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 828 if (ret_val) 829 goto out; 830 831 data &= ~CR_1000T_MS_ENABLE; 832 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 833 if (ret_val) 834 goto out; 835 } 836 837 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 838 if (ret_val) 839 goto out; 840 841 /* load defaults for future use */ 842 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ? 843 ((data & CR_1000T_MS_VALUE) ? 844 e1000_ms_force_master : 845 e1000_ms_force_slave) : 846 e1000_ms_auto; 847 848 switch (phy->ms_type) { 849 case e1000_ms_force_master: 850 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 851 break; 852 case e1000_ms_force_slave: 853 data |= CR_1000T_MS_ENABLE; 854 data &= ~(CR_1000T_MS_VALUE); 855 break; 856 case e1000_ms_auto: 857 data &= ~CR_1000T_MS_ENABLE; 858 default: 859 break; 860 } 861 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 862 if (ret_val) 863 goto out; 864 } 865 866 out: 867 return ret_val; 868 } 869 870 /** 871 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link 872 * @hw: pointer to the HW structure 873 * 874 * Performs initial bounds checking on autoneg advertisement parameter, then 875 * configure to advertise the full capability. Setup the PHY to autoneg 876 * and restart the negotiation process between the link partner. If 877 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 878 **/ 879 static s32 igb_copper_link_autoneg(struct e1000_hw *hw) 880 { 881 struct e1000_phy_info *phy = &hw->phy; 882 s32 ret_val; 883 u16 phy_ctrl; 884 885 /* Perform some bounds checking on the autoneg advertisement 886 * parameter. 887 */ 888 phy->autoneg_advertised &= phy->autoneg_mask; 889 890 /* If autoneg_advertised is zero, we assume it was not defaulted 891 * by the calling code so we set to advertise full capability. 892 */ 893 if (phy->autoneg_advertised == 0) 894 phy->autoneg_advertised = phy->autoneg_mask; 895 896 hw_dbg("Reconfiguring auto-neg advertisement params\n"); 897 ret_val = igb_phy_setup_autoneg(hw); 898 if (ret_val) { 899 hw_dbg("Error Setting up Auto-Negotiation\n"); 900 goto out; 901 } 902 hw_dbg("Restarting Auto-Neg\n"); 903 904 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 905 * the Auto Neg Restart bit in the PHY control register. 906 */ 907 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 908 if (ret_val) 909 goto out; 910 911 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 912 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 913 if (ret_val) 914 goto out; 915 916 /* Does the user want to wait for Auto-Neg to complete here, or 917 * check at a later time (for example, callback routine). 918 */ 919 if (phy->autoneg_wait_to_complete) { 920 ret_val = igb_wait_autoneg(hw); 921 if (ret_val) { 922 hw_dbg("Error while waiting for autoneg to complete\n"); 923 goto out; 924 } 925 } 926 927 hw->mac.get_link_status = true; 928 929 out: 930 return ret_val; 931 } 932 933 /** 934 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation 935 * @hw: pointer to the HW structure 936 * 937 * Reads the MII auto-neg advertisement register and/or the 1000T control 938 * register and if the PHY is already setup for auto-negotiation, then 939 * return successful. Otherwise, setup advertisement and flow control to 940 * the appropriate values for the wanted auto-negotiation. 941 **/ 942 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw) 943 { 944 struct e1000_phy_info *phy = &hw->phy; 945 s32 ret_val; 946 u16 mii_autoneg_adv_reg; 947 u16 mii_1000t_ctrl_reg = 0; 948 949 phy->autoneg_advertised &= phy->autoneg_mask; 950 951 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 952 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 953 if (ret_val) 954 goto out; 955 956 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 957 /* Read the MII 1000Base-T Control Register (Address 9). */ 958 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 959 &mii_1000t_ctrl_reg); 960 if (ret_val) 961 goto out; 962 } 963 964 /* Need to parse both autoneg_advertised and fc and set up 965 * the appropriate PHY registers. First we will parse for 966 * autoneg_advertised software override. Since we can advertise 967 * a plethora of combinations, we need to check each bit 968 * individually. 969 */ 970 971 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 972 * Advertisement Register (Address 4) and the 1000 mb speed bits in 973 * the 1000Base-T Control Register (Address 9). 974 */ 975 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 976 NWAY_AR_100TX_HD_CAPS | 977 NWAY_AR_10T_FD_CAPS | 978 NWAY_AR_10T_HD_CAPS); 979 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 980 981 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); 982 983 /* Do we want to advertise 10 Mb Half Duplex? */ 984 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 985 hw_dbg("Advertise 10mb Half duplex\n"); 986 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 987 } 988 989 /* Do we want to advertise 10 Mb Full Duplex? */ 990 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 991 hw_dbg("Advertise 10mb Full duplex\n"); 992 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 993 } 994 995 /* Do we want to advertise 100 Mb Half Duplex? */ 996 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 997 hw_dbg("Advertise 100mb Half duplex\n"); 998 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 999 } 1000 1001 /* Do we want to advertise 100 Mb Full Duplex? */ 1002 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 1003 hw_dbg("Advertise 100mb Full duplex\n"); 1004 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1005 } 1006 1007 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1008 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 1009 hw_dbg("Advertise 1000mb Half duplex request denied!\n"); 1010 1011 /* Do we want to advertise 1000 Mb Full Duplex? */ 1012 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 1013 hw_dbg("Advertise 1000mb Full duplex\n"); 1014 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1015 } 1016 1017 /* Check for a software override of the flow control settings, and 1018 * setup the PHY advertisement registers accordingly. If 1019 * auto-negotiation is enabled, then software will have to set the 1020 * "PAUSE" bits to the correct value in the Auto-Negotiation 1021 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 1022 * negotiation. 1023 * 1024 * The possible values of the "fc" parameter are: 1025 * 0: Flow control is completely disabled 1026 * 1: Rx flow control is enabled (we can receive pause frames 1027 * but not send pause frames). 1028 * 2: Tx flow control is enabled (we can send pause frames 1029 * but we do not support receiving pause frames). 1030 * 3: Both Rx and TX flow control (symmetric) are enabled. 1031 * other: No software override. The flow control configuration 1032 * in the EEPROM is used. 1033 */ 1034 switch (hw->fc.current_mode) { 1035 case e1000_fc_none: 1036 /* Flow control (RX & TX) is completely disabled by a 1037 * software over-ride. 1038 */ 1039 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1040 break; 1041 case e1000_fc_rx_pause: 1042 /* RX Flow control is enabled, and TX Flow control is 1043 * disabled, by a software over-ride. 1044 * 1045 * Since there really isn't a way to advertise that we are 1046 * capable of RX Pause ONLY, we will advertise that we 1047 * support both symmetric and asymmetric RX PAUSE. Later 1048 * (in e1000_config_fc_after_link_up) we will disable the 1049 * hw's ability to send PAUSE frames. 1050 */ 1051 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1052 break; 1053 case e1000_fc_tx_pause: 1054 /* TX Flow control is enabled, and RX Flow control is 1055 * disabled, by a software over-ride. 1056 */ 1057 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1058 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1059 break; 1060 case e1000_fc_full: 1061 /* Flow control (both RX and TX) is enabled by a software 1062 * over-ride. 1063 */ 1064 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1065 break; 1066 default: 1067 hw_dbg("Flow control param set incorrectly\n"); 1068 ret_val = -E1000_ERR_CONFIG; 1069 goto out; 1070 } 1071 1072 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1073 if (ret_val) 1074 goto out; 1075 1076 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1077 1078 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1079 ret_val = phy->ops.write_reg(hw, 1080 PHY_1000T_CTRL, 1081 mii_1000t_ctrl_reg); 1082 if (ret_val) 1083 goto out; 1084 } 1085 1086 out: 1087 return ret_val; 1088 } 1089 1090 /** 1091 * igb_setup_copper_link - Configure copper link settings 1092 * @hw: pointer to the HW structure 1093 * 1094 * Calls the appropriate function to configure the link for auto-neg or forced 1095 * speed and duplex. Then we check for link, once link is established calls 1096 * to configure collision distance and flow control are called. If link is 1097 * not established, we return -E1000_ERR_PHY (-2). 1098 **/ 1099 s32 igb_setup_copper_link(struct e1000_hw *hw) 1100 { 1101 s32 ret_val; 1102 bool link; 1103 1104 if (hw->mac.autoneg) { 1105 /* Setup autoneg and flow control advertisement and perform 1106 * autonegotiation. 1107 */ 1108 ret_val = igb_copper_link_autoneg(hw); 1109 if (ret_val) 1110 goto out; 1111 } else { 1112 /* PHY will be set to 10H, 10F, 100H or 100F 1113 * depending on user settings. 1114 */ 1115 hw_dbg("Forcing Speed and Duplex\n"); 1116 ret_val = hw->phy.ops.force_speed_duplex(hw); 1117 if (ret_val) { 1118 hw_dbg("Error Forcing Speed and Duplex\n"); 1119 goto out; 1120 } 1121 } 1122 1123 /* Check link status. Wait up to 100 microseconds for link to become 1124 * valid. 1125 */ 1126 ret_val = igb_phy_has_link(hw, COPPER_LINK_UP_LIMIT, 10, &link); 1127 if (ret_val) 1128 goto out; 1129 1130 if (link) { 1131 hw_dbg("Valid link established!!!\n"); 1132 igb_config_collision_dist(hw); 1133 ret_val = igb_config_fc_after_link_up(hw); 1134 } else { 1135 hw_dbg("Unable to establish link!!!\n"); 1136 } 1137 1138 out: 1139 return ret_val; 1140 } 1141 1142 /** 1143 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1144 * @hw: pointer to the HW structure 1145 * 1146 * Calls the PHY setup function to force speed and duplex. Clears the 1147 * auto-crossover to force MDI manually. Waits for link and returns 1148 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1149 **/ 1150 s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1151 { 1152 struct e1000_phy_info *phy = &hw->phy; 1153 s32 ret_val; 1154 u16 phy_data; 1155 bool link; 1156 1157 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1158 if (ret_val) 1159 goto out; 1160 1161 igb_phy_force_speed_duplex_setup(hw, &phy_data); 1162 1163 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1164 if (ret_val) 1165 goto out; 1166 1167 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1168 * forced whenever speed and duplex are forced. 1169 */ 1170 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1171 if (ret_val) 1172 goto out; 1173 1174 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1175 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1176 1177 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1178 if (ret_val) 1179 goto out; 1180 1181 hw_dbg("IGP PSCR: %X\n", phy_data); 1182 1183 udelay(1); 1184 1185 if (phy->autoneg_wait_to_complete) { 1186 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); 1187 1188 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link); 1189 if (ret_val) 1190 goto out; 1191 1192 if (!link) 1193 hw_dbg("Link taking longer than expected.\n"); 1194 1195 /* Try once more */ 1196 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link); 1197 if (ret_val) 1198 goto out; 1199 } 1200 1201 out: 1202 return ret_val; 1203 } 1204 1205 /** 1206 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1207 * @hw: pointer to the HW structure 1208 * 1209 * Calls the PHY setup function to force speed and duplex. Clears the 1210 * auto-crossover to force MDI manually. Resets the PHY to commit the 1211 * changes. If time expires while waiting for link up, we reset the DSP. 1212 * After reset, TX_CLK and CRS on TX must be set. Return successful upon 1213 * successful completion, else return corresponding error code. 1214 **/ 1215 s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1216 { 1217 struct e1000_phy_info *phy = &hw->phy; 1218 s32 ret_val; 1219 u16 phy_data; 1220 bool link; 1221 1222 /* I210 and I211 devices support Auto-Crossover in forced operation. */ 1223 if (phy->type != e1000_phy_i210) { 1224 /* Clear Auto-Crossover to force MDI manually. M88E1000 1225 * requires MDI forced whenever speed and duplex are forced. 1226 */ 1227 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, 1228 &phy_data); 1229 if (ret_val) 1230 goto out; 1231 1232 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1233 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 1234 phy_data); 1235 if (ret_val) 1236 goto out; 1237 1238 hw_dbg("M88E1000 PSCR: %X\n", phy_data); 1239 } 1240 1241 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1242 if (ret_val) 1243 goto out; 1244 1245 igb_phy_force_speed_duplex_setup(hw, &phy_data); 1246 1247 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1248 if (ret_val) 1249 goto out; 1250 1251 /* Reset the phy to commit changes. */ 1252 ret_val = igb_phy_sw_reset(hw); 1253 if (ret_val) 1254 goto out; 1255 1256 if (phy->autoneg_wait_to_complete) { 1257 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); 1258 1259 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); 1260 if (ret_val) 1261 goto out; 1262 1263 if (!link) { 1264 bool reset_dsp = true; 1265 1266 switch (hw->phy.id) { 1267 case I347AT4_E_PHY_ID: 1268 case M88E1112_E_PHY_ID: 1269 case M88E1543_E_PHY_ID: 1270 case M88E1512_E_PHY_ID: 1271 case I210_I_PHY_ID: 1272 reset_dsp = false; 1273 break; 1274 default: 1275 if (hw->phy.type != e1000_phy_m88) 1276 reset_dsp = false; 1277 break; 1278 } 1279 if (!reset_dsp) { 1280 hw_dbg("Link taking longer than expected.\n"); 1281 } else { 1282 /* We didn't get link. 1283 * Reset the DSP and cross our fingers. 1284 */ 1285 ret_val = phy->ops.write_reg(hw, 1286 M88E1000_PHY_PAGE_SELECT, 1287 0x001d); 1288 if (ret_val) 1289 goto out; 1290 ret_val = igb_phy_reset_dsp(hw); 1291 if (ret_val) 1292 goto out; 1293 } 1294 } 1295 1296 /* Try once more */ 1297 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 1298 100000, &link); 1299 if (ret_val) 1300 goto out; 1301 } 1302 1303 if (hw->phy.type != e1000_phy_m88 || 1304 hw->phy.id == I347AT4_E_PHY_ID || 1305 hw->phy.id == M88E1112_E_PHY_ID || 1306 hw->phy.id == M88E1543_E_PHY_ID || 1307 hw->phy.id == M88E1512_E_PHY_ID || 1308 hw->phy.id == I210_I_PHY_ID) 1309 goto out; 1310 1311 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1312 if (ret_val) 1313 goto out; 1314 1315 /* Resetting the phy means we need to re-force TX_CLK in the 1316 * Extended PHY Specific Control Register to 25MHz clock from 1317 * the reset value of 2.5MHz. 1318 */ 1319 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1320 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1321 if (ret_val) 1322 goto out; 1323 1324 /* In addition, we must re-enable CRS on Tx for both half and full 1325 * duplex. 1326 */ 1327 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1328 if (ret_val) 1329 goto out; 1330 1331 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1332 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1333 1334 out: 1335 return ret_val; 1336 } 1337 1338 /** 1339 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 1340 * @hw: pointer to the HW structure 1341 * @phy_ctrl: pointer to current value of PHY_CONTROL 1342 * 1343 * Forces speed and duplex on the PHY by doing the following: disable flow 1344 * control, force speed/duplex on the MAC, disable auto speed detection, 1345 * disable auto-negotiation, configure duplex, configure speed, configure 1346 * the collision distance, write configuration to CTRL register. The 1347 * caller must write to the PHY_CONTROL register for these settings to 1348 * take affect. 1349 **/ 1350 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, 1351 u16 *phy_ctrl) 1352 { 1353 struct e1000_mac_info *mac = &hw->mac; 1354 u32 ctrl; 1355 1356 /* Turn off flow control when forcing speed/duplex */ 1357 hw->fc.current_mode = e1000_fc_none; 1358 1359 /* Force speed/duplex on the mac */ 1360 ctrl = rd32(E1000_CTRL); 1361 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1362 ctrl &= ~E1000_CTRL_SPD_SEL; 1363 1364 /* Disable Auto Speed Detection */ 1365 ctrl &= ~E1000_CTRL_ASDE; 1366 1367 /* Disable autoneg on the phy */ 1368 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 1369 1370 /* Forcing Full or Half Duplex? */ 1371 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 1372 ctrl &= ~E1000_CTRL_FD; 1373 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 1374 hw_dbg("Half Duplex\n"); 1375 } else { 1376 ctrl |= E1000_CTRL_FD; 1377 *phy_ctrl |= MII_CR_FULL_DUPLEX; 1378 hw_dbg("Full Duplex\n"); 1379 } 1380 1381 /* Forcing 10mb or 100mb? */ 1382 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 1383 ctrl |= E1000_CTRL_SPD_100; 1384 *phy_ctrl |= MII_CR_SPEED_100; 1385 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); 1386 hw_dbg("Forcing 100mb\n"); 1387 } else { 1388 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 1389 *phy_ctrl |= MII_CR_SPEED_10; 1390 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 1391 hw_dbg("Forcing 10mb\n"); 1392 } 1393 1394 igb_config_collision_dist(hw); 1395 1396 wr32(E1000_CTRL, ctrl); 1397 } 1398 1399 /** 1400 * igb_set_d3_lplu_state - Sets low power link up state for D3 1401 * @hw: pointer to the HW structure 1402 * @active: boolean used to enable/disable lplu 1403 * 1404 * Success returns 0, Failure returns 1 1405 * 1406 * The low power link up (lplu) state is set to the power management level D3 1407 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1408 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1409 * is used during Dx states where the power conservation is most important. 1410 * During driver activity, SmartSpeed should be enabled so performance is 1411 * maintained. 1412 **/ 1413 s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active) 1414 { 1415 struct e1000_phy_info *phy = &hw->phy; 1416 s32 ret_val = 0; 1417 u16 data; 1418 1419 if (!(hw->phy.ops.read_reg)) 1420 goto out; 1421 1422 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1423 if (ret_val) 1424 goto out; 1425 1426 if (!active) { 1427 data &= ~IGP02E1000_PM_D3_LPLU; 1428 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1429 data); 1430 if (ret_val) 1431 goto out; 1432 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1433 * during Dx states where the power conservation is most 1434 * important. During driver activity we should enable 1435 * SmartSpeed, so performance is maintained. 1436 */ 1437 if (phy->smart_speed == e1000_smart_speed_on) { 1438 ret_val = phy->ops.read_reg(hw, 1439 IGP01E1000_PHY_PORT_CONFIG, 1440 &data); 1441 if (ret_val) 1442 goto out; 1443 1444 data |= IGP01E1000_PSCFR_SMART_SPEED; 1445 ret_val = phy->ops.write_reg(hw, 1446 IGP01E1000_PHY_PORT_CONFIG, 1447 data); 1448 if (ret_val) 1449 goto out; 1450 } else if (phy->smart_speed == e1000_smart_speed_off) { 1451 ret_val = phy->ops.read_reg(hw, 1452 IGP01E1000_PHY_PORT_CONFIG, 1453 &data); 1454 if (ret_val) 1455 goto out; 1456 1457 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1458 ret_val = phy->ops.write_reg(hw, 1459 IGP01E1000_PHY_PORT_CONFIG, 1460 data); 1461 if (ret_val) 1462 goto out; 1463 } 1464 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1465 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1466 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1467 data |= IGP02E1000_PM_D3_LPLU; 1468 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1469 data); 1470 if (ret_val) 1471 goto out; 1472 1473 /* When LPLU is enabled, we should disable SmartSpeed */ 1474 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1475 &data); 1476 if (ret_val) 1477 goto out; 1478 1479 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1480 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1481 data); 1482 } 1483 1484 out: 1485 return ret_val; 1486 } 1487 1488 /** 1489 * igb_check_downshift - Checks whether a downshift in speed occurred 1490 * @hw: pointer to the HW structure 1491 * 1492 * Success returns 0, Failure returns 1 1493 * 1494 * A downshift is detected by querying the PHY link health. 1495 **/ 1496 s32 igb_check_downshift(struct e1000_hw *hw) 1497 { 1498 struct e1000_phy_info *phy = &hw->phy; 1499 s32 ret_val; 1500 u16 phy_data, offset, mask; 1501 1502 switch (phy->type) { 1503 case e1000_phy_i210: 1504 case e1000_phy_m88: 1505 case e1000_phy_gg82563: 1506 offset = M88E1000_PHY_SPEC_STATUS; 1507 mask = M88E1000_PSSR_DOWNSHIFT; 1508 break; 1509 case e1000_phy_igp_2: 1510 case e1000_phy_igp: 1511 case e1000_phy_igp_3: 1512 offset = IGP01E1000_PHY_LINK_HEALTH; 1513 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 1514 break; 1515 default: 1516 /* speed downshift not supported */ 1517 phy->speed_downgraded = false; 1518 ret_val = 0; 1519 goto out; 1520 } 1521 1522 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 1523 1524 if (!ret_val) 1525 phy->speed_downgraded = (phy_data & mask) ? true : false; 1526 1527 out: 1528 return ret_val; 1529 } 1530 1531 /** 1532 * igb_check_polarity_m88 - Checks the polarity. 1533 * @hw: pointer to the HW structure 1534 * 1535 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1536 * 1537 * Polarity is determined based on the PHY specific status register. 1538 **/ 1539 s32 igb_check_polarity_m88(struct e1000_hw *hw) 1540 { 1541 struct e1000_phy_info *phy = &hw->phy; 1542 s32 ret_val; 1543 u16 data; 1544 1545 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 1546 1547 if (!ret_val) 1548 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) 1549 ? e1000_rev_polarity_reversed 1550 : e1000_rev_polarity_normal; 1551 1552 return ret_val; 1553 } 1554 1555 /** 1556 * igb_check_polarity_igp - Checks the polarity. 1557 * @hw: pointer to the HW structure 1558 * 1559 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 1560 * 1561 * Polarity is determined based on the PHY port status register, and the 1562 * current speed (since there is no polarity at 100Mbps). 1563 **/ 1564 static s32 igb_check_polarity_igp(struct e1000_hw *hw) 1565 { 1566 struct e1000_phy_info *phy = &hw->phy; 1567 s32 ret_val; 1568 u16 data, offset, mask; 1569 1570 /* Polarity is determined based on the speed of 1571 * our connection. 1572 */ 1573 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 1574 if (ret_val) 1575 goto out; 1576 1577 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 1578 IGP01E1000_PSSR_SPEED_1000MBPS) { 1579 offset = IGP01E1000_PHY_PCS_INIT_REG; 1580 mask = IGP01E1000_PHY_POLARITY_MASK; 1581 } else { 1582 /* This really only applies to 10Mbps since 1583 * there is no polarity for 100Mbps (always 0). 1584 */ 1585 offset = IGP01E1000_PHY_PORT_STATUS; 1586 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 1587 } 1588 1589 ret_val = phy->ops.read_reg(hw, offset, &data); 1590 1591 if (!ret_val) 1592 phy->cable_polarity = (data & mask) 1593 ? e1000_rev_polarity_reversed 1594 : e1000_rev_polarity_normal; 1595 1596 out: 1597 return ret_val; 1598 } 1599 1600 /** 1601 * igb_wait_autoneg - Wait for auto-neg completion 1602 * @hw: pointer to the HW structure 1603 * 1604 * Waits for auto-negotiation to complete or for the auto-negotiation time 1605 * limit to expire, which ever happens first. 1606 **/ 1607 static s32 igb_wait_autoneg(struct e1000_hw *hw) 1608 { 1609 s32 ret_val = 0; 1610 u16 i, phy_status; 1611 1612 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 1613 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 1614 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1615 if (ret_val) 1616 break; 1617 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1618 if (ret_val) 1619 break; 1620 if (phy_status & MII_SR_AUTONEG_COMPLETE) 1621 break; 1622 msleep(100); 1623 } 1624 1625 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 1626 * has completed. 1627 */ 1628 return ret_val; 1629 } 1630 1631 /** 1632 * igb_phy_has_link - Polls PHY for link 1633 * @hw: pointer to the HW structure 1634 * @iterations: number of times to poll for link 1635 * @usec_interval: delay between polling attempts 1636 * @success: pointer to whether polling was successful or not 1637 * 1638 * Polls the PHY status register for link, 'iterations' number of times. 1639 **/ 1640 s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations, 1641 u32 usec_interval, bool *success) 1642 { 1643 s32 ret_val = 0; 1644 u16 i, phy_status; 1645 1646 for (i = 0; i < iterations; i++) { 1647 /* Some PHYs require the PHY_STATUS register to be read 1648 * twice due to the link bit being sticky. No harm doing 1649 * it across the board. 1650 */ 1651 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1652 if (ret_val && usec_interval > 0) { 1653 /* If the first read fails, another entity may have 1654 * ownership of the resources, wait and try again to 1655 * see if they have relinquished the resources yet. 1656 */ 1657 if (usec_interval >= 1000) 1658 mdelay(usec_interval/1000); 1659 else 1660 udelay(usec_interval); 1661 } 1662 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 1663 if (ret_val) 1664 break; 1665 if (phy_status & MII_SR_LINK_STATUS) 1666 break; 1667 if (usec_interval >= 1000) 1668 mdelay(usec_interval/1000); 1669 else 1670 udelay(usec_interval); 1671 } 1672 1673 *success = (i < iterations) ? true : false; 1674 1675 return ret_val; 1676 } 1677 1678 /** 1679 * igb_get_cable_length_m88 - Determine cable length for m88 PHY 1680 * @hw: pointer to the HW structure 1681 * 1682 * Reads the PHY specific status register to retrieve the cable length 1683 * information. The cable length is determined by averaging the minimum and 1684 * maximum values to get the "average" cable length. The m88 PHY has four 1685 * possible cable length values, which are: 1686 * Register Value Cable Length 1687 * 0 < 50 meters 1688 * 1 50 - 80 meters 1689 * 2 80 - 110 meters 1690 * 3 110 - 140 meters 1691 * 4 > 140 meters 1692 **/ 1693 s32 igb_get_cable_length_m88(struct e1000_hw *hw) 1694 { 1695 struct e1000_phy_info *phy = &hw->phy; 1696 s32 ret_val; 1697 u16 phy_data, index; 1698 1699 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1700 if (ret_val) 1701 goto out; 1702 1703 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1704 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1705 if (index >= ARRAY_SIZE(e1000_m88_cable_length_table) - 1) { 1706 ret_val = -E1000_ERR_PHY; 1707 goto out; 1708 } 1709 1710 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1711 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 1712 1713 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1714 1715 out: 1716 return ret_val; 1717 } 1718 1719 s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw) 1720 { 1721 struct e1000_phy_info *phy = &hw->phy; 1722 s32 ret_val; 1723 u16 phy_data, phy_data2, index, default_page, is_cm; 1724 int len_tot = 0; 1725 u16 len_min; 1726 u16 len_max; 1727 1728 switch (hw->phy.id) { 1729 case M88E1543_E_PHY_ID: 1730 case M88E1512_E_PHY_ID: 1731 case I347AT4_E_PHY_ID: 1732 case I210_I_PHY_ID: 1733 /* Remember the original page select and set it to 7 */ 1734 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 1735 &default_page); 1736 if (ret_val) 1737 goto out; 1738 1739 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07); 1740 if (ret_val) 1741 goto out; 1742 1743 /* Check if the unit of cable length is meters or cm */ 1744 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2); 1745 if (ret_val) 1746 goto out; 1747 1748 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 1749 1750 /* Get cable length from Pair 0 length Regs */ 1751 ret_val = phy->ops.read_reg(hw, I347AT4_PCDL0, &phy_data); 1752 if (ret_val) 1753 goto out; 1754 1755 phy->pair_length[0] = phy_data / (is_cm ? 100 : 1); 1756 len_tot = phy->pair_length[0]; 1757 len_min = phy->pair_length[0]; 1758 len_max = phy->pair_length[0]; 1759 1760 /* Get cable length from Pair 1 length Regs */ 1761 ret_val = phy->ops.read_reg(hw, I347AT4_PCDL1, &phy_data); 1762 if (ret_val) 1763 goto out; 1764 1765 phy->pair_length[1] = phy_data / (is_cm ? 100 : 1); 1766 len_tot += phy->pair_length[1]; 1767 len_min = min(len_min, phy->pair_length[1]); 1768 len_max = max(len_max, phy->pair_length[1]); 1769 1770 /* Get cable length from Pair 2 length Regs */ 1771 ret_val = phy->ops.read_reg(hw, I347AT4_PCDL2, &phy_data); 1772 if (ret_val) 1773 goto out; 1774 1775 phy->pair_length[2] = phy_data / (is_cm ? 100 : 1); 1776 len_tot += phy->pair_length[2]; 1777 len_min = min(len_min, phy->pair_length[2]); 1778 len_max = max(len_max, phy->pair_length[2]); 1779 1780 /* Get cable length from Pair 3 length Regs */ 1781 ret_val = phy->ops.read_reg(hw, I347AT4_PCDL3, &phy_data); 1782 if (ret_val) 1783 goto out; 1784 1785 phy->pair_length[3] = phy_data / (is_cm ? 100 : 1); 1786 len_tot += phy->pair_length[3]; 1787 len_min = min(len_min, phy->pair_length[3]); 1788 len_max = max(len_max, phy->pair_length[3]); 1789 1790 /* Populate the phy structure with cable length in meters */ 1791 phy->min_cable_length = len_min; 1792 phy->max_cable_length = len_max; 1793 phy->cable_length = len_tot / 4; 1794 1795 /* Reset the page selec to its original value */ 1796 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 1797 default_page); 1798 if (ret_val) 1799 goto out; 1800 break; 1801 case M88E1112_E_PHY_ID: 1802 /* Remember the original page select and set it to 5 */ 1803 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 1804 &default_page); 1805 if (ret_val) 1806 goto out; 1807 1808 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05); 1809 if (ret_val) 1810 goto out; 1811 1812 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE, 1813 &phy_data); 1814 if (ret_val) 1815 goto out; 1816 1817 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 1818 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 1819 if (index >= ARRAY_SIZE(e1000_m88_cable_length_table) - 1) { 1820 ret_val = -E1000_ERR_PHY; 1821 goto out; 1822 } 1823 1824 phy->min_cable_length = e1000_m88_cable_length_table[index]; 1825 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 1826 1827 phy->cable_length = (phy->min_cable_length + 1828 phy->max_cable_length) / 2; 1829 1830 /* Reset the page select to its original value */ 1831 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 1832 default_page); 1833 if (ret_val) 1834 goto out; 1835 1836 break; 1837 default: 1838 ret_val = -E1000_ERR_PHY; 1839 goto out; 1840 } 1841 1842 out: 1843 return ret_val; 1844 } 1845 1846 /** 1847 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY 1848 * @hw: pointer to the HW structure 1849 * 1850 * The automatic gain control (agc) normalizes the amplitude of the 1851 * received signal, adjusting for the attenuation produced by the 1852 * cable. By reading the AGC registers, which represent the 1853 * combination of coarse and fine gain value, the value can be put 1854 * into a lookup table to obtain the approximate cable length 1855 * for each channel. 1856 **/ 1857 s32 igb_get_cable_length_igp_2(struct e1000_hw *hw) 1858 { 1859 struct e1000_phy_info *phy = &hw->phy; 1860 s32 ret_val = 0; 1861 u16 phy_data, i, agc_value = 0; 1862 u16 cur_agc_index, max_agc_index = 0; 1863 u16 min_agc_index = ARRAY_SIZE(e1000_igp_2_cable_length_table) - 1; 1864 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { 1865 IGP02E1000_PHY_AGC_A, 1866 IGP02E1000_PHY_AGC_B, 1867 IGP02E1000_PHY_AGC_C, 1868 IGP02E1000_PHY_AGC_D 1869 }; 1870 1871 /* Read the AGC registers for all channels */ 1872 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 1873 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 1874 if (ret_val) 1875 goto out; 1876 1877 /* Getting bits 15:9, which represent the combination of 1878 * coarse and fine gain values. The result is a number 1879 * that can be put into the lookup table to obtain the 1880 * approximate cable length. 1881 */ 1882 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 1883 IGP02E1000_AGC_LENGTH_MASK; 1884 1885 /* Array index bound check. */ 1886 if ((cur_agc_index >= ARRAY_SIZE(e1000_igp_2_cable_length_table)) || 1887 (cur_agc_index == 0)) { 1888 ret_val = -E1000_ERR_PHY; 1889 goto out; 1890 } 1891 1892 /* Remove min & max AGC values from calculation. */ 1893 if (e1000_igp_2_cable_length_table[min_agc_index] > 1894 e1000_igp_2_cable_length_table[cur_agc_index]) 1895 min_agc_index = cur_agc_index; 1896 if (e1000_igp_2_cable_length_table[max_agc_index] < 1897 e1000_igp_2_cable_length_table[cur_agc_index]) 1898 max_agc_index = cur_agc_index; 1899 1900 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 1901 } 1902 1903 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 1904 e1000_igp_2_cable_length_table[max_agc_index]); 1905 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 1906 1907 /* Calculate cable length with the error range of +/- 10 meters. */ 1908 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 1909 (agc_value - IGP02E1000_AGC_RANGE) : 0; 1910 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 1911 1912 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 1913 1914 out: 1915 return ret_val; 1916 } 1917 1918 /** 1919 * igb_get_phy_info_m88 - Retrieve PHY information 1920 * @hw: pointer to the HW structure 1921 * 1922 * Valid for only copper links. Read the PHY status register (sticky read) 1923 * to verify that link is up. Read the PHY special control register to 1924 * determine the polarity and 10base-T extended distance. Read the PHY 1925 * special status register to determine MDI/MDIx and current speed. If 1926 * speed is 1000, then determine cable length, local and remote receiver. 1927 **/ 1928 s32 igb_get_phy_info_m88(struct e1000_hw *hw) 1929 { 1930 struct e1000_phy_info *phy = &hw->phy; 1931 s32 ret_val; 1932 u16 phy_data; 1933 bool link; 1934 1935 if (phy->media_type != e1000_media_type_copper) { 1936 hw_dbg("Phy info is only valid for copper media\n"); 1937 ret_val = -E1000_ERR_CONFIG; 1938 goto out; 1939 } 1940 1941 ret_val = igb_phy_has_link(hw, 1, 0, &link); 1942 if (ret_val) 1943 goto out; 1944 1945 if (!link) { 1946 hw_dbg("Phy info is only valid if link is up\n"); 1947 ret_val = -E1000_ERR_CONFIG; 1948 goto out; 1949 } 1950 1951 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1952 if (ret_val) 1953 goto out; 1954 1955 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL) 1956 ? true : false; 1957 1958 ret_val = igb_check_polarity_m88(hw); 1959 if (ret_val) 1960 goto out; 1961 1962 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 1963 if (ret_val) 1964 goto out; 1965 1966 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false; 1967 1968 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 1969 ret_val = phy->ops.get_cable_length(hw); 1970 if (ret_val) 1971 goto out; 1972 1973 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 1974 if (ret_val) 1975 goto out; 1976 1977 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 1978 ? e1000_1000t_rx_status_ok 1979 : e1000_1000t_rx_status_not_ok; 1980 1981 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 1982 ? e1000_1000t_rx_status_ok 1983 : e1000_1000t_rx_status_not_ok; 1984 } else { 1985 /* Set values to "undefined" */ 1986 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 1987 phy->local_rx = e1000_1000t_rx_status_undefined; 1988 phy->remote_rx = e1000_1000t_rx_status_undefined; 1989 } 1990 1991 out: 1992 return ret_val; 1993 } 1994 1995 /** 1996 * igb_get_phy_info_igp - Retrieve igp PHY information 1997 * @hw: pointer to the HW structure 1998 * 1999 * Read PHY status to determine if link is up. If link is up, then 2000 * set/determine 10base-T extended distance and polarity correction. Read 2001 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2002 * determine on the cable length, local and remote receiver. 2003 **/ 2004 s32 igb_get_phy_info_igp(struct e1000_hw *hw) 2005 { 2006 struct e1000_phy_info *phy = &hw->phy; 2007 s32 ret_val; 2008 u16 data; 2009 bool link; 2010 2011 ret_val = igb_phy_has_link(hw, 1, 0, &link); 2012 if (ret_val) 2013 goto out; 2014 2015 if (!link) { 2016 hw_dbg("Phy info is only valid if link is up\n"); 2017 ret_val = -E1000_ERR_CONFIG; 2018 goto out; 2019 } 2020 2021 phy->polarity_correction = true; 2022 2023 ret_val = igb_check_polarity_igp(hw); 2024 if (ret_val) 2025 goto out; 2026 2027 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2028 if (ret_val) 2029 goto out; 2030 2031 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false; 2032 2033 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2034 IGP01E1000_PSSR_SPEED_1000MBPS) { 2035 ret_val = phy->ops.get_cable_length(hw); 2036 if (ret_val) 2037 goto out; 2038 2039 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2040 if (ret_val) 2041 goto out; 2042 2043 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2044 ? e1000_1000t_rx_status_ok 2045 : e1000_1000t_rx_status_not_ok; 2046 2047 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2048 ? e1000_1000t_rx_status_ok 2049 : e1000_1000t_rx_status_not_ok; 2050 } else { 2051 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2052 phy->local_rx = e1000_1000t_rx_status_undefined; 2053 phy->remote_rx = e1000_1000t_rx_status_undefined; 2054 } 2055 2056 out: 2057 return ret_val; 2058 } 2059 2060 /** 2061 * igb_phy_sw_reset - PHY software reset 2062 * @hw: pointer to the HW structure 2063 * 2064 * Does a software reset of the PHY by reading the PHY control register and 2065 * setting/write the control register reset bit to the PHY. 2066 **/ 2067 s32 igb_phy_sw_reset(struct e1000_hw *hw) 2068 { 2069 s32 ret_val = 0; 2070 u16 phy_ctrl; 2071 2072 if (!(hw->phy.ops.read_reg)) 2073 goto out; 2074 2075 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 2076 if (ret_val) 2077 goto out; 2078 2079 phy_ctrl |= MII_CR_RESET; 2080 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 2081 if (ret_val) 2082 goto out; 2083 2084 udelay(1); 2085 2086 out: 2087 return ret_val; 2088 } 2089 2090 /** 2091 * igb_phy_hw_reset - PHY hardware reset 2092 * @hw: pointer to the HW structure 2093 * 2094 * Verify the reset block is not blocking us from resetting. Acquire 2095 * semaphore (if necessary) and read/set/write the device control reset 2096 * bit in the PHY. Wait the appropriate delay time for the device to 2097 * reset and release the semaphore (if necessary). 2098 **/ 2099 s32 igb_phy_hw_reset(struct e1000_hw *hw) 2100 { 2101 struct e1000_phy_info *phy = &hw->phy; 2102 s32 ret_val; 2103 u32 ctrl; 2104 2105 ret_val = igb_check_reset_block(hw); 2106 if (ret_val) { 2107 ret_val = 0; 2108 goto out; 2109 } 2110 2111 ret_val = phy->ops.acquire(hw); 2112 if (ret_val) 2113 goto out; 2114 2115 ctrl = rd32(E1000_CTRL); 2116 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2117 wrfl(); 2118 2119 udelay(phy->reset_delay_us); 2120 2121 wr32(E1000_CTRL, ctrl); 2122 wrfl(); 2123 2124 udelay(150); 2125 2126 phy->ops.release(hw); 2127 2128 ret_val = phy->ops.get_cfg_done(hw); 2129 2130 out: 2131 return ret_val; 2132 } 2133 2134 /** 2135 * igb_phy_init_script_igp3 - Inits the IGP3 PHY 2136 * @hw: pointer to the HW structure 2137 * 2138 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2139 **/ 2140 s32 igb_phy_init_script_igp3(struct e1000_hw *hw) 2141 { 2142 hw_dbg("Running IGP 3 PHY init script\n"); 2143 2144 /* PHY init IGP 3 */ 2145 /* Enable rise/fall, 10-mode work in class-A */ 2146 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2147 /* Remove all caps from Replica path filter */ 2148 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2149 /* Bias trimming for ADC, AFE and Driver (Default) */ 2150 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2151 /* Increase Hybrid poly bias */ 2152 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2153 /* Add 4% to TX amplitude in Giga mode */ 2154 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2155 /* Disable trimming (TTT) */ 2156 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2157 /* Poly DC correction to 94.6% + 2% for all channels */ 2158 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2159 /* ABS DC correction to 95.9% */ 2160 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2161 /* BG temp curve trim */ 2162 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2163 /* Increasing ADC OPAMP stage 1 currents to max */ 2164 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2165 /* Force 1000 ( required for enabling PHY regs configuration) */ 2166 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2167 /* Set upd_freq to 6 */ 2168 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2169 /* Disable NPDFE */ 2170 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2171 /* Disable adaptive fixed FFE (Default) */ 2172 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2173 /* Enable FFE hysteresis */ 2174 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2175 /* Fixed FFE for short cable lengths */ 2176 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2177 /* Fixed FFE for medium cable lengths */ 2178 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2179 /* Fixed FFE for long cable lengths */ 2180 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2181 /* Enable Adaptive Clip Threshold */ 2182 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2183 /* AHT reset limit to 1 */ 2184 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2185 /* Set AHT master delay to 127 msec */ 2186 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2187 /* Set scan bits for AHT */ 2188 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2189 /* Set AHT Preset bits */ 2190 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2191 /* Change integ_factor of channel A to 3 */ 2192 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2193 /* Change prop_factor of channels BCD to 8 */ 2194 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2195 /* Change cg_icount + enable integbp for channels BCD */ 2196 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2197 /* Change cg_icount + enable integbp + change prop_factor_master 2198 * to 8 for channel A 2199 */ 2200 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2201 /* Disable AHT in Slave mode on channel A */ 2202 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2203 /* Enable LPLU and disable AN to 1000 in non-D0a states, 2204 * Enable SPD+B2B 2205 */ 2206 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2207 /* Enable restart AN on an1000_dis change */ 2208 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2209 /* Enable wh_fifo read clock in 10/100 modes */ 2210 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2211 /* Restart AN, Speed selection is 1000 */ 2212 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2213 2214 return 0; 2215 } 2216 2217 /** 2218 * igb_initialize_M88E1512_phy - Initialize M88E1512 PHY 2219 * @hw: pointer to the HW structure 2220 * 2221 * Initialize Marvel 1512 to work correctly with Avoton. 2222 **/ 2223 s32 igb_initialize_M88E1512_phy(struct e1000_hw *hw) 2224 { 2225 struct e1000_phy_info *phy = &hw->phy; 2226 s32 ret_val = 0; 2227 2228 /* Switch to PHY page 0xFF. */ 2229 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF); 2230 if (ret_val) 2231 goto out; 2232 2233 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B); 2234 if (ret_val) 2235 goto out; 2236 2237 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144); 2238 if (ret_val) 2239 goto out; 2240 2241 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28); 2242 if (ret_val) 2243 goto out; 2244 2245 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146); 2246 if (ret_val) 2247 goto out; 2248 2249 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233); 2250 if (ret_val) 2251 goto out; 2252 2253 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D); 2254 if (ret_val) 2255 goto out; 2256 2257 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xCC0C); 2258 if (ret_val) 2259 goto out; 2260 2261 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159); 2262 if (ret_val) 2263 goto out; 2264 2265 /* Switch to PHY page 0xFB. */ 2266 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB); 2267 if (ret_val) 2268 goto out; 2269 2270 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x000D); 2271 if (ret_val) 2272 goto out; 2273 2274 /* Switch to PHY page 0x12. */ 2275 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12); 2276 if (ret_val) 2277 goto out; 2278 2279 /* Change mode to SGMII-to-Copper */ 2280 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001); 2281 if (ret_val) 2282 goto out; 2283 2284 /* Return the PHY to page 0. */ 2285 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); 2286 if (ret_val) 2287 goto out; 2288 2289 ret_val = igb_phy_sw_reset(hw); 2290 if (ret_val) { 2291 hw_dbg("Error committing the PHY changes\n"); 2292 return ret_val; 2293 } 2294 2295 /* msec_delay(1000); */ 2296 usleep_range(1000, 2000); 2297 out: 2298 return ret_val; 2299 } 2300 2301 /** 2302 * igb_initialize_M88E1543_phy - Initialize M88E1512 PHY 2303 * @hw: pointer to the HW structure 2304 * 2305 * Initialize Marvell 1543 to work correctly with Avoton. 2306 **/ 2307 s32 igb_initialize_M88E1543_phy(struct e1000_hw *hw) 2308 { 2309 struct e1000_phy_info *phy = &hw->phy; 2310 s32 ret_val = 0; 2311 2312 /* Switch to PHY page 0xFF. */ 2313 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FF); 2314 if (ret_val) 2315 goto out; 2316 2317 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x214B); 2318 if (ret_val) 2319 goto out; 2320 2321 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2144); 2322 if (ret_val) 2323 goto out; 2324 2325 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0x0C28); 2326 if (ret_val) 2327 goto out; 2328 2329 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2146); 2330 if (ret_val) 2331 goto out; 2332 2333 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xB233); 2334 if (ret_val) 2335 goto out; 2336 2337 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x214D); 2338 if (ret_val) 2339 goto out; 2340 2341 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_2, 0xDC0C); 2342 if (ret_val) 2343 goto out; 2344 2345 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_1, 0x2159); 2346 if (ret_val) 2347 goto out; 2348 2349 /* Switch to PHY page 0xFB. */ 2350 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x00FB); 2351 if (ret_val) 2352 goto out; 2353 2354 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_CFG_REG_3, 0x0C0D); 2355 if (ret_val) 2356 goto out; 2357 2358 /* Switch to PHY page 0x12. */ 2359 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x12); 2360 if (ret_val) 2361 goto out; 2362 2363 /* Change mode to SGMII-to-Copper */ 2364 ret_val = phy->ops.write_reg(hw, E1000_M88E1512_MODE, 0x8001); 2365 if (ret_val) 2366 goto out; 2367 2368 /* Switch to PHY page 1. */ 2369 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0x1); 2370 if (ret_val) 2371 goto out; 2372 2373 /* Change mode to 1000BASE-X/SGMII and autoneg enable */ 2374 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_FIBER_CTRL, 0x9140); 2375 if (ret_val) 2376 goto out; 2377 2378 /* Return the PHY to page 0. */ 2379 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); 2380 if (ret_val) 2381 goto out; 2382 2383 ret_val = igb_phy_sw_reset(hw); 2384 if (ret_val) { 2385 hw_dbg("Error committing the PHY changes\n"); 2386 return ret_val; 2387 } 2388 2389 /* msec_delay(1000); */ 2390 usleep_range(1000, 2000); 2391 out: 2392 return ret_val; 2393 } 2394 2395 /** 2396 * igb_power_up_phy_copper - Restore copper link in case of PHY power down 2397 * @hw: pointer to the HW structure 2398 * 2399 * In the case of a PHY power down to save power, or to turn off link during a 2400 * driver unload, restore the link to previous settings. 2401 **/ 2402 void igb_power_up_phy_copper(struct e1000_hw *hw) 2403 { 2404 u16 mii_reg = 0; 2405 2406 /* The PHY will retain its settings across a power down/up cycle */ 2407 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2408 mii_reg &= ~MII_CR_POWER_DOWN; 2409 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2410 } 2411 2412 /** 2413 * igb_power_down_phy_copper - Power down copper PHY 2414 * @hw: pointer to the HW structure 2415 * 2416 * Power down PHY to save power when interface is down and wake on lan 2417 * is not enabled. 2418 **/ 2419 void igb_power_down_phy_copper(struct e1000_hw *hw) 2420 { 2421 u16 mii_reg = 0; 2422 2423 /* The PHY will retain its settings across a power down/up cycle */ 2424 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 2425 mii_reg |= MII_CR_POWER_DOWN; 2426 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 2427 usleep_range(1000, 2000); 2428 } 2429 2430 /** 2431 * igb_check_polarity_82580 - Checks the polarity. 2432 * @hw: pointer to the HW structure 2433 * 2434 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2435 * 2436 * Polarity is determined based on the PHY specific status register. 2437 **/ 2438 static s32 igb_check_polarity_82580(struct e1000_hw *hw) 2439 { 2440 struct e1000_phy_info *phy = &hw->phy; 2441 s32 ret_val; 2442 u16 data; 2443 2444 2445 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); 2446 2447 if (!ret_val) 2448 phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY) 2449 ? e1000_rev_polarity_reversed 2450 : e1000_rev_polarity_normal; 2451 2452 return ret_val; 2453 } 2454 2455 /** 2456 * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY 2457 * @hw: pointer to the HW structure 2458 * 2459 * Calls the PHY setup function to force speed and duplex. Clears the 2460 * auto-crossover to force MDI manually. Waits for link and returns 2461 * successful if link up is successful, else -E1000_ERR_PHY (-2). 2462 **/ 2463 s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw) 2464 { 2465 struct e1000_phy_info *phy = &hw->phy; 2466 s32 ret_val; 2467 u16 phy_data; 2468 bool link; 2469 2470 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 2471 if (ret_val) 2472 goto out; 2473 2474 igb_phy_force_speed_duplex_setup(hw, &phy_data); 2475 2476 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 2477 if (ret_val) 2478 goto out; 2479 2480 /* Clear Auto-Crossover to force MDI manually. 82580 requires MDI 2481 * forced whenever speed and duplex are forced. 2482 */ 2483 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data); 2484 if (ret_val) 2485 goto out; 2486 2487 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK; 2488 2489 ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data); 2490 if (ret_val) 2491 goto out; 2492 2493 hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data); 2494 2495 udelay(1); 2496 2497 if (phy->autoneg_wait_to_complete) { 2498 hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n"); 2499 2500 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); 2501 if (ret_val) 2502 goto out; 2503 2504 if (!link) 2505 hw_dbg("Link taking longer than expected.\n"); 2506 2507 /* Try once more */ 2508 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link); 2509 if (ret_val) 2510 goto out; 2511 } 2512 2513 out: 2514 return ret_val; 2515 } 2516 2517 /** 2518 * igb_get_phy_info_82580 - Retrieve I82580 PHY information 2519 * @hw: pointer to the HW structure 2520 * 2521 * Read PHY status to determine if link is up. If link is up, then 2522 * set/determine 10base-T extended distance and polarity correction. Read 2523 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2524 * determine on the cable length, local and remote receiver. 2525 **/ 2526 s32 igb_get_phy_info_82580(struct e1000_hw *hw) 2527 { 2528 struct e1000_phy_info *phy = &hw->phy; 2529 s32 ret_val; 2530 u16 data; 2531 bool link; 2532 2533 ret_val = igb_phy_has_link(hw, 1, 0, &link); 2534 if (ret_val) 2535 goto out; 2536 2537 if (!link) { 2538 hw_dbg("Phy info is only valid if link is up\n"); 2539 ret_val = -E1000_ERR_CONFIG; 2540 goto out; 2541 } 2542 2543 phy->polarity_correction = true; 2544 2545 ret_val = igb_check_polarity_82580(hw); 2546 if (ret_val) 2547 goto out; 2548 2549 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data); 2550 if (ret_val) 2551 goto out; 2552 2553 phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false; 2554 2555 if ((data & I82580_PHY_STATUS2_SPEED_MASK) == 2556 I82580_PHY_STATUS2_SPEED_1000MBPS) { 2557 ret_val = hw->phy.ops.get_cable_length(hw); 2558 if (ret_val) 2559 goto out; 2560 2561 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2562 if (ret_val) 2563 goto out; 2564 2565 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2566 ? e1000_1000t_rx_status_ok 2567 : e1000_1000t_rx_status_not_ok; 2568 2569 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2570 ? e1000_1000t_rx_status_ok 2571 : e1000_1000t_rx_status_not_ok; 2572 } else { 2573 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2574 phy->local_rx = e1000_1000t_rx_status_undefined; 2575 phy->remote_rx = e1000_1000t_rx_status_undefined; 2576 } 2577 2578 out: 2579 return ret_val; 2580 } 2581 2582 /** 2583 * igb_get_cable_length_82580 - Determine cable length for 82580 PHY 2584 * @hw: pointer to the HW structure 2585 * 2586 * Reads the diagnostic status register and verifies result is valid before 2587 * placing it in the phy_cable_length field. 2588 **/ 2589 s32 igb_get_cable_length_82580(struct e1000_hw *hw) 2590 { 2591 struct e1000_phy_info *phy = &hw->phy; 2592 s32 ret_val; 2593 u16 phy_data, length; 2594 2595 ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data); 2596 if (ret_val) 2597 goto out; 2598 2599 length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >> 2600 I82580_DSTATUS_CABLE_LENGTH_SHIFT; 2601 2602 if (length == E1000_CABLE_LENGTH_UNDEFINED) 2603 ret_val = -E1000_ERR_PHY; 2604 2605 phy->cable_length = length; 2606 2607 out: 2608 return ret_val; 2609 } 2610 2611 /** 2612 * igb_set_master_slave_mode - Setup PHY for Master/slave mode 2613 * @hw: pointer to the HW structure 2614 * 2615 * Sets up Master/slave mode 2616 **/ 2617 static s32 igb_set_master_slave_mode(struct e1000_hw *hw) 2618 { 2619 s32 ret_val; 2620 u16 phy_data; 2621 2622 /* Resolve Master/Slave mode */ 2623 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data); 2624 if (ret_val) 2625 return ret_val; 2626 2627 /* load defaults for future use */ 2628 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ? 2629 ((phy_data & CR_1000T_MS_VALUE) ? 2630 e1000_ms_force_master : 2631 e1000_ms_force_slave) : e1000_ms_auto; 2632 2633 switch (hw->phy.ms_type) { 2634 case e1000_ms_force_master: 2635 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 2636 break; 2637 case e1000_ms_force_slave: 2638 phy_data |= CR_1000T_MS_ENABLE; 2639 phy_data &= ~(CR_1000T_MS_VALUE); 2640 break; 2641 case e1000_ms_auto: 2642 phy_data &= ~CR_1000T_MS_ENABLE; 2643 /* fall-through */ 2644 default: 2645 break; 2646 } 2647 2648 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data); 2649 } 2650