1 /******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #include <linux/if_ether.h> 29 #include <linux/delay.h> 30 31 #include "e1000_mac.h" 32 #include "e1000_nvm.h" 33 34 /** 35 * igb_raise_eec_clk - Raise EEPROM clock 36 * @hw: pointer to the HW structure 37 * @eecd: pointer to the EEPROM 38 * 39 * Enable/Raise the EEPROM clock bit. 40 **/ 41 static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) 42 { 43 *eecd = *eecd | E1000_EECD_SK; 44 wr32(E1000_EECD, *eecd); 45 wrfl(); 46 udelay(hw->nvm.delay_usec); 47 } 48 49 /** 50 * igb_lower_eec_clk - Lower EEPROM clock 51 * @hw: pointer to the HW structure 52 * @eecd: pointer to the EEPROM 53 * 54 * Clear/Lower the EEPROM clock bit. 55 **/ 56 static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) 57 { 58 *eecd = *eecd & ~E1000_EECD_SK; 59 wr32(E1000_EECD, *eecd); 60 wrfl(); 61 udelay(hw->nvm.delay_usec); 62 } 63 64 /** 65 * igb_shift_out_eec_bits - Shift data bits our to the EEPROM 66 * @hw: pointer to the HW structure 67 * @data: data to send to the EEPROM 68 * @count: number of bits to shift out 69 * 70 * We need to shift 'count' bits out to the EEPROM. So, the value in the 71 * "data" parameter will be shifted out to the EEPROM one bit at a time. 72 * In order to do this, "data" must be broken down into bits. 73 **/ 74 static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) 75 { 76 struct e1000_nvm_info *nvm = &hw->nvm; 77 u32 eecd = rd32(E1000_EECD); 78 u32 mask; 79 80 mask = 0x01 << (count - 1); 81 if (nvm->type == e1000_nvm_eeprom_spi) 82 eecd |= E1000_EECD_DO; 83 84 do { 85 eecd &= ~E1000_EECD_DI; 86 87 if (data & mask) 88 eecd |= E1000_EECD_DI; 89 90 wr32(E1000_EECD, eecd); 91 wrfl(); 92 93 udelay(nvm->delay_usec); 94 95 igb_raise_eec_clk(hw, &eecd); 96 igb_lower_eec_clk(hw, &eecd); 97 98 mask >>= 1; 99 } while (mask); 100 101 eecd &= ~E1000_EECD_DI; 102 wr32(E1000_EECD, eecd); 103 } 104 105 /** 106 * igb_shift_in_eec_bits - Shift data bits in from the EEPROM 107 * @hw: pointer to the HW structure 108 * @count: number of bits to shift in 109 * 110 * In order to read a register from the EEPROM, we need to shift 'count' bits 111 * in from the EEPROM. Bits are "shifted in" by raising the clock input to 112 * the EEPROM (setting the SK bit), and then reading the value of the data out 113 * "DO" bit. During this "shifting in" process the data in "DI" bit should 114 * always be clear. 115 **/ 116 static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count) 117 { 118 u32 eecd; 119 u32 i; 120 u16 data; 121 122 eecd = rd32(E1000_EECD); 123 124 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 125 data = 0; 126 127 for (i = 0; i < count; i++) { 128 data <<= 1; 129 igb_raise_eec_clk(hw, &eecd); 130 131 eecd = rd32(E1000_EECD); 132 133 eecd &= ~E1000_EECD_DI; 134 if (eecd & E1000_EECD_DO) 135 data |= 1; 136 137 igb_lower_eec_clk(hw, &eecd); 138 } 139 140 return data; 141 } 142 143 /** 144 * igb_poll_eerd_eewr_done - Poll for EEPROM read/write completion 145 * @hw: pointer to the HW structure 146 * @ee_reg: EEPROM flag for polling 147 * 148 * Polls the EEPROM status bit for either read or write completion based 149 * upon the value of 'ee_reg'. 150 **/ 151 static s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) 152 { 153 u32 attempts = 100000; 154 u32 i, reg = 0; 155 s32 ret_val = -E1000_ERR_NVM; 156 157 for (i = 0; i < attempts; i++) { 158 if (ee_reg == E1000_NVM_POLL_READ) 159 reg = rd32(E1000_EERD); 160 else 161 reg = rd32(E1000_EEWR); 162 163 if (reg & E1000_NVM_RW_REG_DONE) { 164 ret_val = 0; 165 break; 166 } 167 168 udelay(5); 169 } 170 171 return ret_val; 172 } 173 174 /** 175 * igb_acquire_nvm - Generic request for access to EEPROM 176 * @hw: pointer to the HW structure 177 * 178 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 179 * Return successful if access grant bit set, else clear the request for 180 * EEPROM access and return -E1000_ERR_NVM (-1). 181 **/ 182 s32 igb_acquire_nvm(struct e1000_hw *hw) 183 { 184 u32 eecd = rd32(E1000_EECD); 185 s32 timeout = E1000_NVM_GRANT_ATTEMPTS; 186 s32 ret_val = 0; 187 188 189 wr32(E1000_EECD, eecd | E1000_EECD_REQ); 190 eecd = rd32(E1000_EECD); 191 192 while (timeout) { 193 if (eecd & E1000_EECD_GNT) 194 break; 195 udelay(5); 196 eecd = rd32(E1000_EECD); 197 timeout--; 198 } 199 200 if (!timeout) { 201 eecd &= ~E1000_EECD_REQ; 202 wr32(E1000_EECD, eecd); 203 hw_dbg("Could not acquire NVM grant\n"); 204 ret_val = -E1000_ERR_NVM; 205 } 206 207 return ret_val; 208 } 209 210 /** 211 * igb_standby_nvm - Return EEPROM to standby state 212 * @hw: pointer to the HW structure 213 * 214 * Return the EEPROM to a standby state. 215 **/ 216 static void igb_standby_nvm(struct e1000_hw *hw) 217 { 218 struct e1000_nvm_info *nvm = &hw->nvm; 219 u32 eecd = rd32(E1000_EECD); 220 221 if (nvm->type == e1000_nvm_eeprom_spi) { 222 /* Toggle CS to flush commands */ 223 eecd |= E1000_EECD_CS; 224 wr32(E1000_EECD, eecd); 225 wrfl(); 226 udelay(nvm->delay_usec); 227 eecd &= ~E1000_EECD_CS; 228 wr32(E1000_EECD, eecd); 229 wrfl(); 230 udelay(nvm->delay_usec); 231 } 232 } 233 234 /** 235 * e1000_stop_nvm - Terminate EEPROM command 236 * @hw: pointer to the HW structure 237 * 238 * Terminates the current command by inverting the EEPROM's chip select pin. 239 **/ 240 static void e1000_stop_nvm(struct e1000_hw *hw) 241 { 242 u32 eecd; 243 244 eecd = rd32(E1000_EECD); 245 if (hw->nvm.type == e1000_nvm_eeprom_spi) { 246 /* Pull CS high */ 247 eecd |= E1000_EECD_CS; 248 igb_lower_eec_clk(hw, &eecd); 249 } 250 } 251 252 /** 253 * igb_release_nvm - Release exclusive access to EEPROM 254 * @hw: pointer to the HW structure 255 * 256 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 257 **/ 258 void igb_release_nvm(struct e1000_hw *hw) 259 { 260 u32 eecd; 261 262 e1000_stop_nvm(hw); 263 264 eecd = rd32(E1000_EECD); 265 eecd &= ~E1000_EECD_REQ; 266 wr32(E1000_EECD, eecd); 267 } 268 269 /** 270 * igb_ready_nvm_eeprom - Prepares EEPROM for read/write 271 * @hw: pointer to the HW structure 272 * 273 * Setups the EEPROM for reading and writing. 274 **/ 275 static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw) 276 { 277 struct e1000_nvm_info *nvm = &hw->nvm; 278 u32 eecd = rd32(E1000_EECD); 279 s32 ret_val = 0; 280 u16 timeout = 0; 281 u8 spi_stat_reg; 282 283 284 if (nvm->type == e1000_nvm_eeprom_spi) { 285 /* Clear SK and CS */ 286 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 287 wr32(E1000_EECD, eecd); 288 wrfl(); 289 udelay(1); 290 timeout = NVM_MAX_RETRY_SPI; 291 292 /* 293 * Read "Status Register" repeatedly until the LSB is cleared. 294 * The EEPROM will signal that the command has been completed 295 * by clearing bit 0 of the internal status register. If it's 296 * not cleared within 'timeout', then error out. 297 */ 298 while (timeout) { 299 igb_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, 300 hw->nvm.opcode_bits); 301 spi_stat_reg = (u8)igb_shift_in_eec_bits(hw, 8); 302 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) 303 break; 304 305 udelay(5); 306 igb_standby_nvm(hw); 307 timeout--; 308 } 309 310 if (!timeout) { 311 hw_dbg("SPI NVM Status error\n"); 312 ret_val = -E1000_ERR_NVM; 313 goto out; 314 } 315 } 316 317 out: 318 return ret_val; 319 } 320 321 /** 322 * igb_read_nvm_spi - Read EEPROM's using SPI 323 * @hw: pointer to the HW structure 324 * @offset: offset of word in the EEPROM to read 325 * @words: number of words to read 326 * @data: word read from the EEPROM 327 * 328 * Reads a 16 bit word from the EEPROM. 329 **/ 330 s32 igb_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 331 { 332 struct e1000_nvm_info *nvm = &hw->nvm; 333 u32 i = 0; 334 s32 ret_val; 335 u16 word_in; 336 u8 read_opcode = NVM_READ_OPCODE_SPI; 337 338 /* 339 * A check for invalid values: offset too large, too many words, 340 * and not enough words. 341 */ 342 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 343 (words == 0)) { 344 hw_dbg("nvm parameter(s) out of bounds\n"); 345 ret_val = -E1000_ERR_NVM; 346 goto out; 347 } 348 349 ret_val = nvm->ops.acquire(hw); 350 if (ret_val) 351 goto out; 352 353 ret_val = igb_ready_nvm_eeprom(hw); 354 if (ret_val) 355 goto release; 356 357 igb_standby_nvm(hw); 358 359 if ((nvm->address_bits == 8) && (offset >= 128)) 360 read_opcode |= NVM_A8_OPCODE_SPI; 361 362 /* Send the READ command (opcode + addr) */ 363 igb_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); 364 igb_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits); 365 366 /* 367 * Read the data. SPI NVMs increment the address with each byte 368 * read and will roll over if reading beyond the end. This allows 369 * us to read the whole NVM from any offset 370 */ 371 for (i = 0; i < words; i++) { 372 word_in = igb_shift_in_eec_bits(hw, 16); 373 data[i] = (word_in >> 8) | (word_in << 8); 374 } 375 376 release: 377 nvm->ops.release(hw); 378 379 out: 380 return ret_val; 381 } 382 383 /** 384 * igb_read_nvm_eerd - Reads EEPROM using EERD register 385 * @hw: pointer to the HW structure 386 * @offset: offset of word in the EEPROM to read 387 * @words: number of words to read 388 * @data: word read from the EEPROM 389 * 390 * Reads a 16 bit word from the EEPROM using the EERD register. 391 **/ 392 s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 393 { 394 struct e1000_nvm_info *nvm = &hw->nvm; 395 u32 i, eerd = 0; 396 s32 ret_val = 0; 397 398 /* 399 * A check for invalid values: offset too large, too many words, 400 * and not enough words. 401 */ 402 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 403 (words == 0)) { 404 hw_dbg("nvm parameter(s) out of bounds\n"); 405 ret_val = -E1000_ERR_NVM; 406 goto out; 407 } 408 409 for (i = 0; i < words; i++) { 410 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) + 411 E1000_NVM_RW_REG_START; 412 413 wr32(E1000_EERD, eerd); 414 ret_val = igb_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); 415 if (ret_val) 416 break; 417 418 data[i] = (rd32(E1000_EERD) >> 419 E1000_NVM_RW_REG_DATA); 420 } 421 422 out: 423 return ret_val; 424 } 425 426 /** 427 * igb_write_nvm_spi - Write to EEPROM using SPI 428 * @hw: pointer to the HW structure 429 * @offset: offset within the EEPROM to be written to 430 * @words: number of words to write 431 * @data: 16 bit word(s) to be written to the EEPROM 432 * 433 * Writes data to EEPROM at offset using SPI interface. 434 * 435 * If e1000_update_nvm_checksum is not called after this function , the 436 * EEPROM will most likley contain an invalid checksum. 437 **/ 438 s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 439 { 440 struct e1000_nvm_info *nvm = &hw->nvm; 441 s32 ret_val = -E1000_ERR_NVM; 442 u16 widx = 0; 443 444 /* 445 * A check for invalid values: offset too large, too many words, 446 * and not enough words. 447 */ 448 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 449 (words == 0)) { 450 hw_dbg("nvm parameter(s) out of bounds\n"); 451 return ret_val; 452 } 453 454 while (widx < words) { 455 u8 write_opcode = NVM_WRITE_OPCODE_SPI; 456 457 ret_val = nvm->ops.acquire(hw); 458 if (ret_val) 459 return ret_val; 460 461 ret_val = igb_ready_nvm_eeprom(hw); 462 if (ret_val) { 463 nvm->ops.release(hw); 464 return ret_val; 465 } 466 467 igb_standby_nvm(hw); 468 469 /* Send the WRITE ENABLE command (8 bit opcode) */ 470 igb_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, 471 nvm->opcode_bits); 472 473 igb_standby_nvm(hw); 474 475 /* 476 * Some SPI eeproms use the 8th address bit embedded in the 477 * opcode 478 */ 479 if ((nvm->address_bits == 8) && (offset >= 128)) 480 write_opcode |= NVM_A8_OPCODE_SPI; 481 482 /* Send the Write command (8-bit opcode + addr) */ 483 igb_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); 484 igb_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), 485 nvm->address_bits); 486 487 /* Loop to allow for up to whole page write of eeprom */ 488 while (widx < words) { 489 u16 word_out = data[widx]; 490 word_out = (word_out >> 8) | (word_out << 8); 491 igb_shift_out_eec_bits(hw, word_out, 16); 492 widx++; 493 494 if ((((offset + widx) * 2) % nvm->page_size) == 0) { 495 igb_standby_nvm(hw); 496 break; 497 } 498 } 499 usleep_range(1000, 2000); 500 nvm->ops.release(hw); 501 } 502 503 return ret_val; 504 } 505 506 /** 507 * igb_read_part_string - Read device part number 508 * @hw: pointer to the HW structure 509 * @part_num: pointer to device part number 510 * @part_num_size: size of part number buffer 511 * 512 * Reads the product board assembly (PBA) number from the EEPROM and stores 513 * the value in part_num. 514 **/ 515 s32 igb_read_part_string(struct e1000_hw *hw, u8 *part_num, u32 part_num_size) 516 { 517 s32 ret_val; 518 u16 nvm_data; 519 u16 pointer; 520 u16 offset; 521 u16 length; 522 523 if (part_num == NULL) { 524 hw_dbg("PBA string buffer was null\n"); 525 ret_val = E1000_ERR_INVALID_ARGUMENT; 526 goto out; 527 } 528 529 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 530 if (ret_val) { 531 hw_dbg("NVM Read Error\n"); 532 goto out; 533 } 534 535 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pointer); 536 if (ret_val) { 537 hw_dbg("NVM Read Error\n"); 538 goto out; 539 } 540 541 /* 542 * if nvm_data is not ptr guard the PBA must be in legacy format which 543 * means pointer is actually our second data word for the PBA number 544 * and we can decode it into an ascii string 545 */ 546 if (nvm_data != NVM_PBA_PTR_GUARD) { 547 hw_dbg("NVM PBA number is not stored as string\n"); 548 549 /* we will need 11 characters to store the PBA */ 550 if (part_num_size < 11) { 551 hw_dbg("PBA string buffer too small\n"); 552 return E1000_ERR_NO_SPACE; 553 } 554 555 /* extract hex string from data and pointer */ 556 part_num[0] = (nvm_data >> 12) & 0xF; 557 part_num[1] = (nvm_data >> 8) & 0xF; 558 part_num[2] = (nvm_data >> 4) & 0xF; 559 part_num[3] = nvm_data & 0xF; 560 part_num[4] = (pointer >> 12) & 0xF; 561 part_num[5] = (pointer >> 8) & 0xF; 562 part_num[6] = '-'; 563 part_num[7] = 0; 564 part_num[8] = (pointer >> 4) & 0xF; 565 part_num[9] = pointer & 0xF; 566 567 /* put a null character on the end of our string */ 568 part_num[10] = '\0'; 569 570 /* switch all the data but the '-' to hex char */ 571 for (offset = 0; offset < 10; offset++) { 572 if (part_num[offset] < 0xA) 573 part_num[offset] += '0'; 574 else if (part_num[offset] < 0x10) 575 part_num[offset] += 'A' - 0xA; 576 } 577 578 goto out; 579 } 580 581 ret_val = hw->nvm.ops.read(hw, pointer, 1, &length); 582 if (ret_val) { 583 hw_dbg("NVM Read Error\n"); 584 goto out; 585 } 586 587 if (length == 0xFFFF || length == 0) { 588 hw_dbg("NVM PBA number section invalid length\n"); 589 ret_val = E1000_ERR_NVM_PBA_SECTION; 590 goto out; 591 } 592 /* check if part_num buffer is big enough */ 593 if (part_num_size < (((u32)length * 2) - 1)) { 594 hw_dbg("PBA string buffer too small\n"); 595 ret_val = E1000_ERR_NO_SPACE; 596 goto out; 597 } 598 599 /* trim pba length from start of string */ 600 pointer++; 601 length--; 602 603 for (offset = 0; offset < length; offset++) { 604 ret_val = hw->nvm.ops.read(hw, pointer + offset, 1, &nvm_data); 605 if (ret_val) { 606 hw_dbg("NVM Read Error\n"); 607 goto out; 608 } 609 part_num[offset * 2] = (u8)(nvm_data >> 8); 610 part_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF); 611 } 612 part_num[offset * 2] = '\0'; 613 614 out: 615 return ret_val; 616 } 617 618 /** 619 * igb_read_mac_addr - Read device MAC address 620 * @hw: pointer to the HW structure 621 * 622 * Reads the device MAC address from the EEPROM and stores the value. 623 * Since devices with two ports use the same EEPROM, we increment the 624 * last bit in the MAC address for the second port. 625 **/ 626 s32 igb_read_mac_addr(struct e1000_hw *hw) 627 { 628 u32 rar_high; 629 u32 rar_low; 630 u16 i; 631 632 rar_high = rd32(E1000_RAH(0)); 633 rar_low = rd32(E1000_RAL(0)); 634 635 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++) 636 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8)); 637 638 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++) 639 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8)); 640 641 for (i = 0; i < ETH_ALEN; i++) 642 hw->mac.addr[i] = hw->mac.perm_addr[i]; 643 644 return 0; 645 } 646 647 /** 648 * igb_validate_nvm_checksum - Validate EEPROM checksum 649 * @hw: pointer to the HW structure 650 * 651 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 652 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 653 **/ 654 s32 igb_validate_nvm_checksum(struct e1000_hw *hw) 655 { 656 s32 ret_val = 0; 657 u16 checksum = 0; 658 u16 i, nvm_data; 659 660 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { 661 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 662 if (ret_val) { 663 hw_dbg("NVM Read Error\n"); 664 goto out; 665 } 666 checksum += nvm_data; 667 } 668 669 if (checksum != (u16) NVM_SUM) { 670 hw_dbg("NVM Checksum Invalid\n"); 671 ret_val = -E1000_ERR_NVM; 672 goto out; 673 } 674 675 out: 676 return ret_val; 677 } 678 679 /** 680 * igb_update_nvm_checksum - Update EEPROM checksum 681 * @hw: pointer to the HW structure 682 * 683 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 684 * up to the checksum. Then calculates the EEPROM checksum and writes the 685 * value to the EEPROM. 686 **/ 687 s32 igb_update_nvm_checksum(struct e1000_hw *hw) 688 { 689 s32 ret_val; 690 u16 checksum = 0; 691 u16 i, nvm_data; 692 693 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 694 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 695 if (ret_val) { 696 hw_dbg("NVM Read Error while updating checksum.\n"); 697 goto out; 698 } 699 checksum += nvm_data; 700 } 701 checksum = (u16) NVM_SUM - checksum; 702 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum); 703 if (ret_val) 704 hw_dbg("NVM Write Error while updating checksum.\n"); 705 706 out: 707 return ret_val; 708 } 709 710 /** 711 * igb_get_fw_version - Get firmware version information 712 * @hw: pointer to the HW structure 713 * @fw_vers: pointer to output structure 714 * 715 * unsupported MAC types will return all 0 version structure 716 **/ 717 void igb_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers) 718 { 719 u16 eeprom_verh, eeprom_verl, comb_verh, comb_verl, comb_offset; 720 u16 fw_version; 721 722 memset(fw_vers, 0, sizeof(struct e1000_fw_version)); 723 724 switch (hw->mac.type) { 725 case e1000_i211: 726 igb_read_invm_version(hw, fw_vers); 727 return; 728 case e1000_82575: 729 case e1000_82576: 730 case e1000_82580: 731 case e1000_i350: 732 case e1000_i210: 733 break; 734 default: 735 return; 736 } 737 /* basic eeprom version numbers */ 738 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version); 739 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK) >> NVM_MAJOR_SHIFT; 740 fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK); 741 742 /* etrack id */ 743 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl); 744 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh); 745 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) | eeprom_verl; 746 747 switch (hw->mac.type) { 748 case e1000_i210: 749 case e1000_i350: 750 /* find combo image version */ 751 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset); 752 if ((comb_offset != 0x0) && (comb_offset != NVM_VER_INVALID)) { 753 754 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset 755 + 1), 1, &comb_verh); 756 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset), 757 1, &comb_verl); 758 759 /* get Option Rom version if it exists and is valid */ 760 if ((comb_verh && comb_verl) && 761 ((comb_verh != NVM_VER_INVALID) && 762 (comb_verl != NVM_VER_INVALID))) { 763 764 fw_vers->or_valid = true; 765 fw_vers->or_major = 766 comb_verl >> NVM_COMB_VER_SHFT; 767 fw_vers->or_build = 768 ((comb_verl << NVM_COMB_VER_SHFT) 769 | (comb_verh >> NVM_COMB_VER_SHFT)); 770 fw_vers->or_patch = 771 comb_verh & NVM_COMB_VER_MASK; 772 } 773 } 774 break; 775 default: 776 break; 777 } 778 return; 779 } 780