1 /******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, see <http://www.gnu.org/licenses/>. 17 18 The full GNU General Public License is included in this distribution in 19 the file called "COPYING". 20 21 Contact Information: 22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 25 *******************************************************************************/ 26 27 #include <linux/if_ether.h> 28 #include <linux/delay.h> 29 30 #include "e1000_mac.h" 31 #include "e1000_nvm.h" 32 33 /** 34 * igb_raise_eec_clk - Raise EEPROM clock 35 * @hw: pointer to the HW structure 36 * @eecd: pointer to the EEPROM 37 * 38 * Enable/Raise the EEPROM clock bit. 39 **/ 40 static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) 41 { 42 *eecd = *eecd | E1000_EECD_SK; 43 wr32(E1000_EECD, *eecd); 44 wrfl(); 45 udelay(hw->nvm.delay_usec); 46 } 47 48 /** 49 * igb_lower_eec_clk - Lower EEPROM clock 50 * @hw: pointer to the HW structure 51 * @eecd: pointer to the EEPROM 52 * 53 * Clear/Lower the EEPROM clock bit. 54 **/ 55 static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) 56 { 57 *eecd = *eecd & ~E1000_EECD_SK; 58 wr32(E1000_EECD, *eecd); 59 wrfl(); 60 udelay(hw->nvm.delay_usec); 61 } 62 63 /** 64 * igb_shift_out_eec_bits - Shift data bits our to the EEPROM 65 * @hw: pointer to the HW structure 66 * @data: data to send to the EEPROM 67 * @count: number of bits to shift out 68 * 69 * We need to shift 'count' bits out to the EEPROM. So, the value in the 70 * "data" parameter will be shifted out to the EEPROM one bit at a time. 71 * In order to do this, "data" must be broken down into bits. 72 **/ 73 static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) 74 { 75 struct e1000_nvm_info *nvm = &hw->nvm; 76 u32 eecd = rd32(E1000_EECD); 77 u32 mask; 78 79 mask = 0x01 << (count - 1); 80 if (nvm->type == e1000_nvm_eeprom_spi) 81 eecd |= E1000_EECD_DO; 82 83 do { 84 eecd &= ~E1000_EECD_DI; 85 86 if (data & mask) 87 eecd |= E1000_EECD_DI; 88 89 wr32(E1000_EECD, eecd); 90 wrfl(); 91 92 udelay(nvm->delay_usec); 93 94 igb_raise_eec_clk(hw, &eecd); 95 igb_lower_eec_clk(hw, &eecd); 96 97 mask >>= 1; 98 } while (mask); 99 100 eecd &= ~E1000_EECD_DI; 101 wr32(E1000_EECD, eecd); 102 } 103 104 /** 105 * igb_shift_in_eec_bits - Shift data bits in from the EEPROM 106 * @hw: pointer to the HW structure 107 * @count: number of bits to shift in 108 * 109 * In order to read a register from the EEPROM, we need to shift 'count' bits 110 * in from the EEPROM. Bits are "shifted in" by raising the clock input to 111 * the EEPROM (setting the SK bit), and then reading the value of the data out 112 * "DO" bit. During this "shifting in" process the data in "DI" bit should 113 * always be clear. 114 **/ 115 static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count) 116 { 117 u32 eecd; 118 u32 i; 119 u16 data; 120 121 eecd = rd32(E1000_EECD); 122 123 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 124 data = 0; 125 126 for (i = 0; i < count; i++) { 127 data <<= 1; 128 igb_raise_eec_clk(hw, &eecd); 129 130 eecd = rd32(E1000_EECD); 131 132 eecd &= ~E1000_EECD_DI; 133 if (eecd & E1000_EECD_DO) 134 data |= 1; 135 136 igb_lower_eec_clk(hw, &eecd); 137 } 138 139 return data; 140 } 141 142 /** 143 * igb_poll_eerd_eewr_done - Poll for EEPROM read/write completion 144 * @hw: pointer to the HW structure 145 * @ee_reg: EEPROM flag for polling 146 * 147 * Polls the EEPROM status bit for either read or write completion based 148 * upon the value of 'ee_reg'. 149 **/ 150 static s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) 151 { 152 u32 attempts = 100000; 153 u32 i, reg = 0; 154 s32 ret_val = -E1000_ERR_NVM; 155 156 for (i = 0; i < attempts; i++) { 157 if (ee_reg == E1000_NVM_POLL_READ) 158 reg = rd32(E1000_EERD); 159 else 160 reg = rd32(E1000_EEWR); 161 162 if (reg & E1000_NVM_RW_REG_DONE) { 163 ret_val = 0; 164 break; 165 } 166 167 udelay(5); 168 } 169 170 return ret_val; 171 } 172 173 /** 174 * igb_acquire_nvm - Generic request for access to EEPROM 175 * @hw: pointer to the HW structure 176 * 177 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 178 * Return successful if access grant bit set, else clear the request for 179 * EEPROM access and return -E1000_ERR_NVM (-1). 180 **/ 181 s32 igb_acquire_nvm(struct e1000_hw *hw) 182 { 183 u32 eecd = rd32(E1000_EECD); 184 s32 timeout = E1000_NVM_GRANT_ATTEMPTS; 185 s32 ret_val = 0; 186 187 188 wr32(E1000_EECD, eecd | E1000_EECD_REQ); 189 eecd = rd32(E1000_EECD); 190 191 while (timeout) { 192 if (eecd & E1000_EECD_GNT) 193 break; 194 udelay(5); 195 eecd = rd32(E1000_EECD); 196 timeout--; 197 } 198 199 if (!timeout) { 200 eecd &= ~E1000_EECD_REQ; 201 wr32(E1000_EECD, eecd); 202 hw_dbg("Could not acquire NVM grant\n"); 203 ret_val = -E1000_ERR_NVM; 204 } 205 206 return ret_val; 207 } 208 209 /** 210 * igb_standby_nvm - Return EEPROM to standby state 211 * @hw: pointer to the HW structure 212 * 213 * Return the EEPROM to a standby state. 214 **/ 215 static void igb_standby_nvm(struct e1000_hw *hw) 216 { 217 struct e1000_nvm_info *nvm = &hw->nvm; 218 u32 eecd = rd32(E1000_EECD); 219 220 if (nvm->type == e1000_nvm_eeprom_spi) { 221 /* Toggle CS to flush commands */ 222 eecd |= E1000_EECD_CS; 223 wr32(E1000_EECD, eecd); 224 wrfl(); 225 udelay(nvm->delay_usec); 226 eecd &= ~E1000_EECD_CS; 227 wr32(E1000_EECD, eecd); 228 wrfl(); 229 udelay(nvm->delay_usec); 230 } 231 } 232 233 /** 234 * e1000_stop_nvm - Terminate EEPROM command 235 * @hw: pointer to the HW structure 236 * 237 * Terminates the current command by inverting the EEPROM's chip select pin. 238 **/ 239 static void e1000_stop_nvm(struct e1000_hw *hw) 240 { 241 u32 eecd; 242 243 eecd = rd32(E1000_EECD); 244 if (hw->nvm.type == e1000_nvm_eeprom_spi) { 245 /* Pull CS high */ 246 eecd |= E1000_EECD_CS; 247 igb_lower_eec_clk(hw, &eecd); 248 } 249 } 250 251 /** 252 * igb_release_nvm - Release exclusive access to EEPROM 253 * @hw: pointer to the HW structure 254 * 255 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 256 **/ 257 void igb_release_nvm(struct e1000_hw *hw) 258 { 259 u32 eecd; 260 261 e1000_stop_nvm(hw); 262 263 eecd = rd32(E1000_EECD); 264 eecd &= ~E1000_EECD_REQ; 265 wr32(E1000_EECD, eecd); 266 } 267 268 /** 269 * igb_ready_nvm_eeprom - Prepares EEPROM for read/write 270 * @hw: pointer to the HW structure 271 * 272 * Setups the EEPROM for reading and writing. 273 **/ 274 static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw) 275 { 276 struct e1000_nvm_info *nvm = &hw->nvm; 277 u32 eecd = rd32(E1000_EECD); 278 s32 ret_val = 0; 279 u16 timeout = 0; 280 u8 spi_stat_reg; 281 282 283 if (nvm->type == e1000_nvm_eeprom_spi) { 284 /* Clear SK and CS */ 285 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 286 wr32(E1000_EECD, eecd); 287 wrfl(); 288 udelay(1); 289 timeout = NVM_MAX_RETRY_SPI; 290 291 /* Read "Status Register" repeatedly until the LSB is cleared. 292 * The EEPROM will signal that the command has been completed 293 * by clearing bit 0 of the internal status register. If it's 294 * not cleared within 'timeout', then error out. 295 */ 296 while (timeout) { 297 igb_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, 298 hw->nvm.opcode_bits); 299 spi_stat_reg = (u8)igb_shift_in_eec_bits(hw, 8); 300 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) 301 break; 302 303 udelay(5); 304 igb_standby_nvm(hw); 305 timeout--; 306 } 307 308 if (!timeout) { 309 hw_dbg("SPI NVM Status error\n"); 310 ret_val = -E1000_ERR_NVM; 311 goto out; 312 } 313 } 314 315 out: 316 return ret_val; 317 } 318 319 /** 320 * igb_read_nvm_spi - Read EEPROM's using SPI 321 * @hw: pointer to the HW structure 322 * @offset: offset of word in the EEPROM to read 323 * @words: number of words to read 324 * @data: word read from the EEPROM 325 * 326 * Reads a 16 bit word from the EEPROM. 327 **/ 328 s32 igb_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 329 { 330 struct e1000_nvm_info *nvm = &hw->nvm; 331 u32 i = 0; 332 s32 ret_val; 333 u16 word_in; 334 u8 read_opcode = NVM_READ_OPCODE_SPI; 335 336 /* A check for invalid values: offset too large, too many words, 337 * and not enough words. 338 */ 339 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 340 (words == 0)) { 341 hw_dbg("nvm parameter(s) out of bounds\n"); 342 ret_val = -E1000_ERR_NVM; 343 goto out; 344 } 345 346 ret_val = nvm->ops.acquire(hw); 347 if (ret_val) 348 goto out; 349 350 ret_val = igb_ready_nvm_eeprom(hw); 351 if (ret_val) 352 goto release; 353 354 igb_standby_nvm(hw); 355 356 if ((nvm->address_bits == 8) && (offset >= 128)) 357 read_opcode |= NVM_A8_OPCODE_SPI; 358 359 /* Send the READ command (opcode + addr) */ 360 igb_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits); 361 igb_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits); 362 363 /* Read the data. SPI NVMs increment the address with each byte 364 * read and will roll over if reading beyond the end. This allows 365 * us to read the whole NVM from any offset 366 */ 367 for (i = 0; i < words; i++) { 368 word_in = igb_shift_in_eec_bits(hw, 16); 369 data[i] = (word_in >> 8) | (word_in << 8); 370 } 371 372 release: 373 nvm->ops.release(hw); 374 375 out: 376 return ret_val; 377 } 378 379 /** 380 * igb_read_nvm_eerd - Reads EEPROM using EERD register 381 * @hw: pointer to the HW structure 382 * @offset: offset of word in the EEPROM to read 383 * @words: number of words to read 384 * @data: word read from the EEPROM 385 * 386 * Reads a 16 bit word from the EEPROM using the EERD register. 387 **/ 388 s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 389 { 390 struct e1000_nvm_info *nvm = &hw->nvm; 391 u32 i, eerd = 0; 392 s32 ret_val = 0; 393 394 /* A check for invalid values: offset too large, too many words, 395 * and not enough words. 396 */ 397 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 398 (words == 0)) { 399 hw_dbg("nvm parameter(s) out of bounds\n"); 400 ret_val = -E1000_ERR_NVM; 401 goto out; 402 } 403 404 for (i = 0; i < words; i++) { 405 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) + 406 E1000_NVM_RW_REG_START; 407 408 wr32(E1000_EERD, eerd); 409 ret_val = igb_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); 410 if (ret_val) 411 break; 412 413 data[i] = (rd32(E1000_EERD) >> 414 E1000_NVM_RW_REG_DATA); 415 } 416 417 out: 418 return ret_val; 419 } 420 421 /** 422 * igb_write_nvm_spi - Write to EEPROM using SPI 423 * @hw: pointer to the HW structure 424 * @offset: offset within the EEPROM to be written to 425 * @words: number of words to write 426 * @data: 16 bit word(s) to be written to the EEPROM 427 * 428 * Writes data to EEPROM at offset using SPI interface. 429 * 430 * If e1000_update_nvm_checksum is not called after this function , the 431 * EEPROM will most likley contain an invalid checksum. 432 **/ 433 s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 434 { 435 struct e1000_nvm_info *nvm = &hw->nvm; 436 s32 ret_val = -E1000_ERR_NVM; 437 u16 widx = 0; 438 439 /* A check for invalid values: offset too large, too many words, 440 * and not enough words. 441 */ 442 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 443 (words == 0)) { 444 hw_dbg("nvm parameter(s) out of bounds\n"); 445 return ret_val; 446 } 447 448 while (widx < words) { 449 u8 write_opcode = NVM_WRITE_OPCODE_SPI; 450 451 ret_val = nvm->ops.acquire(hw); 452 if (ret_val) 453 return ret_val; 454 455 ret_val = igb_ready_nvm_eeprom(hw); 456 if (ret_val) { 457 nvm->ops.release(hw); 458 return ret_val; 459 } 460 461 igb_standby_nvm(hw); 462 463 /* Send the WRITE ENABLE command (8 bit opcode) */ 464 igb_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, 465 nvm->opcode_bits); 466 467 igb_standby_nvm(hw); 468 469 /* Some SPI eeproms use the 8th address bit embedded in the 470 * opcode 471 */ 472 if ((nvm->address_bits == 8) && (offset >= 128)) 473 write_opcode |= NVM_A8_OPCODE_SPI; 474 475 /* Send the Write command (8-bit opcode + addr) */ 476 igb_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); 477 igb_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), 478 nvm->address_bits); 479 480 /* Loop to allow for up to whole page write of eeprom */ 481 while (widx < words) { 482 u16 word_out = data[widx]; 483 word_out = (word_out >> 8) | (word_out << 8); 484 igb_shift_out_eec_bits(hw, word_out, 16); 485 widx++; 486 487 if ((((offset + widx) * 2) % nvm->page_size) == 0) { 488 igb_standby_nvm(hw); 489 break; 490 } 491 } 492 usleep_range(1000, 2000); 493 nvm->ops.release(hw); 494 } 495 496 return ret_val; 497 } 498 499 /** 500 * igb_read_part_string - Read device part number 501 * @hw: pointer to the HW structure 502 * @part_num: pointer to device part number 503 * @part_num_size: size of part number buffer 504 * 505 * Reads the product board assembly (PBA) number from the EEPROM and stores 506 * the value in part_num. 507 **/ 508 s32 igb_read_part_string(struct e1000_hw *hw, u8 *part_num, u32 part_num_size) 509 { 510 s32 ret_val; 511 u16 nvm_data; 512 u16 pointer; 513 u16 offset; 514 u16 length; 515 516 if (part_num == NULL) { 517 hw_dbg("PBA string buffer was null\n"); 518 ret_val = E1000_ERR_INVALID_ARGUMENT; 519 goto out; 520 } 521 522 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 523 if (ret_val) { 524 hw_dbg("NVM Read Error\n"); 525 goto out; 526 } 527 528 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pointer); 529 if (ret_val) { 530 hw_dbg("NVM Read Error\n"); 531 goto out; 532 } 533 534 /* if nvm_data is not ptr guard the PBA must be in legacy format which 535 * means pointer is actually our second data word for the PBA number 536 * and we can decode it into an ascii string 537 */ 538 if (nvm_data != NVM_PBA_PTR_GUARD) { 539 hw_dbg("NVM PBA number is not stored as string\n"); 540 541 /* we will need 11 characters to store the PBA */ 542 if (part_num_size < 11) { 543 hw_dbg("PBA string buffer too small\n"); 544 return E1000_ERR_NO_SPACE; 545 } 546 547 /* extract hex string from data and pointer */ 548 part_num[0] = (nvm_data >> 12) & 0xF; 549 part_num[1] = (nvm_data >> 8) & 0xF; 550 part_num[2] = (nvm_data >> 4) & 0xF; 551 part_num[3] = nvm_data & 0xF; 552 part_num[4] = (pointer >> 12) & 0xF; 553 part_num[5] = (pointer >> 8) & 0xF; 554 part_num[6] = '-'; 555 part_num[7] = 0; 556 part_num[8] = (pointer >> 4) & 0xF; 557 part_num[9] = pointer & 0xF; 558 559 /* put a null character on the end of our string */ 560 part_num[10] = '\0'; 561 562 /* switch all the data but the '-' to hex char */ 563 for (offset = 0; offset < 10; offset++) { 564 if (part_num[offset] < 0xA) 565 part_num[offset] += '0'; 566 else if (part_num[offset] < 0x10) 567 part_num[offset] += 'A' - 0xA; 568 } 569 570 goto out; 571 } 572 573 ret_val = hw->nvm.ops.read(hw, pointer, 1, &length); 574 if (ret_val) { 575 hw_dbg("NVM Read Error\n"); 576 goto out; 577 } 578 579 if (length == 0xFFFF || length == 0) { 580 hw_dbg("NVM PBA number section invalid length\n"); 581 ret_val = E1000_ERR_NVM_PBA_SECTION; 582 goto out; 583 } 584 /* check if part_num buffer is big enough */ 585 if (part_num_size < (((u32)length * 2) - 1)) { 586 hw_dbg("PBA string buffer too small\n"); 587 ret_val = E1000_ERR_NO_SPACE; 588 goto out; 589 } 590 591 /* trim pba length from start of string */ 592 pointer++; 593 length--; 594 595 for (offset = 0; offset < length; offset++) { 596 ret_val = hw->nvm.ops.read(hw, pointer + offset, 1, &nvm_data); 597 if (ret_val) { 598 hw_dbg("NVM Read Error\n"); 599 goto out; 600 } 601 part_num[offset * 2] = (u8)(nvm_data >> 8); 602 part_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF); 603 } 604 part_num[offset * 2] = '\0'; 605 606 out: 607 return ret_val; 608 } 609 610 /** 611 * igb_read_mac_addr - Read device MAC address 612 * @hw: pointer to the HW structure 613 * 614 * Reads the device MAC address from the EEPROM and stores the value. 615 * Since devices with two ports use the same EEPROM, we increment the 616 * last bit in the MAC address for the second port. 617 **/ 618 s32 igb_read_mac_addr(struct e1000_hw *hw) 619 { 620 u32 rar_high; 621 u32 rar_low; 622 u16 i; 623 624 rar_high = rd32(E1000_RAH(0)); 625 rar_low = rd32(E1000_RAL(0)); 626 627 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++) 628 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8)); 629 630 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++) 631 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8)); 632 633 for (i = 0; i < ETH_ALEN; i++) 634 hw->mac.addr[i] = hw->mac.perm_addr[i]; 635 636 return 0; 637 } 638 639 /** 640 * igb_validate_nvm_checksum - Validate EEPROM checksum 641 * @hw: pointer to the HW structure 642 * 643 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 644 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 645 **/ 646 s32 igb_validate_nvm_checksum(struct e1000_hw *hw) 647 { 648 s32 ret_val = 0; 649 u16 checksum = 0; 650 u16 i, nvm_data; 651 652 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { 653 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 654 if (ret_val) { 655 hw_dbg("NVM Read Error\n"); 656 goto out; 657 } 658 checksum += nvm_data; 659 } 660 661 if (checksum != (u16) NVM_SUM) { 662 hw_dbg("NVM Checksum Invalid\n"); 663 ret_val = -E1000_ERR_NVM; 664 goto out; 665 } 666 667 out: 668 return ret_val; 669 } 670 671 /** 672 * igb_update_nvm_checksum - Update EEPROM checksum 673 * @hw: pointer to the HW structure 674 * 675 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 676 * up to the checksum. Then calculates the EEPROM checksum and writes the 677 * value to the EEPROM. 678 **/ 679 s32 igb_update_nvm_checksum(struct e1000_hw *hw) 680 { 681 s32 ret_val; 682 u16 checksum = 0; 683 u16 i, nvm_data; 684 685 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 686 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 687 if (ret_val) { 688 hw_dbg("NVM Read Error while updating checksum.\n"); 689 goto out; 690 } 691 checksum += nvm_data; 692 } 693 checksum = (u16) NVM_SUM - checksum; 694 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum); 695 if (ret_val) 696 hw_dbg("NVM Write Error while updating checksum.\n"); 697 698 out: 699 return ret_val; 700 } 701 702 /** 703 * igb_get_fw_version - Get firmware version information 704 * @hw: pointer to the HW structure 705 * @fw_vers: pointer to output structure 706 * 707 * unsupported MAC types will return all 0 version structure 708 **/ 709 void igb_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers) 710 { 711 u16 eeprom_verh, eeprom_verl, etrack_test, fw_version; 712 u8 q, hval, rem, result; 713 u16 comb_verh, comb_verl, comb_offset; 714 715 memset(fw_vers, 0, sizeof(struct e1000_fw_version)); 716 717 /* basic eeprom version numbers and bits used vary by part and by tool 718 * used to create the nvm images. Check which data format we have. 719 */ 720 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test); 721 switch (hw->mac.type) { 722 case e1000_i211: 723 igb_read_invm_version(hw, fw_vers); 724 return; 725 case e1000_82575: 726 case e1000_82576: 727 case e1000_82580: 728 /* Use this format, unless EETRACK ID exists, 729 * then use alternate format 730 */ 731 if ((etrack_test & NVM_MAJOR_MASK) != NVM_ETRACK_VALID) { 732 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version); 733 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK) 734 >> NVM_MAJOR_SHIFT; 735 fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK) 736 >> NVM_MINOR_SHIFT; 737 fw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK); 738 goto etrack_id; 739 } 740 break; 741 case e1000_i210: 742 if (!(igb_get_flash_presence_i210(hw))) { 743 igb_read_invm_version(hw, fw_vers); 744 return; 745 } 746 /* fall through */ 747 case e1000_i350: 748 /* find combo image version */ 749 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset); 750 if ((comb_offset != 0x0) && 751 (comb_offset != NVM_VER_INVALID)) { 752 753 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset 754 + 1), 1, &comb_verh); 755 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset), 756 1, &comb_verl); 757 758 /* get Option Rom version if it exists and is valid */ 759 if ((comb_verh && comb_verl) && 760 ((comb_verh != NVM_VER_INVALID) && 761 (comb_verl != NVM_VER_INVALID))) { 762 763 fw_vers->or_valid = true; 764 fw_vers->or_major = 765 comb_verl >> NVM_COMB_VER_SHFT; 766 fw_vers->or_build = 767 (comb_verl << NVM_COMB_VER_SHFT) 768 | (comb_verh >> NVM_COMB_VER_SHFT); 769 fw_vers->or_patch = 770 comb_verh & NVM_COMB_VER_MASK; 771 } 772 } 773 break; 774 default: 775 return; 776 } 777 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version); 778 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK) 779 >> NVM_MAJOR_SHIFT; 780 781 /* check for old style version format in newer images*/ 782 if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) { 783 eeprom_verl = (fw_version & NVM_COMB_VER_MASK); 784 } else { 785 eeprom_verl = (fw_version & NVM_MINOR_MASK) 786 >> NVM_MINOR_SHIFT; 787 } 788 /* Convert minor value to hex before assigning to output struct 789 * Val to be converted will not be higher than 99, per tool output 790 */ 791 q = eeprom_verl / NVM_HEX_CONV; 792 hval = q * NVM_HEX_TENS; 793 rem = eeprom_verl % NVM_HEX_CONV; 794 result = hval + rem; 795 fw_vers->eep_minor = result; 796 797 etrack_id: 798 if ((etrack_test & NVM_MAJOR_MASK) == NVM_ETRACK_VALID) { 799 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl); 800 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh); 801 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) 802 | eeprom_verl; 803 } 804 return; 805 } 806