1 /* Intel(R) Gigabit Ethernet Linux driver
2  * Copyright(c) 2007-2014 Intel Corporation.
3  * This program is free software; you can redistribute it and/or modify it
4  * under the terms and conditions of the GNU General Public License,
5  * version 2, as published by the Free Software Foundation.
6  *
7  * This program is distributed in the hope it will be useful, but WITHOUT
8  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
9  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
10  * more details.
11  *
12  * You should have received a copy of the GNU General Public License along with
13  * this program; if not, see <http://www.gnu.org/licenses/>.
14  *
15  * The full GNU General Public License is included in this distribution in
16  * the file called "COPYING".
17  *
18  * Contact Information:
19  * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
20  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
21  */
22 
23 #include <linux/if_ether.h>
24 #include <linux/delay.h>
25 
26 #include "e1000_mac.h"
27 #include "e1000_nvm.h"
28 
29 /**
30  *  igb_raise_eec_clk - Raise EEPROM clock
31  *  @hw: pointer to the HW structure
32  *  @eecd: pointer to the EEPROM
33  *
34  *  Enable/Raise the EEPROM clock bit.
35  **/
36 static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
37 {
38 	*eecd = *eecd | E1000_EECD_SK;
39 	wr32(E1000_EECD, *eecd);
40 	wrfl();
41 	udelay(hw->nvm.delay_usec);
42 }
43 
44 /**
45  *  igb_lower_eec_clk - Lower EEPROM clock
46  *  @hw: pointer to the HW structure
47  *  @eecd: pointer to the EEPROM
48  *
49  *  Clear/Lower the EEPROM clock bit.
50  **/
51 static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
52 {
53 	*eecd = *eecd & ~E1000_EECD_SK;
54 	wr32(E1000_EECD, *eecd);
55 	wrfl();
56 	udelay(hw->nvm.delay_usec);
57 }
58 
59 /**
60  *  igb_shift_out_eec_bits - Shift data bits our to the EEPROM
61  *  @hw: pointer to the HW structure
62  *  @data: data to send to the EEPROM
63  *  @count: number of bits to shift out
64  *
65  *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
66  *  "data" parameter will be shifted out to the EEPROM one bit at a time.
67  *  In order to do this, "data" must be broken down into bits.
68  **/
69 static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
70 {
71 	struct e1000_nvm_info *nvm = &hw->nvm;
72 	u32 eecd = rd32(E1000_EECD);
73 	u32 mask;
74 
75 	mask = 0x01 << (count - 1);
76 	if (nvm->type == e1000_nvm_eeprom_spi)
77 		eecd |= E1000_EECD_DO;
78 
79 	do {
80 		eecd &= ~E1000_EECD_DI;
81 
82 		if (data & mask)
83 			eecd |= E1000_EECD_DI;
84 
85 		wr32(E1000_EECD, eecd);
86 		wrfl();
87 
88 		udelay(nvm->delay_usec);
89 
90 		igb_raise_eec_clk(hw, &eecd);
91 		igb_lower_eec_clk(hw, &eecd);
92 
93 		mask >>= 1;
94 	} while (mask);
95 
96 	eecd &= ~E1000_EECD_DI;
97 	wr32(E1000_EECD, eecd);
98 }
99 
100 /**
101  *  igb_shift_in_eec_bits - Shift data bits in from the EEPROM
102  *  @hw: pointer to the HW structure
103  *  @count: number of bits to shift in
104  *
105  *  In order to read a register from the EEPROM, we need to shift 'count' bits
106  *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to
107  *  the EEPROM (setting the SK bit), and then reading the value of the data out
108  *  "DO" bit.  During this "shifting in" process the data in "DI" bit should
109  *  always be clear.
110  **/
111 static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
112 {
113 	u32 eecd;
114 	u32 i;
115 	u16 data;
116 
117 	eecd = rd32(E1000_EECD);
118 
119 	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
120 	data = 0;
121 
122 	for (i = 0; i < count; i++) {
123 		data <<= 1;
124 		igb_raise_eec_clk(hw, &eecd);
125 
126 		eecd = rd32(E1000_EECD);
127 
128 		eecd &= ~E1000_EECD_DI;
129 		if (eecd & E1000_EECD_DO)
130 			data |= 1;
131 
132 		igb_lower_eec_clk(hw, &eecd);
133 	}
134 
135 	return data;
136 }
137 
138 /**
139  *  igb_poll_eerd_eewr_done - Poll for EEPROM read/write completion
140  *  @hw: pointer to the HW structure
141  *  @ee_reg: EEPROM flag for polling
142  *
143  *  Polls the EEPROM status bit for either read or write completion based
144  *  upon the value of 'ee_reg'.
145  **/
146 static s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
147 {
148 	u32 attempts = 100000;
149 	u32 i, reg = 0;
150 	s32 ret_val = -E1000_ERR_NVM;
151 
152 	for (i = 0; i < attempts; i++) {
153 		if (ee_reg == E1000_NVM_POLL_READ)
154 			reg = rd32(E1000_EERD);
155 		else
156 			reg = rd32(E1000_EEWR);
157 
158 		if (reg & E1000_NVM_RW_REG_DONE) {
159 			ret_val = 0;
160 			break;
161 		}
162 
163 		udelay(5);
164 	}
165 
166 	return ret_val;
167 }
168 
169 /**
170  *  igb_acquire_nvm - Generic request for access to EEPROM
171  *  @hw: pointer to the HW structure
172  *
173  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
174  *  Return successful if access grant bit set, else clear the request for
175  *  EEPROM access and return -E1000_ERR_NVM (-1).
176  **/
177 s32 igb_acquire_nvm(struct e1000_hw *hw)
178 {
179 	u32 eecd = rd32(E1000_EECD);
180 	s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
181 	s32 ret_val = 0;
182 
183 
184 	wr32(E1000_EECD, eecd | E1000_EECD_REQ);
185 	eecd = rd32(E1000_EECD);
186 
187 	while (timeout) {
188 		if (eecd & E1000_EECD_GNT)
189 			break;
190 		udelay(5);
191 		eecd = rd32(E1000_EECD);
192 		timeout--;
193 	}
194 
195 	if (!timeout) {
196 		eecd &= ~E1000_EECD_REQ;
197 		wr32(E1000_EECD, eecd);
198 		hw_dbg("Could not acquire NVM grant\n");
199 		ret_val = -E1000_ERR_NVM;
200 	}
201 
202 	return ret_val;
203 }
204 
205 /**
206  *  igb_standby_nvm - Return EEPROM to standby state
207  *  @hw: pointer to the HW structure
208  *
209  *  Return the EEPROM to a standby state.
210  **/
211 static void igb_standby_nvm(struct e1000_hw *hw)
212 {
213 	struct e1000_nvm_info *nvm = &hw->nvm;
214 	u32 eecd = rd32(E1000_EECD);
215 
216 	if (nvm->type == e1000_nvm_eeprom_spi) {
217 		/* Toggle CS to flush commands */
218 		eecd |= E1000_EECD_CS;
219 		wr32(E1000_EECD, eecd);
220 		wrfl();
221 		udelay(nvm->delay_usec);
222 		eecd &= ~E1000_EECD_CS;
223 		wr32(E1000_EECD, eecd);
224 		wrfl();
225 		udelay(nvm->delay_usec);
226 	}
227 }
228 
229 /**
230  *  e1000_stop_nvm - Terminate EEPROM command
231  *  @hw: pointer to the HW structure
232  *
233  *  Terminates the current command by inverting the EEPROM's chip select pin.
234  **/
235 static void e1000_stop_nvm(struct e1000_hw *hw)
236 {
237 	u32 eecd;
238 
239 	eecd = rd32(E1000_EECD);
240 	if (hw->nvm.type == e1000_nvm_eeprom_spi) {
241 		/* Pull CS high */
242 		eecd |= E1000_EECD_CS;
243 		igb_lower_eec_clk(hw, &eecd);
244 	}
245 }
246 
247 /**
248  *  igb_release_nvm - Release exclusive access to EEPROM
249  *  @hw: pointer to the HW structure
250  *
251  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
252  **/
253 void igb_release_nvm(struct e1000_hw *hw)
254 {
255 	u32 eecd;
256 
257 	e1000_stop_nvm(hw);
258 
259 	eecd = rd32(E1000_EECD);
260 	eecd &= ~E1000_EECD_REQ;
261 	wr32(E1000_EECD, eecd);
262 }
263 
264 /**
265  *  igb_ready_nvm_eeprom - Prepares EEPROM for read/write
266  *  @hw: pointer to the HW structure
267  *
268  *  Setups the EEPROM for reading and writing.
269  **/
270 static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw)
271 {
272 	struct e1000_nvm_info *nvm = &hw->nvm;
273 	u32 eecd = rd32(E1000_EECD);
274 	s32 ret_val = 0;
275 	u16 timeout = 0;
276 	u8 spi_stat_reg;
277 
278 
279 	if (nvm->type == e1000_nvm_eeprom_spi) {
280 		/* Clear SK and CS */
281 		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
282 		wr32(E1000_EECD, eecd);
283 		wrfl();
284 		udelay(1);
285 		timeout = NVM_MAX_RETRY_SPI;
286 
287 		/* Read "Status Register" repeatedly until the LSB is cleared.
288 		 * The EEPROM will signal that the command has been completed
289 		 * by clearing bit 0 of the internal status register.  If it's
290 		 * not cleared within 'timeout', then error out.
291 		 */
292 		while (timeout) {
293 			igb_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
294 					       hw->nvm.opcode_bits);
295 			spi_stat_reg = (u8)igb_shift_in_eec_bits(hw, 8);
296 			if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
297 				break;
298 
299 			udelay(5);
300 			igb_standby_nvm(hw);
301 			timeout--;
302 		}
303 
304 		if (!timeout) {
305 			hw_dbg("SPI NVM Status error\n");
306 			ret_val = -E1000_ERR_NVM;
307 			goto out;
308 		}
309 	}
310 
311 out:
312 	return ret_val;
313 }
314 
315 /**
316  *  igb_read_nvm_spi - Read EEPROM's using SPI
317  *  @hw: pointer to the HW structure
318  *  @offset: offset of word in the EEPROM to read
319  *  @words: number of words to read
320  *  @data: word read from the EEPROM
321  *
322  *  Reads a 16 bit word from the EEPROM.
323  **/
324 s32 igb_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
325 {
326 	struct e1000_nvm_info *nvm = &hw->nvm;
327 	u32 i = 0;
328 	s32 ret_val;
329 	u16 word_in;
330 	u8 read_opcode = NVM_READ_OPCODE_SPI;
331 
332 	/* A check for invalid values:  offset too large, too many words,
333 	 * and not enough words.
334 	 */
335 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
336 	    (words == 0)) {
337 		hw_dbg("nvm parameter(s) out of bounds\n");
338 		ret_val = -E1000_ERR_NVM;
339 		goto out;
340 	}
341 
342 	ret_val = nvm->ops.acquire(hw);
343 	if (ret_val)
344 		goto out;
345 
346 	ret_val = igb_ready_nvm_eeprom(hw);
347 	if (ret_val)
348 		goto release;
349 
350 	igb_standby_nvm(hw);
351 
352 	if ((nvm->address_bits == 8) && (offset >= 128))
353 		read_opcode |= NVM_A8_OPCODE_SPI;
354 
355 	/* Send the READ command (opcode + addr) */
356 	igb_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
357 	igb_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
358 
359 	/* Read the data.  SPI NVMs increment the address with each byte
360 	 * read and will roll over if reading beyond the end.  This allows
361 	 * us to read the whole NVM from any offset
362 	 */
363 	for (i = 0; i < words; i++) {
364 		word_in = igb_shift_in_eec_bits(hw, 16);
365 		data[i] = (word_in >> 8) | (word_in << 8);
366 	}
367 
368 release:
369 	nvm->ops.release(hw);
370 
371 out:
372 	return ret_val;
373 }
374 
375 /**
376  *  igb_read_nvm_eerd - Reads EEPROM using EERD register
377  *  @hw: pointer to the HW structure
378  *  @offset: offset of word in the EEPROM to read
379  *  @words: number of words to read
380  *  @data: word read from the EEPROM
381  *
382  *  Reads a 16 bit word from the EEPROM using the EERD register.
383  **/
384 s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
385 {
386 	struct e1000_nvm_info *nvm = &hw->nvm;
387 	u32 i, eerd = 0;
388 	s32 ret_val = 0;
389 
390 	/* A check for invalid values:  offset too large, too many words,
391 	 * and not enough words.
392 	 */
393 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
394 	    (words == 0)) {
395 		hw_dbg("nvm parameter(s) out of bounds\n");
396 		ret_val = -E1000_ERR_NVM;
397 		goto out;
398 	}
399 
400 	for (i = 0; i < words; i++) {
401 		eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
402 			E1000_NVM_RW_REG_START;
403 
404 		wr32(E1000_EERD, eerd);
405 		ret_val = igb_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
406 		if (ret_val)
407 			break;
408 
409 		data[i] = (rd32(E1000_EERD) >>
410 			E1000_NVM_RW_REG_DATA);
411 	}
412 
413 out:
414 	return ret_val;
415 }
416 
417 /**
418  *  igb_write_nvm_spi - Write to EEPROM using SPI
419  *  @hw: pointer to the HW structure
420  *  @offset: offset within the EEPROM to be written to
421  *  @words: number of words to write
422  *  @data: 16 bit word(s) to be written to the EEPROM
423  *
424  *  Writes data to EEPROM at offset using SPI interface.
425  *
426  *  If e1000_update_nvm_checksum is not called after this function , the
427  *  EEPROM will most likley contain an invalid checksum.
428  **/
429 s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
430 {
431 	struct e1000_nvm_info *nvm = &hw->nvm;
432 	s32 ret_val = -E1000_ERR_NVM;
433 	u16 widx = 0;
434 
435 	/* A check for invalid values:  offset too large, too many words,
436 	 * and not enough words.
437 	 */
438 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
439 	    (words == 0)) {
440 		hw_dbg("nvm parameter(s) out of bounds\n");
441 		return ret_val;
442 	}
443 
444 	while (widx < words) {
445 		u8 write_opcode = NVM_WRITE_OPCODE_SPI;
446 
447 		ret_val = nvm->ops.acquire(hw);
448 		if (ret_val)
449 			return ret_val;
450 
451 		ret_val = igb_ready_nvm_eeprom(hw);
452 		if (ret_val) {
453 			nvm->ops.release(hw);
454 			return ret_val;
455 		}
456 
457 		igb_standby_nvm(hw);
458 
459 		/* Send the WRITE ENABLE command (8 bit opcode) */
460 		igb_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
461 					 nvm->opcode_bits);
462 
463 		igb_standby_nvm(hw);
464 
465 		/* Some SPI eeproms use the 8th address bit embedded in the
466 		 * opcode
467 		 */
468 		if ((nvm->address_bits == 8) && (offset >= 128))
469 			write_opcode |= NVM_A8_OPCODE_SPI;
470 
471 		/* Send the Write command (8-bit opcode + addr) */
472 		igb_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
473 		igb_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
474 					 nvm->address_bits);
475 
476 		/* Loop to allow for up to whole page write of eeprom */
477 		while (widx < words) {
478 			u16 word_out = data[widx];
479 
480 			word_out = (word_out >> 8) | (word_out << 8);
481 			igb_shift_out_eec_bits(hw, word_out, 16);
482 			widx++;
483 
484 			if ((((offset + widx) * 2) % nvm->page_size) == 0) {
485 				igb_standby_nvm(hw);
486 				break;
487 			}
488 		}
489 		usleep_range(1000, 2000);
490 		nvm->ops.release(hw);
491 	}
492 
493 	return ret_val;
494 }
495 
496 /**
497  *  igb_read_part_string - Read device part number
498  *  @hw: pointer to the HW structure
499  *  @part_num: pointer to device part number
500  *  @part_num_size: size of part number buffer
501  *
502  *  Reads the product board assembly (PBA) number from the EEPROM and stores
503  *  the value in part_num.
504  **/
505 s32 igb_read_part_string(struct e1000_hw *hw, u8 *part_num, u32 part_num_size)
506 {
507 	s32 ret_val;
508 	u16 nvm_data;
509 	u16 pointer;
510 	u16 offset;
511 	u16 length;
512 
513 	if (part_num == NULL) {
514 		hw_dbg("PBA string buffer was null\n");
515 		ret_val = E1000_ERR_INVALID_ARGUMENT;
516 		goto out;
517 	}
518 
519 	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
520 	if (ret_val) {
521 		hw_dbg("NVM Read Error\n");
522 		goto out;
523 	}
524 
525 	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pointer);
526 	if (ret_val) {
527 		hw_dbg("NVM Read Error\n");
528 		goto out;
529 	}
530 
531 	/* if nvm_data is not ptr guard the PBA must be in legacy format which
532 	 * means pointer is actually our second data word for the PBA number
533 	 * and we can decode it into an ascii string
534 	 */
535 	if (nvm_data != NVM_PBA_PTR_GUARD) {
536 		hw_dbg("NVM PBA number is not stored as string\n");
537 
538 		/* we will need 11 characters to store the PBA */
539 		if (part_num_size < 11) {
540 			hw_dbg("PBA string buffer too small\n");
541 			return E1000_ERR_NO_SPACE;
542 		}
543 
544 		/* extract hex string from data and pointer */
545 		part_num[0] = (nvm_data >> 12) & 0xF;
546 		part_num[1] = (nvm_data >> 8) & 0xF;
547 		part_num[2] = (nvm_data >> 4) & 0xF;
548 		part_num[3] = nvm_data & 0xF;
549 		part_num[4] = (pointer >> 12) & 0xF;
550 		part_num[5] = (pointer >> 8) & 0xF;
551 		part_num[6] = '-';
552 		part_num[7] = 0;
553 		part_num[8] = (pointer >> 4) & 0xF;
554 		part_num[9] = pointer & 0xF;
555 
556 		/* put a null character on the end of our string */
557 		part_num[10] = '\0';
558 
559 		/* switch all the data but the '-' to hex char */
560 		for (offset = 0; offset < 10; offset++) {
561 			if (part_num[offset] < 0xA)
562 				part_num[offset] += '0';
563 			else if (part_num[offset] < 0x10)
564 				part_num[offset] += 'A' - 0xA;
565 		}
566 
567 		goto out;
568 	}
569 
570 	ret_val = hw->nvm.ops.read(hw, pointer, 1, &length);
571 	if (ret_val) {
572 		hw_dbg("NVM Read Error\n");
573 		goto out;
574 	}
575 
576 	if (length == 0xFFFF || length == 0) {
577 		hw_dbg("NVM PBA number section invalid length\n");
578 		ret_val = E1000_ERR_NVM_PBA_SECTION;
579 		goto out;
580 	}
581 	/* check if part_num buffer is big enough */
582 	if (part_num_size < (((u32)length * 2) - 1)) {
583 		hw_dbg("PBA string buffer too small\n");
584 		ret_val = E1000_ERR_NO_SPACE;
585 		goto out;
586 	}
587 
588 	/* trim pba length from start of string */
589 	pointer++;
590 	length--;
591 
592 	for (offset = 0; offset < length; offset++) {
593 		ret_val = hw->nvm.ops.read(hw, pointer + offset, 1, &nvm_data);
594 		if (ret_val) {
595 			hw_dbg("NVM Read Error\n");
596 			goto out;
597 		}
598 		part_num[offset * 2] = (u8)(nvm_data >> 8);
599 		part_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
600 	}
601 	part_num[offset * 2] = '\0';
602 
603 out:
604 	return ret_val;
605 }
606 
607 /**
608  *  igb_read_mac_addr - Read device MAC address
609  *  @hw: pointer to the HW structure
610  *
611  *  Reads the device MAC address from the EEPROM and stores the value.
612  *  Since devices with two ports use the same EEPROM, we increment the
613  *  last bit in the MAC address for the second port.
614  **/
615 s32 igb_read_mac_addr(struct e1000_hw *hw)
616 {
617 	u32 rar_high;
618 	u32 rar_low;
619 	u16 i;
620 
621 	rar_high = rd32(E1000_RAH(0));
622 	rar_low = rd32(E1000_RAL(0));
623 
624 	for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
625 		hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
626 
627 	for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
628 		hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
629 
630 	for (i = 0; i < ETH_ALEN; i++)
631 		hw->mac.addr[i] = hw->mac.perm_addr[i];
632 
633 	return 0;
634 }
635 
636 /**
637  *  igb_validate_nvm_checksum - Validate EEPROM checksum
638  *  @hw: pointer to the HW structure
639  *
640  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
641  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
642  **/
643 s32 igb_validate_nvm_checksum(struct e1000_hw *hw)
644 {
645 	s32 ret_val = 0;
646 	u16 checksum = 0;
647 	u16 i, nvm_data;
648 
649 	for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
650 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
651 		if (ret_val) {
652 			hw_dbg("NVM Read Error\n");
653 			goto out;
654 		}
655 		checksum += nvm_data;
656 	}
657 
658 	if (checksum != (u16) NVM_SUM) {
659 		hw_dbg("NVM Checksum Invalid\n");
660 		ret_val = -E1000_ERR_NVM;
661 		goto out;
662 	}
663 
664 out:
665 	return ret_val;
666 }
667 
668 /**
669  *  igb_update_nvm_checksum - Update EEPROM checksum
670  *  @hw: pointer to the HW structure
671  *
672  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
673  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
674  *  value to the EEPROM.
675  **/
676 s32 igb_update_nvm_checksum(struct e1000_hw *hw)
677 {
678 	s32  ret_val;
679 	u16 checksum = 0;
680 	u16 i, nvm_data;
681 
682 	for (i = 0; i < NVM_CHECKSUM_REG; i++) {
683 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
684 		if (ret_val) {
685 			hw_dbg("NVM Read Error while updating checksum.\n");
686 			goto out;
687 		}
688 		checksum += nvm_data;
689 	}
690 	checksum = (u16) NVM_SUM - checksum;
691 	ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
692 	if (ret_val)
693 		hw_dbg("NVM Write Error while updating checksum.\n");
694 
695 out:
696 	return ret_val;
697 }
698 
699 /**
700  *  igb_get_fw_version - Get firmware version information
701  *  @hw: pointer to the HW structure
702  *  @fw_vers: pointer to output structure
703  *
704  *  unsupported MAC types will return all 0 version structure
705  **/
706 void igb_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)
707 {
708 	u16 eeprom_verh, eeprom_verl, etrack_test, fw_version;
709 	u8 q, hval, rem, result;
710 	u16 comb_verh, comb_verl, comb_offset;
711 
712 	memset(fw_vers, 0, sizeof(struct e1000_fw_version));
713 
714 	/* basic eeprom version numbers and bits used vary by part and by tool
715 	 * used to create the nvm images. Check which data format we have.
716 	 */
717 	hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
718 	switch (hw->mac.type) {
719 	case e1000_i211:
720 		igb_read_invm_version(hw, fw_vers);
721 		return;
722 	case e1000_82575:
723 	case e1000_82576:
724 	case e1000_82580:
725 		/* Use this format, unless EETRACK ID exists,
726 		 * then use alternate format
727 		 */
728 		if ((etrack_test &  NVM_MAJOR_MASK) != NVM_ETRACK_VALID) {
729 			hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
730 			fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
731 					      >> NVM_MAJOR_SHIFT;
732 			fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK)
733 					      >> NVM_MINOR_SHIFT;
734 			fw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK);
735 			goto etrack_id;
736 		}
737 		break;
738 	case e1000_i210:
739 		if (!(igb_get_flash_presence_i210(hw))) {
740 			igb_read_invm_version(hw, fw_vers);
741 			return;
742 		}
743 		/* fall through */
744 	case e1000_i350:
745 		/* find combo image version */
746 		hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
747 		if ((comb_offset != 0x0) &&
748 		    (comb_offset != NVM_VER_INVALID)) {
749 
750 			hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
751 					 + 1), 1, &comb_verh);
752 			hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
753 					 1, &comb_verl);
754 
755 			/* get Option Rom version if it exists and is valid */
756 			if ((comb_verh && comb_verl) &&
757 			    ((comb_verh != NVM_VER_INVALID) &&
758 			     (comb_verl != NVM_VER_INVALID))) {
759 
760 				fw_vers->or_valid = true;
761 				fw_vers->or_major =
762 					comb_verl >> NVM_COMB_VER_SHFT;
763 				fw_vers->or_build =
764 					(comb_verl << NVM_COMB_VER_SHFT)
765 					| (comb_verh >> NVM_COMB_VER_SHFT);
766 				fw_vers->or_patch =
767 					comb_verh & NVM_COMB_VER_MASK;
768 			}
769 		}
770 		break;
771 	default:
772 		return;
773 	}
774 	hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
775 	fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
776 			      >> NVM_MAJOR_SHIFT;
777 
778 	/* check for old style version format in newer images*/
779 	if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) {
780 		eeprom_verl = (fw_version & NVM_COMB_VER_MASK);
781 	} else {
782 		eeprom_verl = (fw_version & NVM_MINOR_MASK)
783 				>> NVM_MINOR_SHIFT;
784 	}
785 	/* Convert minor value to hex before assigning to output struct
786 	 * Val to be converted will not be higher than 99, per tool output
787 	 */
788 	q = eeprom_verl / NVM_HEX_CONV;
789 	hval = q * NVM_HEX_TENS;
790 	rem = eeprom_verl % NVM_HEX_CONV;
791 	result = hval + rem;
792 	fw_vers->eep_minor = result;
793 
794 etrack_id:
795 	if ((etrack_test &  NVM_MAJOR_MASK) == NVM_ETRACK_VALID) {
796 		hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);
797 		hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);
798 		fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT)
799 			| eeprom_verl;
800 	}
801 }
802