1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Intel(R) Gigabit Ethernet Linux driver 3 * Copyright(c) 2007-2014 Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 #ifndef _E1000_HW_H_ 25 #define _E1000_HW_H_ 26 27 #include <linux/types.h> 28 #include <linux/delay.h> 29 #include <linux/io.h> 30 #include <linux/netdevice.h> 31 32 #include "e1000_regs.h" 33 #include "e1000_defines.h" 34 35 struct e1000_hw; 36 37 #define E1000_DEV_ID_82576 0x10C9 38 #define E1000_DEV_ID_82576_FIBER 0x10E6 39 #define E1000_DEV_ID_82576_SERDES 0x10E7 40 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 41 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 42 #define E1000_DEV_ID_82576_NS 0x150A 43 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 44 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 45 #define E1000_DEV_ID_82575EB_COPPER 0x10A7 46 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 47 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 48 #define E1000_DEV_ID_82580_COPPER 0x150E 49 #define E1000_DEV_ID_82580_FIBER 0x150F 50 #define E1000_DEV_ID_82580_SERDES 0x1510 51 #define E1000_DEV_ID_82580_SGMII 0x1511 52 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 53 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 54 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 55 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 56 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 57 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 58 #define E1000_DEV_ID_I350_COPPER 0x1521 59 #define E1000_DEV_ID_I350_FIBER 0x1522 60 #define E1000_DEV_ID_I350_SERDES 0x1523 61 #define E1000_DEV_ID_I350_SGMII 0x1524 62 #define E1000_DEV_ID_I210_COPPER 0x1533 63 #define E1000_DEV_ID_I210_FIBER 0x1536 64 #define E1000_DEV_ID_I210_SERDES 0x1537 65 #define E1000_DEV_ID_I210_SGMII 0x1538 66 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 67 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 68 #define E1000_DEV_ID_I211_COPPER 0x1539 69 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 70 #define E1000_DEV_ID_I354_SGMII 0x1F41 71 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 72 73 #define E1000_REVISION_2 2 74 #define E1000_REVISION_4 4 75 76 #define E1000_FUNC_0 0 77 #define E1000_FUNC_1 1 78 #define E1000_FUNC_2 2 79 #define E1000_FUNC_3 3 80 81 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 82 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 83 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 84 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 85 86 enum e1000_mac_type { 87 e1000_undefined = 0, 88 e1000_82575, 89 e1000_82576, 90 e1000_82580, 91 e1000_i350, 92 e1000_i354, 93 e1000_i210, 94 e1000_i211, 95 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ 96 }; 97 98 enum e1000_media_type { 99 e1000_media_type_unknown = 0, 100 e1000_media_type_copper = 1, 101 e1000_media_type_fiber = 2, 102 e1000_media_type_internal_serdes = 3, 103 e1000_num_media_types 104 }; 105 106 enum e1000_nvm_type { 107 e1000_nvm_unknown = 0, 108 e1000_nvm_none, 109 e1000_nvm_eeprom_spi, 110 e1000_nvm_flash_hw, 111 e1000_nvm_invm, 112 e1000_nvm_flash_sw 113 }; 114 115 enum e1000_nvm_override { 116 e1000_nvm_override_none = 0, 117 e1000_nvm_override_spi_small, 118 e1000_nvm_override_spi_large, 119 }; 120 121 enum e1000_phy_type { 122 e1000_phy_unknown = 0, 123 e1000_phy_none, 124 e1000_phy_m88, 125 e1000_phy_igp, 126 e1000_phy_igp_2, 127 e1000_phy_gg82563, 128 e1000_phy_igp_3, 129 e1000_phy_ife, 130 e1000_phy_82580, 131 e1000_phy_i210, 132 e1000_phy_bcm54616, 133 }; 134 135 enum e1000_bus_type { 136 e1000_bus_type_unknown = 0, 137 e1000_bus_type_pci, 138 e1000_bus_type_pcix, 139 e1000_bus_type_pci_express, 140 e1000_bus_type_reserved 141 }; 142 143 enum e1000_bus_speed { 144 e1000_bus_speed_unknown = 0, 145 e1000_bus_speed_33, 146 e1000_bus_speed_66, 147 e1000_bus_speed_100, 148 e1000_bus_speed_120, 149 e1000_bus_speed_133, 150 e1000_bus_speed_2500, 151 e1000_bus_speed_5000, 152 e1000_bus_speed_reserved 153 }; 154 155 enum e1000_bus_width { 156 e1000_bus_width_unknown = 0, 157 e1000_bus_width_pcie_x1, 158 e1000_bus_width_pcie_x2, 159 e1000_bus_width_pcie_x4 = 4, 160 e1000_bus_width_pcie_x8 = 8, 161 e1000_bus_width_32, 162 e1000_bus_width_64, 163 e1000_bus_width_reserved 164 }; 165 166 enum e1000_1000t_rx_status { 167 e1000_1000t_rx_status_not_ok = 0, 168 e1000_1000t_rx_status_ok, 169 e1000_1000t_rx_status_undefined = 0xFF 170 }; 171 172 enum e1000_rev_polarity { 173 e1000_rev_polarity_normal = 0, 174 e1000_rev_polarity_reversed, 175 e1000_rev_polarity_undefined = 0xFF 176 }; 177 178 enum e1000_fc_mode { 179 e1000_fc_none = 0, 180 e1000_fc_rx_pause, 181 e1000_fc_tx_pause, 182 e1000_fc_full, 183 e1000_fc_default = 0xFF 184 }; 185 186 /* Statistics counters collected by the MAC */ 187 struct e1000_hw_stats { 188 u64 crcerrs; 189 u64 algnerrc; 190 u64 symerrs; 191 u64 rxerrc; 192 u64 mpc; 193 u64 scc; 194 u64 ecol; 195 u64 mcc; 196 u64 latecol; 197 u64 colc; 198 u64 dc; 199 u64 tncrs; 200 u64 sec; 201 u64 cexterr; 202 u64 rlec; 203 u64 xonrxc; 204 u64 xontxc; 205 u64 xoffrxc; 206 u64 xofftxc; 207 u64 fcruc; 208 u64 prc64; 209 u64 prc127; 210 u64 prc255; 211 u64 prc511; 212 u64 prc1023; 213 u64 prc1522; 214 u64 gprc; 215 u64 bprc; 216 u64 mprc; 217 u64 gptc; 218 u64 gorc; 219 u64 gotc; 220 u64 rnbc; 221 u64 ruc; 222 u64 rfc; 223 u64 roc; 224 u64 rjc; 225 u64 mgprc; 226 u64 mgpdc; 227 u64 mgptc; 228 u64 tor; 229 u64 tot; 230 u64 tpr; 231 u64 tpt; 232 u64 ptc64; 233 u64 ptc127; 234 u64 ptc255; 235 u64 ptc511; 236 u64 ptc1023; 237 u64 ptc1522; 238 u64 mptc; 239 u64 bptc; 240 u64 tsctc; 241 u64 tsctfc; 242 u64 iac; 243 u64 icrxptc; 244 u64 icrxatc; 245 u64 ictxptc; 246 u64 ictxatc; 247 u64 ictxqec; 248 u64 ictxqmtc; 249 u64 icrxdmtc; 250 u64 icrxoc; 251 u64 cbtmpc; 252 u64 htdpmc; 253 u64 cbrdpc; 254 u64 cbrmpc; 255 u64 rpthc; 256 u64 hgptc; 257 u64 htcbdpc; 258 u64 hgorc; 259 u64 hgotc; 260 u64 lenerrs; 261 u64 scvpc; 262 u64 hrmpc; 263 u64 doosync; 264 u64 o2bgptc; 265 u64 o2bspc; 266 u64 b2ospc; 267 u64 b2ogprc; 268 }; 269 270 struct e1000_host_mng_dhcp_cookie { 271 u32 signature; 272 u8 status; 273 u8 reserved0; 274 u16 vlan_id; 275 u32 reserved1; 276 u16 reserved2; 277 u8 reserved3; 278 u8 checksum; 279 }; 280 281 /* Host Interface "Rev 1" */ 282 struct e1000_host_command_header { 283 u8 command_id; 284 u8 command_length; 285 u8 command_options; 286 u8 checksum; 287 }; 288 289 #define E1000_HI_MAX_DATA_LENGTH 252 290 struct e1000_host_command_info { 291 struct e1000_host_command_header command_header; 292 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 293 }; 294 295 /* Host Interface "Rev 2" */ 296 struct e1000_host_mng_command_header { 297 u8 command_id; 298 u8 checksum; 299 u16 reserved1; 300 u16 reserved2; 301 u16 command_length; 302 }; 303 304 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 305 struct e1000_host_mng_command_info { 306 struct e1000_host_mng_command_header command_header; 307 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 308 }; 309 310 #include "e1000_mac.h" 311 #include "e1000_phy.h" 312 #include "e1000_nvm.h" 313 #include "e1000_mbx.h" 314 315 struct e1000_mac_operations { 316 s32 (*check_for_link)(struct e1000_hw *); 317 s32 (*reset_hw)(struct e1000_hw *); 318 s32 (*init_hw)(struct e1000_hw *); 319 bool (*check_mng_mode)(struct e1000_hw *); 320 s32 (*setup_physical_interface)(struct e1000_hw *); 321 void (*rar_set)(struct e1000_hw *, u8 *, u32); 322 s32 (*read_mac_addr)(struct e1000_hw *); 323 s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *); 324 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 325 void (*release_swfw_sync)(struct e1000_hw *, u16); 326 #ifdef CONFIG_IGB_HWMON 327 s32 (*get_thermal_sensor_data)(struct e1000_hw *); 328 s32 (*init_thermal_sensor_thresh)(struct e1000_hw *); 329 #endif 330 void (*write_vfta)(struct e1000_hw *, u32, u32); 331 }; 332 333 struct e1000_phy_operations { 334 s32 (*acquire)(struct e1000_hw *); 335 s32 (*check_polarity)(struct e1000_hw *); 336 s32 (*check_reset_block)(struct e1000_hw *); 337 s32 (*force_speed_duplex)(struct e1000_hw *); 338 s32 (*get_cfg_done)(struct e1000_hw *hw); 339 s32 (*get_cable_length)(struct e1000_hw *); 340 s32 (*get_phy_info)(struct e1000_hw *); 341 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 342 void (*release)(struct e1000_hw *); 343 s32 (*reset)(struct e1000_hw *); 344 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 345 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 346 s32 (*write_reg)(struct e1000_hw *, u32, u16); 347 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 348 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 349 }; 350 351 struct e1000_nvm_operations { 352 s32 (*acquire)(struct e1000_hw *); 353 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 354 void (*release)(struct e1000_hw *); 355 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 356 s32 (*update)(struct e1000_hw *); 357 s32 (*validate)(struct e1000_hw *); 358 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 359 }; 360 361 #define E1000_MAX_SENSORS 3 362 363 struct e1000_thermal_diode_data { 364 u8 location; 365 u8 temp; 366 u8 caution_thresh; 367 u8 max_op_thresh; 368 }; 369 370 struct e1000_thermal_sensor_data { 371 struct e1000_thermal_diode_data sensor[E1000_MAX_SENSORS]; 372 }; 373 374 struct e1000_info { 375 s32 (*get_invariants)(struct e1000_hw *); 376 struct e1000_mac_operations *mac_ops; 377 const struct e1000_phy_operations *phy_ops; 378 struct e1000_nvm_operations *nvm_ops; 379 }; 380 381 extern const struct e1000_info e1000_82575_info; 382 383 struct e1000_mac_info { 384 struct e1000_mac_operations ops; 385 386 u8 addr[6]; 387 u8 perm_addr[6]; 388 389 enum e1000_mac_type type; 390 391 u32 ledctl_default; 392 u32 ledctl_mode1; 393 u32 ledctl_mode2; 394 u32 mc_filter_type; 395 u32 txcw; 396 397 u16 mta_reg_count; 398 u16 uta_reg_count; 399 400 /* Maximum size of the MTA register table in all supported adapters */ 401 #define MAX_MTA_REG 128 402 u32 mta_shadow[MAX_MTA_REG]; 403 u16 rar_entry_count; 404 405 u8 forced_speed_duplex; 406 407 bool adaptive_ifs; 408 bool arc_subsystem_valid; 409 bool asf_firmware_present; 410 bool autoneg; 411 bool autoneg_failed; 412 bool disable_hw_init_bits; 413 bool get_link_status; 414 bool ifs_params_forced; 415 bool in_ifs_mode; 416 bool report_tx_early; 417 bool serdes_has_link; 418 bool tx_pkt_filtering; 419 struct e1000_thermal_sensor_data thermal_sensor_data; 420 }; 421 422 struct e1000_phy_info { 423 struct e1000_phy_operations ops; 424 425 enum e1000_phy_type type; 426 427 enum e1000_1000t_rx_status local_rx; 428 enum e1000_1000t_rx_status remote_rx; 429 enum e1000_ms_type ms_type; 430 enum e1000_ms_type original_ms_type; 431 enum e1000_rev_polarity cable_polarity; 432 enum e1000_smart_speed smart_speed; 433 434 u32 addr; 435 u32 id; 436 u32 reset_delay_us; /* in usec */ 437 u32 revision; 438 439 enum e1000_media_type media_type; 440 441 u16 autoneg_advertised; 442 u16 autoneg_mask; 443 u16 cable_length; 444 u16 max_cable_length; 445 u16 min_cable_length; 446 u16 pair_length[4]; 447 448 u8 mdix; 449 450 bool disable_polarity_correction; 451 bool is_mdix; 452 bool polarity_correction; 453 bool reset_disable; 454 bool speed_downgraded; 455 bool autoneg_wait_to_complete; 456 }; 457 458 struct e1000_nvm_info { 459 struct e1000_nvm_operations ops; 460 enum e1000_nvm_type type; 461 enum e1000_nvm_override override; 462 463 u32 flash_bank_size; 464 u32 flash_base_addr; 465 466 u16 word_size; 467 u16 delay_usec; 468 u16 address_bits; 469 u16 opcode_bits; 470 u16 page_size; 471 }; 472 473 struct e1000_bus_info { 474 enum e1000_bus_type type; 475 enum e1000_bus_speed speed; 476 enum e1000_bus_width width; 477 478 u32 snoop; 479 480 u16 func; 481 u16 pci_cmd_word; 482 }; 483 484 struct e1000_fc_info { 485 u32 high_water; /* Flow control high-water mark */ 486 u32 low_water; /* Flow control low-water mark */ 487 u16 pause_time; /* Flow control pause timer */ 488 bool send_xon; /* Flow control send XON */ 489 bool strict_ieee; /* Strict IEEE mode */ 490 enum e1000_fc_mode current_mode; /* Type of flow control */ 491 enum e1000_fc_mode requested_mode; 492 }; 493 494 struct e1000_mbx_operations { 495 s32 (*init_params)(struct e1000_hw *hw); 496 s32 (*read)(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id, 497 bool unlock); 498 s32 (*write)(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id); 499 s32 (*read_posted)(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id); 500 s32 (*write_posted)(struct e1000_hw *hw, u32 *msg, u16 size, 501 u16 mbx_id); 502 s32 (*check_for_msg)(struct e1000_hw *hw, u16 mbx_id); 503 s32 (*check_for_ack)(struct e1000_hw *hw, u16 mbx_id); 504 s32 (*check_for_rst)(struct e1000_hw *hw, u16 mbx_id); 505 s32 (*unlock)(struct e1000_hw *hw, u16 mbx_id); 506 }; 507 508 struct e1000_mbx_stats { 509 u32 msgs_tx; 510 u32 msgs_rx; 511 512 u32 acks; 513 u32 reqs; 514 u32 rsts; 515 }; 516 517 struct e1000_mbx_info { 518 struct e1000_mbx_operations ops; 519 struct e1000_mbx_stats stats; 520 u32 timeout; 521 u32 usec_delay; 522 u16 size; 523 }; 524 525 struct e1000_dev_spec_82575 { 526 bool sgmii_active; 527 bool global_device_reset; 528 bool eee_disable; 529 bool clear_semaphore_once; 530 struct e1000_sfp_flags eth_flags; 531 bool module_plugged; 532 u8 media_port; 533 bool media_changed; 534 bool mas_capable; 535 }; 536 537 struct e1000_hw { 538 void *back; 539 540 u8 __iomem *hw_addr; 541 u8 __iomem *flash_address; 542 unsigned long io_base; 543 544 struct e1000_mac_info mac; 545 struct e1000_fc_info fc; 546 struct e1000_phy_info phy; 547 struct e1000_nvm_info nvm; 548 struct e1000_bus_info bus; 549 struct e1000_mbx_info mbx; 550 struct e1000_host_mng_dhcp_cookie mng_cookie; 551 552 union { 553 struct e1000_dev_spec_82575 _82575; 554 } dev_spec; 555 556 u16 device_id; 557 u16 subsystem_vendor_id; 558 u16 subsystem_device_id; 559 u16 vendor_id; 560 561 u8 revision_id; 562 }; 563 564 struct net_device *igb_get_hw_dev(struct e1000_hw *hw); 565 #define hw_dbg(format, arg...) \ 566 netdev_dbg(igb_get_hw_dev(hw), format, ##arg) 567 568 /* These functions must be implemented by drivers */ 569 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 570 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 571 572 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 573 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 574 #endif /* _E1000_HW_H_ */ 575