1 /******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26 *******************************************************************************/ 27 28 #ifndef _E1000_DEFINES_H_ 29 #define _E1000_DEFINES_H_ 30 31 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 32 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 33 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 34 35 /* Definitions for power management and wakeup registers */ 36 /* Wake Up Control */ 37 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 38 39 /* Wake Up Filter Control */ 40 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 41 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 42 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 43 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 44 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 45 46 /* Extended Device Control */ 47 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */ 48 /* Physical Func Reset Done Indication */ 49 #define E1000_CTRL_EXT_PFRSTD 0x00004000 50 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 51 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 52 #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000 53 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 54 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 55 #define E1000_CTRL_EXT_EIAME 0x01000000 56 #define E1000_CTRL_EXT_IRCA 0x00000001 57 /* Interrupt delay cancellation */ 58 /* Driver loaded bit for FW */ 59 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 60 /* Interrupt acknowledge Auto-mask */ 61 /* Clear Interrupt timers after IMS clear */ 62 /* packet buffer parity error detection enabled */ 63 /* descriptor FIFO parity error detection enable */ 64 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 65 #define E1000_I2CCMD_REG_ADDR_SHIFT 16 66 #define E1000_I2CCMD_PHY_ADDR_SHIFT 24 67 #define E1000_I2CCMD_OPCODE_READ 0x08000000 68 #define E1000_I2CCMD_OPCODE_WRITE 0x00000000 69 #define E1000_I2CCMD_READY 0x20000000 70 #define E1000_I2CCMD_ERROR 0x80000000 71 #define E1000_MAX_SGMII_PHY_REG_ADDR 255 72 #define E1000_I2CCMD_PHY_TIMEOUT 200 73 #define E1000_IVAR_VALID 0x80 74 #define E1000_GPIE_NSICR 0x00000001 75 #define E1000_GPIE_MSIX_MODE 0x00000010 76 #define E1000_GPIE_EIAME 0x40000000 77 #define E1000_GPIE_PBA 0x80000000 78 79 /* Receive Descriptor bit definitions */ 80 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 81 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 82 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 83 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 84 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 85 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 86 #define E1000_RXD_STAT_TS 0x10000 /* Pkt was time stamped */ 87 88 #define E1000_RXDEXT_STATERR_LB 0x00040000 89 #define E1000_RXDEXT_STATERR_CE 0x01000000 90 #define E1000_RXDEXT_STATERR_SE 0x02000000 91 #define E1000_RXDEXT_STATERR_SEQ 0x04000000 92 #define E1000_RXDEXT_STATERR_CXE 0x10000000 93 #define E1000_RXDEXT_STATERR_TCPE 0x20000000 94 #define E1000_RXDEXT_STATERR_IPE 0x40000000 95 #define E1000_RXDEXT_STATERR_RXE 0x80000000 96 97 /* Same mask, but for extended and packet split descriptors */ 98 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 99 E1000_RXDEXT_STATERR_CE | \ 100 E1000_RXDEXT_STATERR_SE | \ 101 E1000_RXDEXT_STATERR_SEQ | \ 102 E1000_RXDEXT_STATERR_CXE | \ 103 E1000_RXDEXT_STATERR_RXE) 104 105 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 106 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 107 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 108 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 109 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 110 111 112 /* Management Control */ 113 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 114 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 115 #define E1000_MANC_EN_BMC2OS 0x10000000 /* OSBMC is Enabled or not */ 116 /* Enable Neighbor Discovery Filtering */ 117 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 118 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 119 /* Enable MAC address filtering */ 120 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 121 122 /* Receive Control */ 123 #define E1000_RCTL_EN 0x00000002 /* enable */ 124 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 125 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 126 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 127 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 128 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 129 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 130 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 131 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 132 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 133 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ 134 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ 135 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 136 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 137 #define E1000_RCTL_DPF 0x00400000 /* Discard Pause Frames */ 138 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 139 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 140 141 /* Use byte values for the following shift parameters 142 * Usage: 143 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 144 * E1000_PSRCTL_BSIZE0_MASK) | 145 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 146 * E1000_PSRCTL_BSIZE1_MASK) | 147 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 148 * E1000_PSRCTL_BSIZE2_MASK) | 149 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 150 * E1000_PSRCTL_BSIZE3_MASK)) 151 * where value0 = [128..16256], default=256 152 * value1 = [1024..64512], default=4096 153 * value2 = [0..64512], default=4096 154 * value3 = [0..64512], default=0 155 */ 156 157 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 158 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 159 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 160 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 161 162 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 163 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 164 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 165 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 166 167 /* SWFW_SYNC Definitions */ 168 #define E1000_SWFW_EEP_SM 0x1 169 #define E1000_SWFW_PHY0_SM 0x2 170 #define E1000_SWFW_PHY1_SM 0x4 171 #define E1000_SWFW_PHY2_SM 0x20 172 #define E1000_SWFW_PHY3_SM 0x40 173 174 /* FACTPS Definitions */ 175 /* Device Control */ 176 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 177 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 178 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 179 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 180 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 181 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 182 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 183 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 184 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 185 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 186 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 187 /* Defined polarity of Dock/Undock indication in SDP[0] */ 188 /* Reset both PHY ports, through PHYRST_N pin */ 189 /* enable link status from external LINK_0 and LINK_1 pins */ 190 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 191 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 192 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 193 #define E1000_CTRL_RST 0x04000000 /* Global reset */ 194 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 195 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 196 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 197 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 198 /* Initiate an interrupt to manageability engine */ 199 #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ 200 201 /* Bit definitions for the Management Data IO (MDIO) and Management Data 202 * Clock (MDC) pins in the Device Control Register. 203 */ 204 205 #define E1000_CONNSW_ENRGSRC 0x4 206 #define E1000_PCS_CFG_PCS_EN 8 207 #define E1000_PCS_LCTL_FLV_LINK_UP 1 208 #define E1000_PCS_LCTL_FSV_100 2 209 #define E1000_PCS_LCTL_FSV_1000 4 210 #define E1000_PCS_LCTL_FDV_FULL 8 211 #define E1000_PCS_LCTL_FSD 0x10 212 #define E1000_PCS_LCTL_FORCE_LINK 0x20 213 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 214 #define E1000_PCS_LCTL_AN_ENABLE 0x10000 215 #define E1000_PCS_LCTL_AN_RESTART 0x20000 216 #define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 217 #define E1000_ENABLE_SERDES_LOOPBACK 0x0410 218 219 #define E1000_PCS_LSTS_LINK_OK 1 220 #define E1000_PCS_LSTS_SPEED_100 2 221 #define E1000_PCS_LSTS_SPEED_1000 4 222 #define E1000_PCS_LSTS_DUPLEX_FULL 8 223 #define E1000_PCS_LSTS_SYNK_OK 0x10 224 225 /* Device Status */ 226 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 227 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 228 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 229 #define E1000_STATUS_FUNC_SHIFT 2 230 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 231 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 232 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 233 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 234 /* Change in Dock/Undock state. Clear on write '0'. */ 235 /* Status of Master requests. */ 236 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 237 /* BMC external code execution disabled */ 238 239 #define E1000_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */ 240 #define E1000_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */ 241 /* Constants used to intrepret the masked PCI-X bus speed. */ 242 243 #define SPEED_10 10 244 #define SPEED_100 100 245 #define SPEED_1000 1000 246 #define SPEED_2500 2500 247 #define HALF_DUPLEX 1 248 #define FULL_DUPLEX 2 249 250 251 #define ADVERTISE_10_HALF 0x0001 252 #define ADVERTISE_10_FULL 0x0002 253 #define ADVERTISE_100_HALF 0x0004 254 #define ADVERTISE_100_FULL 0x0008 255 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 256 #define ADVERTISE_1000_FULL 0x0020 257 258 /* 1000/H is not supported, nor spec-compliant. */ 259 #define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 260 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 261 ADVERTISE_1000_FULL) 262 #define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 263 ADVERTISE_100_HALF | ADVERTISE_100_FULL) 264 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 265 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 266 #define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ 267 ADVERTISE_1000_FULL) 268 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 269 270 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 271 272 /* LED Control */ 273 #define E1000_LEDCTL_LED0_MODE_SHIFT 0 274 #define E1000_LEDCTL_LED0_BLINK 0x00000080 275 276 #define E1000_LEDCTL_MODE_LED_ON 0xE 277 #define E1000_LEDCTL_MODE_LED_OFF 0xF 278 279 /* Transmit Descriptor bit definitions */ 280 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 281 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 282 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 283 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 284 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 285 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 286 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 287 /* Extended desc bits for Linksec and timesync */ 288 289 /* Transmit Control */ 290 #define E1000_TCTL_EN 0x00000002 /* enable tx */ 291 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 292 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 293 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 294 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 295 296 /* DMA Coalescing register fields */ 297 #define E1000_DMACR_DMACWT_MASK 0x00003FFF /* DMA Coalescing 298 * Watchdog Timer */ 299 #define E1000_DMACR_DMACTHR_MASK 0x00FF0000 /* DMA Coalescing Receive 300 * Threshold */ 301 #define E1000_DMACR_DMACTHR_SHIFT 16 302 #define E1000_DMACR_DMAC_LX_MASK 0x30000000 /* Lx when no PCIe 303 * transactions */ 304 #define E1000_DMACR_DMAC_LX_SHIFT 28 305 #define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */ 306 /* DMA Coalescing BMC-to-OS Watchdog Enable */ 307 #define E1000_DMACR_DC_BMC2OSW_EN 0x00008000 308 309 #define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF /* DMA Coalescing Transmit 310 * Threshold */ 311 312 #define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */ 313 314 #define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF /* Receive Traffic Rate 315 * Threshold */ 316 #define E1000_DMCRTRH_LRPRCW 0x80000000 /* Rcv packet rate in 317 * current window */ 318 319 #define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF /* DMA Coal Rcv Traffic 320 * Current Cnt */ 321 322 #define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 /* Flow ctrl Rcv Threshold 323 * High val */ 324 #define E1000_FCRTC_RTH_COAL_SHIFT 4 325 #define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision */ 326 327 /* Timestamp in Rx buffer */ 328 #define E1000_RXPBS_CFG_TS_EN 0x80000000 329 330 /* SerDes Control */ 331 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 332 333 /* Receive Checksum Control */ 334 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 335 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 336 #define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ 337 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 338 339 /* Header split receive */ 340 #define E1000_RFCTL_LEF 0x00040000 341 342 /* Collision related configuration parameters */ 343 #define E1000_COLLISION_THRESHOLD 15 344 #define E1000_CT_SHIFT 4 345 #define E1000_COLLISION_DISTANCE 63 346 #define E1000_COLD_SHIFT 12 347 348 /* Ethertype field values */ 349 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 350 351 #define MAX_JUMBO_FRAME_SIZE 0x3F00 352 353 /* PBA constants */ 354 #define E1000_PBA_34K 0x0022 355 #define E1000_PBA_64K 0x0040 /* 64KB */ 356 357 /* SW Semaphore Register */ 358 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 359 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 360 361 /* Interrupt Cause Read */ 362 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 363 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 364 #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ 365 #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 366 #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 367 #define E1000_ICR_VMMB 0x00000100 /* VM MB event */ 368 #define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */ 369 #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ 370 /* If this bit asserted, the driver should claim the interrupt */ 371 #define E1000_ICR_INT_ASSERTED 0x80000000 372 /* LAN connected device generates an interrupt */ 373 #define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 374 375 /* Extended Interrupt Cause Read */ 376 #define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ 377 #define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ 378 #define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ 379 #define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ 380 #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ 381 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ 382 #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ 383 #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ 384 #define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 385 /* TCP Timer */ 386 387 /* This defines the bits that are set in the Interrupt Mask 388 * Set/Read Register. Each bit is documented below: 389 * o RXT0 = Receiver Timer Interrupt (ring 0) 390 * o TXDW = Transmit Descriptor Written Back 391 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 392 * o RXSEQ = Receive Sequence Error 393 * o LSC = Link Status Change 394 */ 395 #define IMS_ENABLE_MASK ( \ 396 E1000_IMS_RXT0 | \ 397 E1000_IMS_TXDW | \ 398 E1000_IMS_RXDMT0 | \ 399 E1000_IMS_RXSEQ | \ 400 E1000_IMS_LSC | \ 401 E1000_IMS_DOUTSYNC) 402 403 /* Interrupt Mask Set */ 404 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 405 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 406 #define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */ 407 #define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */ 408 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 409 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 410 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 411 #define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */ 412 #define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ 413 414 /* Extended Interrupt Mask Set */ 415 #define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ 416 417 /* Interrupt Cause Set */ 418 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 419 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 420 #define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */ 421 422 /* Extended Interrupt Cause Set */ 423 /* E1000_EITR_CNT_IGNR is only for 82576 and newer */ 424 #define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */ 425 426 427 /* Transmit Descriptor Control */ 428 /* Enable the counting of descriptors still to be processed. */ 429 430 /* Flow Control Constants */ 431 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 432 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 433 #define FLOW_CONTROL_TYPE 0x8808 434 435 /* Transmit Config Word */ 436 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 437 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 438 439 /* 802.1q VLAN Packet Size */ 440 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ 441 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 442 443 /* Receive Address */ 444 /* Number of high/low register pairs in the RAR. The RAR (Receive Address 445 * Registers) holds the directed and multicast addresses that we monitor. 446 * Technically, we have 16 spots. However, we reserve one of these spots 447 * (RAR[15]) for our directed address used by controllers with 448 * manageability enabled, allowing us room for 15 multicast addresses. 449 */ 450 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 451 #define E1000_RAL_MAC_ADDR_LEN 4 452 #define E1000_RAH_MAC_ADDR_LEN 2 453 #define E1000_RAH_POOL_MASK 0x03FC0000 454 #define E1000_RAH_POOL_1 0x00040000 455 456 /* Error Codes */ 457 #define E1000_SUCCESS 0 458 #define E1000_ERR_NVM 1 459 #define E1000_ERR_PHY 2 460 #define E1000_ERR_CONFIG 3 461 #define E1000_ERR_PARAM 4 462 #define E1000_ERR_MAC_INIT 5 463 #define E1000_ERR_RESET 9 464 #define E1000_ERR_MASTER_REQUESTS_PENDING 10 465 #define E1000_BLK_PHY_RESET 12 466 #define E1000_ERR_SWFW_SYNC 13 467 #define E1000_NOT_IMPLEMENTED 14 468 #define E1000_ERR_MBX 15 469 #define E1000_ERR_INVALID_ARGUMENT 16 470 #define E1000_ERR_NO_SPACE 17 471 #define E1000_ERR_NVM_PBA_SECTION 18 472 #define E1000_ERR_INVM_VALUE_NOT_FOUND 19 473 #define E1000_ERR_I2C 20 474 475 /* Loop limit on how long we wait for auto-negotiation to complete */ 476 #define COPPER_LINK_UP_LIMIT 10 477 #define PHY_AUTO_NEG_LIMIT 45 478 #define PHY_FORCE_LIMIT 20 479 /* Number of 100 microseconds we wait for PCI Express master disable */ 480 #define MASTER_DISABLE_TIMEOUT 800 481 /* Number of milliseconds we wait for PHY configuration done after MAC reset */ 482 #define PHY_CFG_TIMEOUT 100 483 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 484 /* Number of milliseconds for NVM auto read done after MAC reset. */ 485 #define AUTO_READ_DONE_TIMEOUT 10 486 487 /* Flow Control */ 488 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 489 490 #define E1000_TSYNCTXCTL_VALID 0x00000001 /* tx timestamp valid */ 491 #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable tx timestampping */ 492 493 #define E1000_TSYNCRXCTL_VALID 0x00000001 /* rx timestamp valid */ 494 #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* rx type mask */ 495 #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 496 #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 497 #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 498 #define E1000_TSYNCRXCTL_TYPE_ALL 0x08 499 #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 500 #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable rx timestampping */ 501 502 #define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF 503 #define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 504 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01 505 #define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02 506 #define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03 507 #define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04 508 509 #define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00 510 #define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000 511 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100 512 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200 513 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300 514 #define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800 515 #define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900 516 #define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00 517 #define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00 518 #define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00 519 #define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00 520 521 #define E1000_TIMINCA_16NS_SHIFT 24 522 523 #define E1000_TSICR_TXTS 0x00000002 524 #define E1000_TSIM_TXTS 0x00000002 525 526 #define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */ 527 #define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */ 528 #define E1000_MDICNFG_PHY_MASK 0x03E00000 529 #define E1000_MDICNFG_PHY_SHIFT 21 530 531 /* PCI Express Control */ 532 #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 533 #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 534 #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 535 #define E1000_GCR_CAP_VER2 0x00040000 536 537 /* mPHY Address Control and Data Registers */ 538 #define E1000_MPHY_ADDR_CTL 0x0024 /* mPHY Address Control Register */ 539 #define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000 540 #define E1000_MPHY_DATA 0x0E10 /* mPHY Data Register */ 541 542 /* mPHY PCS CLK Register */ 543 #define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004 /* mPHY PCS CLK AFE CSR Offset */ 544 /* mPHY Near End Digital Loopback Override Bit */ 545 #define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10 546 547 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 548 #define E1000_PCS_LSTS_AN_COMPLETE 0x10000 549 550 /* PHY Control Register */ 551 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 552 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 553 #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 554 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 555 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 556 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 557 #define MII_CR_SPEED_1000 0x0040 558 #define MII_CR_SPEED_100 0x2000 559 #define MII_CR_SPEED_10 0x0000 560 561 /* PHY Status Register */ 562 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 563 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 564 565 /* Autoneg Advertisement Register */ 566 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 567 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 568 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 569 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 570 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 571 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 572 573 /* Link Partner Ability Register (Base Page) */ 574 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 575 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 576 577 /* Autoneg Expansion Register */ 578 579 /* 1000BASE-T Control Register */ 580 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 581 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 582 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 583 /* 0=Configure PHY as Slave */ 584 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 585 /* 0=Automatic Master/Slave config */ 586 587 /* 1000BASE-T Status Register */ 588 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 589 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 590 591 592 /* PHY 1000 MII Register/Bit Definitions */ 593 /* PHY Registers defined by IEEE */ 594 #define PHY_CONTROL 0x00 /* Control Register */ 595 #define PHY_STATUS 0x01 /* Status Register */ 596 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 597 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 598 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 599 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 600 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 601 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 602 603 /* NVM Control */ 604 #define E1000_EECD_SK 0x00000001 /* NVM Clock */ 605 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ 606 #define E1000_EECD_DI 0x00000004 /* NVM Data In */ 607 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ 608 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ 609 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ 610 #define E1000_EECD_PRES 0x00000100 /* NVM Present */ 611 /* NVM Addressing bits based on type 0=small, 1=large */ 612 #define E1000_EECD_ADDR_BITS 0x00000400 613 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 614 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 615 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 616 #define E1000_EECD_SIZE_EX_SHIFT 11 617 #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ 618 #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/ 619 #define E1000_FLUDONE_ATTEMPTS 20000 620 #define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ 621 #define E1000_I210_FIFO_SEL_RX 0x00 622 #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) 623 #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0) 624 #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06 625 #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01 626 #define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ 627 #define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/ 628 #define E1000_FLUDONE_ATTEMPTS 20000 629 #define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ 630 #define E1000_I210_FIFO_SEL_RX 0x00 631 #define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) 632 #define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0) 633 #define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06 634 #define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01 635 636 637 /* Offset to data in NVM read/write registers */ 638 #define E1000_NVM_RW_REG_DATA 16 639 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 640 #define E1000_NVM_RW_REG_START 1 /* Start operation */ 641 #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 642 #define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ 643 644 /* NVM Word Offsets */ 645 #define NVM_COMPAT 0x0003 646 #define NVM_ID_LED_SETTINGS 0x0004 /* SERDES output amplitude */ 647 #define NVM_VERSION 0x0005 648 #define NVM_INIT_CONTROL2_REG 0x000F 649 #define NVM_INIT_CONTROL3_PORT_B 0x0014 650 #define NVM_INIT_CONTROL3_PORT_A 0x0024 651 #define NVM_ALT_MAC_ADDR_PTR 0x0037 652 #define NVM_CHECKSUM_REG 0x003F 653 #define NVM_COMPATIBILITY_REG_3 0x0003 654 #define NVM_COMPATIBILITY_BIT_MASK 0x8000 655 #define NVM_MAC_ADDR 0x0000 656 #define NVM_SUB_DEV_ID 0x000B 657 #define NVM_SUB_VEN_ID 0x000C 658 #define NVM_DEV_ID 0x000D 659 #define NVM_VEN_ID 0x000E 660 #define NVM_INIT_CTRL_2 0x000F 661 #define NVM_INIT_CTRL_4 0x0013 662 #define NVM_LED_1_CFG 0x001C 663 #define NVM_LED_0_2_CFG 0x001F 664 665 /* NVM version defines */ 666 #define NVM_ETRACK_WORD 0x0042 667 #define NVM_COMB_VER_OFF 0x0083 668 #define NVM_COMB_VER_PTR 0x003d 669 #define NVM_MAJOR_MASK 0xF000 670 #define NVM_MINOR_MASK 0x0FF0 671 #define NVM_BUILD_MASK 0x000F 672 #define NVM_COMB_VER_MASK 0x00FF 673 #define NVM_MAJOR_SHIFT 12 674 #define NVM_MINOR_SHIFT 4 675 #define NVM_COMB_VER_SHFT 8 676 #define NVM_VER_INVALID 0xFFFF 677 #define NVM_ETRACK_SHIFT 16 678 #define NVM_ETS_CFG 0x003E 679 #define NVM_ETS_LTHRES_DELTA_MASK 0x07C0 680 #define NVM_ETS_LTHRES_DELTA_SHIFT 6 681 #define NVM_ETS_TYPE_MASK 0x0038 682 #define NVM_ETS_TYPE_SHIFT 3 683 #define NVM_ETS_TYPE_EMC 0x000 684 #define NVM_ETS_NUM_SENSORS_MASK 0x0007 685 #define NVM_ETS_DATA_LOC_MASK 0x3C00 686 #define NVM_ETS_DATA_LOC_SHIFT 10 687 #define NVM_ETS_DATA_INDEX_MASK 0x0300 688 #define NVM_ETS_DATA_INDEX_SHIFT 8 689 #define NVM_ETS_DATA_HTHRESH_MASK 0x00FF 690 691 #define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ 692 #define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ 693 #define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */ 694 #define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */ 695 696 #define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0) 697 698 /* Mask bits for fields in Word 0x24 of the NVM */ 699 #define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */ 700 #define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed external */ 701 702 /* Mask bits for fields in Word 0x0f of the NVM */ 703 #define NVM_WORD0F_PAUSE_MASK 0x3000 704 #define NVM_WORD0F_ASM_DIR 0x2000 705 706 /* Mask bits for fields in Word 0x1a of the NVM */ 707 708 /* length of string needed to store part num */ 709 #define E1000_PBANUM_LENGTH 11 710 711 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 712 #define NVM_SUM 0xBABA 713 714 #define NVM_PBA_OFFSET_0 8 715 #define NVM_PBA_OFFSET_1 9 716 #define NVM_RESERVED_WORD 0xFFFF 717 #define NVM_PBA_PTR_GUARD 0xFAFA 718 #define NVM_WORD_SIZE_BASE_SHIFT 6 719 720 /* NVM Commands - Microwire */ 721 722 /* NVM Commands - SPI */ 723 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 724 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 725 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 726 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 727 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 728 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 729 730 /* SPI NVM Status Register */ 731 #define NVM_STATUS_RDY_SPI 0x01 732 733 /* Word definitions for ID LED Settings */ 734 #define ID_LED_RESERVED_0000 0x0000 735 #define ID_LED_RESERVED_FFFF 0xFFFF 736 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 737 (ID_LED_OFF1_OFF2 << 8) | \ 738 (ID_LED_DEF1_DEF2 << 4) | \ 739 (ID_LED_DEF1_DEF2)) 740 #define ID_LED_DEF1_DEF2 0x1 741 #define ID_LED_DEF1_ON2 0x2 742 #define ID_LED_DEF1_OFF2 0x3 743 #define ID_LED_ON1_DEF2 0x4 744 #define ID_LED_ON1_ON2 0x5 745 #define ID_LED_ON1_OFF2 0x6 746 #define ID_LED_OFF1_DEF2 0x7 747 #define ID_LED_OFF1_ON2 0x8 748 #define ID_LED_OFF1_OFF2 0x9 749 750 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 751 #define IGP_ACTIVITY_LED_ENABLE 0x0300 752 #define IGP_LED3_MODE 0x07000000 753 754 /* PCI/PCI-X/PCI-EX Config space */ 755 #define PCIE_DEVICE_CONTROL2 0x28 756 #define PCIE_DEVICE_CONTROL2_16ms 0x0005 757 758 #define PHY_REVISION_MASK 0xFFFFFFF0 759 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 760 #define MAX_PHY_MULTI_PAGE_REG 0xF 761 762 /* Bit definitions for valid PHY IDs. */ 763 /* I = Integrated 764 * E = External 765 */ 766 #define M88E1111_I_PHY_ID 0x01410CC0 767 #define M88E1112_E_PHY_ID 0x01410C90 768 #define I347AT4_E_PHY_ID 0x01410DC0 769 #define IGP03E1000_E_PHY_ID 0x02A80390 770 #define I82580_I_PHY_ID 0x015403A0 771 #define I350_I_PHY_ID 0x015403B0 772 #define M88_VENDOR 0x0141 773 #define I210_I_PHY_ID 0x01410C00 774 #define M88E1545_E_PHY_ID 0x01410EA0 775 776 /* M88E1000 Specific Registers */ 777 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 778 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 779 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 780 781 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 782 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 783 784 /* M88E1000 PHY Specific Control Register */ 785 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 786 /* 1=CLK125 low, 0=CLK125 toggling */ 787 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 788 /* Manual MDI configuration */ 789 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 790 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 791 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 792 /* Auto crossover enabled all speeds */ 793 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 794 /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold 795 * 0=Normal 10BASE-T Rx Threshold 796 */ 797 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */ 798 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 799 800 /* M88E1000 PHY Specific Status Register */ 801 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 802 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 803 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 804 /* 0 = <50M 805 * 1 = 50-80M 806 * 2 = 80-110M 807 * 3 = 110-140M 808 * 4 = >140M 809 */ 810 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 811 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 812 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 813 814 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 815 816 /* M88E1000 Extended PHY Specific Control Register */ 817 /* 1 = Lost lock detect enabled. 818 * Will assert lost lock and bring 819 * link down if idle not seen 820 * within 1ms in 1000BASE-T 821 */ 822 /* Number of times we will attempt to autonegotiate before downshifting if we 823 * are the master 824 */ 825 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 826 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 827 /* Number of times we will attempt to autonegotiate before downshifting if we 828 * are the slave 829 */ 830 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 831 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 832 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 833 834 /* Intel i347-AT4 Registers */ 835 836 #define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */ 837 #define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */ 838 #define I347AT4_PAGE_SELECT 0x16 839 840 /* i347-AT4 Extended PHY Specific Control Register */ 841 842 /* Number of times we will attempt to autonegotiate before downshifting if we 843 * are the master 844 */ 845 #define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800 846 #define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000 847 #define I347AT4_PSCR_DOWNSHIFT_1X 0x0000 848 #define I347AT4_PSCR_DOWNSHIFT_2X 0x1000 849 #define I347AT4_PSCR_DOWNSHIFT_3X 0x2000 850 #define I347AT4_PSCR_DOWNSHIFT_4X 0x3000 851 #define I347AT4_PSCR_DOWNSHIFT_5X 0x4000 852 #define I347AT4_PSCR_DOWNSHIFT_6X 0x5000 853 #define I347AT4_PSCR_DOWNSHIFT_7X 0x6000 854 #define I347AT4_PSCR_DOWNSHIFT_8X 0x7000 855 856 /* i347-AT4 PHY Cable Diagnostics Control */ 857 #define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */ 858 859 /* Marvell 1112 only registers */ 860 #define M88E1112_VCT_DSP_DISTANCE 0x001A 861 862 /* M88EC018 Rev 2 specific DownShift settings */ 863 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 864 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 865 866 /* MDI Control */ 867 #define E1000_MDIC_DATA_MASK 0x0000FFFF 868 #define E1000_MDIC_REG_MASK 0x001F0000 869 #define E1000_MDIC_REG_SHIFT 16 870 #define E1000_MDIC_PHY_MASK 0x03E00000 871 #define E1000_MDIC_PHY_SHIFT 21 872 #define E1000_MDIC_OP_WRITE 0x04000000 873 #define E1000_MDIC_OP_READ 0x08000000 874 #define E1000_MDIC_READY 0x10000000 875 #define E1000_MDIC_INT_EN 0x20000000 876 #define E1000_MDIC_ERROR 0x40000000 877 #define E1000_MDIC_DEST 0x80000000 878 879 /* Thermal Sensor */ 880 #define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */ 881 #define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Speed Throttle Event */ 882 883 /* Energy Efficient Ethernet */ 884 #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* EEE Enable 1G AN */ 885 #define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* EEE Enable 100M AN */ 886 #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEE Tx LPI Enable */ 887 #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEE Rx LPI Enable */ 888 #define E1000_EEER_FRC_AN 0x10000000 /* Enable EEE in loopback */ 889 #define E1000_EEER_LPI_FC 0x00040000 /* EEE Enable on FC */ 890 #define E1000_EEE_SU_LPI_CLK_STP 0X00800000 /* EEE LPI Clock Stop */ 891 #define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */ 892 #define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */ 893 #define E1000_EEE_LP_ADV_DEV_I210 7 /* EEE LP Adv Device */ 894 #define E1000_EEE_LP_ADV_ADDR_I210 61 /* EEE LP Adv Register */ 895 #define E1000_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */ 896 #define E1000_M88E1545_PAGE_ADDR 0x16 /* Page Offset Register */ 897 #define E1000_M88E1545_EEE_CTRL_1 0x0 898 #define E1000_M88E1545_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */ 899 #define E1000_EEE_ADV_DEV_I354 7 900 #define E1000_EEE_ADV_ADDR_I354 60 901 #define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */ 902 #define E1000_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */ 903 #define E1000_PCS_STATUS_DEV_I354 3 904 #define E1000_PCS_STATUS_ADDR_I354 1 905 #define E1000_PCS_STATUS_TX_LPI_IND 0x0200 /* Tx in LPI state */ 906 #define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400 907 #define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800 908 909 /* SerDes Control */ 910 #define E1000_GEN_CTL_READY 0x80000000 911 #define E1000_GEN_CTL_ADDRESS_SHIFT 8 912 #define E1000_GEN_POLL_TIMEOUT 640 913 914 #define E1000_VFTA_ENTRY_SHIFT 5 915 #define E1000_VFTA_ENTRY_MASK 0x7F 916 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 917 918 /* DMA Coalescing register fields */ 919 #define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision based 920 on DMA coal */ 921 922 /* Tx Rate-Scheduler Config fields */ 923 #define E1000_RTTBCNRC_RS_ENA 0x80000000 924 #define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF 925 #define E1000_RTTBCNRC_RF_INT_SHIFT 14 926 #define E1000_RTTBCNRC_RF_INT_MASK \ 927 (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT) 928 929 #endif 930