1 /* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2015 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 /* e1000_82575 25 * e1000_82576 26 */ 27 28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 29 30 #include <linux/types.h> 31 #include <linux/if_ether.h> 32 #include <linux/i2c.h> 33 34 #include "e1000_mac.h" 35 #include "e1000_82575.h" 36 #include "e1000_i210.h" 37 38 static s32 igb_get_invariants_82575(struct e1000_hw *); 39 static s32 igb_acquire_phy_82575(struct e1000_hw *); 40 static void igb_release_phy_82575(struct e1000_hw *); 41 static s32 igb_acquire_nvm_82575(struct e1000_hw *); 42 static void igb_release_nvm_82575(struct e1000_hw *); 43 static s32 igb_check_for_link_82575(struct e1000_hw *); 44 static s32 igb_get_cfg_done_82575(struct e1000_hw *); 45 static s32 igb_init_hw_82575(struct e1000_hw *); 46 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *); 47 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *); 48 static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *); 49 static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16); 50 static s32 igb_reset_hw_82575(struct e1000_hw *); 51 static s32 igb_reset_hw_82580(struct e1000_hw *); 52 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); 53 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool); 54 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool); 55 static s32 igb_setup_copper_link_82575(struct e1000_hw *); 56 static s32 igb_setup_serdes_link_82575(struct e1000_hw *); 57 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16); 58 static void igb_clear_hw_cntrs_82575(struct e1000_hw *); 59 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16); 60 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *, 61 u16 *); 62 static s32 igb_get_phy_id_82575(struct e1000_hw *); 63 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16); 64 static bool igb_sgmii_active_82575(struct e1000_hw *); 65 static s32 igb_reset_init_script_82575(struct e1000_hw *); 66 static s32 igb_read_mac_addr_82575(struct e1000_hw *); 67 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw); 68 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw); 69 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw); 70 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw); 71 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw); 72 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw); 73 static const u16 e1000_82580_rxpbs_table[] = { 74 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 }; 75 76 /** 77 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO 78 * @hw: pointer to the HW structure 79 * 80 * Called to determine if the I2C pins are being used for I2C or as an 81 * external MDIO interface since the two options are mutually exclusive. 82 **/ 83 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw) 84 { 85 u32 reg = 0; 86 bool ext_mdio = false; 87 88 switch (hw->mac.type) { 89 case e1000_82575: 90 case e1000_82576: 91 reg = rd32(E1000_MDIC); 92 ext_mdio = !!(reg & E1000_MDIC_DEST); 93 break; 94 case e1000_82580: 95 case e1000_i350: 96 case e1000_i354: 97 case e1000_i210: 98 case e1000_i211: 99 reg = rd32(E1000_MDICNFG); 100 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); 101 break; 102 default: 103 break; 104 } 105 return ext_mdio; 106 } 107 108 /** 109 * igb_check_for_link_media_swap - Check which M88E1112 interface linked 110 * @hw: pointer to the HW structure 111 * 112 * Poll the M88E1112 interfaces to see which interface achieved link. 113 */ 114 static s32 igb_check_for_link_media_swap(struct e1000_hw *hw) 115 { 116 struct e1000_phy_info *phy = &hw->phy; 117 s32 ret_val; 118 u16 data; 119 u8 port = 0; 120 121 /* Check the copper medium. */ 122 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 123 if (ret_val) 124 return ret_val; 125 126 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); 127 if (ret_val) 128 return ret_val; 129 130 if (data & E1000_M88E1112_STATUS_LINK) 131 port = E1000_MEDIA_PORT_COPPER; 132 133 /* Check the other medium. */ 134 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1); 135 if (ret_val) 136 return ret_val; 137 138 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); 139 if (ret_val) 140 return ret_val; 141 142 143 if (data & E1000_M88E1112_STATUS_LINK) 144 port = E1000_MEDIA_PORT_OTHER; 145 146 /* Determine if a swap needs to happen. */ 147 if (port && (hw->dev_spec._82575.media_port != port)) { 148 hw->dev_spec._82575.media_port = port; 149 hw->dev_spec._82575.media_changed = true; 150 } 151 152 if (port == E1000_MEDIA_PORT_COPPER) { 153 /* reset page to 0 */ 154 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 155 if (ret_val) 156 return ret_val; 157 igb_check_for_link_82575(hw); 158 } else { 159 igb_check_for_link_82575(hw); 160 /* reset page to 0 */ 161 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 162 if (ret_val) 163 return ret_val; 164 } 165 166 return 0; 167 } 168 169 /** 170 * igb_init_phy_params_82575 - Init PHY func ptrs. 171 * @hw: pointer to the HW structure 172 **/ 173 static s32 igb_init_phy_params_82575(struct e1000_hw *hw) 174 { 175 struct e1000_phy_info *phy = &hw->phy; 176 s32 ret_val = 0; 177 u32 ctrl_ext; 178 179 if (hw->phy.media_type != e1000_media_type_copper) { 180 phy->type = e1000_phy_none; 181 goto out; 182 } 183 184 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 185 phy->reset_delay_us = 100; 186 187 ctrl_ext = rd32(E1000_CTRL_EXT); 188 189 if (igb_sgmii_active_82575(hw)) { 190 phy->ops.reset = igb_phy_hw_reset_sgmii_82575; 191 ctrl_ext |= E1000_CTRL_I2C_ENA; 192 } else { 193 phy->ops.reset = igb_phy_hw_reset; 194 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 195 } 196 197 wr32(E1000_CTRL_EXT, ctrl_ext); 198 igb_reset_mdicnfg_82580(hw); 199 200 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) { 201 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575; 202 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575; 203 } else { 204 switch (hw->mac.type) { 205 case e1000_82580: 206 case e1000_i350: 207 case e1000_i354: 208 phy->ops.read_reg = igb_read_phy_reg_82580; 209 phy->ops.write_reg = igb_write_phy_reg_82580; 210 break; 211 case e1000_i210: 212 case e1000_i211: 213 phy->ops.read_reg = igb_read_phy_reg_gs40g; 214 phy->ops.write_reg = igb_write_phy_reg_gs40g; 215 break; 216 default: 217 phy->ops.read_reg = igb_read_phy_reg_igp; 218 phy->ops.write_reg = igb_write_phy_reg_igp; 219 } 220 } 221 222 /* set lan id */ 223 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >> 224 E1000_STATUS_FUNC_SHIFT; 225 226 /* Set phy->phy_addr and phy->id. */ 227 ret_val = igb_get_phy_id_82575(hw); 228 if (ret_val) 229 return ret_val; 230 231 /* Verify phy id and set remaining function pointers */ 232 switch (phy->id) { 233 case M88E1543_E_PHY_ID: 234 case I347AT4_E_PHY_ID: 235 case M88E1112_E_PHY_ID: 236 case M88E1111_I_PHY_ID: 237 phy->type = e1000_phy_m88; 238 phy->ops.check_polarity = igb_check_polarity_m88; 239 phy->ops.get_phy_info = igb_get_phy_info_m88; 240 if (phy->id != M88E1111_I_PHY_ID) 241 phy->ops.get_cable_length = 242 igb_get_cable_length_m88_gen2; 243 else 244 phy->ops.get_cable_length = igb_get_cable_length_m88; 245 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; 246 /* Check if this PHY is confgured for media swap. */ 247 if (phy->id == M88E1112_E_PHY_ID) { 248 u16 data; 249 250 ret_val = phy->ops.write_reg(hw, 251 E1000_M88E1112_PAGE_ADDR, 252 2); 253 if (ret_val) 254 goto out; 255 256 ret_val = phy->ops.read_reg(hw, 257 E1000_M88E1112_MAC_CTRL_1, 258 &data); 259 if (ret_val) 260 goto out; 261 262 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >> 263 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT; 264 if (data == E1000_M88E1112_AUTO_COPPER_SGMII || 265 data == E1000_M88E1112_AUTO_COPPER_BASEX) 266 hw->mac.ops.check_for_link = 267 igb_check_for_link_media_swap; 268 } 269 break; 270 case IGP03E1000_E_PHY_ID: 271 phy->type = e1000_phy_igp_3; 272 phy->ops.get_phy_info = igb_get_phy_info_igp; 273 phy->ops.get_cable_length = igb_get_cable_length_igp_2; 274 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp; 275 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575; 276 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state; 277 break; 278 case I82580_I_PHY_ID: 279 case I350_I_PHY_ID: 280 phy->type = e1000_phy_82580; 281 phy->ops.force_speed_duplex = 282 igb_phy_force_speed_duplex_82580; 283 phy->ops.get_cable_length = igb_get_cable_length_82580; 284 phy->ops.get_phy_info = igb_get_phy_info_82580; 285 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580; 286 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580; 287 break; 288 case I210_I_PHY_ID: 289 phy->type = e1000_phy_i210; 290 phy->ops.check_polarity = igb_check_polarity_m88; 291 phy->ops.get_phy_info = igb_get_phy_info_m88; 292 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2; 293 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580; 294 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580; 295 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; 296 break; 297 default: 298 ret_val = -E1000_ERR_PHY; 299 goto out; 300 } 301 302 out: 303 return ret_val; 304 } 305 306 /** 307 * igb_init_nvm_params_82575 - Init NVM func ptrs. 308 * @hw: pointer to the HW structure 309 **/ 310 static s32 igb_init_nvm_params_82575(struct e1000_hw *hw) 311 { 312 struct e1000_nvm_info *nvm = &hw->nvm; 313 u32 eecd = rd32(E1000_EECD); 314 u16 size; 315 316 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 317 E1000_EECD_SIZE_EX_SHIFT); 318 319 /* Added to a constant, "size" becomes the left-shift value 320 * for setting word_size. 321 */ 322 size += NVM_WORD_SIZE_BASE_SHIFT; 323 324 /* Just in case size is out of range, cap it to the largest 325 * EEPROM size supported 326 */ 327 if (size > 15) 328 size = 15; 329 330 nvm->word_size = 1 << size; 331 nvm->opcode_bits = 8; 332 nvm->delay_usec = 1; 333 334 switch (nvm->override) { 335 case e1000_nvm_override_spi_large: 336 nvm->page_size = 32; 337 nvm->address_bits = 16; 338 break; 339 case e1000_nvm_override_spi_small: 340 nvm->page_size = 8; 341 nvm->address_bits = 8; 342 break; 343 default: 344 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 345 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 346 16 : 8; 347 break; 348 } 349 if (nvm->word_size == (1 << 15)) 350 nvm->page_size = 128; 351 352 nvm->type = e1000_nvm_eeprom_spi; 353 354 /* NVM Function Pointers */ 355 nvm->ops.acquire = igb_acquire_nvm_82575; 356 nvm->ops.release = igb_release_nvm_82575; 357 nvm->ops.write = igb_write_nvm_spi; 358 nvm->ops.validate = igb_validate_nvm_checksum; 359 nvm->ops.update = igb_update_nvm_checksum; 360 if (nvm->word_size < (1 << 15)) 361 nvm->ops.read = igb_read_nvm_eerd; 362 else 363 nvm->ops.read = igb_read_nvm_spi; 364 365 /* override generic family function pointers for specific descendants */ 366 switch (hw->mac.type) { 367 case e1000_82580: 368 nvm->ops.validate = igb_validate_nvm_checksum_82580; 369 nvm->ops.update = igb_update_nvm_checksum_82580; 370 break; 371 case e1000_i354: 372 case e1000_i350: 373 nvm->ops.validate = igb_validate_nvm_checksum_i350; 374 nvm->ops.update = igb_update_nvm_checksum_i350; 375 break; 376 default: 377 break; 378 } 379 380 return 0; 381 } 382 383 /** 384 * igb_init_mac_params_82575 - Init MAC func ptrs. 385 * @hw: pointer to the HW structure 386 **/ 387 static s32 igb_init_mac_params_82575(struct e1000_hw *hw) 388 { 389 struct e1000_mac_info *mac = &hw->mac; 390 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 391 392 /* Set mta register count */ 393 mac->mta_reg_count = 128; 394 /* Set rar entry count */ 395 switch (mac->type) { 396 case e1000_82576: 397 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 398 break; 399 case e1000_82580: 400 mac->rar_entry_count = E1000_RAR_ENTRIES_82580; 401 break; 402 case e1000_i350: 403 case e1000_i354: 404 mac->rar_entry_count = E1000_RAR_ENTRIES_I350; 405 break; 406 default: 407 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 408 break; 409 } 410 /* reset */ 411 if (mac->type >= e1000_82580) 412 mac->ops.reset_hw = igb_reset_hw_82580; 413 else 414 mac->ops.reset_hw = igb_reset_hw_82575; 415 416 if (mac->type >= e1000_i210) { 417 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210; 418 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210; 419 420 } else { 421 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575; 422 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575; 423 } 424 425 /* Set if part includes ASF firmware */ 426 mac->asf_firmware_present = true; 427 /* Set if manageability features are enabled. */ 428 mac->arc_subsystem_valid = 429 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK) 430 ? true : false; 431 /* enable EEE on i350 parts and later parts */ 432 if (mac->type >= e1000_i350) 433 dev_spec->eee_disable = false; 434 else 435 dev_spec->eee_disable = true; 436 /* Allow a single clear of the SW semaphore on I210 and newer */ 437 if (mac->type >= e1000_i210) 438 dev_spec->clear_semaphore_once = true; 439 /* physical interface link setup */ 440 mac->ops.setup_physical_interface = 441 (hw->phy.media_type == e1000_media_type_copper) 442 ? igb_setup_copper_link_82575 443 : igb_setup_serdes_link_82575; 444 445 if (mac->type == e1000_82580) { 446 switch (hw->device_id) { 447 /* feature not supported on these id's */ 448 case E1000_DEV_ID_DH89XXCC_SGMII: 449 case E1000_DEV_ID_DH89XXCC_SERDES: 450 case E1000_DEV_ID_DH89XXCC_BACKPLANE: 451 case E1000_DEV_ID_DH89XXCC_SFP: 452 break; 453 default: 454 hw->dev_spec._82575.mas_capable = true; 455 break; 456 } 457 } 458 return 0; 459 } 460 461 /** 462 * igb_set_sfp_media_type_82575 - derives SFP module media type. 463 * @hw: pointer to the HW structure 464 * 465 * The media type is chosen based on SFP module. 466 * compatibility flags retrieved from SFP ID EEPROM. 467 **/ 468 static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw) 469 { 470 s32 ret_val = E1000_ERR_CONFIG; 471 u32 ctrl_ext = 0; 472 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 473 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags; 474 u8 tranceiver_type = 0; 475 s32 timeout = 3; 476 477 /* Turn I2C interface ON and power on sfp cage */ 478 ctrl_ext = rd32(E1000_CTRL_EXT); 479 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 480 wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); 481 482 wrfl(); 483 484 /* Read SFP module data */ 485 while (timeout) { 486 ret_val = igb_read_sfp_data_byte(hw, 487 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET), 488 &tranceiver_type); 489 if (ret_val == 0) 490 break; 491 msleep(100); 492 timeout--; 493 } 494 if (ret_val != 0) 495 goto out; 496 497 ret_val = igb_read_sfp_data_byte(hw, 498 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET), 499 (u8 *)eth_flags); 500 if (ret_val != 0) 501 goto out; 502 503 /* Check if there is some SFP module plugged and powered */ 504 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) || 505 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) { 506 dev_spec->module_plugged = true; 507 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) { 508 hw->phy.media_type = e1000_media_type_internal_serdes; 509 } else if (eth_flags->e100_base_fx) { 510 dev_spec->sgmii_active = true; 511 hw->phy.media_type = e1000_media_type_internal_serdes; 512 } else if (eth_flags->e1000_base_t) { 513 dev_spec->sgmii_active = true; 514 hw->phy.media_type = e1000_media_type_copper; 515 } else { 516 hw->phy.media_type = e1000_media_type_unknown; 517 hw_dbg("PHY module has not been recognized\n"); 518 goto out; 519 } 520 } else { 521 hw->phy.media_type = e1000_media_type_unknown; 522 } 523 ret_val = 0; 524 out: 525 /* Restore I2C interface setting */ 526 wr32(E1000_CTRL_EXT, ctrl_ext); 527 return ret_val; 528 } 529 530 static s32 igb_get_invariants_82575(struct e1000_hw *hw) 531 { 532 struct e1000_mac_info *mac = &hw->mac; 533 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 534 s32 ret_val; 535 u32 ctrl_ext = 0; 536 u32 link_mode = 0; 537 538 switch (hw->device_id) { 539 case E1000_DEV_ID_82575EB_COPPER: 540 case E1000_DEV_ID_82575EB_FIBER_SERDES: 541 case E1000_DEV_ID_82575GB_QUAD_COPPER: 542 mac->type = e1000_82575; 543 break; 544 case E1000_DEV_ID_82576: 545 case E1000_DEV_ID_82576_NS: 546 case E1000_DEV_ID_82576_NS_SERDES: 547 case E1000_DEV_ID_82576_FIBER: 548 case E1000_DEV_ID_82576_SERDES: 549 case E1000_DEV_ID_82576_QUAD_COPPER: 550 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 551 case E1000_DEV_ID_82576_SERDES_QUAD: 552 mac->type = e1000_82576; 553 break; 554 case E1000_DEV_ID_82580_COPPER: 555 case E1000_DEV_ID_82580_FIBER: 556 case E1000_DEV_ID_82580_QUAD_FIBER: 557 case E1000_DEV_ID_82580_SERDES: 558 case E1000_DEV_ID_82580_SGMII: 559 case E1000_DEV_ID_82580_COPPER_DUAL: 560 case E1000_DEV_ID_DH89XXCC_SGMII: 561 case E1000_DEV_ID_DH89XXCC_SERDES: 562 case E1000_DEV_ID_DH89XXCC_BACKPLANE: 563 case E1000_DEV_ID_DH89XXCC_SFP: 564 mac->type = e1000_82580; 565 break; 566 case E1000_DEV_ID_I350_COPPER: 567 case E1000_DEV_ID_I350_FIBER: 568 case E1000_DEV_ID_I350_SERDES: 569 case E1000_DEV_ID_I350_SGMII: 570 mac->type = e1000_i350; 571 break; 572 case E1000_DEV_ID_I210_COPPER: 573 case E1000_DEV_ID_I210_FIBER: 574 case E1000_DEV_ID_I210_SERDES: 575 case E1000_DEV_ID_I210_SGMII: 576 case E1000_DEV_ID_I210_COPPER_FLASHLESS: 577 case E1000_DEV_ID_I210_SERDES_FLASHLESS: 578 mac->type = e1000_i210; 579 break; 580 case E1000_DEV_ID_I211_COPPER: 581 mac->type = e1000_i211; 582 break; 583 case E1000_DEV_ID_I354_BACKPLANE_1GBPS: 584 case E1000_DEV_ID_I354_SGMII: 585 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS: 586 mac->type = e1000_i354; 587 break; 588 default: 589 return -E1000_ERR_MAC_INIT; 590 } 591 592 /* Set media type */ 593 /* The 82575 uses bits 22:23 for link mode. The mode can be changed 594 * based on the EEPROM. We cannot rely upon device ID. There 595 * is no distinguishable difference between fiber and internal 596 * SerDes mode on the 82575. There can be an external PHY attached 597 * on the SGMII interface. For this, we'll set sgmii_active to true. 598 */ 599 hw->phy.media_type = e1000_media_type_copper; 600 dev_spec->sgmii_active = false; 601 dev_spec->module_plugged = false; 602 603 ctrl_ext = rd32(E1000_CTRL_EXT); 604 605 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK; 606 switch (link_mode) { 607 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 608 hw->phy.media_type = e1000_media_type_internal_serdes; 609 break; 610 case E1000_CTRL_EXT_LINK_MODE_SGMII: 611 /* Get phy control interface type set (MDIO vs. I2C)*/ 612 if (igb_sgmii_uses_mdio_82575(hw)) { 613 hw->phy.media_type = e1000_media_type_copper; 614 dev_spec->sgmii_active = true; 615 break; 616 } 617 /* fall through for I2C based SGMII */ 618 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 619 /* read media type from SFP EEPROM */ 620 ret_val = igb_set_sfp_media_type_82575(hw); 621 if ((ret_val != 0) || 622 (hw->phy.media_type == e1000_media_type_unknown)) { 623 /* If media type was not identified then return media 624 * type defined by the CTRL_EXT settings. 625 */ 626 hw->phy.media_type = e1000_media_type_internal_serdes; 627 628 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) { 629 hw->phy.media_type = e1000_media_type_copper; 630 dev_spec->sgmii_active = true; 631 } 632 633 break; 634 } 635 636 /* do not change link mode for 100BaseFX */ 637 if (dev_spec->eth_flags.e100_base_fx) 638 break; 639 640 /* change current link mode setting */ 641 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 642 643 if (hw->phy.media_type == e1000_media_type_copper) 644 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII; 645 else 646 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 647 648 wr32(E1000_CTRL_EXT, ctrl_ext); 649 650 break; 651 default: 652 break; 653 } 654 655 /* mac initialization and operations */ 656 ret_val = igb_init_mac_params_82575(hw); 657 if (ret_val) 658 goto out; 659 660 /* NVM initialization */ 661 ret_val = igb_init_nvm_params_82575(hw); 662 switch (hw->mac.type) { 663 case e1000_i210: 664 case e1000_i211: 665 ret_val = igb_init_nvm_params_i210(hw); 666 break; 667 default: 668 break; 669 } 670 671 if (ret_val) 672 goto out; 673 674 /* if part supports SR-IOV then initialize mailbox parameters */ 675 switch (mac->type) { 676 case e1000_82576: 677 case e1000_i350: 678 igb_init_mbx_params_pf(hw); 679 break; 680 default: 681 break; 682 } 683 684 /* setup PHY parameters */ 685 ret_val = igb_init_phy_params_82575(hw); 686 687 out: 688 return ret_val; 689 } 690 691 /** 692 * igb_acquire_phy_82575 - Acquire rights to access PHY 693 * @hw: pointer to the HW structure 694 * 695 * Acquire access rights to the correct PHY. This is a 696 * function pointer entry point called by the api module. 697 **/ 698 static s32 igb_acquire_phy_82575(struct e1000_hw *hw) 699 { 700 u16 mask = E1000_SWFW_PHY0_SM; 701 702 if (hw->bus.func == E1000_FUNC_1) 703 mask = E1000_SWFW_PHY1_SM; 704 else if (hw->bus.func == E1000_FUNC_2) 705 mask = E1000_SWFW_PHY2_SM; 706 else if (hw->bus.func == E1000_FUNC_3) 707 mask = E1000_SWFW_PHY3_SM; 708 709 return hw->mac.ops.acquire_swfw_sync(hw, mask); 710 } 711 712 /** 713 * igb_release_phy_82575 - Release rights to access PHY 714 * @hw: pointer to the HW structure 715 * 716 * A wrapper to release access rights to the correct PHY. This is a 717 * function pointer entry point called by the api module. 718 **/ 719 static void igb_release_phy_82575(struct e1000_hw *hw) 720 { 721 u16 mask = E1000_SWFW_PHY0_SM; 722 723 if (hw->bus.func == E1000_FUNC_1) 724 mask = E1000_SWFW_PHY1_SM; 725 else if (hw->bus.func == E1000_FUNC_2) 726 mask = E1000_SWFW_PHY2_SM; 727 else if (hw->bus.func == E1000_FUNC_3) 728 mask = E1000_SWFW_PHY3_SM; 729 730 hw->mac.ops.release_swfw_sync(hw, mask); 731 } 732 733 /** 734 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 735 * @hw: pointer to the HW structure 736 * @offset: register offset to be read 737 * @data: pointer to the read data 738 * 739 * Reads the PHY register at offset using the serial gigabit media independent 740 * interface and stores the retrieved information in data. 741 **/ 742 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 743 u16 *data) 744 { 745 s32 ret_val = -E1000_ERR_PARAM; 746 747 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 748 hw_dbg("PHY Address %u is out of range\n", offset); 749 goto out; 750 } 751 752 ret_val = hw->phy.ops.acquire(hw); 753 if (ret_val) 754 goto out; 755 756 ret_val = igb_read_phy_reg_i2c(hw, offset, data); 757 758 hw->phy.ops.release(hw); 759 760 out: 761 return ret_val; 762 } 763 764 /** 765 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 766 * @hw: pointer to the HW structure 767 * @offset: register offset to write to 768 * @data: data to write at register offset 769 * 770 * Writes the data to PHY register at the offset using the serial gigabit 771 * media independent interface. 772 **/ 773 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 774 u16 data) 775 { 776 s32 ret_val = -E1000_ERR_PARAM; 777 778 779 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 780 hw_dbg("PHY Address %d is out of range\n", offset); 781 goto out; 782 } 783 784 ret_val = hw->phy.ops.acquire(hw); 785 if (ret_val) 786 goto out; 787 788 ret_val = igb_write_phy_reg_i2c(hw, offset, data); 789 790 hw->phy.ops.release(hw); 791 792 out: 793 return ret_val; 794 } 795 796 /** 797 * igb_get_phy_id_82575 - Retrieve PHY addr and id 798 * @hw: pointer to the HW structure 799 * 800 * Retrieves the PHY address and ID for both PHY's which do and do not use 801 * sgmi interface. 802 **/ 803 static s32 igb_get_phy_id_82575(struct e1000_hw *hw) 804 { 805 struct e1000_phy_info *phy = &hw->phy; 806 s32 ret_val = 0; 807 u16 phy_id; 808 u32 ctrl_ext; 809 u32 mdic; 810 811 /* Extra read required for some PHY's on i354 */ 812 if (hw->mac.type == e1000_i354) 813 igb_get_phy_id(hw); 814 815 /* For SGMII PHYs, we try the list of possible addresses until 816 * we find one that works. For non-SGMII PHYs 817 * (e.g. integrated copper PHYs), an address of 1 should 818 * work. The result of this function should mean phy->phy_addr 819 * and phy->id are set correctly. 820 */ 821 if (!(igb_sgmii_active_82575(hw))) { 822 phy->addr = 1; 823 ret_val = igb_get_phy_id(hw); 824 goto out; 825 } 826 827 if (igb_sgmii_uses_mdio_82575(hw)) { 828 switch (hw->mac.type) { 829 case e1000_82575: 830 case e1000_82576: 831 mdic = rd32(E1000_MDIC); 832 mdic &= E1000_MDIC_PHY_MASK; 833 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; 834 break; 835 case e1000_82580: 836 case e1000_i350: 837 case e1000_i354: 838 case e1000_i210: 839 case e1000_i211: 840 mdic = rd32(E1000_MDICNFG); 841 mdic &= E1000_MDICNFG_PHY_MASK; 842 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 843 break; 844 default: 845 ret_val = -E1000_ERR_PHY; 846 goto out; 847 } 848 ret_val = igb_get_phy_id(hw); 849 goto out; 850 } 851 852 /* Power on sgmii phy if it is disabled */ 853 ctrl_ext = rd32(E1000_CTRL_EXT); 854 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 855 wrfl(); 856 msleep(300); 857 858 /* The address field in the I2CCMD register is 3 bits and 0 is invalid. 859 * Therefore, we need to test 1-7 860 */ 861 for (phy->addr = 1; phy->addr < 8; phy->addr++) { 862 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 863 if (ret_val == 0) { 864 hw_dbg("Vendor ID 0x%08X read at address %u\n", 865 phy_id, phy->addr); 866 /* At the time of this writing, The M88 part is 867 * the only supported SGMII PHY product. 868 */ 869 if (phy_id == M88_VENDOR) 870 break; 871 } else { 872 hw_dbg("PHY address %u was unreadable\n", phy->addr); 873 } 874 } 875 876 /* A valid PHY type couldn't be found. */ 877 if (phy->addr == 8) { 878 phy->addr = 0; 879 ret_val = -E1000_ERR_PHY; 880 goto out; 881 } else { 882 ret_val = igb_get_phy_id(hw); 883 } 884 885 /* restore previous sfp cage power state */ 886 wr32(E1000_CTRL_EXT, ctrl_ext); 887 888 out: 889 return ret_val; 890 } 891 892 /** 893 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset 894 * @hw: pointer to the HW structure 895 * 896 * Resets the PHY using the serial gigabit media independent interface. 897 **/ 898 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 899 { 900 s32 ret_val; 901 902 /* This isn't a true "hard" reset, but is the only reset 903 * available to us at this time. 904 */ 905 906 hw_dbg("Soft resetting SGMII attached PHY...\n"); 907 908 /* SFP documentation requires the following to configure the SPF module 909 * to work on SGMII. No further documentation is given. 910 */ 911 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 912 if (ret_val) 913 goto out; 914 915 ret_val = igb_phy_sw_reset(hw); 916 917 out: 918 return ret_val; 919 } 920 921 /** 922 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 923 * @hw: pointer to the HW structure 924 * @active: true to enable LPLU, false to disable 925 * 926 * Sets the LPLU D0 state according to the active flag. When 927 * activating LPLU this function also disables smart speed 928 * and vice versa. LPLU will not be activated unless the 929 * device autonegotiation advertisement meets standards of 930 * either 10 or 10/100 or 10/100/1000 at all duplexes. 931 * This is a function pointer entry point only called by 932 * PHY setup routines. 933 **/ 934 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 935 { 936 struct e1000_phy_info *phy = &hw->phy; 937 s32 ret_val; 938 u16 data; 939 940 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 941 if (ret_val) 942 goto out; 943 944 if (active) { 945 data |= IGP02E1000_PM_D0_LPLU; 946 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 947 data); 948 if (ret_val) 949 goto out; 950 951 /* When LPLU is enabled, we should disable SmartSpeed */ 952 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 953 &data); 954 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 955 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 956 data); 957 if (ret_val) 958 goto out; 959 } else { 960 data &= ~IGP02E1000_PM_D0_LPLU; 961 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 962 data); 963 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 964 * during Dx states where the power conservation is most 965 * important. During driver activity we should enable 966 * SmartSpeed, so performance is maintained. 967 */ 968 if (phy->smart_speed == e1000_smart_speed_on) { 969 ret_val = phy->ops.read_reg(hw, 970 IGP01E1000_PHY_PORT_CONFIG, &data); 971 if (ret_val) 972 goto out; 973 974 data |= IGP01E1000_PSCFR_SMART_SPEED; 975 ret_val = phy->ops.write_reg(hw, 976 IGP01E1000_PHY_PORT_CONFIG, data); 977 if (ret_val) 978 goto out; 979 } else if (phy->smart_speed == e1000_smart_speed_off) { 980 ret_val = phy->ops.read_reg(hw, 981 IGP01E1000_PHY_PORT_CONFIG, &data); 982 if (ret_val) 983 goto out; 984 985 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 986 ret_val = phy->ops.write_reg(hw, 987 IGP01E1000_PHY_PORT_CONFIG, data); 988 if (ret_val) 989 goto out; 990 } 991 } 992 993 out: 994 return ret_val; 995 } 996 997 /** 998 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state 999 * @hw: pointer to the HW structure 1000 * @active: true to enable LPLU, false to disable 1001 * 1002 * Sets the LPLU D0 state according to the active flag. When 1003 * activating LPLU this function also disables smart speed 1004 * and vice versa. LPLU will not be activated unless the 1005 * device autonegotiation advertisement meets standards of 1006 * either 10 or 10/100 or 10/100/1000 at all duplexes. 1007 * This is a function pointer entry point only called by 1008 * PHY setup routines. 1009 **/ 1010 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) 1011 { 1012 struct e1000_phy_info *phy = &hw->phy; 1013 u16 data; 1014 1015 data = rd32(E1000_82580_PHY_POWER_MGMT); 1016 1017 if (active) { 1018 data |= E1000_82580_PM_D0_LPLU; 1019 1020 /* When LPLU is enabled, we should disable SmartSpeed */ 1021 data &= ~E1000_82580_PM_SPD; 1022 } else { 1023 data &= ~E1000_82580_PM_D0_LPLU; 1024 1025 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1026 * during Dx states where the power conservation is most 1027 * important. During driver activity we should enable 1028 * SmartSpeed, so performance is maintained. 1029 */ 1030 if (phy->smart_speed == e1000_smart_speed_on) 1031 data |= E1000_82580_PM_SPD; 1032 else if (phy->smart_speed == e1000_smart_speed_off) 1033 data &= ~E1000_82580_PM_SPD; } 1034 1035 wr32(E1000_82580_PHY_POWER_MGMT, data); 1036 return 0; 1037 } 1038 1039 /** 1040 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3 1041 * @hw: pointer to the HW structure 1042 * @active: boolean used to enable/disable lplu 1043 * 1044 * Success returns 0, Failure returns 1 1045 * 1046 * The low power link up (lplu) state is set to the power management level D3 1047 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1048 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1049 * is used during Dx states where the power conservation is most important. 1050 * During driver activity, SmartSpeed should be enabled so performance is 1051 * maintained. 1052 **/ 1053 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) 1054 { 1055 struct e1000_phy_info *phy = &hw->phy; 1056 u16 data; 1057 1058 data = rd32(E1000_82580_PHY_POWER_MGMT); 1059 1060 if (!active) { 1061 data &= ~E1000_82580_PM_D3_LPLU; 1062 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1063 * during Dx states where the power conservation is most 1064 * important. During driver activity we should enable 1065 * SmartSpeed, so performance is maintained. 1066 */ 1067 if (phy->smart_speed == e1000_smart_speed_on) 1068 data |= E1000_82580_PM_SPD; 1069 else if (phy->smart_speed == e1000_smart_speed_off) 1070 data &= ~E1000_82580_PM_SPD; 1071 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1072 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1073 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1074 data |= E1000_82580_PM_D3_LPLU; 1075 /* When LPLU is enabled, we should disable SmartSpeed */ 1076 data &= ~E1000_82580_PM_SPD; 1077 } 1078 1079 wr32(E1000_82580_PHY_POWER_MGMT, data); 1080 return 0; 1081 } 1082 1083 /** 1084 * igb_acquire_nvm_82575 - Request for access to EEPROM 1085 * @hw: pointer to the HW structure 1086 * 1087 * Acquire the necessary semaphores for exclusive access to the EEPROM. 1088 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 1089 * Return successful if access grant bit set, else clear the request for 1090 * EEPROM access and return -E1000_ERR_NVM (-1). 1091 **/ 1092 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw) 1093 { 1094 s32 ret_val; 1095 1096 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM); 1097 if (ret_val) 1098 goto out; 1099 1100 ret_val = igb_acquire_nvm(hw); 1101 1102 if (ret_val) 1103 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM); 1104 1105 out: 1106 return ret_val; 1107 } 1108 1109 /** 1110 * igb_release_nvm_82575 - Release exclusive access to EEPROM 1111 * @hw: pointer to the HW structure 1112 * 1113 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 1114 * then release the semaphores acquired. 1115 **/ 1116 static void igb_release_nvm_82575(struct e1000_hw *hw) 1117 { 1118 igb_release_nvm(hw); 1119 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM); 1120 } 1121 1122 /** 1123 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 1124 * @hw: pointer to the HW structure 1125 * @mask: specifies which semaphore to acquire 1126 * 1127 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 1128 * will also specify which port we're acquiring the lock for. 1129 **/ 1130 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1131 { 1132 u32 swfw_sync; 1133 u32 swmask = mask; 1134 u32 fwmask = mask << 16; 1135 s32 ret_val = 0; 1136 s32 i = 0, timeout = 200; 1137 1138 while (i < timeout) { 1139 if (igb_get_hw_semaphore(hw)) { 1140 ret_val = -E1000_ERR_SWFW_SYNC; 1141 goto out; 1142 } 1143 1144 swfw_sync = rd32(E1000_SW_FW_SYNC); 1145 if (!(swfw_sync & (fwmask | swmask))) 1146 break; 1147 1148 /* Firmware currently using resource (fwmask) 1149 * or other software thread using resource (swmask) 1150 */ 1151 igb_put_hw_semaphore(hw); 1152 mdelay(5); 1153 i++; 1154 } 1155 1156 if (i == timeout) { 1157 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1158 ret_val = -E1000_ERR_SWFW_SYNC; 1159 goto out; 1160 } 1161 1162 swfw_sync |= swmask; 1163 wr32(E1000_SW_FW_SYNC, swfw_sync); 1164 1165 igb_put_hw_semaphore(hw); 1166 1167 out: 1168 return ret_val; 1169 } 1170 1171 /** 1172 * igb_release_swfw_sync_82575 - Release SW/FW semaphore 1173 * @hw: pointer to the HW structure 1174 * @mask: specifies which semaphore to acquire 1175 * 1176 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 1177 * will also specify which port we're releasing the lock for. 1178 **/ 1179 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1180 { 1181 u32 swfw_sync; 1182 1183 while (igb_get_hw_semaphore(hw) != 0) 1184 ; /* Empty */ 1185 1186 swfw_sync = rd32(E1000_SW_FW_SYNC); 1187 swfw_sync &= ~mask; 1188 wr32(E1000_SW_FW_SYNC, swfw_sync); 1189 1190 igb_put_hw_semaphore(hw); 1191 } 1192 1193 /** 1194 * igb_get_cfg_done_82575 - Read config done bit 1195 * @hw: pointer to the HW structure 1196 * 1197 * Read the management control register for the config done bit for 1198 * completion status. NOTE: silicon which is EEPROM-less will fail trying 1199 * to read the config done bit, so an error is *ONLY* logged and returns 1200 * 0. If we were to return with error, EEPROM-less silicon 1201 * would not be able to be reset or change link. 1202 **/ 1203 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw) 1204 { 1205 s32 timeout = PHY_CFG_TIMEOUT; 1206 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 1207 1208 if (hw->bus.func == 1) 1209 mask = E1000_NVM_CFG_DONE_PORT_1; 1210 else if (hw->bus.func == E1000_FUNC_2) 1211 mask = E1000_NVM_CFG_DONE_PORT_2; 1212 else if (hw->bus.func == E1000_FUNC_3) 1213 mask = E1000_NVM_CFG_DONE_PORT_3; 1214 1215 while (timeout) { 1216 if (rd32(E1000_EEMNGCTL) & mask) 1217 break; 1218 usleep_range(1000, 2000); 1219 timeout--; 1220 } 1221 if (!timeout) 1222 hw_dbg("MNG configuration cycle has not completed.\n"); 1223 1224 /* If EEPROM is not marked present, init the PHY manually */ 1225 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) && 1226 (hw->phy.type == e1000_phy_igp_3)) 1227 igb_phy_init_script_igp3(hw); 1228 1229 return 0; 1230 } 1231 1232 /** 1233 * igb_get_link_up_info_82575 - Get link speed/duplex info 1234 * @hw: pointer to the HW structure 1235 * @speed: stores the current speed 1236 * @duplex: stores the current duplex 1237 * 1238 * This is a wrapper function, if using the serial gigabit media independent 1239 * interface, use PCS to retrieve the link speed and duplex information. 1240 * Otherwise, use the generic function to get the link speed and duplex info. 1241 **/ 1242 static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 1243 u16 *duplex) 1244 { 1245 s32 ret_val; 1246 1247 if (hw->phy.media_type != e1000_media_type_copper) 1248 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed, 1249 duplex); 1250 else 1251 ret_val = igb_get_speed_and_duplex_copper(hw, speed, 1252 duplex); 1253 1254 return ret_val; 1255 } 1256 1257 /** 1258 * igb_check_for_link_82575 - Check for link 1259 * @hw: pointer to the HW structure 1260 * 1261 * If sgmii is enabled, then use the pcs register to determine link, otherwise 1262 * use the generic interface for determining link. 1263 **/ 1264 static s32 igb_check_for_link_82575(struct e1000_hw *hw) 1265 { 1266 s32 ret_val; 1267 u16 speed, duplex; 1268 1269 if (hw->phy.media_type != e1000_media_type_copper) { 1270 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, 1271 &duplex); 1272 /* Use this flag to determine if link needs to be checked or 1273 * not. If we have link clear the flag so that we do not 1274 * continue to check for link. 1275 */ 1276 hw->mac.get_link_status = !hw->mac.serdes_has_link; 1277 1278 /* Configure Flow Control now that Auto-Neg has completed. 1279 * First, we need to restore the desired flow control 1280 * settings because we may have had to re-autoneg with a 1281 * different link partner. 1282 */ 1283 ret_val = igb_config_fc_after_link_up(hw); 1284 if (ret_val) 1285 hw_dbg("Error configuring flow control\n"); 1286 } else { 1287 ret_val = igb_check_for_copper_link(hw); 1288 } 1289 1290 return ret_val; 1291 } 1292 1293 /** 1294 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown 1295 * @hw: pointer to the HW structure 1296 **/ 1297 void igb_power_up_serdes_link_82575(struct e1000_hw *hw) 1298 { 1299 u32 reg; 1300 1301 1302 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1303 !igb_sgmii_active_82575(hw)) 1304 return; 1305 1306 /* Enable PCS to turn on link */ 1307 reg = rd32(E1000_PCS_CFG0); 1308 reg |= E1000_PCS_CFG_PCS_EN; 1309 wr32(E1000_PCS_CFG0, reg); 1310 1311 /* Power up the laser */ 1312 reg = rd32(E1000_CTRL_EXT); 1313 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1314 wr32(E1000_CTRL_EXT, reg); 1315 1316 /* flush the write to verify completion */ 1317 wrfl(); 1318 usleep_range(1000, 2000); 1319 } 1320 1321 /** 1322 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 1323 * @hw: pointer to the HW structure 1324 * @speed: stores the current speed 1325 * @duplex: stores the current duplex 1326 * 1327 * Using the physical coding sub-layer (PCS), retrieve the current speed and 1328 * duplex, then store the values in the pointers provided. 1329 **/ 1330 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, 1331 u16 *duplex) 1332 { 1333 struct e1000_mac_info *mac = &hw->mac; 1334 u32 pcs, status; 1335 1336 /* Set up defaults for the return values of this function */ 1337 mac->serdes_has_link = false; 1338 *speed = 0; 1339 *duplex = 0; 1340 1341 /* Read the PCS Status register for link state. For non-copper mode, 1342 * the status register is not accurate. The PCS status register is 1343 * used instead. 1344 */ 1345 pcs = rd32(E1000_PCS_LSTAT); 1346 1347 /* The link up bit determines when link is up on autoneg. The sync ok 1348 * gets set once both sides sync up and agree upon link. Stable link 1349 * can be determined by checking for both link up and link sync ok 1350 */ 1351 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 1352 mac->serdes_has_link = true; 1353 1354 /* Detect and store PCS speed */ 1355 if (pcs & E1000_PCS_LSTS_SPEED_1000) 1356 *speed = SPEED_1000; 1357 else if (pcs & E1000_PCS_LSTS_SPEED_100) 1358 *speed = SPEED_100; 1359 else 1360 *speed = SPEED_10; 1361 1362 /* Detect and store PCS duplex */ 1363 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) 1364 *duplex = FULL_DUPLEX; 1365 else 1366 *duplex = HALF_DUPLEX; 1367 1368 /* Check if it is an I354 2.5Gb backplane connection. */ 1369 if (mac->type == e1000_i354) { 1370 status = rd32(E1000_STATUS); 1371 if ((status & E1000_STATUS_2P5_SKU) && 1372 !(status & E1000_STATUS_2P5_SKU_OVER)) { 1373 *speed = SPEED_2500; 1374 *duplex = FULL_DUPLEX; 1375 hw_dbg("2500 Mbs, "); 1376 hw_dbg("Full Duplex\n"); 1377 } 1378 } 1379 1380 } 1381 1382 return 0; 1383 } 1384 1385 /** 1386 * igb_shutdown_serdes_link_82575 - Remove link during power down 1387 * @hw: pointer to the HW structure 1388 * 1389 * In the case of fiber serdes, shut down optics and PCS on driver unload 1390 * when management pass thru is not enabled. 1391 **/ 1392 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw) 1393 { 1394 u32 reg; 1395 1396 if (hw->phy.media_type != e1000_media_type_internal_serdes && 1397 igb_sgmii_active_82575(hw)) 1398 return; 1399 1400 if (!igb_enable_mng_pass_thru(hw)) { 1401 /* Disable PCS to turn off link */ 1402 reg = rd32(E1000_PCS_CFG0); 1403 reg &= ~E1000_PCS_CFG_PCS_EN; 1404 wr32(E1000_PCS_CFG0, reg); 1405 1406 /* shutdown the laser */ 1407 reg = rd32(E1000_CTRL_EXT); 1408 reg |= E1000_CTRL_EXT_SDP3_DATA; 1409 wr32(E1000_CTRL_EXT, reg); 1410 1411 /* flush the write to verify completion */ 1412 wrfl(); 1413 usleep_range(1000, 2000); 1414 } 1415 } 1416 1417 /** 1418 * igb_reset_hw_82575 - Reset hardware 1419 * @hw: pointer to the HW structure 1420 * 1421 * This resets the hardware into a known state. This is a 1422 * function pointer entry point called by the api module. 1423 **/ 1424 static s32 igb_reset_hw_82575(struct e1000_hw *hw) 1425 { 1426 u32 ctrl; 1427 s32 ret_val; 1428 1429 /* Prevent the PCI-E bus from sticking if there is no TLP connection 1430 * on the last TLP read/write transaction when MAC is reset. 1431 */ 1432 ret_val = igb_disable_pcie_master(hw); 1433 if (ret_val) 1434 hw_dbg("PCI-E Master disable polling has failed.\n"); 1435 1436 /* set the completion timeout for interface */ 1437 ret_val = igb_set_pcie_completion_timeout(hw); 1438 if (ret_val) 1439 hw_dbg("PCI-E Set completion timeout has failed.\n"); 1440 1441 hw_dbg("Masking off all interrupts\n"); 1442 wr32(E1000_IMC, 0xffffffff); 1443 1444 wr32(E1000_RCTL, 0); 1445 wr32(E1000_TCTL, E1000_TCTL_PSP); 1446 wrfl(); 1447 1448 usleep_range(10000, 20000); 1449 1450 ctrl = rd32(E1000_CTRL); 1451 1452 hw_dbg("Issuing a global reset to MAC\n"); 1453 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST); 1454 1455 ret_val = igb_get_auto_rd_done(hw); 1456 if (ret_val) { 1457 /* When auto config read does not complete, do not 1458 * return with an error. This can happen in situations 1459 * where there is no eeprom and prevents getting link. 1460 */ 1461 hw_dbg("Auto Read Done did not complete\n"); 1462 } 1463 1464 /* If EEPROM is not present, run manual init scripts */ 1465 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) 1466 igb_reset_init_script_82575(hw); 1467 1468 /* Clear any pending interrupt events. */ 1469 wr32(E1000_IMC, 0xffffffff); 1470 rd32(E1000_ICR); 1471 1472 /* Install any alternate MAC address into RAR0 */ 1473 ret_val = igb_check_alt_mac_addr(hw); 1474 1475 return ret_val; 1476 } 1477 1478 /** 1479 * igb_init_hw_82575 - Initialize hardware 1480 * @hw: pointer to the HW structure 1481 * 1482 * This inits the hardware readying it for operation. 1483 **/ 1484 static s32 igb_init_hw_82575(struct e1000_hw *hw) 1485 { 1486 struct e1000_mac_info *mac = &hw->mac; 1487 s32 ret_val; 1488 u16 i, rar_count = mac->rar_entry_count; 1489 1490 if ((hw->mac.type >= e1000_i210) && 1491 !(igb_get_flash_presence_i210(hw))) { 1492 ret_val = igb_pll_workaround_i210(hw); 1493 if (ret_val) 1494 return ret_val; 1495 } 1496 1497 /* Initialize identification LED */ 1498 ret_val = igb_id_led_init(hw); 1499 if (ret_val) { 1500 hw_dbg("Error initializing identification LED\n"); 1501 /* This is not fatal and we should not stop init due to this */ 1502 } 1503 1504 /* Disabling VLAN filtering */ 1505 hw_dbg("Initializing the IEEE VLAN\n"); 1506 if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354)) 1507 igb_clear_vfta_i350(hw); 1508 else 1509 igb_clear_vfta(hw); 1510 1511 /* Setup the receive address */ 1512 igb_init_rx_addrs(hw, rar_count); 1513 1514 /* Zero out the Multicast HASH table */ 1515 hw_dbg("Zeroing the MTA\n"); 1516 for (i = 0; i < mac->mta_reg_count; i++) 1517 array_wr32(E1000_MTA, i, 0); 1518 1519 /* Zero out the Unicast HASH table */ 1520 hw_dbg("Zeroing the UTA\n"); 1521 for (i = 0; i < mac->uta_reg_count; i++) 1522 array_wr32(E1000_UTA, i, 0); 1523 1524 /* Setup link and flow control */ 1525 ret_val = igb_setup_link(hw); 1526 1527 /* Clear all of the statistics registers (clear on read). It is 1528 * important that we do this after we have tried to establish link 1529 * because the symbol error count will increment wildly if there 1530 * is no link. 1531 */ 1532 igb_clear_hw_cntrs_82575(hw); 1533 return ret_val; 1534 } 1535 1536 /** 1537 * igb_setup_copper_link_82575 - Configure copper link settings 1538 * @hw: pointer to the HW structure 1539 * 1540 * Configures the link for auto-neg or forced speed and duplex. Then we check 1541 * for link, once link is established calls to configure collision distance 1542 * and flow control are called. 1543 **/ 1544 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw) 1545 { 1546 u32 ctrl; 1547 s32 ret_val; 1548 u32 phpm_reg; 1549 1550 ctrl = rd32(E1000_CTRL); 1551 ctrl |= E1000_CTRL_SLU; 1552 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1553 wr32(E1000_CTRL, ctrl); 1554 1555 /* Clear Go Link Disconnect bit on supported devices */ 1556 switch (hw->mac.type) { 1557 case e1000_82580: 1558 case e1000_i350: 1559 case e1000_i210: 1560 case e1000_i211: 1561 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT); 1562 phpm_reg &= ~E1000_82580_PM_GO_LINKD; 1563 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg); 1564 break; 1565 default: 1566 break; 1567 } 1568 1569 ret_val = igb_setup_serdes_link_82575(hw); 1570 if (ret_val) 1571 goto out; 1572 1573 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) { 1574 /* allow time for SFP cage time to power up phy */ 1575 msleep(300); 1576 1577 ret_val = hw->phy.ops.reset(hw); 1578 if (ret_val) { 1579 hw_dbg("Error resetting the PHY.\n"); 1580 goto out; 1581 } 1582 } 1583 switch (hw->phy.type) { 1584 case e1000_phy_i210: 1585 case e1000_phy_m88: 1586 switch (hw->phy.id) { 1587 case I347AT4_E_PHY_ID: 1588 case M88E1112_E_PHY_ID: 1589 case M88E1543_E_PHY_ID: 1590 case I210_I_PHY_ID: 1591 ret_val = igb_copper_link_setup_m88_gen2(hw); 1592 break; 1593 default: 1594 ret_val = igb_copper_link_setup_m88(hw); 1595 break; 1596 } 1597 break; 1598 case e1000_phy_igp_3: 1599 ret_val = igb_copper_link_setup_igp(hw); 1600 break; 1601 case e1000_phy_82580: 1602 ret_val = igb_copper_link_setup_82580(hw); 1603 break; 1604 default: 1605 ret_val = -E1000_ERR_PHY; 1606 break; 1607 } 1608 1609 if (ret_val) 1610 goto out; 1611 1612 ret_val = igb_setup_copper_link(hw); 1613 out: 1614 return ret_val; 1615 } 1616 1617 /** 1618 * igb_setup_serdes_link_82575 - Setup link for serdes 1619 * @hw: pointer to the HW structure 1620 * 1621 * Configure the physical coding sub-layer (PCS) link. The PCS link is 1622 * used on copper connections where the serialized gigabit media independent 1623 * interface (sgmii), or serdes fiber is being used. Configures the link 1624 * for auto-negotiation or forces speed/duplex. 1625 **/ 1626 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw) 1627 { 1628 u32 ctrl_ext, ctrl_reg, reg, anadv_reg; 1629 bool pcs_autoneg; 1630 s32 ret_val = 0; 1631 u16 data; 1632 1633 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1634 !igb_sgmii_active_82575(hw)) 1635 return ret_val; 1636 1637 1638 /* On the 82575, SerDes loopback mode persists until it is 1639 * explicitly turned off or a power cycle is performed. A read to 1640 * the register does not indicate its status. Therefore, we ensure 1641 * loopback mode is disabled during initialization. 1642 */ 1643 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1644 1645 /* power on the sfp cage if present and turn on I2C */ 1646 ctrl_ext = rd32(E1000_CTRL_EXT); 1647 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1648 ctrl_ext |= E1000_CTRL_I2C_ENA; 1649 wr32(E1000_CTRL_EXT, ctrl_ext); 1650 1651 ctrl_reg = rd32(E1000_CTRL); 1652 ctrl_reg |= E1000_CTRL_SLU; 1653 1654 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { 1655 /* set both sw defined pins */ 1656 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1657 1658 /* Set switch control to serdes energy detect */ 1659 reg = rd32(E1000_CONNSW); 1660 reg |= E1000_CONNSW_ENRGSRC; 1661 wr32(E1000_CONNSW, reg); 1662 } 1663 1664 reg = rd32(E1000_PCS_LCTL); 1665 1666 /* default pcs_autoneg to the same setting as mac autoneg */ 1667 pcs_autoneg = hw->mac.autoneg; 1668 1669 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1670 case E1000_CTRL_EXT_LINK_MODE_SGMII: 1671 /* sgmii mode lets the phy handle forcing speed/duplex */ 1672 pcs_autoneg = true; 1673 /* autoneg time out should be disabled for SGMII mode */ 1674 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1675 break; 1676 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1677 /* disable PCS autoneg and support parallel detect only */ 1678 pcs_autoneg = false; 1679 default: 1680 if (hw->mac.type == e1000_82575 || 1681 hw->mac.type == e1000_82576) { 1682 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data); 1683 if (ret_val) { 1684 hw_dbg(KERN_DEBUG "NVM Read Error\n\n"); 1685 return ret_val; 1686 } 1687 1688 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT) 1689 pcs_autoneg = false; 1690 } 1691 1692 /* non-SGMII modes only supports a speed of 1000/Full for the 1693 * link so it is best to just force the MAC and let the pcs 1694 * link either autoneg or be forced to 1000/Full 1695 */ 1696 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | 1697 E1000_CTRL_FD | E1000_CTRL_FRCDPX; 1698 1699 /* set speed of 1000/Full if speed/duplex is forced */ 1700 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1701 break; 1702 } 1703 1704 wr32(E1000_CTRL, ctrl_reg); 1705 1706 /* New SerDes mode allows for forcing speed or autonegotiating speed 1707 * at 1gb. Autoneg should be default set by most drivers. This is the 1708 * mode that will be compatible with older link partners and switches. 1709 * However, both are supported by the hardware and some drivers/tools. 1710 */ 1711 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1712 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1713 1714 if (pcs_autoneg) { 1715 /* Set PCS register for autoneg */ 1716 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1717 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1718 1719 /* Disable force flow control for autoneg */ 1720 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL; 1721 1722 /* Configure flow control advertisement for autoneg */ 1723 anadv_reg = rd32(E1000_PCS_ANADV); 1724 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE); 1725 switch (hw->fc.requested_mode) { 1726 case e1000_fc_full: 1727 case e1000_fc_rx_pause: 1728 anadv_reg |= E1000_TXCW_ASM_DIR; 1729 anadv_reg |= E1000_TXCW_PAUSE; 1730 break; 1731 case e1000_fc_tx_pause: 1732 anadv_reg |= E1000_TXCW_ASM_DIR; 1733 break; 1734 default: 1735 break; 1736 } 1737 wr32(E1000_PCS_ANADV, anadv_reg); 1738 1739 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); 1740 } else { 1741 /* Set PCS register for forced link */ 1742 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1743 1744 /* Force flow control for forced link */ 1745 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1746 1747 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); 1748 } 1749 1750 wr32(E1000_PCS_LCTL, reg); 1751 1752 if (!pcs_autoneg && !igb_sgmii_active_82575(hw)) 1753 igb_force_mac_fc(hw); 1754 1755 return ret_val; 1756 } 1757 1758 /** 1759 * igb_sgmii_active_82575 - Return sgmii state 1760 * @hw: pointer to the HW structure 1761 * 1762 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1763 * which can be enabled for use in the embedded applications. Simply 1764 * return the current state of the sgmii interface. 1765 **/ 1766 static bool igb_sgmii_active_82575(struct e1000_hw *hw) 1767 { 1768 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1769 return dev_spec->sgmii_active; 1770 } 1771 1772 /** 1773 * igb_reset_init_script_82575 - Inits HW defaults after reset 1774 * @hw: pointer to the HW structure 1775 * 1776 * Inits recommended HW defaults after a reset when there is no EEPROM 1777 * detected. This is only for the 82575. 1778 **/ 1779 static s32 igb_reset_init_script_82575(struct e1000_hw *hw) 1780 { 1781 if (hw->mac.type == e1000_82575) { 1782 hw_dbg("Running reset init script for 82575\n"); 1783 /* SerDes configuration via SERDESCTRL */ 1784 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C); 1785 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78); 1786 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23); 1787 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15); 1788 1789 /* CCM configuration via CCMCTL register */ 1790 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00); 1791 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00); 1792 1793 /* PCIe lanes configuration */ 1794 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC); 1795 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF); 1796 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05); 1797 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81); 1798 1799 /* PCIe PLL Configuration */ 1800 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47); 1801 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00); 1802 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00); 1803 } 1804 1805 return 0; 1806 } 1807 1808 /** 1809 * igb_read_mac_addr_82575 - Read device MAC address 1810 * @hw: pointer to the HW structure 1811 **/ 1812 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw) 1813 { 1814 s32 ret_val = 0; 1815 1816 /* If there's an alternate MAC address place it in RAR0 1817 * so that it will override the Si installed default perm 1818 * address. 1819 */ 1820 ret_val = igb_check_alt_mac_addr(hw); 1821 if (ret_val) 1822 goto out; 1823 1824 ret_val = igb_read_mac_addr(hw); 1825 1826 out: 1827 return ret_val; 1828 } 1829 1830 /** 1831 * igb_power_down_phy_copper_82575 - Remove link during PHY power down 1832 * @hw: pointer to the HW structure 1833 * 1834 * In the case of a PHY power down to save power, or to turn off link during a 1835 * driver unload, or wake on lan is not enabled, remove the link. 1836 **/ 1837 void igb_power_down_phy_copper_82575(struct e1000_hw *hw) 1838 { 1839 /* If the management interface is not enabled, then power down */ 1840 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw))) 1841 igb_power_down_phy_copper(hw); 1842 } 1843 1844 /** 1845 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters 1846 * @hw: pointer to the HW structure 1847 * 1848 * Clears the hardware counters by reading the counter registers. 1849 **/ 1850 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw) 1851 { 1852 igb_clear_hw_cntrs_base(hw); 1853 1854 rd32(E1000_PRC64); 1855 rd32(E1000_PRC127); 1856 rd32(E1000_PRC255); 1857 rd32(E1000_PRC511); 1858 rd32(E1000_PRC1023); 1859 rd32(E1000_PRC1522); 1860 rd32(E1000_PTC64); 1861 rd32(E1000_PTC127); 1862 rd32(E1000_PTC255); 1863 rd32(E1000_PTC511); 1864 rd32(E1000_PTC1023); 1865 rd32(E1000_PTC1522); 1866 1867 rd32(E1000_ALGNERRC); 1868 rd32(E1000_RXERRC); 1869 rd32(E1000_TNCRS); 1870 rd32(E1000_CEXTERR); 1871 rd32(E1000_TSCTC); 1872 rd32(E1000_TSCTFC); 1873 1874 rd32(E1000_MGTPRC); 1875 rd32(E1000_MGTPDC); 1876 rd32(E1000_MGTPTC); 1877 1878 rd32(E1000_IAC); 1879 rd32(E1000_ICRXOC); 1880 1881 rd32(E1000_ICRXPTC); 1882 rd32(E1000_ICRXATC); 1883 rd32(E1000_ICTXPTC); 1884 rd32(E1000_ICTXATC); 1885 rd32(E1000_ICTXQEC); 1886 rd32(E1000_ICTXQMTC); 1887 rd32(E1000_ICRXDMTC); 1888 1889 rd32(E1000_CBTMPC); 1890 rd32(E1000_HTDPMC); 1891 rd32(E1000_CBRMPC); 1892 rd32(E1000_RPTHC); 1893 rd32(E1000_HGPTC); 1894 rd32(E1000_HTCBDPC); 1895 rd32(E1000_HGORCL); 1896 rd32(E1000_HGORCH); 1897 rd32(E1000_HGOTCL); 1898 rd32(E1000_HGOTCH); 1899 rd32(E1000_LENERRS); 1900 1901 /* This register should not be read in copper configurations */ 1902 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1903 igb_sgmii_active_82575(hw)) 1904 rd32(E1000_SCVPC); 1905 } 1906 1907 /** 1908 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable 1909 * @hw: pointer to the HW structure 1910 * 1911 * After rx enable if manageability is enabled then there is likely some 1912 * bad data at the start of the fifo and possibly in the DMA fifo. This 1913 * function clears the fifos and flushes any packets that came in as rx was 1914 * being enabled. 1915 **/ 1916 void igb_rx_fifo_flush_82575(struct e1000_hw *hw) 1917 { 1918 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 1919 int i, ms_wait; 1920 1921 /* disable IPv6 options as per hardware errata */ 1922 rfctl = rd32(E1000_RFCTL); 1923 rfctl |= E1000_RFCTL_IPV6_EX_DIS; 1924 wr32(E1000_RFCTL, rfctl); 1925 1926 if (hw->mac.type != e1000_82575 || 1927 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 1928 return; 1929 1930 /* Disable all RX queues */ 1931 for (i = 0; i < 4; i++) { 1932 rxdctl[i] = rd32(E1000_RXDCTL(i)); 1933 wr32(E1000_RXDCTL(i), 1934 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 1935 } 1936 /* Poll all queues to verify they have shut down */ 1937 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 1938 usleep_range(1000, 2000); 1939 rx_enabled = 0; 1940 for (i = 0; i < 4; i++) 1941 rx_enabled |= rd32(E1000_RXDCTL(i)); 1942 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 1943 break; 1944 } 1945 1946 if (ms_wait == 10) 1947 hw_dbg("Queue disable timed out after 10ms\n"); 1948 1949 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 1950 * incoming packets are rejected. Set enable and wait 2ms so that 1951 * any packet that was coming in as RCTL.EN was set is flushed 1952 */ 1953 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 1954 1955 rlpml = rd32(E1000_RLPML); 1956 wr32(E1000_RLPML, 0); 1957 1958 rctl = rd32(E1000_RCTL); 1959 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 1960 temp_rctl |= E1000_RCTL_LPE; 1961 1962 wr32(E1000_RCTL, temp_rctl); 1963 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN); 1964 wrfl(); 1965 usleep_range(2000, 3000); 1966 1967 /* Enable RX queues that were previously enabled and restore our 1968 * previous state 1969 */ 1970 for (i = 0; i < 4; i++) 1971 wr32(E1000_RXDCTL(i), rxdctl[i]); 1972 wr32(E1000_RCTL, rctl); 1973 wrfl(); 1974 1975 wr32(E1000_RLPML, rlpml); 1976 wr32(E1000_RFCTL, rfctl); 1977 1978 /* Flush receive errors generated by workaround */ 1979 rd32(E1000_ROC); 1980 rd32(E1000_RNBC); 1981 rd32(E1000_MPC); 1982 } 1983 1984 /** 1985 * igb_set_pcie_completion_timeout - set pci-e completion timeout 1986 * @hw: pointer to the HW structure 1987 * 1988 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 1989 * however the hardware default for these parts is 500us to 1ms which is less 1990 * than the 10ms recommended by the pci-e spec. To address this we need to 1991 * increase the value to either 10ms to 200ms for capability version 1 config, 1992 * or 16ms to 55ms for version 2. 1993 **/ 1994 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw) 1995 { 1996 u32 gcr = rd32(E1000_GCR); 1997 s32 ret_val = 0; 1998 u16 pcie_devctl2; 1999 2000 /* only take action if timeout value is defaulted to 0 */ 2001 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 2002 goto out; 2003 2004 /* if capabilities version is type 1 we can write the 2005 * timeout of 10ms to 200ms through the GCR register 2006 */ 2007 if (!(gcr & E1000_GCR_CAP_VER2)) { 2008 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 2009 goto out; 2010 } 2011 2012 /* for version 2 capabilities we need to write the config space 2013 * directly in order to set the completion timeout value for 2014 * 16ms to 55ms 2015 */ 2016 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2017 &pcie_devctl2); 2018 if (ret_val) 2019 goto out; 2020 2021 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 2022 2023 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2024 &pcie_devctl2); 2025 out: 2026 /* disable completion timeout resend */ 2027 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 2028 2029 wr32(E1000_GCR, gcr); 2030 return ret_val; 2031 } 2032 2033 /** 2034 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing 2035 * @hw: pointer to the hardware struct 2036 * @enable: state to enter, either enabled or disabled 2037 * @pf: Physical Function pool - do not set anti-spoofing for the PF 2038 * 2039 * enables/disables L2 switch anti-spoofing functionality. 2040 **/ 2041 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) 2042 { 2043 u32 reg_val, reg_offset; 2044 2045 switch (hw->mac.type) { 2046 case e1000_82576: 2047 reg_offset = E1000_DTXSWC; 2048 break; 2049 case e1000_i350: 2050 case e1000_i354: 2051 reg_offset = E1000_TXSWC; 2052 break; 2053 default: 2054 return; 2055 } 2056 2057 reg_val = rd32(reg_offset); 2058 if (enable) { 2059 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK | 2060 E1000_DTXSWC_VLAN_SPOOF_MASK); 2061 /* The PF can spoof - it has to in order to 2062 * support emulation mode NICs 2063 */ 2064 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS)); 2065 } else { 2066 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | 2067 E1000_DTXSWC_VLAN_SPOOF_MASK); 2068 } 2069 wr32(reg_offset, reg_val); 2070 } 2071 2072 /** 2073 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback 2074 * @hw: pointer to the hardware struct 2075 * @enable: state to enter, either enabled or disabled 2076 * 2077 * enables/disables L2 switch loopback functionality. 2078 **/ 2079 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 2080 { 2081 u32 dtxswc; 2082 2083 switch (hw->mac.type) { 2084 case e1000_82576: 2085 dtxswc = rd32(E1000_DTXSWC); 2086 if (enable) 2087 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2088 else 2089 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2090 wr32(E1000_DTXSWC, dtxswc); 2091 break; 2092 case e1000_i354: 2093 case e1000_i350: 2094 dtxswc = rd32(E1000_TXSWC); 2095 if (enable) 2096 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2097 else 2098 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2099 wr32(E1000_TXSWC, dtxswc); 2100 break; 2101 default: 2102 /* Currently no other hardware supports loopback */ 2103 break; 2104 } 2105 2106 } 2107 2108 /** 2109 * igb_vmdq_set_replication_pf - enable or disable vmdq replication 2110 * @hw: pointer to the hardware struct 2111 * @enable: state to enter, either enabled or disabled 2112 * 2113 * enables/disables replication of packets across multiple pools. 2114 **/ 2115 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 2116 { 2117 u32 vt_ctl = rd32(E1000_VT_CTL); 2118 2119 if (enable) 2120 vt_ctl |= E1000_VT_CTL_VM_REPL_EN; 2121 else 2122 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; 2123 2124 wr32(E1000_VT_CTL, vt_ctl); 2125 } 2126 2127 /** 2128 * igb_read_phy_reg_82580 - Read 82580 MDI control register 2129 * @hw: pointer to the HW structure 2130 * @offset: register offset to be read 2131 * @data: pointer to the read data 2132 * 2133 * Reads the MDI control register in the PHY at offset and stores the 2134 * information read to data. 2135 **/ 2136 static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) 2137 { 2138 s32 ret_val; 2139 2140 ret_val = hw->phy.ops.acquire(hw); 2141 if (ret_val) 2142 goto out; 2143 2144 ret_val = igb_read_phy_reg_mdic(hw, offset, data); 2145 2146 hw->phy.ops.release(hw); 2147 2148 out: 2149 return ret_val; 2150 } 2151 2152 /** 2153 * igb_write_phy_reg_82580 - Write 82580 MDI control register 2154 * @hw: pointer to the HW structure 2155 * @offset: register offset to write to 2156 * @data: data to write to register at offset 2157 * 2158 * Writes data to MDI control register in the PHY at offset. 2159 **/ 2160 static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) 2161 { 2162 s32 ret_val; 2163 2164 2165 ret_val = hw->phy.ops.acquire(hw); 2166 if (ret_val) 2167 goto out; 2168 2169 ret_val = igb_write_phy_reg_mdic(hw, offset, data); 2170 2171 hw->phy.ops.release(hw); 2172 2173 out: 2174 return ret_val; 2175 } 2176 2177 /** 2178 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits 2179 * @hw: pointer to the HW structure 2180 * 2181 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on 2182 * the values found in the EEPROM. This addresses an issue in which these 2183 * bits are not restored from EEPROM after reset. 2184 **/ 2185 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw) 2186 { 2187 s32 ret_val = 0; 2188 u32 mdicnfg; 2189 u16 nvm_data = 0; 2190 2191 if (hw->mac.type != e1000_82580) 2192 goto out; 2193 if (!igb_sgmii_active_82575(hw)) 2194 goto out; 2195 2196 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2197 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2198 &nvm_data); 2199 if (ret_val) { 2200 hw_dbg("NVM Read Error\n"); 2201 goto out; 2202 } 2203 2204 mdicnfg = rd32(E1000_MDICNFG); 2205 if (nvm_data & NVM_WORD24_EXT_MDIO) 2206 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 2207 if (nvm_data & NVM_WORD24_COM_MDIO) 2208 mdicnfg |= E1000_MDICNFG_COM_MDIO; 2209 wr32(E1000_MDICNFG, mdicnfg); 2210 out: 2211 return ret_val; 2212 } 2213 2214 /** 2215 * igb_reset_hw_82580 - Reset hardware 2216 * @hw: pointer to the HW structure 2217 * 2218 * This resets function or entire device (all ports, etc.) 2219 * to a known state. 2220 **/ 2221 static s32 igb_reset_hw_82580(struct e1000_hw *hw) 2222 { 2223 s32 ret_val = 0; 2224 /* BH SW mailbox bit in SW_FW_SYNC */ 2225 u16 swmbsw_mask = E1000_SW_SYNCH_MB; 2226 u32 ctrl; 2227 bool global_device_reset = hw->dev_spec._82575.global_device_reset; 2228 2229 hw->dev_spec._82575.global_device_reset = false; 2230 2231 /* due to hw errata, global device reset doesn't always 2232 * work on 82580 2233 */ 2234 if (hw->mac.type == e1000_82580) 2235 global_device_reset = false; 2236 2237 /* Get current control state. */ 2238 ctrl = rd32(E1000_CTRL); 2239 2240 /* Prevent the PCI-E bus from sticking if there is no TLP connection 2241 * on the last TLP read/write transaction when MAC is reset. 2242 */ 2243 ret_val = igb_disable_pcie_master(hw); 2244 if (ret_val) 2245 hw_dbg("PCI-E Master disable polling has failed.\n"); 2246 2247 hw_dbg("Masking off all interrupts\n"); 2248 wr32(E1000_IMC, 0xffffffff); 2249 wr32(E1000_RCTL, 0); 2250 wr32(E1000_TCTL, E1000_TCTL_PSP); 2251 wrfl(); 2252 2253 usleep_range(10000, 11000); 2254 2255 /* Determine whether or not a global dev reset is requested */ 2256 if (global_device_reset && 2257 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask)) 2258 global_device_reset = false; 2259 2260 if (global_device_reset && 2261 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET)) 2262 ctrl |= E1000_CTRL_DEV_RST; 2263 else 2264 ctrl |= E1000_CTRL_RST; 2265 2266 wr32(E1000_CTRL, ctrl); 2267 wrfl(); 2268 2269 /* Add delay to insure DEV_RST has time to complete */ 2270 if (global_device_reset) 2271 usleep_range(5000, 6000); 2272 2273 ret_val = igb_get_auto_rd_done(hw); 2274 if (ret_val) { 2275 /* When auto config read does not complete, do not 2276 * return with an error. This can happen in situations 2277 * where there is no eeprom and prevents getting link. 2278 */ 2279 hw_dbg("Auto Read Done did not complete\n"); 2280 } 2281 2282 /* clear global device reset status bit */ 2283 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET); 2284 2285 /* Clear any pending interrupt events. */ 2286 wr32(E1000_IMC, 0xffffffff); 2287 rd32(E1000_ICR); 2288 2289 ret_val = igb_reset_mdicnfg_82580(hw); 2290 if (ret_val) 2291 hw_dbg("Could not reset MDICNFG based on EEPROM\n"); 2292 2293 /* Install any alternate MAC address into RAR0 */ 2294 ret_val = igb_check_alt_mac_addr(hw); 2295 2296 /* Release semaphore */ 2297 if (global_device_reset) 2298 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask); 2299 2300 return ret_val; 2301 } 2302 2303 /** 2304 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size 2305 * @data: data received by reading RXPBS register 2306 * 2307 * The 82580 uses a table based approach for packet buffer allocation sizes. 2308 * This function converts the retrieved value into the correct table value 2309 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 2310 * 0x0 36 72 144 1 2 4 8 16 2311 * 0x8 35 70 140 rsv rsv rsv rsv rsv 2312 */ 2313 u16 igb_rxpbs_adjust_82580(u32 data) 2314 { 2315 u16 ret_val = 0; 2316 2317 if (data < ARRAY_SIZE(e1000_82580_rxpbs_table)) 2318 ret_val = e1000_82580_rxpbs_table[data]; 2319 2320 return ret_val; 2321 } 2322 2323 /** 2324 * igb_validate_nvm_checksum_with_offset - Validate EEPROM 2325 * checksum 2326 * @hw: pointer to the HW structure 2327 * @offset: offset in words of the checksum protected region 2328 * 2329 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 2330 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 2331 **/ 2332 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw, 2333 u16 offset) 2334 { 2335 s32 ret_val = 0; 2336 u16 checksum = 0; 2337 u16 i, nvm_data; 2338 2339 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) { 2340 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2341 if (ret_val) { 2342 hw_dbg("NVM Read Error\n"); 2343 goto out; 2344 } 2345 checksum += nvm_data; 2346 } 2347 2348 if (checksum != (u16) NVM_SUM) { 2349 hw_dbg("NVM Checksum Invalid\n"); 2350 ret_val = -E1000_ERR_NVM; 2351 goto out; 2352 } 2353 2354 out: 2355 return ret_val; 2356 } 2357 2358 /** 2359 * igb_update_nvm_checksum_with_offset - Update EEPROM 2360 * checksum 2361 * @hw: pointer to the HW structure 2362 * @offset: offset in words of the checksum protected region 2363 * 2364 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 2365 * up to the checksum. Then calculates the EEPROM checksum and writes the 2366 * value to the EEPROM. 2367 **/ 2368 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2369 { 2370 s32 ret_val; 2371 u16 checksum = 0; 2372 u16 i, nvm_data; 2373 2374 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) { 2375 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2376 if (ret_val) { 2377 hw_dbg("NVM Read Error while updating checksum.\n"); 2378 goto out; 2379 } 2380 checksum += nvm_data; 2381 } 2382 checksum = (u16) NVM_SUM - checksum; 2383 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, 2384 &checksum); 2385 if (ret_val) 2386 hw_dbg("NVM Write Error while updating checksum.\n"); 2387 2388 out: 2389 return ret_val; 2390 } 2391 2392 /** 2393 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum 2394 * @hw: pointer to the HW structure 2395 * 2396 * Calculates the EEPROM section checksum by reading/adding each word of 2397 * the EEPROM and then verifies that the sum of the EEPROM is 2398 * equal to 0xBABA. 2399 **/ 2400 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw) 2401 { 2402 s32 ret_val = 0; 2403 u16 eeprom_regions_count = 1; 2404 u16 j, nvm_data; 2405 u16 nvm_offset; 2406 2407 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2408 if (ret_val) { 2409 hw_dbg("NVM Read Error\n"); 2410 goto out; 2411 } 2412 2413 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) { 2414 /* if checksums compatibility bit is set validate checksums 2415 * for all 4 ports. 2416 */ 2417 eeprom_regions_count = 4; 2418 } 2419 2420 for (j = 0; j < eeprom_regions_count; j++) { 2421 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2422 ret_val = igb_validate_nvm_checksum_with_offset(hw, 2423 nvm_offset); 2424 if (ret_val != 0) 2425 goto out; 2426 } 2427 2428 out: 2429 return ret_val; 2430 } 2431 2432 /** 2433 * igb_update_nvm_checksum_82580 - Update EEPROM checksum 2434 * @hw: pointer to the HW structure 2435 * 2436 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2437 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2438 * checksum and writes the value to the EEPROM. 2439 **/ 2440 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw) 2441 { 2442 s32 ret_val; 2443 u16 j, nvm_data; 2444 u16 nvm_offset; 2445 2446 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2447 if (ret_val) { 2448 hw_dbg("NVM Read Error while updating checksum compatibility bit.\n"); 2449 goto out; 2450 } 2451 2452 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) { 2453 /* set compatibility bit to validate checksums appropriately */ 2454 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK; 2455 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, 2456 &nvm_data); 2457 if (ret_val) { 2458 hw_dbg("NVM Write Error while updating checksum compatibility bit.\n"); 2459 goto out; 2460 } 2461 } 2462 2463 for (j = 0; j < 4; j++) { 2464 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2465 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset); 2466 if (ret_val) 2467 goto out; 2468 } 2469 2470 out: 2471 return ret_val; 2472 } 2473 2474 /** 2475 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum 2476 * @hw: pointer to the HW structure 2477 * 2478 * Calculates the EEPROM section checksum by reading/adding each word of 2479 * the EEPROM and then verifies that the sum of the EEPROM is 2480 * equal to 0xBABA. 2481 **/ 2482 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw) 2483 { 2484 s32 ret_val = 0; 2485 u16 j; 2486 u16 nvm_offset; 2487 2488 for (j = 0; j < 4; j++) { 2489 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2490 ret_val = igb_validate_nvm_checksum_with_offset(hw, 2491 nvm_offset); 2492 if (ret_val != 0) 2493 goto out; 2494 } 2495 2496 out: 2497 return ret_val; 2498 } 2499 2500 /** 2501 * igb_update_nvm_checksum_i350 - Update EEPROM checksum 2502 * @hw: pointer to the HW structure 2503 * 2504 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2505 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2506 * checksum and writes the value to the EEPROM. 2507 **/ 2508 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw) 2509 { 2510 s32 ret_val = 0; 2511 u16 j; 2512 u16 nvm_offset; 2513 2514 for (j = 0; j < 4; j++) { 2515 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2516 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset); 2517 if (ret_val != 0) 2518 goto out; 2519 } 2520 2521 out: 2522 return ret_val; 2523 } 2524 2525 /** 2526 * __igb_access_emi_reg - Read/write EMI register 2527 * @hw: pointer to the HW structure 2528 * @addr: EMI address to program 2529 * @data: pointer to value to read/write from/to the EMI address 2530 * @read: boolean flag to indicate read or write 2531 **/ 2532 static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address, 2533 u16 *data, bool read) 2534 { 2535 s32 ret_val = 0; 2536 2537 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address); 2538 if (ret_val) 2539 return ret_val; 2540 2541 if (read) 2542 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data); 2543 else 2544 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data); 2545 2546 return ret_val; 2547 } 2548 2549 /** 2550 * igb_read_emi_reg - Read Extended Management Interface register 2551 * @hw: pointer to the HW structure 2552 * @addr: EMI address to program 2553 * @data: value to be read from the EMI address 2554 **/ 2555 s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data) 2556 { 2557 return __igb_access_emi_reg(hw, addr, data, true); 2558 } 2559 2560 /** 2561 * igb_set_eee_i350 - Enable/disable EEE support 2562 * @hw: pointer to the HW structure 2563 * @adv1G: boolean flag enabling 1G EEE advertisement 2564 * @adv100m: boolean flag enabling 100M EEE advertisement 2565 * 2566 * Enable/disable EEE based on setting in dev_spec structure. 2567 * 2568 **/ 2569 s32 igb_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M) 2570 { 2571 u32 ipcnfg, eeer; 2572 2573 if ((hw->mac.type < e1000_i350) || 2574 (hw->phy.media_type != e1000_media_type_copper)) 2575 goto out; 2576 ipcnfg = rd32(E1000_IPCNFG); 2577 eeer = rd32(E1000_EEER); 2578 2579 /* enable or disable per user setting */ 2580 if (!(hw->dev_spec._82575.eee_disable)) { 2581 u32 eee_su = rd32(E1000_EEE_SU); 2582 2583 if (adv100M) 2584 ipcnfg |= E1000_IPCNFG_EEE_100M_AN; 2585 else 2586 ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN; 2587 2588 if (adv1G) 2589 ipcnfg |= E1000_IPCNFG_EEE_1G_AN; 2590 else 2591 ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN; 2592 2593 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 2594 E1000_EEER_LPI_FC); 2595 2596 /* This bit should not be set in normal operation. */ 2597 if (eee_su & E1000_EEE_SU_LPI_CLK_STP) 2598 hw_dbg("LPI Clock Stop Bit should not be set!\n"); 2599 2600 } else { 2601 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | 2602 E1000_IPCNFG_EEE_100M_AN); 2603 eeer &= ~(E1000_EEER_TX_LPI_EN | 2604 E1000_EEER_RX_LPI_EN | 2605 E1000_EEER_LPI_FC); 2606 } 2607 wr32(E1000_IPCNFG, ipcnfg); 2608 wr32(E1000_EEER, eeer); 2609 rd32(E1000_IPCNFG); 2610 rd32(E1000_EEER); 2611 out: 2612 2613 return 0; 2614 } 2615 2616 /** 2617 * igb_set_eee_i354 - Enable/disable EEE support 2618 * @hw: pointer to the HW structure 2619 * @adv1G: boolean flag enabling 1G EEE advertisement 2620 * @adv100m: boolean flag enabling 100M EEE advertisement 2621 * 2622 * Enable/disable EEE legacy mode based on setting in dev_spec structure. 2623 * 2624 **/ 2625 s32 igb_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M) 2626 { 2627 struct e1000_phy_info *phy = &hw->phy; 2628 s32 ret_val = 0; 2629 u16 phy_data; 2630 2631 if ((hw->phy.media_type != e1000_media_type_copper) || 2632 (phy->id != M88E1543_E_PHY_ID)) 2633 goto out; 2634 2635 if (!hw->dev_spec._82575.eee_disable) { 2636 /* Switch to PHY page 18. */ 2637 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18); 2638 if (ret_val) 2639 goto out; 2640 2641 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1, 2642 &phy_data); 2643 if (ret_val) 2644 goto out; 2645 2646 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS; 2647 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1, 2648 phy_data); 2649 if (ret_val) 2650 goto out; 2651 2652 /* Return the PHY to page 0. */ 2653 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); 2654 if (ret_val) 2655 goto out; 2656 2657 /* Turn on EEE advertisement. */ 2658 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2659 E1000_EEE_ADV_DEV_I354, 2660 &phy_data); 2661 if (ret_val) 2662 goto out; 2663 2664 if (adv100M) 2665 phy_data |= E1000_EEE_ADV_100_SUPPORTED; 2666 else 2667 phy_data &= ~E1000_EEE_ADV_100_SUPPORTED; 2668 2669 if (adv1G) 2670 phy_data |= E1000_EEE_ADV_1000_SUPPORTED; 2671 else 2672 phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED; 2673 2674 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2675 E1000_EEE_ADV_DEV_I354, 2676 phy_data); 2677 } else { 2678 /* Turn off EEE advertisement. */ 2679 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2680 E1000_EEE_ADV_DEV_I354, 2681 &phy_data); 2682 if (ret_val) 2683 goto out; 2684 2685 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED | 2686 E1000_EEE_ADV_1000_SUPPORTED); 2687 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2688 E1000_EEE_ADV_DEV_I354, 2689 phy_data); 2690 } 2691 2692 out: 2693 return ret_val; 2694 } 2695 2696 /** 2697 * igb_get_eee_status_i354 - Get EEE status 2698 * @hw: pointer to the HW structure 2699 * @status: EEE status 2700 * 2701 * Get EEE status by guessing based on whether Tx or Rx LPI indications have 2702 * been received. 2703 **/ 2704 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status) 2705 { 2706 struct e1000_phy_info *phy = &hw->phy; 2707 s32 ret_val = 0; 2708 u16 phy_data; 2709 2710 /* Check if EEE is supported on this device. */ 2711 if ((hw->phy.media_type != e1000_media_type_copper) || 2712 (phy->id != M88E1543_E_PHY_ID)) 2713 goto out; 2714 2715 ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354, 2716 E1000_PCS_STATUS_DEV_I354, 2717 &phy_data); 2718 if (ret_val) 2719 goto out; 2720 2721 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD | 2722 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false; 2723 2724 out: 2725 return ret_val; 2726 } 2727 2728 static const u8 e1000_emc_temp_data[4] = { 2729 E1000_EMC_INTERNAL_DATA, 2730 E1000_EMC_DIODE1_DATA, 2731 E1000_EMC_DIODE2_DATA, 2732 E1000_EMC_DIODE3_DATA 2733 }; 2734 static const u8 e1000_emc_therm_limit[4] = { 2735 E1000_EMC_INTERNAL_THERM_LIMIT, 2736 E1000_EMC_DIODE1_THERM_LIMIT, 2737 E1000_EMC_DIODE2_THERM_LIMIT, 2738 E1000_EMC_DIODE3_THERM_LIMIT 2739 }; 2740 2741 #ifdef CONFIG_IGB_HWMON 2742 /** 2743 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data 2744 * @hw: pointer to hardware structure 2745 * 2746 * Updates the temperatures in mac.thermal_sensor_data 2747 **/ 2748 static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw) 2749 { 2750 u16 ets_offset; 2751 u16 ets_cfg; 2752 u16 ets_sensor; 2753 u8 num_sensors; 2754 u8 sensor_index; 2755 u8 sensor_location; 2756 u8 i; 2757 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 2758 2759 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0)) 2760 return E1000_NOT_IMPLEMENTED; 2761 2762 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF); 2763 2764 /* Return the internal sensor only if ETS is unsupported */ 2765 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset); 2766 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) 2767 return 0; 2768 2769 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg); 2770 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT) 2771 != NVM_ETS_TYPE_EMC) 2772 return E1000_NOT_IMPLEMENTED; 2773 2774 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK); 2775 if (num_sensors > E1000_MAX_SENSORS) 2776 num_sensors = E1000_MAX_SENSORS; 2777 2778 for (i = 1; i < num_sensors; i++) { 2779 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor); 2780 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >> 2781 NVM_ETS_DATA_INDEX_SHIFT); 2782 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >> 2783 NVM_ETS_DATA_LOC_SHIFT); 2784 2785 if (sensor_location != 0) 2786 hw->phy.ops.read_i2c_byte(hw, 2787 e1000_emc_temp_data[sensor_index], 2788 E1000_I2C_THERMAL_SENSOR_ADDR, 2789 &data->sensor[i].temp); 2790 } 2791 return 0; 2792 } 2793 2794 /** 2795 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds 2796 * @hw: pointer to hardware structure 2797 * 2798 * Sets the thermal sensor thresholds according to the NVM map 2799 * and save off the threshold and location values into mac.thermal_sensor_data 2800 **/ 2801 static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw) 2802 { 2803 u16 ets_offset; 2804 u16 ets_cfg; 2805 u16 ets_sensor; 2806 u8 low_thresh_delta; 2807 u8 num_sensors; 2808 u8 sensor_index; 2809 u8 sensor_location; 2810 u8 therm_limit; 2811 u8 i; 2812 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 2813 2814 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0)) 2815 return E1000_NOT_IMPLEMENTED; 2816 2817 memset(data, 0, sizeof(struct e1000_thermal_sensor_data)); 2818 2819 data->sensor[0].location = 0x1; 2820 data->sensor[0].caution_thresh = 2821 (rd32(E1000_THHIGHTC) & 0xFF); 2822 data->sensor[0].max_op_thresh = 2823 (rd32(E1000_THLOWTC) & 0xFF); 2824 2825 /* Return the internal sensor only if ETS is unsupported */ 2826 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset); 2827 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) 2828 return 0; 2829 2830 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg); 2831 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT) 2832 != NVM_ETS_TYPE_EMC) 2833 return E1000_NOT_IMPLEMENTED; 2834 2835 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >> 2836 NVM_ETS_LTHRES_DELTA_SHIFT); 2837 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK); 2838 2839 for (i = 1; i <= num_sensors; i++) { 2840 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor); 2841 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >> 2842 NVM_ETS_DATA_INDEX_SHIFT); 2843 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >> 2844 NVM_ETS_DATA_LOC_SHIFT); 2845 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK; 2846 2847 hw->phy.ops.write_i2c_byte(hw, 2848 e1000_emc_therm_limit[sensor_index], 2849 E1000_I2C_THERMAL_SENSOR_ADDR, 2850 therm_limit); 2851 2852 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) { 2853 data->sensor[i].location = sensor_location; 2854 data->sensor[i].caution_thresh = therm_limit; 2855 data->sensor[i].max_op_thresh = therm_limit - 2856 low_thresh_delta; 2857 } 2858 } 2859 return 0; 2860 } 2861 2862 #endif 2863 static struct e1000_mac_operations e1000_mac_ops_82575 = { 2864 .init_hw = igb_init_hw_82575, 2865 .check_for_link = igb_check_for_link_82575, 2866 .rar_set = igb_rar_set, 2867 .read_mac_addr = igb_read_mac_addr_82575, 2868 .get_speed_and_duplex = igb_get_link_up_info_82575, 2869 #ifdef CONFIG_IGB_HWMON 2870 .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic, 2871 .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic, 2872 #endif 2873 }; 2874 2875 static struct e1000_phy_operations e1000_phy_ops_82575 = { 2876 .acquire = igb_acquire_phy_82575, 2877 .get_cfg_done = igb_get_cfg_done_82575, 2878 .release = igb_release_phy_82575, 2879 .write_i2c_byte = igb_write_i2c_byte, 2880 .read_i2c_byte = igb_read_i2c_byte, 2881 }; 2882 2883 static struct e1000_nvm_operations e1000_nvm_ops_82575 = { 2884 .acquire = igb_acquire_nvm_82575, 2885 .read = igb_read_nvm_eerd, 2886 .release = igb_release_nvm_82575, 2887 .write = igb_write_nvm_spi, 2888 }; 2889 2890 const struct e1000_info e1000_82575_info = { 2891 .get_invariants = igb_get_invariants_82575, 2892 .mac_ops = &e1000_mac_ops_82575, 2893 .phy_ops = &e1000_phy_ops_82575, 2894 .nvm_ops = &e1000_nvm_ops_82575, 2895 }; 2896 2897