1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2007 - 2018 Intel Corporation. */ 3 4 /* e1000_82575 5 * e1000_82576 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <linux/types.h> 11 #include <linux/if_ether.h> 12 #include <linux/i2c.h> 13 14 #include "e1000_mac.h" 15 #include "e1000_82575.h" 16 #include "e1000_i210.h" 17 #include "igb.h" 18 19 static s32 igb_get_invariants_82575(struct e1000_hw *); 20 static s32 igb_acquire_phy_82575(struct e1000_hw *); 21 static void igb_release_phy_82575(struct e1000_hw *); 22 static s32 igb_acquire_nvm_82575(struct e1000_hw *); 23 static void igb_release_nvm_82575(struct e1000_hw *); 24 static s32 igb_check_for_link_82575(struct e1000_hw *); 25 static s32 igb_get_cfg_done_82575(struct e1000_hw *); 26 static s32 igb_init_hw_82575(struct e1000_hw *); 27 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *); 28 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *); 29 static s32 igb_reset_hw_82575(struct e1000_hw *); 30 static s32 igb_reset_hw_82580(struct e1000_hw *); 31 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); 32 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool); 33 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool); 34 static s32 igb_setup_copper_link_82575(struct e1000_hw *); 35 static s32 igb_setup_serdes_link_82575(struct e1000_hw *); 36 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16); 37 static void igb_clear_hw_cntrs_82575(struct e1000_hw *); 38 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16); 39 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *, 40 u16 *); 41 static s32 igb_get_phy_id_82575(struct e1000_hw *); 42 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16); 43 static bool igb_sgmii_active_82575(struct e1000_hw *); 44 static s32 igb_reset_init_script_82575(struct e1000_hw *); 45 static s32 igb_read_mac_addr_82575(struct e1000_hw *); 46 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw); 47 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw); 48 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw); 49 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw); 50 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw); 51 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw); 52 static const u16 e1000_82580_rxpbs_table[] = { 53 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 }; 54 55 /* Due to a hw errata, if the host tries to configure the VFTA register 56 * while performing queries from the BMC or DMA, then the VFTA in some 57 * cases won't be written. 58 */ 59 60 /** 61 * igb_write_vfta_i350 - Write value to VLAN filter table 62 * @hw: pointer to the HW structure 63 * @offset: register offset in VLAN filter table 64 * @value: register value written to VLAN filter table 65 * 66 * Writes value at the given offset in the register array which stores 67 * the VLAN filter table. 68 **/ 69 static void igb_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value) 70 { 71 struct igb_adapter *adapter = hw->back; 72 int i; 73 74 for (i = 10; i--;) 75 array_wr32(E1000_VFTA, offset, value); 76 77 wrfl(); 78 adapter->shadow_vfta[offset] = value; 79 } 80 81 /** 82 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO 83 * @hw: pointer to the HW structure 84 * 85 * Called to determine if the I2C pins are being used for I2C or as an 86 * external MDIO interface since the two options are mutually exclusive. 87 **/ 88 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw) 89 { 90 u32 reg = 0; 91 bool ext_mdio = false; 92 93 switch (hw->mac.type) { 94 case e1000_82575: 95 case e1000_82576: 96 reg = rd32(E1000_MDIC); 97 ext_mdio = !!(reg & E1000_MDIC_DEST); 98 break; 99 case e1000_82580: 100 case e1000_i350: 101 case e1000_i354: 102 case e1000_i210: 103 case e1000_i211: 104 reg = rd32(E1000_MDICNFG); 105 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); 106 break; 107 default: 108 break; 109 } 110 return ext_mdio; 111 } 112 113 /** 114 * igb_check_for_link_media_swap - Check which M88E1112 interface linked 115 * @hw: pointer to the HW structure 116 * 117 * Poll the M88E1112 interfaces to see which interface achieved link. 118 */ 119 static s32 igb_check_for_link_media_swap(struct e1000_hw *hw) 120 { 121 struct e1000_phy_info *phy = &hw->phy; 122 s32 ret_val; 123 u16 data; 124 u8 port = 0; 125 126 /* Check the copper medium. */ 127 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 128 if (ret_val) 129 return ret_val; 130 131 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); 132 if (ret_val) 133 return ret_val; 134 135 if (data & E1000_M88E1112_STATUS_LINK) 136 port = E1000_MEDIA_PORT_COPPER; 137 138 /* Check the other medium. */ 139 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1); 140 if (ret_val) 141 return ret_val; 142 143 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); 144 if (ret_val) 145 return ret_val; 146 147 148 if (data & E1000_M88E1112_STATUS_LINK) 149 port = E1000_MEDIA_PORT_OTHER; 150 151 /* Determine if a swap needs to happen. */ 152 if (port && (hw->dev_spec._82575.media_port != port)) { 153 hw->dev_spec._82575.media_port = port; 154 hw->dev_spec._82575.media_changed = true; 155 } 156 157 if (port == E1000_MEDIA_PORT_COPPER) { 158 /* reset page to 0 */ 159 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 160 if (ret_val) 161 return ret_val; 162 igb_check_for_link_82575(hw); 163 } else { 164 igb_check_for_link_82575(hw); 165 /* reset page to 0 */ 166 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 167 if (ret_val) 168 return ret_val; 169 } 170 171 return 0; 172 } 173 174 /** 175 * igb_init_phy_params_82575 - Init PHY func ptrs. 176 * @hw: pointer to the HW structure 177 **/ 178 static s32 igb_init_phy_params_82575(struct e1000_hw *hw) 179 { 180 struct e1000_phy_info *phy = &hw->phy; 181 s32 ret_val = 0; 182 u32 ctrl_ext; 183 184 if (hw->phy.media_type != e1000_media_type_copper) { 185 phy->type = e1000_phy_none; 186 goto out; 187 } 188 189 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 190 phy->reset_delay_us = 100; 191 192 ctrl_ext = rd32(E1000_CTRL_EXT); 193 194 if (igb_sgmii_active_82575(hw)) { 195 phy->ops.reset = igb_phy_hw_reset_sgmii_82575; 196 ctrl_ext |= E1000_CTRL_I2C_ENA; 197 } else { 198 phy->ops.reset = igb_phy_hw_reset; 199 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 200 } 201 202 wr32(E1000_CTRL_EXT, ctrl_ext); 203 igb_reset_mdicnfg_82580(hw); 204 205 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) { 206 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575; 207 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575; 208 } else { 209 switch (hw->mac.type) { 210 case e1000_82580: 211 case e1000_i350: 212 case e1000_i354: 213 case e1000_i210: 214 case e1000_i211: 215 phy->ops.read_reg = igb_read_phy_reg_82580; 216 phy->ops.write_reg = igb_write_phy_reg_82580; 217 break; 218 default: 219 phy->ops.read_reg = igb_read_phy_reg_igp; 220 phy->ops.write_reg = igb_write_phy_reg_igp; 221 } 222 } 223 224 /* set lan id */ 225 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >> 226 E1000_STATUS_FUNC_SHIFT; 227 228 /* Set phy->phy_addr and phy->id. */ 229 ret_val = igb_get_phy_id_82575(hw); 230 if (ret_val) 231 return ret_val; 232 233 /* Verify phy id and set remaining function pointers */ 234 switch (phy->id) { 235 case M88E1543_E_PHY_ID: 236 case M88E1512_E_PHY_ID: 237 case I347AT4_E_PHY_ID: 238 case M88E1112_E_PHY_ID: 239 case M88E1111_I_PHY_ID: 240 phy->type = e1000_phy_m88; 241 phy->ops.check_polarity = igb_check_polarity_m88; 242 phy->ops.get_phy_info = igb_get_phy_info_m88; 243 if (phy->id != M88E1111_I_PHY_ID) 244 phy->ops.get_cable_length = 245 igb_get_cable_length_m88_gen2; 246 else 247 phy->ops.get_cable_length = igb_get_cable_length_m88; 248 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; 249 /* Check if this PHY is configured for media swap. */ 250 if (phy->id == M88E1112_E_PHY_ID) { 251 u16 data; 252 253 ret_val = phy->ops.write_reg(hw, 254 E1000_M88E1112_PAGE_ADDR, 255 2); 256 if (ret_val) 257 goto out; 258 259 ret_val = phy->ops.read_reg(hw, 260 E1000_M88E1112_MAC_CTRL_1, 261 &data); 262 if (ret_val) 263 goto out; 264 265 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >> 266 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT; 267 if (data == E1000_M88E1112_AUTO_COPPER_SGMII || 268 data == E1000_M88E1112_AUTO_COPPER_BASEX) 269 hw->mac.ops.check_for_link = 270 igb_check_for_link_media_swap; 271 } 272 if (phy->id == M88E1512_E_PHY_ID) { 273 ret_val = igb_initialize_M88E1512_phy(hw); 274 if (ret_val) 275 goto out; 276 } 277 if (phy->id == M88E1543_E_PHY_ID) { 278 ret_val = igb_initialize_M88E1543_phy(hw); 279 if (ret_val) 280 goto out; 281 } 282 break; 283 case IGP03E1000_E_PHY_ID: 284 phy->type = e1000_phy_igp_3; 285 phy->ops.get_phy_info = igb_get_phy_info_igp; 286 phy->ops.get_cable_length = igb_get_cable_length_igp_2; 287 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp; 288 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575; 289 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state; 290 break; 291 case I82580_I_PHY_ID: 292 case I350_I_PHY_ID: 293 phy->type = e1000_phy_82580; 294 phy->ops.force_speed_duplex = 295 igb_phy_force_speed_duplex_82580; 296 phy->ops.get_cable_length = igb_get_cable_length_82580; 297 phy->ops.get_phy_info = igb_get_phy_info_82580; 298 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580; 299 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580; 300 break; 301 case I210_I_PHY_ID: 302 phy->type = e1000_phy_i210; 303 phy->ops.check_polarity = igb_check_polarity_m88; 304 phy->ops.get_cfg_done = igb_get_cfg_done_i210; 305 phy->ops.get_phy_info = igb_get_phy_info_m88; 306 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2; 307 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580; 308 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580; 309 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; 310 break; 311 case BCM54616_E_PHY_ID: 312 phy->type = e1000_phy_bcm54616; 313 break; 314 default: 315 ret_val = -E1000_ERR_PHY; 316 goto out; 317 } 318 319 out: 320 return ret_val; 321 } 322 323 /** 324 * igb_init_nvm_params_82575 - Init NVM func ptrs. 325 * @hw: pointer to the HW structure 326 **/ 327 static s32 igb_init_nvm_params_82575(struct e1000_hw *hw) 328 { 329 struct e1000_nvm_info *nvm = &hw->nvm; 330 u32 eecd = rd32(E1000_EECD); 331 u16 size; 332 333 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 334 E1000_EECD_SIZE_EX_SHIFT); 335 336 /* Added to a constant, "size" becomes the left-shift value 337 * for setting word_size. 338 */ 339 size += NVM_WORD_SIZE_BASE_SHIFT; 340 341 /* Just in case size is out of range, cap it to the largest 342 * EEPROM size supported 343 */ 344 if (size > 15) 345 size = 15; 346 347 nvm->word_size = BIT(size); 348 nvm->opcode_bits = 8; 349 nvm->delay_usec = 1; 350 351 switch (nvm->override) { 352 case e1000_nvm_override_spi_large: 353 nvm->page_size = 32; 354 nvm->address_bits = 16; 355 break; 356 case e1000_nvm_override_spi_small: 357 nvm->page_size = 8; 358 nvm->address_bits = 8; 359 break; 360 default: 361 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 362 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 363 16 : 8; 364 break; 365 } 366 if (nvm->word_size == BIT(15)) 367 nvm->page_size = 128; 368 369 nvm->type = e1000_nvm_eeprom_spi; 370 371 /* NVM Function Pointers */ 372 nvm->ops.acquire = igb_acquire_nvm_82575; 373 nvm->ops.release = igb_release_nvm_82575; 374 nvm->ops.write = igb_write_nvm_spi; 375 nvm->ops.validate = igb_validate_nvm_checksum; 376 nvm->ops.update = igb_update_nvm_checksum; 377 if (nvm->word_size < BIT(15)) 378 nvm->ops.read = igb_read_nvm_eerd; 379 else 380 nvm->ops.read = igb_read_nvm_spi; 381 382 /* override generic family function pointers for specific descendants */ 383 switch (hw->mac.type) { 384 case e1000_82580: 385 nvm->ops.validate = igb_validate_nvm_checksum_82580; 386 nvm->ops.update = igb_update_nvm_checksum_82580; 387 break; 388 case e1000_i354: 389 case e1000_i350: 390 nvm->ops.validate = igb_validate_nvm_checksum_i350; 391 nvm->ops.update = igb_update_nvm_checksum_i350; 392 break; 393 default: 394 break; 395 } 396 397 return 0; 398 } 399 400 /** 401 * igb_init_mac_params_82575 - Init MAC func ptrs. 402 * @hw: pointer to the HW structure 403 **/ 404 static s32 igb_init_mac_params_82575(struct e1000_hw *hw) 405 { 406 struct e1000_mac_info *mac = &hw->mac; 407 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 408 409 /* Set mta register count */ 410 mac->mta_reg_count = 128; 411 /* Set uta register count */ 412 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128; 413 /* Set rar entry count */ 414 switch (mac->type) { 415 case e1000_82576: 416 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 417 break; 418 case e1000_82580: 419 mac->rar_entry_count = E1000_RAR_ENTRIES_82580; 420 break; 421 case e1000_i350: 422 case e1000_i354: 423 mac->rar_entry_count = E1000_RAR_ENTRIES_I350; 424 break; 425 default: 426 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 427 break; 428 } 429 /* reset */ 430 if (mac->type >= e1000_82580) 431 mac->ops.reset_hw = igb_reset_hw_82580; 432 else 433 mac->ops.reset_hw = igb_reset_hw_82575; 434 435 if (mac->type >= e1000_i210) { 436 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210; 437 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210; 438 439 } else { 440 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575; 441 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575; 442 } 443 444 if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354)) 445 mac->ops.write_vfta = igb_write_vfta_i350; 446 else 447 mac->ops.write_vfta = igb_write_vfta; 448 449 /* Set if part includes ASF firmware */ 450 mac->asf_firmware_present = true; 451 /* Set if manageability features are enabled. */ 452 mac->arc_subsystem_valid = 453 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK) 454 ? true : false; 455 /* enable EEE on i350 parts and later parts */ 456 if (mac->type >= e1000_i350) 457 dev_spec->eee_disable = false; 458 else 459 dev_spec->eee_disable = true; 460 /* Allow a single clear of the SW semaphore on I210 and newer */ 461 if (mac->type >= e1000_i210) 462 dev_spec->clear_semaphore_once = true; 463 /* physical interface link setup */ 464 mac->ops.setup_physical_interface = 465 (hw->phy.media_type == e1000_media_type_copper) 466 ? igb_setup_copper_link_82575 467 : igb_setup_serdes_link_82575; 468 469 if (mac->type == e1000_82580) { 470 switch (hw->device_id) { 471 /* feature not supported on these id's */ 472 case E1000_DEV_ID_DH89XXCC_SGMII: 473 case E1000_DEV_ID_DH89XXCC_SERDES: 474 case E1000_DEV_ID_DH89XXCC_BACKPLANE: 475 case E1000_DEV_ID_DH89XXCC_SFP: 476 break; 477 default: 478 hw->dev_spec._82575.mas_capable = true; 479 break; 480 } 481 } 482 return 0; 483 } 484 485 /** 486 * igb_set_sfp_media_type_82575 - derives SFP module media type. 487 * @hw: pointer to the HW structure 488 * 489 * The media type is chosen based on SFP module. 490 * compatibility flags retrieved from SFP ID EEPROM. 491 **/ 492 static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw) 493 { 494 s32 ret_val = E1000_ERR_CONFIG; 495 u32 ctrl_ext = 0; 496 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 497 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags; 498 u8 tranceiver_type = 0; 499 s32 timeout = 3; 500 501 /* Turn I2C interface ON and power on sfp cage */ 502 ctrl_ext = rd32(E1000_CTRL_EXT); 503 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 504 wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); 505 506 wrfl(); 507 508 /* Read SFP module data */ 509 while (timeout) { 510 ret_val = igb_read_sfp_data_byte(hw, 511 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET), 512 &tranceiver_type); 513 if (ret_val == 0) 514 break; 515 msleep(100); 516 timeout--; 517 } 518 if (ret_val != 0) 519 goto out; 520 521 ret_val = igb_read_sfp_data_byte(hw, 522 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET), 523 (u8 *)eth_flags); 524 if (ret_val != 0) 525 goto out; 526 527 /* Check if there is some SFP module plugged and powered */ 528 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) || 529 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) { 530 dev_spec->module_plugged = true; 531 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) { 532 hw->phy.media_type = e1000_media_type_internal_serdes; 533 } else if (eth_flags->e100_base_fx) { 534 dev_spec->sgmii_active = true; 535 hw->phy.media_type = e1000_media_type_internal_serdes; 536 } else if (eth_flags->e1000_base_t) { 537 dev_spec->sgmii_active = true; 538 hw->phy.media_type = e1000_media_type_copper; 539 } else { 540 hw->phy.media_type = e1000_media_type_unknown; 541 hw_dbg("PHY module has not been recognized\n"); 542 goto out; 543 } 544 } else { 545 hw->phy.media_type = e1000_media_type_unknown; 546 } 547 ret_val = 0; 548 out: 549 /* Restore I2C interface setting */ 550 wr32(E1000_CTRL_EXT, ctrl_ext); 551 return ret_val; 552 } 553 554 static s32 igb_get_invariants_82575(struct e1000_hw *hw) 555 { 556 struct e1000_mac_info *mac = &hw->mac; 557 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 558 s32 ret_val; 559 u32 ctrl_ext = 0; 560 u32 link_mode = 0; 561 562 switch (hw->device_id) { 563 case E1000_DEV_ID_82575EB_COPPER: 564 case E1000_DEV_ID_82575EB_FIBER_SERDES: 565 case E1000_DEV_ID_82575GB_QUAD_COPPER: 566 mac->type = e1000_82575; 567 break; 568 case E1000_DEV_ID_82576: 569 case E1000_DEV_ID_82576_NS: 570 case E1000_DEV_ID_82576_NS_SERDES: 571 case E1000_DEV_ID_82576_FIBER: 572 case E1000_DEV_ID_82576_SERDES: 573 case E1000_DEV_ID_82576_QUAD_COPPER: 574 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 575 case E1000_DEV_ID_82576_SERDES_QUAD: 576 mac->type = e1000_82576; 577 break; 578 case E1000_DEV_ID_82580_COPPER: 579 case E1000_DEV_ID_82580_FIBER: 580 case E1000_DEV_ID_82580_QUAD_FIBER: 581 case E1000_DEV_ID_82580_SERDES: 582 case E1000_DEV_ID_82580_SGMII: 583 case E1000_DEV_ID_82580_COPPER_DUAL: 584 case E1000_DEV_ID_DH89XXCC_SGMII: 585 case E1000_DEV_ID_DH89XXCC_SERDES: 586 case E1000_DEV_ID_DH89XXCC_BACKPLANE: 587 case E1000_DEV_ID_DH89XXCC_SFP: 588 mac->type = e1000_82580; 589 break; 590 case E1000_DEV_ID_I350_COPPER: 591 case E1000_DEV_ID_I350_FIBER: 592 case E1000_DEV_ID_I350_SERDES: 593 case E1000_DEV_ID_I350_SGMII: 594 mac->type = e1000_i350; 595 break; 596 case E1000_DEV_ID_I210_COPPER: 597 case E1000_DEV_ID_I210_FIBER: 598 case E1000_DEV_ID_I210_SERDES: 599 case E1000_DEV_ID_I210_SGMII: 600 case E1000_DEV_ID_I210_COPPER_FLASHLESS: 601 case E1000_DEV_ID_I210_SERDES_FLASHLESS: 602 mac->type = e1000_i210; 603 break; 604 case E1000_DEV_ID_I211_COPPER: 605 mac->type = e1000_i211; 606 break; 607 case E1000_DEV_ID_I354_BACKPLANE_1GBPS: 608 case E1000_DEV_ID_I354_SGMII: 609 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS: 610 mac->type = e1000_i354; 611 break; 612 default: 613 return -E1000_ERR_MAC_INIT; 614 } 615 616 /* Set media type */ 617 /* The 82575 uses bits 22:23 for link mode. The mode can be changed 618 * based on the EEPROM. We cannot rely upon device ID. There 619 * is no distinguishable difference between fiber and internal 620 * SerDes mode on the 82575. There can be an external PHY attached 621 * on the SGMII interface. For this, we'll set sgmii_active to true. 622 */ 623 hw->phy.media_type = e1000_media_type_copper; 624 dev_spec->sgmii_active = false; 625 dev_spec->module_plugged = false; 626 627 ctrl_ext = rd32(E1000_CTRL_EXT); 628 629 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK; 630 switch (link_mode) { 631 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 632 hw->phy.media_type = e1000_media_type_internal_serdes; 633 break; 634 case E1000_CTRL_EXT_LINK_MODE_SGMII: 635 /* Get phy control interface type set (MDIO vs. I2C)*/ 636 if (igb_sgmii_uses_mdio_82575(hw)) { 637 hw->phy.media_type = e1000_media_type_copper; 638 dev_spec->sgmii_active = true; 639 break; 640 } 641 /* fall through - for I2C based SGMII */ 642 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 643 /* read media type from SFP EEPROM */ 644 ret_val = igb_set_sfp_media_type_82575(hw); 645 if ((ret_val != 0) || 646 (hw->phy.media_type == e1000_media_type_unknown)) { 647 /* If media type was not identified then return media 648 * type defined by the CTRL_EXT settings. 649 */ 650 hw->phy.media_type = e1000_media_type_internal_serdes; 651 652 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) { 653 hw->phy.media_type = e1000_media_type_copper; 654 dev_spec->sgmii_active = true; 655 } 656 657 break; 658 } 659 660 /* do not change link mode for 100BaseFX */ 661 if (dev_spec->eth_flags.e100_base_fx) 662 break; 663 664 /* change current link mode setting */ 665 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 666 667 if (hw->phy.media_type == e1000_media_type_copper) 668 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII; 669 else 670 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 671 672 wr32(E1000_CTRL_EXT, ctrl_ext); 673 674 break; 675 default: 676 break; 677 } 678 679 /* mac initialization and operations */ 680 ret_val = igb_init_mac_params_82575(hw); 681 if (ret_val) 682 goto out; 683 684 /* NVM initialization */ 685 ret_val = igb_init_nvm_params_82575(hw); 686 switch (hw->mac.type) { 687 case e1000_i210: 688 case e1000_i211: 689 ret_val = igb_init_nvm_params_i210(hw); 690 break; 691 default: 692 break; 693 } 694 695 if (ret_val) 696 goto out; 697 698 /* if part supports SR-IOV then initialize mailbox parameters */ 699 switch (mac->type) { 700 case e1000_82576: 701 case e1000_i350: 702 igb_init_mbx_params_pf(hw); 703 break; 704 default: 705 break; 706 } 707 708 /* setup PHY parameters */ 709 ret_val = igb_init_phy_params_82575(hw); 710 711 out: 712 return ret_val; 713 } 714 715 /** 716 * igb_acquire_phy_82575 - Acquire rights to access PHY 717 * @hw: pointer to the HW structure 718 * 719 * Acquire access rights to the correct PHY. This is a 720 * function pointer entry point called by the api module. 721 **/ 722 static s32 igb_acquire_phy_82575(struct e1000_hw *hw) 723 { 724 u16 mask = E1000_SWFW_PHY0_SM; 725 726 if (hw->bus.func == E1000_FUNC_1) 727 mask = E1000_SWFW_PHY1_SM; 728 else if (hw->bus.func == E1000_FUNC_2) 729 mask = E1000_SWFW_PHY2_SM; 730 else if (hw->bus.func == E1000_FUNC_3) 731 mask = E1000_SWFW_PHY3_SM; 732 733 return hw->mac.ops.acquire_swfw_sync(hw, mask); 734 } 735 736 /** 737 * igb_release_phy_82575 - Release rights to access PHY 738 * @hw: pointer to the HW structure 739 * 740 * A wrapper to release access rights to the correct PHY. This is a 741 * function pointer entry point called by the api module. 742 **/ 743 static void igb_release_phy_82575(struct e1000_hw *hw) 744 { 745 u16 mask = E1000_SWFW_PHY0_SM; 746 747 if (hw->bus.func == E1000_FUNC_1) 748 mask = E1000_SWFW_PHY1_SM; 749 else if (hw->bus.func == E1000_FUNC_2) 750 mask = E1000_SWFW_PHY2_SM; 751 else if (hw->bus.func == E1000_FUNC_3) 752 mask = E1000_SWFW_PHY3_SM; 753 754 hw->mac.ops.release_swfw_sync(hw, mask); 755 } 756 757 /** 758 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 759 * @hw: pointer to the HW structure 760 * @offset: register offset to be read 761 * @data: pointer to the read data 762 * 763 * Reads the PHY register at offset using the serial gigabit media independent 764 * interface and stores the retrieved information in data. 765 **/ 766 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 767 u16 *data) 768 { 769 s32 ret_val = -E1000_ERR_PARAM; 770 771 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 772 hw_dbg("PHY Address %u is out of range\n", offset); 773 goto out; 774 } 775 776 ret_val = hw->phy.ops.acquire(hw); 777 if (ret_val) 778 goto out; 779 780 ret_val = igb_read_phy_reg_i2c(hw, offset, data); 781 782 hw->phy.ops.release(hw); 783 784 out: 785 return ret_val; 786 } 787 788 /** 789 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 790 * @hw: pointer to the HW structure 791 * @offset: register offset to write to 792 * @data: data to write at register offset 793 * 794 * Writes the data to PHY register at the offset using the serial gigabit 795 * media independent interface. 796 **/ 797 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 798 u16 data) 799 { 800 s32 ret_val = -E1000_ERR_PARAM; 801 802 803 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 804 hw_dbg("PHY Address %d is out of range\n", offset); 805 goto out; 806 } 807 808 ret_val = hw->phy.ops.acquire(hw); 809 if (ret_val) 810 goto out; 811 812 ret_val = igb_write_phy_reg_i2c(hw, offset, data); 813 814 hw->phy.ops.release(hw); 815 816 out: 817 return ret_val; 818 } 819 820 /** 821 * igb_get_phy_id_82575 - Retrieve PHY addr and id 822 * @hw: pointer to the HW structure 823 * 824 * Retrieves the PHY address and ID for both PHY's which do and do not use 825 * sgmi interface. 826 **/ 827 static s32 igb_get_phy_id_82575(struct e1000_hw *hw) 828 { 829 struct e1000_phy_info *phy = &hw->phy; 830 s32 ret_val = 0; 831 u16 phy_id; 832 u32 ctrl_ext; 833 u32 mdic; 834 835 /* Extra read required for some PHY's on i354 */ 836 if (hw->mac.type == e1000_i354) 837 igb_get_phy_id(hw); 838 839 /* For SGMII PHYs, we try the list of possible addresses until 840 * we find one that works. For non-SGMII PHYs 841 * (e.g. integrated copper PHYs), an address of 1 should 842 * work. The result of this function should mean phy->phy_addr 843 * and phy->id are set correctly. 844 */ 845 if (!(igb_sgmii_active_82575(hw))) { 846 phy->addr = 1; 847 ret_val = igb_get_phy_id(hw); 848 goto out; 849 } 850 851 if (igb_sgmii_uses_mdio_82575(hw)) { 852 switch (hw->mac.type) { 853 case e1000_82575: 854 case e1000_82576: 855 mdic = rd32(E1000_MDIC); 856 mdic &= E1000_MDIC_PHY_MASK; 857 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; 858 break; 859 case e1000_82580: 860 case e1000_i350: 861 case e1000_i354: 862 case e1000_i210: 863 case e1000_i211: 864 mdic = rd32(E1000_MDICNFG); 865 mdic &= E1000_MDICNFG_PHY_MASK; 866 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 867 break; 868 default: 869 ret_val = -E1000_ERR_PHY; 870 goto out; 871 } 872 ret_val = igb_get_phy_id(hw); 873 goto out; 874 } 875 876 /* Power on sgmii phy if it is disabled */ 877 ctrl_ext = rd32(E1000_CTRL_EXT); 878 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 879 wrfl(); 880 msleep(300); 881 882 /* The address field in the I2CCMD register is 3 bits and 0 is invalid. 883 * Therefore, we need to test 1-7 884 */ 885 for (phy->addr = 1; phy->addr < 8; phy->addr++) { 886 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 887 if (ret_val == 0) { 888 hw_dbg("Vendor ID 0x%08X read at address %u\n", 889 phy_id, phy->addr); 890 /* At the time of this writing, The M88 part is 891 * the only supported SGMII PHY product. 892 */ 893 if (phy_id == M88_VENDOR) 894 break; 895 } else { 896 hw_dbg("PHY address %u was unreadable\n", phy->addr); 897 } 898 } 899 900 /* A valid PHY type couldn't be found. */ 901 if (phy->addr == 8) { 902 phy->addr = 0; 903 ret_val = -E1000_ERR_PHY; 904 goto out; 905 } else { 906 ret_val = igb_get_phy_id(hw); 907 } 908 909 /* restore previous sfp cage power state */ 910 wr32(E1000_CTRL_EXT, ctrl_ext); 911 912 out: 913 return ret_val; 914 } 915 916 /** 917 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset 918 * @hw: pointer to the HW structure 919 * 920 * Resets the PHY using the serial gigabit media independent interface. 921 **/ 922 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 923 { 924 struct e1000_phy_info *phy = &hw->phy; 925 s32 ret_val; 926 927 /* This isn't a true "hard" reset, but is the only reset 928 * available to us at this time. 929 */ 930 931 hw_dbg("Soft resetting SGMII attached PHY...\n"); 932 933 /* SFP documentation requires the following to configure the SPF module 934 * to work on SGMII. No further documentation is given. 935 */ 936 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 937 if (ret_val) 938 goto out; 939 940 ret_val = igb_phy_sw_reset(hw); 941 if (ret_val) 942 goto out; 943 944 if (phy->id == M88E1512_E_PHY_ID) 945 ret_val = igb_initialize_M88E1512_phy(hw); 946 if (phy->id == M88E1543_E_PHY_ID) 947 ret_val = igb_initialize_M88E1543_phy(hw); 948 out: 949 return ret_val; 950 } 951 952 /** 953 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 954 * @hw: pointer to the HW structure 955 * @active: true to enable LPLU, false to disable 956 * 957 * Sets the LPLU D0 state according to the active flag. When 958 * activating LPLU this function also disables smart speed 959 * and vice versa. LPLU will not be activated unless the 960 * device autonegotiation advertisement meets standards of 961 * either 10 or 10/100 or 10/100/1000 at all duplexes. 962 * This is a function pointer entry point only called by 963 * PHY setup routines. 964 **/ 965 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 966 { 967 struct e1000_phy_info *phy = &hw->phy; 968 s32 ret_val; 969 u16 data; 970 971 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 972 if (ret_val) 973 goto out; 974 975 if (active) { 976 data |= IGP02E1000_PM_D0_LPLU; 977 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 978 data); 979 if (ret_val) 980 goto out; 981 982 /* When LPLU is enabled, we should disable SmartSpeed */ 983 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 984 &data); 985 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 986 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 987 data); 988 if (ret_val) 989 goto out; 990 } else { 991 data &= ~IGP02E1000_PM_D0_LPLU; 992 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 993 data); 994 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 995 * during Dx states where the power conservation is most 996 * important. During driver activity we should enable 997 * SmartSpeed, so performance is maintained. 998 */ 999 if (phy->smart_speed == e1000_smart_speed_on) { 1000 ret_val = phy->ops.read_reg(hw, 1001 IGP01E1000_PHY_PORT_CONFIG, &data); 1002 if (ret_val) 1003 goto out; 1004 1005 data |= IGP01E1000_PSCFR_SMART_SPEED; 1006 ret_val = phy->ops.write_reg(hw, 1007 IGP01E1000_PHY_PORT_CONFIG, data); 1008 if (ret_val) 1009 goto out; 1010 } else if (phy->smart_speed == e1000_smart_speed_off) { 1011 ret_val = phy->ops.read_reg(hw, 1012 IGP01E1000_PHY_PORT_CONFIG, &data); 1013 if (ret_val) 1014 goto out; 1015 1016 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1017 ret_val = phy->ops.write_reg(hw, 1018 IGP01E1000_PHY_PORT_CONFIG, data); 1019 if (ret_val) 1020 goto out; 1021 } 1022 } 1023 1024 out: 1025 return ret_val; 1026 } 1027 1028 /** 1029 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state 1030 * @hw: pointer to the HW structure 1031 * @active: true to enable LPLU, false to disable 1032 * 1033 * Sets the LPLU D0 state according to the active flag. When 1034 * activating LPLU this function also disables smart speed 1035 * and vice versa. LPLU will not be activated unless the 1036 * device autonegotiation advertisement meets standards of 1037 * either 10 or 10/100 or 10/100/1000 at all duplexes. 1038 * This is a function pointer entry point only called by 1039 * PHY setup routines. 1040 **/ 1041 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) 1042 { 1043 struct e1000_phy_info *phy = &hw->phy; 1044 u16 data; 1045 1046 data = rd32(E1000_82580_PHY_POWER_MGMT); 1047 1048 if (active) { 1049 data |= E1000_82580_PM_D0_LPLU; 1050 1051 /* When LPLU is enabled, we should disable SmartSpeed */ 1052 data &= ~E1000_82580_PM_SPD; 1053 } else { 1054 data &= ~E1000_82580_PM_D0_LPLU; 1055 1056 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1057 * during Dx states where the power conservation is most 1058 * important. During driver activity we should enable 1059 * SmartSpeed, so performance is maintained. 1060 */ 1061 if (phy->smart_speed == e1000_smart_speed_on) 1062 data |= E1000_82580_PM_SPD; 1063 else if (phy->smart_speed == e1000_smart_speed_off) 1064 data &= ~E1000_82580_PM_SPD; } 1065 1066 wr32(E1000_82580_PHY_POWER_MGMT, data); 1067 return 0; 1068 } 1069 1070 /** 1071 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3 1072 * @hw: pointer to the HW structure 1073 * @active: boolean used to enable/disable lplu 1074 * 1075 * Success returns 0, Failure returns 1 1076 * 1077 * The low power link up (lplu) state is set to the power management level D3 1078 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1079 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1080 * is used during Dx states where the power conservation is most important. 1081 * During driver activity, SmartSpeed should be enabled so performance is 1082 * maintained. 1083 **/ 1084 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) 1085 { 1086 struct e1000_phy_info *phy = &hw->phy; 1087 u16 data; 1088 1089 data = rd32(E1000_82580_PHY_POWER_MGMT); 1090 1091 if (!active) { 1092 data &= ~E1000_82580_PM_D3_LPLU; 1093 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1094 * during Dx states where the power conservation is most 1095 * important. During driver activity we should enable 1096 * SmartSpeed, so performance is maintained. 1097 */ 1098 if (phy->smart_speed == e1000_smart_speed_on) 1099 data |= E1000_82580_PM_SPD; 1100 else if (phy->smart_speed == e1000_smart_speed_off) 1101 data &= ~E1000_82580_PM_SPD; 1102 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1103 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1104 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1105 data |= E1000_82580_PM_D3_LPLU; 1106 /* When LPLU is enabled, we should disable SmartSpeed */ 1107 data &= ~E1000_82580_PM_SPD; 1108 } 1109 1110 wr32(E1000_82580_PHY_POWER_MGMT, data); 1111 return 0; 1112 } 1113 1114 /** 1115 * igb_acquire_nvm_82575 - Request for access to EEPROM 1116 * @hw: pointer to the HW structure 1117 * 1118 * Acquire the necessary semaphores for exclusive access to the EEPROM. 1119 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 1120 * Return successful if access grant bit set, else clear the request for 1121 * EEPROM access and return -E1000_ERR_NVM (-1). 1122 **/ 1123 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw) 1124 { 1125 s32 ret_val; 1126 1127 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM); 1128 if (ret_val) 1129 goto out; 1130 1131 ret_val = igb_acquire_nvm(hw); 1132 1133 if (ret_val) 1134 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM); 1135 1136 out: 1137 return ret_val; 1138 } 1139 1140 /** 1141 * igb_release_nvm_82575 - Release exclusive access to EEPROM 1142 * @hw: pointer to the HW structure 1143 * 1144 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 1145 * then release the semaphores acquired. 1146 **/ 1147 static void igb_release_nvm_82575(struct e1000_hw *hw) 1148 { 1149 igb_release_nvm(hw); 1150 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM); 1151 } 1152 1153 /** 1154 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 1155 * @hw: pointer to the HW structure 1156 * @mask: specifies which semaphore to acquire 1157 * 1158 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 1159 * will also specify which port we're acquiring the lock for. 1160 **/ 1161 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1162 { 1163 u32 swfw_sync; 1164 u32 swmask = mask; 1165 u32 fwmask = mask << 16; 1166 s32 ret_val = 0; 1167 s32 i = 0, timeout = 200; 1168 1169 while (i < timeout) { 1170 if (igb_get_hw_semaphore(hw)) { 1171 ret_val = -E1000_ERR_SWFW_SYNC; 1172 goto out; 1173 } 1174 1175 swfw_sync = rd32(E1000_SW_FW_SYNC); 1176 if (!(swfw_sync & (fwmask | swmask))) 1177 break; 1178 1179 /* Firmware currently using resource (fwmask) 1180 * or other software thread using resource (swmask) 1181 */ 1182 igb_put_hw_semaphore(hw); 1183 mdelay(5); 1184 i++; 1185 } 1186 1187 if (i == timeout) { 1188 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1189 ret_val = -E1000_ERR_SWFW_SYNC; 1190 goto out; 1191 } 1192 1193 swfw_sync |= swmask; 1194 wr32(E1000_SW_FW_SYNC, swfw_sync); 1195 1196 igb_put_hw_semaphore(hw); 1197 1198 out: 1199 return ret_val; 1200 } 1201 1202 /** 1203 * igb_release_swfw_sync_82575 - Release SW/FW semaphore 1204 * @hw: pointer to the HW structure 1205 * @mask: specifies which semaphore to acquire 1206 * 1207 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 1208 * will also specify which port we're releasing the lock for. 1209 **/ 1210 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1211 { 1212 u32 swfw_sync; 1213 1214 while (igb_get_hw_semaphore(hw) != 0) 1215 ; /* Empty */ 1216 1217 swfw_sync = rd32(E1000_SW_FW_SYNC); 1218 swfw_sync &= ~mask; 1219 wr32(E1000_SW_FW_SYNC, swfw_sync); 1220 1221 igb_put_hw_semaphore(hw); 1222 } 1223 1224 /** 1225 * igb_get_cfg_done_82575 - Read config done bit 1226 * @hw: pointer to the HW structure 1227 * 1228 * Read the management control register for the config done bit for 1229 * completion status. NOTE: silicon which is EEPROM-less will fail trying 1230 * to read the config done bit, so an error is *ONLY* logged and returns 1231 * 0. If we were to return with error, EEPROM-less silicon 1232 * would not be able to be reset or change link. 1233 **/ 1234 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw) 1235 { 1236 s32 timeout = PHY_CFG_TIMEOUT; 1237 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 1238 1239 if (hw->bus.func == 1) 1240 mask = E1000_NVM_CFG_DONE_PORT_1; 1241 else if (hw->bus.func == E1000_FUNC_2) 1242 mask = E1000_NVM_CFG_DONE_PORT_2; 1243 else if (hw->bus.func == E1000_FUNC_3) 1244 mask = E1000_NVM_CFG_DONE_PORT_3; 1245 1246 while (timeout) { 1247 if (rd32(E1000_EEMNGCTL) & mask) 1248 break; 1249 usleep_range(1000, 2000); 1250 timeout--; 1251 } 1252 if (!timeout) 1253 hw_dbg("MNG configuration cycle has not completed.\n"); 1254 1255 /* If EEPROM is not marked present, init the PHY manually */ 1256 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) && 1257 (hw->phy.type == e1000_phy_igp_3)) 1258 igb_phy_init_script_igp3(hw); 1259 1260 return 0; 1261 } 1262 1263 /** 1264 * igb_get_link_up_info_82575 - Get link speed/duplex info 1265 * @hw: pointer to the HW structure 1266 * @speed: stores the current speed 1267 * @duplex: stores the current duplex 1268 * 1269 * This is a wrapper function, if using the serial gigabit media independent 1270 * interface, use PCS to retrieve the link speed and duplex information. 1271 * Otherwise, use the generic function to get the link speed and duplex info. 1272 **/ 1273 static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 1274 u16 *duplex) 1275 { 1276 s32 ret_val; 1277 1278 if (hw->phy.media_type != e1000_media_type_copper) 1279 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed, 1280 duplex); 1281 else 1282 ret_val = igb_get_speed_and_duplex_copper(hw, speed, 1283 duplex); 1284 1285 return ret_val; 1286 } 1287 1288 /** 1289 * igb_check_for_link_82575 - Check for link 1290 * @hw: pointer to the HW structure 1291 * 1292 * If sgmii is enabled, then use the pcs register to determine link, otherwise 1293 * use the generic interface for determining link. 1294 **/ 1295 static s32 igb_check_for_link_82575(struct e1000_hw *hw) 1296 { 1297 s32 ret_val; 1298 u16 speed, duplex; 1299 1300 if (hw->phy.media_type != e1000_media_type_copper) { 1301 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, 1302 &duplex); 1303 /* Use this flag to determine if link needs to be checked or 1304 * not. If we have link clear the flag so that we do not 1305 * continue to check for link. 1306 */ 1307 hw->mac.get_link_status = !hw->mac.serdes_has_link; 1308 1309 /* Configure Flow Control now that Auto-Neg has completed. 1310 * First, we need to restore the desired flow control 1311 * settings because we may have had to re-autoneg with a 1312 * different link partner. 1313 */ 1314 ret_val = igb_config_fc_after_link_up(hw); 1315 if (ret_val) 1316 hw_dbg("Error configuring flow control\n"); 1317 } else { 1318 ret_val = igb_check_for_copper_link(hw); 1319 } 1320 1321 return ret_val; 1322 } 1323 1324 /** 1325 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown 1326 * @hw: pointer to the HW structure 1327 **/ 1328 void igb_power_up_serdes_link_82575(struct e1000_hw *hw) 1329 { 1330 u32 reg; 1331 1332 1333 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1334 !igb_sgmii_active_82575(hw)) 1335 return; 1336 1337 /* Enable PCS to turn on link */ 1338 reg = rd32(E1000_PCS_CFG0); 1339 reg |= E1000_PCS_CFG_PCS_EN; 1340 wr32(E1000_PCS_CFG0, reg); 1341 1342 /* Power up the laser */ 1343 reg = rd32(E1000_CTRL_EXT); 1344 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1345 wr32(E1000_CTRL_EXT, reg); 1346 1347 /* flush the write to verify completion */ 1348 wrfl(); 1349 usleep_range(1000, 2000); 1350 } 1351 1352 /** 1353 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 1354 * @hw: pointer to the HW structure 1355 * @speed: stores the current speed 1356 * @duplex: stores the current duplex 1357 * 1358 * Using the physical coding sub-layer (PCS), retrieve the current speed and 1359 * duplex, then store the values in the pointers provided. 1360 **/ 1361 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, 1362 u16 *duplex) 1363 { 1364 struct e1000_mac_info *mac = &hw->mac; 1365 u32 pcs, status; 1366 1367 /* Set up defaults for the return values of this function */ 1368 mac->serdes_has_link = false; 1369 *speed = 0; 1370 *duplex = 0; 1371 1372 /* Read the PCS Status register for link state. For non-copper mode, 1373 * the status register is not accurate. The PCS status register is 1374 * used instead. 1375 */ 1376 pcs = rd32(E1000_PCS_LSTAT); 1377 1378 /* The link up bit determines when link is up on autoneg. The sync ok 1379 * gets set once both sides sync up and agree upon link. Stable link 1380 * can be determined by checking for both link up and link sync ok 1381 */ 1382 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 1383 mac->serdes_has_link = true; 1384 1385 /* Detect and store PCS speed */ 1386 if (pcs & E1000_PCS_LSTS_SPEED_1000) 1387 *speed = SPEED_1000; 1388 else if (pcs & E1000_PCS_LSTS_SPEED_100) 1389 *speed = SPEED_100; 1390 else 1391 *speed = SPEED_10; 1392 1393 /* Detect and store PCS duplex */ 1394 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) 1395 *duplex = FULL_DUPLEX; 1396 else 1397 *duplex = HALF_DUPLEX; 1398 1399 /* Check if it is an I354 2.5Gb backplane connection. */ 1400 if (mac->type == e1000_i354) { 1401 status = rd32(E1000_STATUS); 1402 if ((status & E1000_STATUS_2P5_SKU) && 1403 !(status & E1000_STATUS_2P5_SKU_OVER)) { 1404 *speed = SPEED_2500; 1405 *duplex = FULL_DUPLEX; 1406 hw_dbg("2500 Mbs, "); 1407 hw_dbg("Full Duplex\n"); 1408 } 1409 } 1410 1411 } 1412 1413 return 0; 1414 } 1415 1416 /** 1417 * igb_shutdown_serdes_link_82575 - Remove link during power down 1418 * @hw: pointer to the HW structure 1419 * 1420 * In the case of fiber serdes, shut down optics and PCS on driver unload 1421 * when management pass thru is not enabled. 1422 **/ 1423 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw) 1424 { 1425 u32 reg; 1426 1427 if (hw->phy.media_type != e1000_media_type_internal_serdes && 1428 igb_sgmii_active_82575(hw)) 1429 return; 1430 1431 if (!igb_enable_mng_pass_thru(hw)) { 1432 /* Disable PCS to turn off link */ 1433 reg = rd32(E1000_PCS_CFG0); 1434 reg &= ~E1000_PCS_CFG_PCS_EN; 1435 wr32(E1000_PCS_CFG0, reg); 1436 1437 /* shutdown the laser */ 1438 reg = rd32(E1000_CTRL_EXT); 1439 reg |= E1000_CTRL_EXT_SDP3_DATA; 1440 wr32(E1000_CTRL_EXT, reg); 1441 1442 /* flush the write to verify completion */ 1443 wrfl(); 1444 usleep_range(1000, 2000); 1445 } 1446 } 1447 1448 /** 1449 * igb_reset_hw_82575 - Reset hardware 1450 * @hw: pointer to the HW structure 1451 * 1452 * This resets the hardware into a known state. This is a 1453 * function pointer entry point called by the api module. 1454 **/ 1455 static s32 igb_reset_hw_82575(struct e1000_hw *hw) 1456 { 1457 u32 ctrl; 1458 s32 ret_val; 1459 1460 /* Prevent the PCI-E bus from sticking if there is no TLP connection 1461 * on the last TLP read/write transaction when MAC is reset. 1462 */ 1463 ret_val = igb_disable_pcie_master(hw); 1464 if (ret_val) 1465 hw_dbg("PCI-E Master disable polling has failed.\n"); 1466 1467 /* set the completion timeout for interface */ 1468 ret_val = igb_set_pcie_completion_timeout(hw); 1469 if (ret_val) 1470 hw_dbg("PCI-E Set completion timeout has failed.\n"); 1471 1472 hw_dbg("Masking off all interrupts\n"); 1473 wr32(E1000_IMC, 0xffffffff); 1474 1475 wr32(E1000_RCTL, 0); 1476 wr32(E1000_TCTL, E1000_TCTL_PSP); 1477 wrfl(); 1478 1479 usleep_range(10000, 20000); 1480 1481 ctrl = rd32(E1000_CTRL); 1482 1483 hw_dbg("Issuing a global reset to MAC\n"); 1484 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST); 1485 1486 ret_val = igb_get_auto_rd_done(hw); 1487 if (ret_val) { 1488 /* When auto config read does not complete, do not 1489 * return with an error. This can happen in situations 1490 * where there is no eeprom and prevents getting link. 1491 */ 1492 hw_dbg("Auto Read Done did not complete\n"); 1493 } 1494 1495 /* If EEPROM is not present, run manual init scripts */ 1496 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) 1497 igb_reset_init_script_82575(hw); 1498 1499 /* Clear any pending interrupt events. */ 1500 wr32(E1000_IMC, 0xffffffff); 1501 rd32(E1000_ICR); 1502 1503 /* Install any alternate MAC address into RAR0 */ 1504 ret_val = igb_check_alt_mac_addr(hw); 1505 1506 return ret_val; 1507 } 1508 1509 /** 1510 * igb_init_hw_82575 - Initialize hardware 1511 * @hw: pointer to the HW structure 1512 * 1513 * This inits the hardware readying it for operation. 1514 **/ 1515 static s32 igb_init_hw_82575(struct e1000_hw *hw) 1516 { 1517 struct e1000_mac_info *mac = &hw->mac; 1518 s32 ret_val; 1519 u16 i, rar_count = mac->rar_entry_count; 1520 1521 if ((hw->mac.type >= e1000_i210) && 1522 !(igb_get_flash_presence_i210(hw))) { 1523 ret_val = igb_pll_workaround_i210(hw); 1524 if (ret_val) 1525 return ret_val; 1526 } 1527 1528 /* Initialize identification LED */ 1529 ret_val = igb_id_led_init(hw); 1530 if (ret_val) { 1531 hw_dbg("Error initializing identification LED\n"); 1532 /* This is not fatal and we should not stop init due to this */ 1533 } 1534 1535 /* Disabling VLAN filtering */ 1536 hw_dbg("Initializing the IEEE VLAN\n"); 1537 igb_clear_vfta(hw); 1538 1539 /* Setup the receive address */ 1540 igb_init_rx_addrs(hw, rar_count); 1541 1542 /* Zero out the Multicast HASH table */ 1543 hw_dbg("Zeroing the MTA\n"); 1544 for (i = 0; i < mac->mta_reg_count; i++) 1545 array_wr32(E1000_MTA, i, 0); 1546 1547 /* Zero out the Unicast HASH table */ 1548 hw_dbg("Zeroing the UTA\n"); 1549 for (i = 0; i < mac->uta_reg_count; i++) 1550 array_wr32(E1000_UTA, i, 0); 1551 1552 /* Setup link and flow control */ 1553 ret_val = igb_setup_link(hw); 1554 1555 /* Clear all of the statistics registers (clear on read). It is 1556 * important that we do this after we have tried to establish link 1557 * because the symbol error count will increment wildly if there 1558 * is no link. 1559 */ 1560 igb_clear_hw_cntrs_82575(hw); 1561 return ret_val; 1562 } 1563 1564 /** 1565 * igb_setup_copper_link_82575 - Configure copper link settings 1566 * @hw: pointer to the HW structure 1567 * 1568 * Configures the link for auto-neg or forced speed and duplex. Then we check 1569 * for link, once link is established calls to configure collision distance 1570 * and flow control are called. 1571 **/ 1572 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw) 1573 { 1574 u32 ctrl; 1575 s32 ret_val; 1576 u32 phpm_reg; 1577 1578 ctrl = rd32(E1000_CTRL); 1579 ctrl |= E1000_CTRL_SLU; 1580 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1581 wr32(E1000_CTRL, ctrl); 1582 1583 /* Clear Go Link Disconnect bit on supported devices */ 1584 switch (hw->mac.type) { 1585 case e1000_82580: 1586 case e1000_i350: 1587 case e1000_i210: 1588 case e1000_i211: 1589 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT); 1590 phpm_reg &= ~E1000_82580_PM_GO_LINKD; 1591 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg); 1592 break; 1593 default: 1594 break; 1595 } 1596 1597 ret_val = igb_setup_serdes_link_82575(hw); 1598 if (ret_val) 1599 goto out; 1600 1601 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) { 1602 /* allow time for SFP cage time to power up phy */ 1603 msleep(300); 1604 1605 ret_val = hw->phy.ops.reset(hw); 1606 if (ret_val) { 1607 hw_dbg("Error resetting the PHY.\n"); 1608 goto out; 1609 } 1610 } 1611 switch (hw->phy.type) { 1612 case e1000_phy_i210: 1613 case e1000_phy_m88: 1614 switch (hw->phy.id) { 1615 case I347AT4_E_PHY_ID: 1616 case M88E1112_E_PHY_ID: 1617 case M88E1543_E_PHY_ID: 1618 case M88E1512_E_PHY_ID: 1619 case I210_I_PHY_ID: 1620 ret_val = igb_copper_link_setup_m88_gen2(hw); 1621 break; 1622 default: 1623 ret_val = igb_copper_link_setup_m88(hw); 1624 break; 1625 } 1626 break; 1627 case e1000_phy_igp_3: 1628 ret_val = igb_copper_link_setup_igp(hw); 1629 break; 1630 case e1000_phy_82580: 1631 ret_val = igb_copper_link_setup_82580(hw); 1632 break; 1633 case e1000_phy_bcm54616: 1634 ret_val = 0; 1635 break; 1636 default: 1637 ret_val = -E1000_ERR_PHY; 1638 break; 1639 } 1640 1641 if (ret_val) 1642 goto out; 1643 1644 ret_val = igb_setup_copper_link(hw); 1645 out: 1646 return ret_val; 1647 } 1648 1649 /** 1650 * igb_setup_serdes_link_82575 - Setup link for serdes 1651 * @hw: pointer to the HW structure 1652 * 1653 * Configure the physical coding sub-layer (PCS) link. The PCS link is 1654 * used on copper connections where the serialized gigabit media independent 1655 * interface (sgmii), or serdes fiber is being used. Configures the link 1656 * for auto-negotiation or forces speed/duplex. 1657 **/ 1658 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw) 1659 { 1660 u32 ctrl_ext, ctrl_reg, reg, anadv_reg; 1661 bool pcs_autoneg; 1662 s32 ret_val = 0; 1663 u16 data; 1664 1665 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1666 !igb_sgmii_active_82575(hw)) 1667 return ret_val; 1668 1669 1670 /* On the 82575, SerDes loopback mode persists until it is 1671 * explicitly turned off or a power cycle is performed. A read to 1672 * the register does not indicate its status. Therefore, we ensure 1673 * loopback mode is disabled during initialization. 1674 */ 1675 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1676 1677 /* power on the sfp cage if present and turn on I2C */ 1678 ctrl_ext = rd32(E1000_CTRL_EXT); 1679 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1680 ctrl_ext |= E1000_CTRL_I2C_ENA; 1681 wr32(E1000_CTRL_EXT, ctrl_ext); 1682 1683 ctrl_reg = rd32(E1000_CTRL); 1684 ctrl_reg |= E1000_CTRL_SLU; 1685 1686 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { 1687 /* set both sw defined pins */ 1688 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1689 1690 /* Set switch control to serdes energy detect */ 1691 reg = rd32(E1000_CONNSW); 1692 reg |= E1000_CONNSW_ENRGSRC; 1693 wr32(E1000_CONNSW, reg); 1694 } 1695 1696 reg = rd32(E1000_PCS_LCTL); 1697 1698 /* default pcs_autoneg to the same setting as mac autoneg */ 1699 pcs_autoneg = hw->mac.autoneg; 1700 1701 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1702 case E1000_CTRL_EXT_LINK_MODE_SGMII: 1703 /* sgmii mode lets the phy handle forcing speed/duplex */ 1704 pcs_autoneg = true; 1705 /* autoneg time out should be disabled for SGMII mode */ 1706 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1707 break; 1708 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1709 /* disable PCS autoneg and support parallel detect only */ 1710 pcs_autoneg = false; 1711 /* fall through */ 1712 default: 1713 if (hw->mac.type == e1000_82575 || 1714 hw->mac.type == e1000_82576) { 1715 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data); 1716 if (ret_val) { 1717 hw_dbg(KERN_DEBUG "NVM Read Error\n\n"); 1718 return ret_val; 1719 } 1720 1721 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT) 1722 pcs_autoneg = false; 1723 } 1724 1725 /* non-SGMII modes only supports a speed of 1000/Full for the 1726 * link so it is best to just force the MAC and let the pcs 1727 * link either autoneg or be forced to 1000/Full 1728 */ 1729 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | 1730 E1000_CTRL_FD | E1000_CTRL_FRCDPX; 1731 1732 /* set speed of 1000/Full if speed/duplex is forced */ 1733 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1734 break; 1735 } 1736 1737 wr32(E1000_CTRL, ctrl_reg); 1738 1739 /* New SerDes mode allows for forcing speed or autonegotiating speed 1740 * at 1gb. Autoneg should be default set by most drivers. This is the 1741 * mode that will be compatible with older link partners and switches. 1742 * However, both are supported by the hardware and some drivers/tools. 1743 */ 1744 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1745 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1746 1747 if (pcs_autoneg) { 1748 /* Set PCS register for autoneg */ 1749 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1750 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1751 1752 /* Disable force flow control for autoneg */ 1753 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL; 1754 1755 /* Configure flow control advertisement for autoneg */ 1756 anadv_reg = rd32(E1000_PCS_ANADV); 1757 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE); 1758 switch (hw->fc.requested_mode) { 1759 case e1000_fc_full: 1760 case e1000_fc_rx_pause: 1761 anadv_reg |= E1000_TXCW_ASM_DIR; 1762 anadv_reg |= E1000_TXCW_PAUSE; 1763 break; 1764 case e1000_fc_tx_pause: 1765 anadv_reg |= E1000_TXCW_ASM_DIR; 1766 break; 1767 default: 1768 break; 1769 } 1770 wr32(E1000_PCS_ANADV, anadv_reg); 1771 1772 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); 1773 } else { 1774 /* Set PCS register for forced link */ 1775 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1776 1777 /* Force flow control for forced link */ 1778 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1779 1780 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); 1781 } 1782 1783 wr32(E1000_PCS_LCTL, reg); 1784 1785 if (!pcs_autoneg && !igb_sgmii_active_82575(hw)) 1786 igb_force_mac_fc(hw); 1787 1788 return ret_val; 1789 } 1790 1791 /** 1792 * igb_sgmii_active_82575 - Return sgmii state 1793 * @hw: pointer to the HW structure 1794 * 1795 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1796 * which can be enabled for use in the embedded applications. Simply 1797 * return the current state of the sgmii interface. 1798 **/ 1799 static bool igb_sgmii_active_82575(struct e1000_hw *hw) 1800 { 1801 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1802 return dev_spec->sgmii_active; 1803 } 1804 1805 /** 1806 * igb_reset_init_script_82575 - Inits HW defaults after reset 1807 * @hw: pointer to the HW structure 1808 * 1809 * Inits recommended HW defaults after a reset when there is no EEPROM 1810 * detected. This is only for the 82575. 1811 **/ 1812 static s32 igb_reset_init_script_82575(struct e1000_hw *hw) 1813 { 1814 if (hw->mac.type == e1000_82575) { 1815 hw_dbg("Running reset init script for 82575\n"); 1816 /* SerDes configuration via SERDESCTRL */ 1817 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C); 1818 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78); 1819 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23); 1820 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15); 1821 1822 /* CCM configuration via CCMCTL register */ 1823 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00); 1824 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00); 1825 1826 /* PCIe lanes configuration */ 1827 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC); 1828 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF); 1829 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05); 1830 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81); 1831 1832 /* PCIe PLL Configuration */ 1833 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47); 1834 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00); 1835 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00); 1836 } 1837 1838 return 0; 1839 } 1840 1841 /** 1842 * igb_read_mac_addr_82575 - Read device MAC address 1843 * @hw: pointer to the HW structure 1844 **/ 1845 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw) 1846 { 1847 s32 ret_val = 0; 1848 1849 /* If there's an alternate MAC address place it in RAR0 1850 * so that it will override the Si installed default perm 1851 * address. 1852 */ 1853 ret_val = igb_check_alt_mac_addr(hw); 1854 if (ret_val) 1855 goto out; 1856 1857 ret_val = igb_read_mac_addr(hw); 1858 1859 out: 1860 return ret_val; 1861 } 1862 1863 /** 1864 * igb_power_down_phy_copper_82575 - Remove link during PHY power down 1865 * @hw: pointer to the HW structure 1866 * 1867 * In the case of a PHY power down to save power, or to turn off link during a 1868 * driver unload, or wake on lan is not enabled, remove the link. 1869 **/ 1870 void igb_power_down_phy_copper_82575(struct e1000_hw *hw) 1871 { 1872 /* If the management interface is not enabled, then power down */ 1873 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw))) 1874 igb_power_down_phy_copper(hw); 1875 } 1876 1877 /** 1878 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters 1879 * @hw: pointer to the HW structure 1880 * 1881 * Clears the hardware counters by reading the counter registers. 1882 **/ 1883 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw) 1884 { 1885 igb_clear_hw_cntrs_base(hw); 1886 1887 rd32(E1000_PRC64); 1888 rd32(E1000_PRC127); 1889 rd32(E1000_PRC255); 1890 rd32(E1000_PRC511); 1891 rd32(E1000_PRC1023); 1892 rd32(E1000_PRC1522); 1893 rd32(E1000_PTC64); 1894 rd32(E1000_PTC127); 1895 rd32(E1000_PTC255); 1896 rd32(E1000_PTC511); 1897 rd32(E1000_PTC1023); 1898 rd32(E1000_PTC1522); 1899 1900 rd32(E1000_ALGNERRC); 1901 rd32(E1000_RXERRC); 1902 rd32(E1000_TNCRS); 1903 rd32(E1000_CEXTERR); 1904 rd32(E1000_TSCTC); 1905 rd32(E1000_TSCTFC); 1906 1907 rd32(E1000_MGTPRC); 1908 rd32(E1000_MGTPDC); 1909 rd32(E1000_MGTPTC); 1910 1911 rd32(E1000_IAC); 1912 rd32(E1000_ICRXOC); 1913 1914 rd32(E1000_ICRXPTC); 1915 rd32(E1000_ICRXATC); 1916 rd32(E1000_ICTXPTC); 1917 rd32(E1000_ICTXATC); 1918 rd32(E1000_ICTXQEC); 1919 rd32(E1000_ICTXQMTC); 1920 rd32(E1000_ICRXDMTC); 1921 1922 rd32(E1000_CBTMPC); 1923 rd32(E1000_HTDPMC); 1924 rd32(E1000_CBRMPC); 1925 rd32(E1000_RPTHC); 1926 rd32(E1000_HGPTC); 1927 rd32(E1000_HTCBDPC); 1928 rd32(E1000_HGORCL); 1929 rd32(E1000_HGORCH); 1930 rd32(E1000_HGOTCL); 1931 rd32(E1000_HGOTCH); 1932 rd32(E1000_LENERRS); 1933 1934 /* This register should not be read in copper configurations */ 1935 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1936 igb_sgmii_active_82575(hw)) 1937 rd32(E1000_SCVPC); 1938 } 1939 1940 /** 1941 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable 1942 * @hw: pointer to the HW structure 1943 * 1944 * After rx enable if manageability is enabled then there is likely some 1945 * bad data at the start of the fifo and possibly in the DMA fifo. This 1946 * function clears the fifos and flushes any packets that came in as rx was 1947 * being enabled. 1948 **/ 1949 void igb_rx_fifo_flush_82575(struct e1000_hw *hw) 1950 { 1951 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 1952 int i, ms_wait; 1953 1954 /* disable IPv6 options as per hardware errata */ 1955 rfctl = rd32(E1000_RFCTL); 1956 rfctl |= E1000_RFCTL_IPV6_EX_DIS; 1957 wr32(E1000_RFCTL, rfctl); 1958 1959 if (hw->mac.type != e1000_82575 || 1960 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 1961 return; 1962 1963 /* Disable all RX queues */ 1964 for (i = 0; i < 4; i++) { 1965 rxdctl[i] = rd32(E1000_RXDCTL(i)); 1966 wr32(E1000_RXDCTL(i), 1967 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 1968 } 1969 /* Poll all queues to verify they have shut down */ 1970 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 1971 usleep_range(1000, 2000); 1972 rx_enabled = 0; 1973 for (i = 0; i < 4; i++) 1974 rx_enabled |= rd32(E1000_RXDCTL(i)); 1975 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 1976 break; 1977 } 1978 1979 if (ms_wait == 10) 1980 hw_dbg("Queue disable timed out after 10ms\n"); 1981 1982 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 1983 * incoming packets are rejected. Set enable and wait 2ms so that 1984 * any packet that was coming in as RCTL.EN was set is flushed 1985 */ 1986 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 1987 1988 rlpml = rd32(E1000_RLPML); 1989 wr32(E1000_RLPML, 0); 1990 1991 rctl = rd32(E1000_RCTL); 1992 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 1993 temp_rctl |= E1000_RCTL_LPE; 1994 1995 wr32(E1000_RCTL, temp_rctl); 1996 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN); 1997 wrfl(); 1998 usleep_range(2000, 3000); 1999 2000 /* Enable RX queues that were previously enabled and restore our 2001 * previous state 2002 */ 2003 for (i = 0; i < 4; i++) 2004 wr32(E1000_RXDCTL(i), rxdctl[i]); 2005 wr32(E1000_RCTL, rctl); 2006 wrfl(); 2007 2008 wr32(E1000_RLPML, rlpml); 2009 wr32(E1000_RFCTL, rfctl); 2010 2011 /* Flush receive errors generated by workaround */ 2012 rd32(E1000_ROC); 2013 rd32(E1000_RNBC); 2014 rd32(E1000_MPC); 2015 } 2016 2017 /** 2018 * igb_set_pcie_completion_timeout - set pci-e completion timeout 2019 * @hw: pointer to the HW structure 2020 * 2021 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 2022 * however the hardware default for these parts is 500us to 1ms which is less 2023 * than the 10ms recommended by the pci-e spec. To address this we need to 2024 * increase the value to either 10ms to 200ms for capability version 1 config, 2025 * or 16ms to 55ms for version 2. 2026 **/ 2027 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw) 2028 { 2029 u32 gcr = rd32(E1000_GCR); 2030 s32 ret_val = 0; 2031 u16 pcie_devctl2; 2032 2033 /* only take action if timeout value is defaulted to 0 */ 2034 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 2035 goto out; 2036 2037 /* if capabilities version is type 1 we can write the 2038 * timeout of 10ms to 200ms through the GCR register 2039 */ 2040 if (!(gcr & E1000_GCR_CAP_VER2)) { 2041 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 2042 goto out; 2043 } 2044 2045 /* for version 2 capabilities we need to write the config space 2046 * directly in order to set the completion timeout value for 2047 * 16ms to 55ms 2048 */ 2049 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2050 &pcie_devctl2); 2051 if (ret_val) 2052 goto out; 2053 2054 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 2055 2056 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2057 &pcie_devctl2); 2058 out: 2059 /* disable completion timeout resend */ 2060 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 2061 2062 wr32(E1000_GCR, gcr); 2063 return ret_val; 2064 } 2065 2066 /** 2067 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing 2068 * @hw: pointer to the hardware struct 2069 * @enable: state to enter, either enabled or disabled 2070 * @pf: Physical Function pool - do not set anti-spoofing for the PF 2071 * 2072 * enables/disables L2 switch anti-spoofing functionality. 2073 **/ 2074 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) 2075 { 2076 u32 reg_val, reg_offset; 2077 2078 switch (hw->mac.type) { 2079 case e1000_82576: 2080 reg_offset = E1000_DTXSWC; 2081 break; 2082 case e1000_i350: 2083 case e1000_i354: 2084 reg_offset = E1000_TXSWC; 2085 break; 2086 default: 2087 return; 2088 } 2089 2090 reg_val = rd32(reg_offset); 2091 if (enable) { 2092 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK | 2093 E1000_DTXSWC_VLAN_SPOOF_MASK); 2094 /* The PF can spoof - it has to in order to 2095 * support emulation mode NICs 2096 */ 2097 reg_val ^= (BIT(pf) | BIT(pf + MAX_NUM_VFS)); 2098 } else { 2099 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | 2100 E1000_DTXSWC_VLAN_SPOOF_MASK); 2101 } 2102 wr32(reg_offset, reg_val); 2103 } 2104 2105 /** 2106 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback 2107 * @hw: pointer to the hardware struct 2108 * @enable: state to enter, either enabled or disabled 2109 * 2110 * enables/disables L2 switch loopback functionality. 2111 **/ 2112 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 2113 { 2114 u32 dtxswc; 2115 2116 switch (hw->mac.type) { 2117 case e1000_82576: 2118 dtxswc = rd32(E1000_DTXSWC); 2119 if (enable) 2120 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2121 else 2122 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2123 wr32(E1000_DTXSWC, dtxswc); 2124 break; 2125 case e1000_i354: 2126 case e1000_i350: 2127 dtxswc = rd32(E1000_TXSWC); 2128 if (enable) 2129 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2130 else 2131 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2132 wr32(E1000_TXSWC, dtxswc); 2133 break; 2134 default: 2135 /* Currently no other hardware supports loopback */ 2136 break; 2137 } 2138 2139 } 2140 2141 /** 2142 * igb_vmdq_set_replication_pf - enable or disable vmdq replication 2143 * @hw: pointer to the hardware struct 2144 * @enable: state to enter, either enabled or disabled 2145 * 2146 * enables/disables replication of packets across multiple pools. 2147 **/ 2148 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 2149 { 2150 u32 vt_ctl = rd32(E1000_VT_CTL); 2151 2152 if (enable) 2153 vt_ctl |= E1000_VT_CTL_VM_REPL_EN; 2154 else 2155 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; 2156 2157 wr32(E1000_VT_CTL, vt_ctl); 2158 } 2159 2160 /** 2161 * igb_read_phy_reg_82580 - Read 82580 MDI control register 2162 * @hw: pointer to the HW structure 2163 * @offset: register offset to be read 2164 * @data: pointer to the read data 2165 * 2166 * Reads the MDI control register in the PHY at offset and stores the 2167 * information read to data. 2168 **/ 2169 s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) 2170 { 2171 s32 ret_val; 2172 2173 ret_val = hw->phy.ops.acquire(hw); 2174 if (ret_val) 2175 goto out; 2176 2177 ret_val = igb_read_phy_reg_mdic(hw, offset, data); 2178 2179 hw->phy.ops.release(hw); 2180 2181 out: 2182 return ret_val; 2183 } 2184 2185 /** 2186 * igb_write_phy_reg_82580 - Write 82580 MDI control register 2187 * @hw: pointer to the HW structure 2188 * @offset: register offset to write to 2189 * @data: data to write to register at offset 2190 * 2191 * Writes data to MDI control register in the PHY at offset. 2192 **/ 2193 s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) 2194 { 2195 s32 ret_val; 2196 2197 2198 ret_val = hw->phy.ops.acquire(hw); 2199 if (ret_val) 2200 goto out; 2201 2202 ret_val = igb_write_phy_reg_mdic(hw, offset, data); 2203 2204 hw->phy.ops.release(hw); 2205 2206 out: 2207 return ret_val; 2208 } 2209 2210 /** 2211 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits 2212 * @hw: pointer to the HW structure 2213 * 2214 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on 2215 * the values found in the EEPROM. This addresses an issue in which these 2216 * bits are not restored from EEPROM after reset. 2217 **/ 2218 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw) 2219 { 2220 s32 ret_val = 0; 2221 u32 mdicnfg; 2222 u16 nvm_data = 0; 2223 2224 if (hw->mac.type != e1000_82580) 2225 goto out; 2226 if (!igb_sgmii_active_82575(hw)) 2227 goto out; 2228 2229 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2230 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2231 &nvm_data); 2232 if (ret_val) { 2233 hw_dbg("NVM Read Error\n"); 2234 goto out; 2235 } 2236 2237 mdicnfg = rd32(E1000_MDICNFG); 2238 if (nvm_data & NVM_WORD24_EXT_MDIO) 2239 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 2240 if (nvm_data & NVM_WORD24_COM_MDIO) 2241 mdicnfg |= E1000_MDICNFG_COM_MDIO; 2242 wr32(E1000_MDICNFG, mdicnfg); 2243 out: 2244 return ret_val; 2245 } 2246 2247 /** 2248 * igb_reset_hw_82580 - Reset hardware 2249 * @hw: pointer to the HW structure 2250 * 2251 * This resets function or entire device (all ports, etc.) 2252 * to a known state. 2253 **/ 2254 static s32 igb_reset_hw_82580(struct e1000_hw *hw) 2255 { 2256 s32 ret_val = 0; 2257 /* BH SW mailbox bit in SW_FW_SYNC */ 2258 u16 swmbsw_mask = E1000_SW_SYNCH_MB; 2259 u32 ctrl; 2260 bool global_device_reset = hw->dev_spec._82575.global_device_reset; 2261 2262 hw->dev_spec._82575.global_device_reset = false; 2263 2264 /* due to hw errata, global device reset doesn't always 2265 * work on 82580 2266 */ 2267 if (hw->mac.type == e1000_82580) 2268 global_device_reset = false; 2269 2270 /* Get current control state. */ 2271 ctrl = rd32(E1000_CTRL); 2272 2273 /* Prevent the PCI-E bus from sticking if there is no TLP connection 2274 * on the last TLP read/write transaction when MAC is reset. 2275 */ 2276 ret_val = igb_disable_pcie_master(hw); 2277 if (ret_val) 2278 hw_dbg("PCI-E Master disable polling has failed.\n"); 2279 2280 hw_dbg("Masking off all interrupts\n"); 2281 wr32(E1000_IMC, 0xffffffff); 2282 wr32(E1000_RCTL, 0); 2283 wr32(E1000_TCTL, E1000_TCTL_PSP); 2284 wrfl(); 2285 2286 usleep_range(10000, 11000); 2287 2288 /* Determine whether or not a global dev reset is requested */ 2289 if (global_device_reset && 2290 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask)) 2291 global_device_reset = false; 2292 2293 if (global_device_reset && 2294 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET)) 2295 ctrl |= E1000_CTRL_DEV_RST; 2296 else 2297 ctrl |= E1000_CTRL_RST; 2298 2299 wr32(E1000_CTRL, ctrl); 2300 wrfl(); 2301 2302 /* Add delay to insure DEV_RST has time to complete */ 2303 if (global_device_reset) 2304 usleep_range(5000, 6000); 2305 2306 ret_val = igb_get_auto_rd_done(hw); 2307 if (ret_val) { 2308 /* When auto config read does not complete, do not 2309 * return with an error. This can happen in situations 2310 * where there is no eeprom and prevents getting link. 2311 */ 2312 hw_dbg("Auto Read Done did not complete\n"); 2313 } 2314 2315 /* clear global device reset status bit */ 2316 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET); 2317 2318 /* Clear any pending interrupt events. */ 2319 wr32(E1000_IMC, 0xffffffff); 2320 rd32(E1000_ICR); 2321 2322 ret_val = igb_reset_mdicnfg_82580(hw); 2323 if (ret_val) 2324 hw_dbg("Could not reset MDICNFG based on EEPROM\n"); 2325 2326 /* Install any alternate MAC address into RAR0 */ 2327 ret_val = igb_check_alt_mac_addr(hw); 2328 2329 /* Release semaphore */ 2330 if (global_device_reset) 2331 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask); 2332 2333 return ret_val; 2334 } 2335 2336 /** 2337 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size 2338 * @data: data received by reading RXPBS register 2339 * 2340 * The 82580 uses a table based approach for packet buffer allocation sizes. 2341 * This function converts the retrieved value into the correct table value 2342 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 2343 * 0x0 36 72 144 1 2 4 8 16 2344 * 0x8 35 70 140 rsv rsv rsv rsv rsv 2345 */ 2346 u16 igb_rxpbs_adjust_82580(u32 data) 2347 { 2348 u16 ret_val = 0; 2349 2350 if (data < ARRAY_SIZE(e1000_82580_rxpbs_table)) 2351 ret_val = e1000_82580_rxpbs_table[data]; 2352 2353 return ret_val; 2354 } 2355 2356 /** 2357 * igb_validate_nvm_checksum_with_offset - Validate EEPROM 2358 * checksum 2359 * @hw: pointer to the HW structure 2360 * @offset: offset in words of the checksum protected region 2361 * 2362 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 2363 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 2364 **/ 2365 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw, 2366 u16 offset) 2367 { 2368 s32 ret_val = 0; 2369 u16 checksum = 0; 2370 u16 i, nvm_data; 2371 2372 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) { 2373 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2374 if (ret_val) { 2375 hw_dbg("NVM Read Error\n"); 2376 goto out; 2377 } 2378 checksum += nvm_data; 2379 } 2380 2381 if (checksum != (u16) NVM_SUM) { 2382 hw_dbg("NVM Checksum Invalid\n"); 2383 ret_val = -E1000_ERR_NVM; 2384 goto out; 2385 } 2386 2387 out: 2388 return ret_val; 2389 } 2390 2391 /** 2392 * igb_update_nvm_checksum_with_offset - Update EEPROM 2393 * checksum 2394 * @hw: pointer to the HW structure 2395 * @offset: offset in words of the checksum protected region 2396 * 2397 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 2398 * up to the checksum. Then calculates the EEPROM checksum and writes the 2399 * value to the EEPROM. 2400 **/ 2401 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2402 { 2403 s32 ret_val; 2404 u16 checksum = 0; 2405 u16 i, nvm_data; 2406 2407 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) { 2408 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2409 if (ret_val) { 2410 hw_dbg("NVM Read Error while updating checksum.\n"); 2411 goto out; 2412 } 2413 checksum += nvm_data; 2414 } 2415 checksum = (u16) NVM_SUM - checksum; 2416 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, 2417 &checksum); 2418 if (ret_val) 2419 hw_dbg("NVM Write Error while updating checksum.\n"); 2420 2421 out: 2422 return ret_val; 2423 } 2424 2425 /** 2426 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum 2427 * @hw: pointer to the HW structure 2428 * 2429 * Calculates the EEPROM section checksum by reading/adding each word of 2430 * the EEPROM and then verifies that the sum of the EEPROM is 2431 * equal to 0xBABA. 2432 **/ 2433 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw) 2434 { 2435 s32 ret_val = 0; 2436 u16 eeprom_regions_count = 1; 2437 u16 j, nvm_data; 2438 u16 nvm_offset; 2439 2440 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2441 if (ret_val) { 2442 hw_dbg("NVM Read Error\n"); 2443 goto out; 2444 } 2445 2446 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) { 2447 /* if checksums compatibility bit is set validate checksums 2448 * for all 4 ports. 2449 */ 2450 eeprom_regions_count = 4; 2451 } 2452 2453 for (j = 0; j < eeprom_regions_count; j++) { 2454 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2455 ret_val = igb_validate_nvm_checksum_with_offset(hw, 2456 nvm_offset); 2457 if (ret_val != 0) 2458 goto out; 2459 } 2460 2461 out: 2462 return ret_val; 2463 } 2464 2465 /** 2466 * igb_update_nvm_checksum_82580 - Update EEPROM checksum 2467 * @hw: pointer to the HW structure 2468 * 2469 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2470 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2471 * checksum and writes the value to the EEPROM. 2472 **/ 2473 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw) 2474 { 2475 s32 ret_val; 2476 u16 j, nvm_data; 2477 u16 nvm_offset; 2478 2479 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2480 if (ret_val) { 2481 hw_dbg("NVM Read Error while updating checksum compatibility bit.\n"); 2482 goto out; 2483 } 2484 2485 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) { 2486 /* set compatibility bit to validate checksums appropriately */ 2487 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK; 2488 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, 2489 &nvm_data); 2490 if (ret_val) { 2491 hw_dbg("NVM Write Error while updating checksum compatibility bit.\n"); 2492 goto out; 2493 } 2494 } 2495 2496 for (j = 0; j < 4; j++) { 2497 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2498 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset); 2499 if (ret_val) 2500 goto out; 2501 } 2502 2503 out: 2504 return ret_val; 2505 } 2506 2507 /** 2508 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum 2509 * @hw: pointer to the HW structure 2510 * 2511 * Calculates the EEPROM section checksum by reading/adding each word of 2512 * the EEPROM and then verifies that the sum of the EEPROM is 2513 * equal to 0xBABA. 2514 **/ 2515 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw) 2516 { 2517 s32 ret_val = 0; 2518 u16 j; 2519 u16 nvm_offset; 2520 2521 for (j = 0; j < 4; j++) { 2522 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2523 ret_val = igb_validate_nvm_checksum_with_offset(hw, 2524 nvm_offset); 2525 if (ret_val != 0) 2526 goto out; 2527 } 2528 2529 out: 2530 return ret_val; 2531 } 2532 2533 /** 2534 * igb_update_nvm_checksum_i350 - Update EEPROM checksum 2535 * @hw: pointer to the HW structure 2536 * 2537 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2538 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2539 * checksum and writes the value to the EEPROM. 2540 **/ 2541 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw) 2542 { 2543 s32 ret_val = 0; 2544 u16 j; 2545 u16 nvm_offset; 2546 2547 for (j = 0; j < 4; j++) { 2548 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2549 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset); 2550 if (ret_val != 0) 2551 goto out; 2552 } 2553 2554 out: 2555 return ret_val; 2556 } 2557 2558 /** 2559 * __igb_access_emi_reg - Read/write EMI register 2560 * @hw: pointer to the HW structure 2561 * @addr: EMI address to program 2562 * @data: pointer to value to read/write from/to the EMI address 2563 * @read: boolean flag to indicate read or write 2564 **/ 2565 static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address, 2566 u16 *data, bool read) 2567 { 2568 s32 ret_val = 0; 2569 2570 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address); 2571 if (ret_val) 2572 return ret_val; 2573 2574 if (read) 2575 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data); 2576 else 2577 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data); 2578 2579 return ret_val; 2580 } 2581 2582 /** 2583 * igb_read_emi_reg - Read Extended Management Interface register 2584 * @hw: pointer to the HW structure 2585 * @addr: EMI address to program 2586 * @data: value to be read from the EMI address 2587 **/ 2588 s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data) 2589 { 2590 return __igb_access_emi_reg(hw, addr, data, true); 2591 } 2592 2593 /** 2594 * igb_set_eee_i350 - Enable/disable EEE support 2595 * @hw: pointer to the HW structure 2596 * @adv1G: boolean flag enabling 1G EEE advertisement 2597 * @adv100m: boolean flag enabling 100M EEE advertisement 2598 * 2599 * Enable/disable EEE based on setting in dev_spec structure. 2600 * 2601 **/ 2602 s32 igb_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M) 2603 { 2604 u32 ipcnfg, eeer; 2605 2606 if ((hw->mac.type < e1000_i350) || 2607 (hw->phy.media_type != e1000_media_type_copper)) 2608 goto out; 2609 ipcnfg = rd32(E1000_IPCNFG); 2610 eeer = rd32(E1000_EEER); 2611 2612 /* enable or disable per user setting */ 2613 if (!(hw->dev_spec._82575.eee_disable)) { 2614 u32 eee_su = rd32(E1000_EEE_SU); 2615 2616 if (adv100M) 2617 ipcnfg |= E1000_IPCNFG_EEE_100M_AN; 2618 else 2619 ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN; 2620 2621 if (adv1G) 2622 ipcnfg |= E1000_IPCNFG_EEE_1G_AN; 2623 else 2624 ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN; 2625 2626 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 2627 E1000_EEER_LPI_FC); 2628 2629 /* This bit should not be set in normal operation. */ 2630 if (eee_su & E1000_EEE_SU_LPI_CLK_STP) 2631 hw_dbg("LPI Clock Stop Bit should not be set!\n"); 2632 2633 } else { 2634 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | 2635 E1000_IPCNFG_EEE_100M_AN); 2636 eeer &= ~(E1000_EEER_TX_LPI_EN | 2637 E1000_EEER_RX_LPI_EN | 2638 E1000_EEER_LPI_FC); 2639 } 2640 wr32(E1000_IPCNFG, ipcnfg); 2641 wr32(E1000_EEER, eeer); 2642 rd32(E1000_IPCNFG); 2643 rd32(E1000_EEER); 2644 out: 2645 2646 return 0; 2647 } 2648 2649 /** 2650 * igb_set_eee_i354 - Enable/disable EEE support 2651 * @hw: pointer to the HW structure 2652 * @adv1G: boolean flag enabling 1G EEE advertisement 2653 * @adv100m: boolean flag enabling 100M EEE advertisement 2654 * 2655 * Enable/disable EEE legacy mode based on setting in dev_spec structure. 2656 * 2657 **/ 2658 s32 igb_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M) 2659 { 2660 struct e1000_phy_info *phy = &hw->phy; 2661 s32 ret_val = 0; 2662 u16 phy_data; 2663 2664 if ((hw->phy.media_type != e1000_media_type_copper) || 2665 ((phy->id != M88E1543_E_PHY_ID) && 2666 (phy->id != M88E1512_E_PHY_ID))) 2667 goto out; 2668 2669 if (!hw->dev_spec._82575.eee_disable) { 2670 /* Switch to PHY page 18. */ 2671 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18); 2672 if (ret_val) 2673 goto out; 2674 2675 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1, 2676 &phy_data); 2677 if (ret_val) 2678 goto out; 2679 2680 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS; 2681 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1, 2682 phy_data); 2683 if (ret_val) 2684 goto out; 2685 2686 /* Return the PHY to page 0. */ 2687 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); 2688 if (ret_val) 2689 goto out; 2690 2691 /* Turn on EEE advertisement. */ 2692 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2693 E1000_EEE_ADV_DEV_I354, 2694 &phy_data); 2695 if (ret_val) 2696 goto out; 2697 2698 if (adv100M) 2699 phy_data |= E1000_EEE_ADV_100_SUPPORTED; 2700 else 2701 phy_data &= ~E1000_EEE_ADV_100_SUPPORTED; 2702 2703 if (adv1G) 2704 phy_data |= E1000_EEE_ADV_1000_SUPPORTED; 2705 else 2706 phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED; 2707 2708 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2709 E1000_EEE_ADV_DEV_I354, 2710 phy_data); 2711 } else { 2712 /* Turn off EEE advertisement. */ 2713 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2714 E1000_EEE_ADV_DEV_I354, 2715 &phy_data); 2716 if (ret_val) 2717 goto out; 2718 2719 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED | 2720 E1000_EEE_ADV_1000_SUPPORTED); 2721 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2722 E1000_EEE_ADV_DEV_I354, 2723 phy_data); 2724 } 2725 2726 out: 2727 return ret_val; 2728 } 2729 2730 /** 2731 * igb_get_eee_status_i354 - Get EEE status 2732 * @hw: pointer to the HW structure 2733 * @status: EEE status 2734 * 2735 * Get EEE status by guessing based on whether Tx or Rx LPI indications have 2736 * been received. 2737 **/ 2738 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status) 2739 { 2740 struct e1000_phy_info *phy = &hw->phy; 2741 s32 ret_val = 0; 2742 u16 phy_data; 2743 2744 /* Check if EEE is supported on this device. */ 2745 if ((hw->phy.media_type != e1000_media_type_copper) || 2746 ((phy->id != M88E1543_E_PHY_ID) && 2747 (phy->id != M88E1512_E_PHY_ID))) 2748 goto out; 2749 2750 ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354, 2751 E1000_PCS_STATUS_DEV_I354, 2752 &phy_data); 2753 if (ret_val) 2754 goto out; 2755 2756 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD | 2757 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false; 2758 2759 out: 2760 return ret_val; 2761 } 2762 2763 static const u8 e1000_emc_temp_data[4] = { 2764 E1000_EMC_INTERNAL_DATA, 2765 E1000_EMC_DIODE1_DATA, 2766 E1000_EMC_DIODE2_DATA, 2767 E1000_EMC_DIODE3_DATA 2768 }; 2769 static const u8 e1000_emc_therm_limit[4] = { 2770 E1000_EMC_INTERNAL_THERM_LIMIT, 2771 E1000_EMC_DIODE1_THERM_LIMIT, 2772 E1000_EMC_DIODE2_THERM_LIMIT, 2773 E1000_EMC_DIODE3_THERM_LIMIT 2774 }; 2775 2776 #ifdef CONFIG_IGB_HWMON 2777 /** 2778 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data 2779 * @hw: pointer to hardware structure 2780 * 2781 * Updates the temperatures in mac.thermal_sensor_data 2782 **/ 2783 static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw) 2784 { 2785 u16 ets_offset; 2786 u16 ets_cfg; 2787 u16 ets_sensor; 2788 u8 num_sensors; 2789 u8 sensor_index; 2790 u8 sensor_location; 2791 u8 i; 2792 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 2793 2794 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0)) 2795 return E1000_NOT_IMPLEMENTED; 2796 2797 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF); 2798 2799 /* Return the internal sensor only if ETS is unsupported */ 2800 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset); 2801 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) 2802 return 0; 2803 2804 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg); 2805 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT) 2806 != NVM_ETS_TYPE_EMC) 2807 return E1000_NOT_IMPLEMENTED; 2808 2809 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK); 2810 if (num_sensors > E1000_MAX_SENSORS) 2811 num_sensors = E1000_MAX_SENSORS; 2812 2813 for (i = 1; i < num_sensors; i++) { 2814 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor); 2815 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >> 2816 NVM_ETS_DATA_INDEX_SHIFT); 2817 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >> 2818 NVM_ETS_DATA_LOC_SHIFT); 2819 2820 if (sensor_location != 0) 2821 hw->phy.ops.read_i2c_byte(hw, 2822 e1000_emc_temp_data[sensor_index], 2823 E1000_I2C_THERMAL_SENSOR_ADDR, 2824 &data->sensor[i].temp); 2825 } 2826 return 0; 2827 } 2828 2829 /** 2830 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds 2831 * @hw: pointer to hardware structure 2832 * 2833 * Sets the thermal sensor thresholds according to the NVM map 2834 * and save off the threshold and location values into mac.thermal_sensor_data 2835 **/ 2836 static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw) 2837 { 2838 u16 ets_offset; 2839 u16 ets_cfg; 2840 u16 ets_sensor; 2841 u8 low_thresh_delta; 2842 u8 num_sensors; 2843 u8 sensor_index; 2844 u8 sensor_location; 2845 u8 therm_limit; 2846 u8 i; 2847 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 2848 2849 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0)) 2850 return E1000_NOT_IMPLEMENTED; 2851 2852 memset(data, 0, sizeof(struct e1000_thermal_sensor_data)); 2853 2854 data->sensor[0].location = 0x1; 2855 data->sensor[0].caution_thresh = 2856 (rd32(E1000_THHIGHTC) & 0xFF); 2857 data->sensor[0].max_op_thresh = 2858 (rd32(E1000_THLOWTC) & 0xFF); 2859 2860 /* Return the internal sensor only if ETS is unsupported */ 2861 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset); 2862 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) 2863 return 0; 2864 2865 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg); 2866 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT) 2867 != NVM_ETS_TYPE_EMC) 2868 return E1000_NOT_IMPLEMENTED; 2869 2870 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >> 2871 NVM_ETS_LTHRES_DELTA_SHIFT); 2872 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK); 2873 2874 for (i = 1; i <= num_sensors; i++) { 2875 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor); 2876 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >> 2877 NVM_ETS_DATA_INDEX_SHIFT); 2878 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >> 2879 NVM_ETS_DATA_LOC_SHIFT); 2880 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK; 2881 2882 hw->phy.ops.write_i2c_byte(hw, 2883 e1000_emc_therm_limit[sensor_index], 2884 E1000_I2C_THERMAL_SENSOR_ADDR, 2885 therm_limit); 2886 2887 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) { 2888 data->sensor[i].location = sensor_location; 2889 data->sensor[i].caution_thresh = therm_limit; 2890 data->sensor[i].max_op_thresh = therm_limit - 2891 low_thresh_delta; 2892 } 2893 } 2894 return 0; 2895 } 2896 2897 #endif 2898 static struct e1000_mac_operations e1000_mac_ops_82575 = { 2899 .init_hw = igb_init_hw_82575, 2900 .check_for_link = igb_check_for_link_82575, 2901 .rar_set = igb_rar_set, 2902 .read_mac_addr = igb_read_mac_addr_82575, 2903 .get_speed_and_duplex = igb_get_link_up_info_82575, 2904 #ifdef CONFIG_IGB_HWMON 2905 .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic, 2906 .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic, 2907 #endif 2908 }; 2909 2910 static const struct e1000_phy_operations e1000_phy_ops_82575 = { 2911 .acquire = igb_acquire_phy_82575, 2912 .get_cfg_done = igb_get_cfg_done_82575, 2913 .release = igb_release_phy_82575, 2914 .write_i2c_byte = igb_write_i2c_byte, 2915 .read_i2c_byte = igb_read_i2c_byte, 2916 }; 2917 2918 static struct e1000_nvm_operations e1000_nvm_ops_82575 = { 2919 .acquire = igb_acquire_nvm_82575, 2920 .read = igb_read_nvm_eerd, 2921 .release = igb_release_nvm_82575, 2922 .write = igb_write_nvm_spi, 2923 }; 2924 2925 const struct e1000_info e1000_82575_info = { 2926 .get_invariants = igb_get_invariants_82575, 2927 .mac_ops = &e1000_mac_ops_82575, 2928 .phy_ops = &e1000_phy_ops_82575, 2929 .nvm_ops = &e1000_nvm_ops_82575, 2930 }; 2931 2932