1 /* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2015 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 /* e1000_82575 25 * e1000_82576 26 */ 27 28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 29 30 #include <linux/types.h> 31 #include <linux/if_ether.h> 32 #include <linux/i2c.h> 33 34 #include "e1000_mac.h" 35 #include "e1000_82575.h" 36 #include "e1000_i210.h" 37 38 static s32 igb_get_invariants_82575(struct e1000_hw *); 39 static s32 igb_acquire_phy_82575(struct e1000_hw *); 40 static void igb_release_phy_82575(struct e1000_hw *); 41 static s32 igb_acquire_nvm_82575(struct e1000_hw *); 42 static void igb_release_nvm_82575(struct e1000_hw *); 43 static s32 igb_check_for_link_82575(struct e1000_hw *); 44 static s32 igb_get_cfg_done_82575(struct e1000_hw *); 45 static s32 igb_init_hw_82575(struct e1000_hw *); 46 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *); 47 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *); 48 static s32 igb_reset_hw_82575(struct e1000_hw *); 49 static s32 igb_reset_hw_82580(struct e1000_hw *); 50 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); 51 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool); 52 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool); 53 static s32 igb_setup_copper_link_82575(struct e1000_hw *); 54 static s32 igb_setup_serdes_link_82575(struct e1000_hw *); 55 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16); 56 static void igb_clear_hw_cntrs_82575(struct e1000_hw *); 57 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16); 58 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *, 59 u16 *); 60 static s32 igb_get_phy_id_82575(struct e1000_hw *); 61 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16); 62 static bool igb_sgmii_active_82575(struct e1000_hw *); 63 static s32 igb_reset_init_script_82575(struct e1000_hw *); 64 static s32 igb_read_mac_addr_82575(struct e1000_hw *); 65 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw); 66 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw); 67 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw); 68 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw); 69 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw); 70 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw); 71 static const u16 e1000_82580_rxpbs_table[] = { 72 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 }; 73 74 /** 75 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO 76 * @hw: pointer to the HW structure 77 * 78 * Called to determine if the I2C pins are being used for I2C or as an 79 * external MDIO interface since the two options are mutually exclusive. 80 **/ 81 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw) 82 { 83 u32 reg = 0; 84 bool ext_mdio = false; 85 86 switch (hw->mac.type) { 87 case e1000_82575: 88 case e1000_82576: 89 reg = rd32(E1000_MDIC); 90 ext_mdio = !!(reg & E1000_MDIC_DEST); 91 break; 92 case e1000_82580: 93 case e1000_i350: 94 case e1000_i354: 95 case e1000_i210: 96 case e1000_i211: 97 reg = rd32(E1000_MDICNFG); 98 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); 99 break; 100 default: 101 break; 102 } 103 return ext_mdio; 104 } 105 106 /** 107 * igb_check_for_link_media_swap - Check which M88E1112 interface linked 108 * @hw: pointer to the HW structure 109 * 110 * Poll the M88E1112 interfaces to see which interface achieved link. 111 */ 112 static s32 igb_check_for_link_media_swap(struct e1000_hw *hw) 113 { 114 struct e1000_phy_info *phy = &hw->phy; 115 s32 ret_val; 116 u16 data; 117 u8 port = 0; 118 119 /* Check the copper medium. */ 120 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 121 if (ret_val) 122 return ret_val; 123 124 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); 125 if (ret_val) 126 return ret_val; 127 128 if (data & E1000_M88E1112_STATUS_LINK) 129 port = E1000_MEDIA_PORT_COPPER; 130 131 /* Check the other medium. */ 132 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1); 133 if (ret_val) 134 return ret_val; 135 136 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); 137 if (ret_val) 138 return ret_val; 139 140 141 if (data & E1000_M88E1112_STATUS_LINK) 142 port = E1000_MEDIA_PORT_OTHER; 143 144 /* Determine if a swap needs to happen. */ 145 if (port && (hw->dev_spec._82575.media_port != port)) { 146 hw->dev_spec._82575.media_port = port; 147 hw->dev_spec._82575.media_changed = true; 148 } 149 150 if (port == E1000_MEDIA_PORT_COPPER) { 151 /* reset page to 0 */ 152 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 153 if (ret_val) 154 return ret_val; 155 igb_check_for_link_82575(hw); 156 } else { 157 igb_check_for_link_82575(hw); 158 /* reset page to 0 */ 159 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 160 if (ret_val) 161 return ret_val; 162 } 163 164 return 0; 165 } 166 167 /** 168 * igb_init_phy_params_82575 - Init PHY func ptrs. 169 * @hw: pointer to the HW structure 170 **/ 171 static s32 igb_init_phy_params_82575(struct e1000_hw *hw) 172 { 173 struct e1000_phy_info *phy = &hw->phy; 174 s32 ret_val = 0; 175 u32 ctrl_ext; 176 177 if (hw->phy.media_type != e1000_media_type_copper) { 178 phy->type = e1000_phy_none; 179 goto out; 180 } 181 182 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 183 phy->reset_delay_us = 100; 184 185 ctrl_ext = rd32(E1000_CTRL_EXT); 186 187 if (igb_sgmii_active_82575(hw)) { 188 phy->ops.reset = igb_phy_hw_reset_sgmii_82575; 189 ctrl_ext |= E1000_CTRL_I2C_ENA; 190 } else { 191 phy->ops.reset = igb_phy_hw_reset; 192 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 193 } 194 195 wr32(E1000_CTRL_EXT, ctrl_ext); 196 igb_reset_mdicnfg_82580(hw); 197 198 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) { 199 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575; 200 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575; 201 } else { 202 switch (hw->mac.type) { 203 case e1000_82580: 204 case e1000_i350: 205 case e1000_i354: 206 case e1000_i210: 207 case e1000_i211: 208 phy->ops.read_reg = igb_read_phy_reg_82580; 209 phy->ops.write_reg = igb_write_phy_reg_82580; 210 break; 211 default: 212 phy->ops.read_reg = igb_read_phy_reg_igp; 213 phy->ops.write_reg = igb_write_phy_reg_igp; 214 } 215 } 216 217 /* set lan id */ 218 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >> 219 E1000_STATUS_FUNC_SHIFT; 220 221 /* Set phy->phy_addr and phy->id. */ 222 ret_val = igb_get_phy_id_82575(hw); 223 if (ret_val) 224 return ret_val; 225 226 /* Verify phy id and set remaining function pointers */ 227 switch (phy->id) { 228 case M88E1543_E_PHY_ID: 229 case M88E1512_E_PHY_ID: 230 case I347AT4_E_PHY_ID: 231 case M88E1112_E_PHY_ID: 232 case M88E1111_I_PHY_ID: 233 phy->type = e1000_phy_m88; 234 phy->ops.check_polarity = igb_check_polarity_m88; 235 phy->ops.get_phy_info = igb_get_phy_info_m88; 236 if (phy->id != M88E1111_I_PHY_ID) 237 phy->ops.get_cable_length = 238 igb_get_cable_length_m88_gen2; 239 else 240 phy->ops.get_cable_length = igb_get_cable_length_m88; 241 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; 242 /* Check if this PHY is configured for media swap. */ 243 if (phy->id == M88E1112_E_PHY_ID) { 244 u16 data; 245 246 ret_val = phy->ops.write_reg(hw, 247 E1000_M88E1112_PAGE_ADDR, 248 2); 249 if (ret_val) 250 goto out; 251 252 ret_val = phy->ops.read_reg(hw, 253 E1000_M88E1112_MAC_CTRL_1, 254 &data); 255 if (ret_val) 256 goto out; 257 258 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >> 259 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT; 260 if (data == E1000_M88E1112_AUTO_COPPER_SGMII || 261 data == E1000_M88E1112_AUTO_COPPER_BASEX) 262 hw->mac.ops.check_for_link = 263 igb_check_for_link_media_swap; 264 } 265 if (phy->id == M88E1512_E_PHY_ID) { 266 ret_val = igb_initialize_M88E1512_phy(hw); 267 if (ret_val) 268 goto out; 269 } 270 if (phy->id == M88E1543_E_PHY_ID) { 271 ret_val = igb_initialize_M88E1543_phy(hw); 272 if (ret_val) 273 goto out; 274 } 275 break; 276 case IGP03E1000_E_PHY_ID: 277 phy->type = e1000_phy_igp_3; 278 phy->ops.get_phy_info = igb_get_phy_info_igp; 279 phy->ops.get_cable_length = igb_get_cable_length_igp_2; 280 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp; 281 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575; 282 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state; 283 break; 284 case I82580_I_PHY_ID: 285 case I350_I_PHY_ID: 286 phy->type = e1000_phy_82580; 287 phy->ops.force_speed_duplex = 288 igb_phy_force_speed_duplex_82580; 289 phy->ops.get_cable_length = igb_get_cable_length_82580; 290 phy->ops.get_phy_info = igb_get_phy_info_82580; 291 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580; 292 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580; 293 break; 294 case I210_I_PHY_ID: 295 phy->type = e1000_phy_i210; 296 phy->ops.check_polarity = igb_check_polarity_m88; 297 phy->ops.get_cfg_done = igb_get_cfg_done_i210; 298 phy->ops.get_phy_info = igb_get_phy_info_m88; 299 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2; 300 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580; 301 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580; 302 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; 303 break; 304 default: 305 ret_val = -E1000_ERR_PHY; 306 goto out; 307 } 308 309 out: 310 return ret_val; 311 } 312 313 /** 314 * igb_init_nvm_params_82575 - Init NVM func ptrs. 315 * @hw: pointer to the HW structure 316 **/ 317 static s32 igb_init_nvm_params_82575(struct e1000_hw *hw) 318 { 319 struct e1000_nvm_info *nvm = &hw->nvm; 320 u32 eecd = rd32(E1000_EECD); 321 u16 size; 322 323 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 324 E1000_EECD_SIZE_EX_SHIFT); 325 326 /* Added to a constant, "size" becomes the left-shift value 327 * for setting word_size. 328 */ 329 size += NVM_WORD_SIZE_BASE_SHIFT; 330 331 /* Just in case size is out of range, cap it to the largest 332 * EEPROM size supported 333 */ 334 if (size > 15) 335 size = 15; 336 337 nvm->word_size = 1 << size; 338 nvm->opcode_bits = 8; 339 nvm->delay_usec = 1; 340 341 switch (nvm->override) { 342 case e1000_nvm_override_spi_large: 343 nvm->page_size = 32; 344 nvm->address_bits = 16; 345 break; 346 case e1000_nvm_override_spi_small: 347 nvm->page_size = 8; 348 nvm->address_bits = 8; 349 break; 350 default: 351 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 352 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 353 16 : 8; 354 break; 355 } 356 if (nvm->word_size == (1 << 15)) 357 nvm->page_size = 128; 358 359 nvm->type = e1000_nvm_eeprom_spi; 360 361 /* NVM Function Pointers */ 362 nvm->ops.acquire = igb_acquire_nvm_82575; 363 nvm->ops.release = igb_release_nvm_82575; 364 nvm->ops.write = igb_write_nvm_spi; 365 nvm->ops.validate = igb_validate_nvm_checksum; 366 nvm->ops.update = igb_update_nvm_checksum; 367 if (nvm->word_size < (1 << 15)) 368 nvm->ops.read = igb_read_nvm_eerd; 369 else 370 nvm->ops.read = igb_read_nvm_spi; 371 372 /* override generic family function pointers for specific descendants */ 373 switch (hw->mac.type) { 374 case e1000_82580: 375 nvm->ops.validate = igb_validate_nvm_checksum_82580; 376 nvm->ops.update = igb_update_nvm_checksum_82580; 377 break; 378 case e1000_i354: 379 case e1000_i350: 380 nvm->ops.validate = igb_validate_nvm_checksum_i350; 381 nvm->ops.update = igb_update_nvm_checksum_i350; 382 break; 383 default: 384 break; 385 } 386 387 return 0; 388 } 389 390 /** 391 * igb_init_mac_params_82575 - Init MAC func ptrs. 392 * @hw: pointer to the HW structure 393 **/ 394 static s32 igb_init_mac_params_82575(struct e1000_hw *hw) 395 { 396 struct e1000_mac_info *mac = &hw->mac; 397 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 398 399 /* Set mta register count */ 400 mac->mta_reg_count = 128; 401 /* Set rar entry count */ 402 switch (mac->type) { 403 case e1000_82576: 404 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 405 break; 406 case e1000_82580: 407 mac->rar_entry_count = E1000_RAR_ENTRIES_82580; 408 break; 409 case e1000_i350: 410 case e1000_i354: 411 mac->rar_entry_count = E1000_RAR_ENTRIES_I350; 412 break; 413 default: 414 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 415 break; 416 } 417 /* reset */ 418 if (mac->type >= e1000_82580) 419 mac->ops.reset_hw = igb_reset_hw_82580; 420 else 421 mac->ops.reset_hw = igb_reset_hw_82575; 422 423 if (mac->type >= e1000_i210) { 424 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210; 425 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210; 426 427 } else { 428 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575; 429 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575; 430 } 431 432 /* Set if part includes ASF firmware */ 433 mac->asf_firmware_present = true; 434 /* Set if manageability features are enabled. */ 435 mac->arc_subsystem_valid = 436 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK) 437 ? true : false; 438 /* enable EEE on i350 parts and later parts */ 439 if (mac->type >= e1000_i350) 440 dev_spec->eee_disable = false; 441 else 442 dev_spec->eee_disable = true; 443 /* Allow a single clear of the SW semaphore on I210 and newer */ 444 if (mac->type >= e1000_i210) 445 dev_spec->clear_semaphore_once = true; 446 /* physical interface link setup */ 447 mac->ops.setup_physical_interface = 448 (hw->phy.media_type == e1000_media_type_copper) 449 ? igb_setup_copper_link_82575 450 : igb_setup_serdes_link_82575; 451 452 if (mac->type == e1000_82580) { 453 switch (hw->device_id) { 454 /* feature not supported on these id's */ 455 case E1000_DEV_ID_DH89XXCC_SGMII: 456 case E1000_DEV_ID_DH89XXCC_SERDES: 457 case E1000_DEV_ID_DH89XXCC_BACKPLANE: 458 case E1000_DEV_ID_DH89XXCC_SFP: 459 break; 460 default: 461 hw->dev_spec._82575.mas_capable = true; 462 break; 463 } 464 } 465 return 0; 466 } 467 468 /** 469 * igb_set_sfp_media_type_82575 - derives SFP module media type. 470 * @hw: pointer to the HW structure 471 * 472 * The media type is chosen based on SFP module. 473 * compatibility flags retrieved from SFP ID EEPROM. 474 **/ 475 static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw) 476 { 477 s32 ret_val = E1000_ERR_CONFIG; 478 u32 ctrl_ext = 0; 479 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 480 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags; 481 u8 tranceiver_type = 0; 482 s32 timeout = 3; 483 484 /* Turn I2C interface ON and power on sfp cage */ 485 ctrl_ext = rd32(E1000_CTRL_EXT); 486 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 487 wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); 488 489 wrfl(); 490 491 /* Read SFP module data */ 492 while (timeout) { 493 ret_val = igb_read_sfp_data_byte(hw, 494 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET), 495 &tranceiver_type); 496 if (ret_val == 0) 497 break; 498 msleep(100); 499 timeout--; 500 } 501 if (ret_val != 0) 502 goto out; 503 504 ret_val = igb_read_sfp_data_byte(hw, 505 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET), 506 (u8 *)eth_flags); 507 if (ret_val != 0) 508 goto out; 509 510 /* Check if there is some SFP module plugged and powered */ 511 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) || 512 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) { 513 dev_spec->module_plugged = true; 514 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) { 515 hw->phy.media_type = e1000_media_type_internal_serdes; 516 } else if (eth_flags->e100_base_fx) { 517 dev_spec->sgmii_active = true; 518 hw->phy.media_type = e1000_media_type_internal_serdes; 519 } else if (eth_flags->e1000_base_t) { 520 dev_spec->sgmii_active = true; 521 hw->phy.media_type = e1000_media_type_copper; 522 } else { 523 hw->phy.media_type = e1000_media_type_unknown; 524 hw_dbg("PHY module has not been recognized\n"); 525 goto out; 526 } 527 } else { 528 hw->phy.media_type = e1000_media_type_unknown; 529 } 530 ret_val = 0; 531 out: 532 /* Restore I2C interface setting */ 533 wr32(E1000_CTRL_EXT, ctrl_ext); 534 return ret_val; 535 } 536 537 static s32 igb_get_invariants_82575(struct e1000_hw *hw) 538 { 539 struct e1000_mac_info *mac = &hw->mac; 540 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 541 s32 ret_val; 542 u32 ctrl_ext = 0; 543 u32 link_mode = 0; 544 545 switch (hw->device_id) { 546 case E1000_DEV_ID_82575EB_COPPER: 547 case E1000_DEV_ID_82575EB_FIBER_SERDES: 548 case E1000_DEV_ID_82575GB_QUAD_COPPER: 549 mac->type = e1000_82575; 550 break; 551 case E1000_DEV_ID_82576: 552 case E1000_DEV_ID_82576_NS: 553 case E1000_DEV_ID_82576_NS_SERDES: 554 case E1000_DEV_ID_82576_FIBER: 555 case E1000_DEV_ID_82576_SERDES: 556 case E1000_DEV_ID_82576_QUAD_COPPER: 557 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 558 case E1000_DEV_ID_82576_SERDES_QUAD: 559 mac->type = e1000_82576; 560 break; 561 case E1000_DEV_ID_82580_COPPER: 562 case E1000_DEV_ID_82580_FIBER: 563 case E1000_DEV_ID_82580_QUAD_FIBER: 564 case E1000_DEV_ID_82580_SERDES: 565 case E1000_DEV_ID_82580_SGMII: 566 case E1000_DEV_ID_82580_COPPER_DUAL: 567 case E1000_DEV_ID_DH89XXCC_SGMII: 568 case E1000_DEV_ID_DH89XXCC_SERDES: 569 case E1000_DEV_ID_DH89XXCC_BACKPLANE: 570 case E1000_DEV_ID_DH89XXCC_SFP: 571 mac->type = e1000_82580; 572 break; 573 case E1000_DEV_ID_I350_COPPER: 574 case E1000_DEV_ID_I350_FIBER: 575 case E1000_DEV_ID_I350_SERDES: 576 case E1000_DEV_ID_I350_SGMII: 577 mac->type = e1000_i350; 578 break; 579 case E1000_DEV_ID_I210_COPPER: 580 case E1000_DEV_ID_I210_FIBER: 581 case E1000_DEV_ID_I210_SERDES: 582 case E1000_DEV_ID_I210_SGMII: 583 case E1000_DEV_ID_I210_COPPER_FLASHLESS: 584 case E1000_DEV_ID_I210_SERDES_FLASHLESS: 585 mac->type = e1000_i210; 586 break; 587 case E1000_DEV_ID_I211_COPPER: 588 mac->type = e1000_i211; 589 break; 590 case E1000_DEV_ID_I354_BACKPLANE_1GBPS: 591 case E1000_DEV_ID_I354_SGMII: 592 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS: 593 mac->type = e1000_i354; 594 break; 595 default: 596 return -E1000_ERR_MAC_INIT; 597 } 598 599 /* Set media type */ 600 /* The 82575 uses bits 22:23 for link mode. The mode can be changed 601 * based on the EEPROM. We cannot rely upon device ID. There 602 * is no distinguishable difference between fiber and internal 603 * SerDes mode on the 82575. There can be an external PHY attached 604 * on the SGMII interface. For this, we'll set sgmii_active to true. 605 */ 606 hw->phy.media_type = e1000_media_type_copper; 607 dev_spec->sgmii_active = false; 608 dev_spec->module_plugged = false; 609 610 ctrl_ext = rd32(E1000_CTRL_EXT); 611 612 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK; 613 switch (link_mode) { 614 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 615 hw->phy.media_type = e1000_media_type_internal_serdes; 616 break; 617 case E1000_CTRL_EXT_LINK_MODE_SGMII: 618 /* Get phy control interface type set (MDIO vs. I2C)*/ 619 if (igb_sgmii_uses_mdio_82575(hw)) { 620 hw->phy.media_type = e1000_media_type_copper; 621 dev_spec->sgmii_active = true; 622 break; 623 } 624 /* fall through for I2C based SGMII */ 625 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 626 /* read media type from SFP EEPROM */ 627 ret_val = igb_set_sfp_media_type_82575(hw); 628 if ((ret_val != 0) || 629 (hw->phy.media_type == e1000_media_type_unknown)) { 630 /* If media type was not identified then return media 631 * type defined by the CTRL_EXT settings. 632 */ 633 hw->phy.media_type = e1000_media_type_internal_serdes; 634 635 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) { 636 hw->phy.media_type = e1000_media_type_copper; 637 dev_spec->sgmii_active = true; 638 } 639 640 break; 641 } 642 643 /* do not change link mode for 100BaseFX */ 644 if (dev_spec->eth_flags.e100_base_fx) 645 break; 646 647 /* change current link mode setting */ 648 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 649 650 if (hw->phy.media_type == e1000_media_type_copper) 651 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII; 652 else 653 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 654 655 wr32(E1000_CTRL_EXT, ctrl_ext); 656 657 break; 658 default: 659 break; 660 } 661 662 /* mac initialization and operations */ 663 ret_val = igb_init_mac_params_82575(hw); 664 if (ret_val) 665 goto out; 666 667 /* NVM initialization */ 668 ret_val = igb_init_nvm_params_82575(hw); 669 switch (hw->mac.type) { 670 case e1000_i210: 671 case e1000_i211: 672 ret_val = igb_init_nvm_params_i210(hw); 673 break; 674 default: 675 break; 676 } 677 678 if (ret_val) 679 goto out; 680 681 /* if part supports SR-IOV then initialize mailbox parameters */ 682 switch (mac->type) { 683 case e1000_82576: 684 case e1000_i350: 685 igb_init_mbx_params_pf(hw); 686 break; 687 default: 688 break; 689 } 690 691 /* setup PHY parameters */ 692 ret_val = igb_init_phy_params_82575(hw); 693 694 out: 695 return ret_val; 696 } 697 698 /** 699 * igb_acquire_phy_82575 - Acquire rights to access PHY 700 * @hw: pointer to the HW structure 701 * 702 * Acquire access rights to the correct PHY. This is a 703 * function pointer entry point called by the api module. 704 **/ 705 static s32 igb_acquire_phy_82575(struct e1000_hw *hw) 706 { 707 u16 mask = E1000_SWFW_PHY0_SM; 708 709 if (hw->bus.func == E1000_FUNC_1) 710 mask = E1000_SWFW_PHY1_SM; 711 else if (hw->bus.func == E1000_FUNC_2) 712 mask = E1000_SWFW_PHY2_SM; 713 else if (hw->bus.func == E1000_FUNC_3) 714 mask = E1000_SWFW_PHY3_SM; 715 716 return hw->mac.ops.acquire_swfw_sync(hw, mask); 717 } 718 719 /** 720 * igb_release_phy_82575 - Release rights to access PHY 721 * @hw: pointer to the HW structure 722 * 723 * A wrapper to release access rights to the correct PHY. This is a 724 * function pointer entry point called by the api module. 725 **/ 726 static void igb_release_phy_82575(struct e1000_hw *hw) 727 { 728 u16 mask = E1000_SWFW_PHY0_SM; 729 730 if (hw->bus.func == E1000_FUNC_1) 731 mask = E1000_SWFW_PHY1_SM; 732 else if (hw->bus.func == E1000_FUNC_2) 733 mask = E1000_SWFW_PHY2_SM; 734 else if (hw->bus.func == E1000_FUNC_3) 735 mask = E1000_SWFW_PHY3_SM; 736 737 hw->mac.ops.release_swfw_sync(hw, mask); 738 } 739 740 /** 741 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 742 * @hw: pointer to the HW structure 743 * @offset: register offset to be read 744 * @data: pointer to the read data 745 * 746 * Reads the PHY register at offset using the serial gigabit media independent 747 * interface and stores the retrieved information in data. 748 **/ 749 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 750 u16 *data) 751 { 752 s32 ret_val = -E1000_ERR_PARAM; 753 754 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 755 hw_dbg("PHY Address %u is out of range\n", offset); 756 goto out; 757 } 758 759 ret_val = hw->phy.ops.acquire(hw); 760 if (ret_val) 761 goto out; 762 763 ret_val = igb_read_phy_reg_i2c(hw, offset, data); 764 765 hw->phy.ops.release(hw); 766 767 out: 768 return ret_val; 769 } 770 771 /** 772 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 773 * @hw: pointer to the HW structure 774 * @offset: register offset to write to 775 * @data: data to write at register offset 776 * 777 * Writes the data to PHY register at the offset using the serial gigabit 778 * media independent interface. 779 **/ 780 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 781 u16 data) 782 { 783 s32 ret_val = -E1000_ERR_PARAM; 784 785 786 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 787 hw_dbg("PHY Address %d is out of range\n", offset); 788 goto out; 789 } 790 791 ret_val = hw->phy.ops.acquire(hw); 792 if (ret_val) 793 goto out; 794 795 ret_val = igb_write_phy_reg_i2c(hw, offset, data); 796 797 hw->phy.ops.release(hw); 798 799 out: 800 return ret_val; 801 } 802 803 /** 804 * igb_get_phy_id_82575 - Retrieve PHY addr and id 805 * @hw: pointer to the HW structure 806 * 807 * Retrieves the PHY address and ID for both PHY's which do and do not use 808 * sgmi interface. 809 **/ 810 static s32 igb_get_phy_id_82575(struct e1000_hw *hw) 811 { 812 struct e1000_phy_info *phy = &hw->phy; 813 s32 ret_val = 0; 814 u16 phy_id; 815 u32 ctrl_ext; 816 u32 mdic; 817 818 /* Extra read required for some PHY's on i354 */ 819 if (hw->mac.type == e1000_i354) 820 igb_get_phy_id(hw); 821 822 /* For SGMII PHYs, we try the list of possible addresses until 823 * we find one that works. For non-SGMII PHYs 824 * (e.g. integrated copper PHYs), an address of 1 should 825 * work. The result of this function should mean phy->phy_addr 826 * and phy->id are set correctly. 827 */ 828 if (!(igb_sgmii_active_82575(hw))) { 829 phy->addr = 1; 830 ret_val = igb_get_phy_id(hw); 831 goto out; 832 } 833 834 if (igb_sgmii_uses_mdio_82575(hw)) { 835 switch (hw->mac.type) { 836 case e1000_82575: 837 case e1000_82576: 838 mdic = rd32(E1000_MDIC); 839 mdic &= E1000_MDIC_PHY_MASK; 840 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; 841 break; 842 case e1000_82580: 843 case e1000_i350: 844 case e1000_i354: 845 case e1000_i210: 846 case e1000_i211: 847 mdic = rd32(E1000_MDICNFG); 848 mdic &= E1000_MDICNFG_PHY_MASK; 849 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 850 break; 851 default: 852 ret_val = -E1000_ERR_PHY; 853 goto out; 854 } 855 ret_val = igb_get_phy_id(hw); 856 goto out; 857 } 858 859 /* Power on sgmii phy if it is disabled */ 860 ctrl_ext = rd32(E1000_CTRL_EXT); 861 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 862 wrfl(); 863 msleep(300); 864 865 /* The address field in the I2CCMD register is 3 bits and 0 is invalid. 866 * Therefore, we need to test 1-7 867 */ 868 for (phy->addr = 1; phy->addr < 8; phy->addr++) { 869 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 870 if (ret_val == 0) { 871 hw_dbg("Vendor ID 0x%08X read at address %u\n", 872 phy_id, phy->addr); 873 /* At the time of this writing, The M88 part is 874 * the only supported SGMII PHY product. 875 */ 876 if (phy_id == M88_VENDOR) 877 break; 878 } else { 879 hw_dbg("PHY address %u was unreadable\n", phy->addr); 880 } 881 } 882 883 /* A valid PHY type couldn't be found. */ 884 if (phy->addr == 8) { 885 phy->addr = 0; 886 ret_val = -E1000_ERR_PHY; 887 goto out; 888 } else { 889 ret_val = igb_get_phy_id(hw); 890 } 891 892 /* restore previous sfp cage power state */ 893 wr32(E1000_CTRL_EXT, ctrl_ext); 894 895 out: 896 return ret_val; 897 } 898 899 /** 900 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset 901 * @hw: pointer to the HW structure 902 * 903 * Resets the PHY using the serial gigabit media independent interface. 904 **/ 905 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 906 { 907 struct e1000_phy_info *phy = &hw->phy; 908 s32 ret_val; 909 910 /* This isn't a true "hard" reset, but is the only reset 911 * available to us at this time. 912 */ 913 914 hw_dbg("Soft resetting SGMII attached PHY...\n"); 915 916 /* SFP documentation requires the following to configure the SPF module 917 * to work on SGMII. No further documentation is given. 918 */ 919 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 920 if (ret_val) 921 goto out; 922 923 ret_val = igb_phy_sw_reset(hw); 924 if (ret_val) 925 goto out; 926 927 if (phy->id == M88E1512_E_PHY_ID) 928 ret_val = igb_initialize_M88E1512_phy(hw); 929 if (phy->id == M88E1543_E_PHY_ID) 930 ret_val = igb_initialize_M88E1543_phy(hw); 931 out: 932 return ret_val; 933 } 934 935 /** 936 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 937 * @hw: pointer to the HW structure 938 * @active: true to enable LPLU, false to disable 939 * 940 * Sets the LPLU D0 state according to the active flag. When 941 * activating LPLU this function also disables smart speed 942 * and vice versa. LPLU will not be activated unless the 943 * device autonegotiation advertisement meets standards of 944 * either 10 or 10/100 or 10/100/1000 at all duplexes. 945 * This is a function pointer entry point only called by 946 * PHY setup routines. 947 **/ 948 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 949 { 950 struct e1000_phy_info *phy = &hw->phy; 951 s32 ret_val; 952 u16 data; 953 954 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 955 if (ret_val) 956 goto out; 957 958 if (active) { 959 data |= IGP02E1000_PM_D0_LPLU; 960 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 961 data); 962 if (ret_val) 963 goto out; 964 965 /* When LPLU is enabled, we should disable SmartSpeed */ 966 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 967 &data); 968 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 969 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 970 data); 971 if (ret_val) 972 goto out; 973 } else { 974 data &= ~IGP02E1000_PM_D0_LPLU; 975 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 976 data); 977 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 978 * during Dx states where the power conservation is most 979 * important. During driver activity we should enable 980 * SmartSpeed, so performance is maintained. 981 */ 982 if (phy->smart_speed == e1000_smart_speed_on) { 983 ret_val = phy->ops.read_reg(hw, 984 IGP01E1000_PHY_PORT_CONFIG, &data); 985 if (ret_val) 986 goto out; 987 988 data |= IGP01E1000_PSCFR_SMART_SPEED; 989 ret_val = phy->ops.write_reg(hw, 990 IGP01E1000_PHY_PORT_CONFIG, data); 991 if (ret_val) 992 goto out; 993 } else if (phy->smart_speed == e1000_smart_speed_off) { 994 ret_val = phy->ops.read_reg(hw, 995 IGP01E1000_PHY_PORT_CONFIG, &data); 996 if (ret_val) 997 goto out; 998 999 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1000 ret_val = phy->ops.write_reg(hw, 1001 IGP01E1000_PHY_PORT_CONFIG, data); 1002 if (ret_val) 1003 goto out; 1004 } 1005 } 1006 1007 out: 1008 return ret_val; 1009 } 1010 1011 /** 1012 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state 1013 * @hw: pointer to the HW structure 1014 * @active: true to enable LPLU, false to disable 1015 * 1016 * Sets the LPLU D0 state according to the active flag. When 1017 * activating LPLU this function also disables smart speed 1018 * and vice versa. LPLU will not be activated unless the 1019 * device autonegotiation advertisement meets standards of 1020 * either 10 or 10/100 or 10/100/1000 at all duplexes. 1021 * This is a function pointer entry point only called by 1022 * PHY setup routines. 1023 **/ 1024 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) 1025 { 1026 struct e1000_phy_info *phy = &hw->phy; 1027 u16 data; 1028 1029 data = rd32(E1000_82580_PHY_POWER_MGMT); 1030 1031 if (active) { 1032 data |= E1000_82580_PM_D0_LPLU; 1033 1034 /* When LPLU is enabled, we should disable SmartSpeed */ 1035 data &= ~E1000_82580_PM_SPD; 1036 } else { 1037 data &= ~E1000_82580_PM_D0_LPLU; 1038 1039 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1040 * during Dx states where the power conservation is most 1041 * important. During driver activity we should enable 1042 * SmartSpeed, so performance is maintained. 1043 */ 1044 if (phy->smart_speed == e1000_smart_speed_on) 1045 data |= E1000_82580_PM_SPD; 1046 else if (phy->smart_speed == e1000_smart_speed_off) 1047 data &= ~E1000_82580_PM_SPD; } 1048 1049 wr32(E1000_82580_PHY_POWER_MGMT, data); 1050 return 0; 1051 } 1052 1053 /** 1054 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3 1055 * @hw: pointer to the HW structure 1056 * @active: boolean used to enable/disable lplu 1057 * 1058 * Success returns 0, Failure returns 1 1059 * 1060 * The low power link up (lplu) state is set to the power management level D3 1061 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1062 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1063 * is used during Dx states where the power conservation is most important. 1064 * During driver activity, SmartSpeed should be enabled so performance is 1065 * maintained. 1066 **/ 1067 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) 1068 { 1069 struct e1000_phy_info *phy = &hw->phy; 1070 u16 data; 1071 1072 data = rd32(E1000_82580_PHY_POWER_MGMT); 1073 1074 if (!active) { 1075 data &= ~E1000_82580_PM_D3_LPLU; 1076 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1077 * during Dx states where the power conservation is most 1078 * important. During driver activity we should enable 1079 * SmartSpeed, so performance is maintained. 1080 */ 1081 if (phy->smart_speed == e1000_smart_speed_on) 1082 data |= E1000_82580_PM_SPD; 1083 else if (phy->smart_speed == e1000_smart_speed_off) 1084 data &= ~E1000_82580_PM_SPD; 1085 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1086 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1087 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1088 data |= E1000_82580_PM_D3_LPLU; 1089 /* When LPLU is enabled, we should disable SmartSpeed */ 1090 data &= ~E1000_82580_PM_SPD; 1091 } 1092 1093 wr32(E1000_82580_PHY_POWER_MGMT, data); 1094 return 0; 1095 } 1096 1097 /** 1098 * igb_acquire_nvm_82575 - Request for access to EEPROM 1099 * @hw: pointer to the HW structure 1100 * 1101 * Acquire the necessary semaphores for exclusive access to the EEPROM. 1102 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 1103 * Return successful if access grant bit set, else clear the request for 1104 * EEPROM access and return -E1000_ERR_NVM (-1). 1105 **/ 1106 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw) 1107 { 1108 s32 ret_val; 1109 1110 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM); 1111 if (ret_val) 1112 goto out; 1113 1114 ret_val = igb_acquire_nvm(hw); 1115 1116 if (ret_val) 1117 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM); 1118 1119 out: 1120 return ret_val; 1121 } 1122 1123 /** 1124 * igb_release_nvm_82575 - Release exclusive access to EEPROM 1125 * @hw: pointer to the HW structure 1126 * 1127 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 1128 * then release the semaphores acquired. 1129 **/ 1130 static void igb_release_nvm_82575(struct e1000_hw *hw) 1131 { 1132 igb_release_nvm(hw); 1133 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM); 1134 } 1135 1136 /** 1137 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 1138 * @hw: pointer to the HW structure 1139 * @mask: specifies which semaphore to acquire 1140 * 1141 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 1142 * will also specify which port we're acquiring the lock for. 1143 **/ 1144 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1145 { 1146 u32 swfw_sync; 1147 u32 swmask = mask; 1148 u32 fwmask = mask << 16; 1149 s32 ret_val = 0; 1150 s32 i = 0, timeout = 200; 1151 1152 while (i < timeout) { 1153 if (igb_get_hw_semaphore(hw)) { 1154 ret_val = -E1000_ERR_SWFW_SYNC; 1155 goto out; 1156 } 1157 1158 swfw_sync = rd32(E1000_SW_FW_SYNC); 1159 if (!(swfw_sync & (fwmask | swmask))) 1160 break; 1161 1162 /* Firmware currently using resource (fwmask) 1163 * or other software thread using resource (swmask) 1164 */ 1165 igb_put_hw_semaphore(hw); 1166 mdelay(5); 1167 i++; 1168 } 1169 1170 if (i == timeout) { 1171 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1172 ret_val = -E1000_ERR_SWFW_SYNC; 1173 goto out; 1174 } 1175 1176 swfw_sync |= swmask; 1177 wr32(E1000_SW_FW_SYNC, swfw_sync); 1178 1179 igb_put_hw_semaphore(hw); 1180 1181 out: 1182 return ret_val; 1183 } 1184 1185 /** 1186 * igb_release_swfw_sync_82575 - Release SW/FW semaphore 1187 * @hw: pointer to the HW structure 1188 * @mask: specifies which semaphore to acquire 1189 * 1190 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 1191 * will also specify which port we're releasing the lock for. 1192 **/ 1193 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1194 { 1195 u32 swfw_sync; 1196 1197 while (igb_get_hw_semaphore(hw) != 0) 1198 ; /* Empty */ 1199 1200 swfw_sync = rd32(E1000_SW_FW_SYNC); 1201 swfw_sync &= ~mask; 1202 wr32(E1000_SW_FW_SYNC, swfw_sync); 1203 1204 igb_put_hw_semaphore(hw); 1205 } 1206 1207 /** 1208 * igb_get_cfg_done_82575 - Read config done bit 1209 * @hw: pointer to the HW structure 1210 * 1211 * Read the management control register for the config done bit for 1212 * completion status. NOTE: silicon which is EEPROM-less will fail trying 1213 * to read the config done bit, so an error is *ONLY* logged and returns 1214 * 0. If we were to return with error, EEPROM-less silicon 1215 * would not be able to be reset or change link. 1216 **/ 1217 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw) 1218 { 1219 s32 timeout = PHY_CFG_TIMEOUT; 1220 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 1221 1222 if (hw->bus.func == 1) 1223 mask = E1000_NVM_CFG_DONE_PORT_1; 1224 else if (hw->bus.func == E1000_FUNC_2) 1225 mask = E1000_NVM_CFG_DONE_PORT_2; 1226 else if (hw->bus.func == E1000_FUNC_3) 1227 mask = E1000_NVM_CFG_DONE_PORT_3; 1228 1229 while (timeout) { 1230 if (rd32(E1000_EEMNGCTL) & mask) 1231 break; 1232 usleep_range(1000, 2000); 1233 timeout--; 1234 } 1235 if (!timeout) 1236 hw_dbg("MNG configuration cycle has not completed.\n"); 1237 1238 /* If EEPROM is not marked present, init the PHY manually */ 1239 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) && 1240 (hw->phy.type == e1000_phy_igp_3)) 1241 igb_phy_init_script_igp3(hw); 1242 1243 return 0; 1244 } 1245 1246 /** 1247 * igb_get_link_up_info_82575 - Get link speed/duplex info 1248 * @hw: pointer to the HW structure 1249 * @speed: stores the current speed 1250 * @duplex: stores the current duplex 1251 * 1252 * This is a wrapper function, if using the serial gigabit media independent 1253 * interface, use PCS to retrieve the link speed and duplex information. 1254 * Otherwise, use the generic function to get the link speed and duplex info. 1255 **/ 1256 static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 1257 u16 *duplex) 1258 { 1259 s32 ret_val; 1260 1261 if (hw->phy.media_type != e1000_media_type_copper) 1262 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed, 1263 duplex); 1264 else 1265 ret_val = igb_get_speed_and_duplex_copper(hw, speed, 1266 duplex); 1267 1268 return ret_val; 1269 } 1270 1271 /** 1272 * igb_check_for_link_82575 - Check for link 1273 * @hw: pointer to the HW structure 1274 * 1275 * If sgmii is enabled, then use the pcs register to determine link, otherwise 1276 * use the generic interface for determining link. 1277 **/ 1278 static s32 igb_check_for_link_82575(struct e1000_hw *hw) 1279 { 1280 s32 ret_val; 1281 u16 speed, duplex; 1282 1283 if (hw->phy.media_type != e1000_media_type_copper) { 1284 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, 1285 &duplex); 1286 /* Use this flag to determine if link needs to be checked or 1287 * not. If we have link clear the flag so that we do not 1288 * continue to check for link. 1289 */ 1290 hw->mac.get_link_status = !hw->mac.serdes_has_link; 1291 1292 /* Configure Flow Control now that Auto-Neg has completed. 1293 * First, we need to restore the desired flow control 1294 * settings because we may have had to re-autoneg with a 1295 * different link partner. 1296 */ 1297 ret_val = igb_config_fc_after_link_up(hw); 1298 if (ret_val) 1299 hw_dbg("Error configuring flow control\n"); 1300 } else { 1301 ret_val = igb_check_for_copper_link(hw); 1302 } 1303 1304 return ret_val; 1305 } 1306 1307 /** 1308 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown 1309 * @hw: pointer to the HW structure 1310 **/ 1311 void igb_power_up_serdes_link_82575(struct e1000_hw *hw) 1312 { 1313 u32 reg; 1314 1315 1316 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1317 !igb_sgmii_active_82575(hw)) 1318 return; 1319 1320 /* Enable PCS to turn on link */ 1321 reg = rd32(E1000_PCS_CFG0); 1322 reg |= E1000_PCS_CFG_PCS_EN; 1323 wr32(E1000_PCS_CFG0, reg); 1324 1325 /* Power up the laser */ 1326 reg = rd32(E1000_CTRL_EXT); 1327 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1328 wr32(E1000_CTRL_EXT, reg); 1329 1330 /* flush the write to verify completion */ 1331 wrfl(); 1332 usleep_range(1000, 2000); 1333 } 1334 1335 /** 1336 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 1337 * @hw: pointer to the HW structure 1338 * @speed: stores the current speed 1339 * @duplex: stores the current duplex 1340 * 1341 * Using the physical coding sub-layer (PCS), retrieve the current speed and 1342 * duplex, then store the values in the pointers provided. 1343 **/ 1344 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, 1345 u16 *duplex) 1346 { 1347 struct e1000_mac_info *mac = &hw->mac; 1348 u32 pcs, status; 1349 1350 /* Set up defaults for the return values of this function */ 1351 mac->serdes_has_link = false; 1352 *speed = 0; 1353 *duplex = 0; 1354 1355 /* Read the PCS Status register for link state. For non-copper mode, 1356 * the status register is not accurate. The PCS status register is 1357 * used instead. 1358 */ 1359 pcs = rd32(E1000_PCS_LSTAT); 1360 1361 /* The link up bit determines when link is up on autoneg. The sync ok 1362 * gets set once both sides sync up and agree upon link. Stable link 1363 * can be determined by checking for both link up and link sync ok 1364 */ 1365 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 1366 mac->serdes_has_link = true; 1367 1368 /* Detect and store PCS speed */ 1369 if (pcs & E1000_PCS_LSTS_SPEED_1000) 1370 *speed = SPEED_1000; 1371 else if (pcs & E1000_PCS_LSTS_SPEED_100) 1372 *speed = SPEED_100; 1373 else 1374 *speed = SPEED_10; 1375 1376 /* Detect and store PCS duplex */ 1377 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) 1378 *duplex = FULL_DUPLEX; 1379 else 1380 *duplex = HALF_DUPLEX; 1381 1382 /* Check if it is an I354 2.5Gb backplane connection. */ 1383 if (mac->type == e1000_i354) { 1384 status = rd32(E1000_STATUS); 1385 if ((status & E1000_STATUS_2P5_SKU) && 1386 !(status & E1000_STATUS_2P5_SKU_OVER)) { 1387 *speed = SPEED_2500; 1388 *duplex = FULL_DUPLEX; 1389 hw_dbg("2500 Mbs, "); 1390 hw_dbg("Full Duplex\n"); 1391 } 1392 } 1393 1394 } 1395 1396 return 0; 1397 } 1398 1399 /** 1400 * igb_shutdown_serdes_link_82575 - Remove link during power down 1401 * @hw: pointer to the HW structure 1402 * 1403 * In the case of fiber serdes, shut down optics and PCS on driver unload 1404 * when management pass thru is not enabled. 1405 **/ 1406 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw) 1407 { 1408 u32 reg; 1409 1410 if (hw->phy.media_type != e1000_media_type_internal_serdes && 1411 igb_sgmii_active_82575(hw)) 1412 return; 1413 1414 if (!igb_enable_mng_pass_thru(hw)) { 1415 /* Disable PCS to turn off link */ 1416 reg = rd32(E1000_PCS_CFG0); 1417 reg &= ~E1000_PCS_CFG_PCS_EN; 1418 wr32(E1000_PCS_CFG0, reg); 1419 1420 /* shutdown the laser */ 1421 reg = rd32(E1000_CTRL_EXT); 1422 reg |= E1000_CTRL_EXT_SDP3_DATA; 1423 wr32(E1000_CTRL_EXT, reg); 1424 1425 /* flush the write to verify completion */ 1426 wrfl(); 1427 usleep_range(1000, 2000); 1428 } 1429 } 1430 1431 /** 1432 * igb_reset_hw_82575 - Reset hardware 1433 * @hw: pointer to the HW structure 1434 * 1435 * This resets the hardware into a known state. This is a 1436 * function pointer entry point called by the api module. 1437 **/ 1438 static s32 igb_reset_hw_82575(struct e1000_hw *hw) 1439 { 1440 u32 ctrl; 1441 s32 ret_val; 1442 1443 /* Prevent the PCI-E bus from sticking if there is no TLP connection 1444 * on the last TLP read/write transaction when MAC is reset. 1445 */ 1446 ret_val = igb_disable_pcie_master(hw); 1447 if (ret_val) 1448 hw_dbg("PCI-E Master disable polling has failed.\n"); 1449 1450 /* set the completion timeout for interface */ 1451 ret_val = igb_set_pcie_completion_timeout(hw); 1452 if (ret_val) 1453 hw_dbg("PCI-E Set completion timeout has failed.\n"); 1454 1455 hw_dbg("Masking off all interrupts\n"); 1456 wr32(E1000_IMC, 0xffffffff); 1457 1458 wr32(E1000_RCTL, 0); 1459 wr32(E1000_TCTL, E1000_TCTL_PSP); 1460 wrfl(); 1461 1462 usleep_range(10000, 20000); 1463 1464 ctrl = rd32(E1000_CTRL); 1465 1466 hw_dbg("Issuing a global reset to MAC\n"); 1467 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST); 1468 1469 ret_val = igb_get_auto_rd_done(hw); 1470 if (ret_val) { 1471 /* When auto config read does not complete, do not 1472 * return with an error. This can happen in situations 1473 * where there is no eeprom and prevents getting link. 1474 */ 1475 hw_dbg("Auto Read Done did not complete\n"); 1476 } 1477 1478 /* If EEPROM is not present, run manual init scripts */ 1479 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) 1480 igb_reset_init_script_82575(hw); 1481 1482 /* Clear any pending interrupt events. */ 1483 wr32(E1000_IMC, 0xffffffff); 1484 rd32(E1000_ICR); 1485 1486 /* Install any alternate MAC address into RAR0 */ 1487 ret_val = igb_check_alt_mac_addr(hw); 1488 1489 return ret_val; 1490 } 1491 1492 /** 1493 * igb_init_hw_82575 - Initialize hardware 1494 * @hw: pointer to the HW structure 1495 * 1496 * This inits the hardware readying it for operation. 1497 **/ 1498 static s32 igb_init_hw_82575(struct e1000_hw *hw) 1499 { 1500 struct e1000_mac_info *mac = &hw->mac; 1501 s32 ret_val; 1502 u16 i, rar_count = mac->rar_entry_count; 1503 1504 if ((hw->mac.type >= e1000_i210) && 1505 !(igb_get_flash_presence_i210(hw))) { 1506 ret_val = igb_pll_workaround_i210(hw); 1507 if (ret_val) 1508 return ret_val; 1509 } 1510 1511 /* Initialize identification LED */ 1512 ret_val = igb_id_led_init(hw); 1513 if (ret_val) { 1514 hw_dbg("Error initializing identification LED\n"); 1515 /* This is not fatal and we should not stop init due to this */ 1516 } 1517 1518 /* Disabling VLAN filtering */ 1519 hw_dbg("Initializing the IEEE VLAN\n"); 1520 if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354)) 1521 igb_clear_vfta_i350(hw); 1522 else 1523 igb_clear_vfta(hw); 1524 1525 /* Setup the receive address */ 1526 igb_init_rx_addrs(hw, rar_count); 1527 1528 /* Zero out the Multicast HASH table */ 1529 hw_dbg("Zeroing the MTA\n"); 1530 for (i = 0; i < mac->mta_reg_count; i++) 1531 array_wr32(E1000_MTA, i, 0); 1532 1533 /* Zero out the Unicast HASH table */ 1534 hw_dbg("Zeroing the UTA\n"); 1535 for (i = 0; i < mac->uta_reg_count; i++) 1536 array_wr32(E1000_UTA, i, 0); 1537 1538 /* Setup link and flow control */ 1539 ret_val = igb_setup_link(hw); 1540 1541 /* Clear all of the statistics registers (clear on read). It is 1542 * important that we do this after we have tried to establish link 1543 * because the symbol error count will increment wildly if there 1544 * is no link. 1545 */ 1546 igb_clear_hw_cntrs_82575(hw); 1547 return ret_val; 1548 } 1549 1550 /** 1551 * igb_setup_copper_link_82575 - Configure copper link settings 1552 * @hw: pointer to the HW structure 1553 * 1554 * Configures the link for auto-neg or forced speed and duplex. Then we check 1555 * for link, once link is established calls to configure collision distance 1556 * and flow control are called. 1557 **/ 1558 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw) 1559 { 1560 u32 ctrl; 1561 s32 ret_val; 1562 u32 phpm_reg; 1563 1564 ctrl = rd32(E1000_CTRL); 1565 ctrl |= E1000_CTRL_SLU; 1566 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1567 wr32(E1000_CTRL, ctrl); 1568 1569 /* Clear Go Link Disconnect bit on supported devices */ 1570 switch (hw->mac.type) { 1571 case e1000_82580: 1572 case e1000_i350: 1573 case e1000_i210: 1574 case e1000_i211: 1575 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT); 1576 phpm_reg &= ~E1000_82580_PM_GO_LINKD; 1577 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg); 1578 break; 1579 default: 1580 break; 1581 } 1582 1583 ret_val = igb_setup_serdes_link_82575(hw); 1584 if (ret_val) 1585 goto out; 1586 1587 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) { 1588 /* allow time for SFP cage time to power up phy */ 1589 msleep(300); 1590 1591 ret_val = hw->phy.ops.reset(hw); 1592 if (ret_val) { 1593 hw_dbg("Error resetting the PHY.\n"); 1594 goto out; 1595 } 1596 } 1597 switch (hw->phy.type) { 1598 case e1000_phy_i210: 1599 case e1000_phy_m88: 1600 switch (hw->phy.id) { 1601 case I347AT4_E_PHY_ID: 1602 case M88E1112_E_PHY_ID: 1603 case M88E1543_E_PHY_ID: 1604 case M88E1512_E_PHY_ID: 1605 case I210_I_PHY_ID: 1606 ret_val = igb_copper_link_setup_m88_gen2(hw); 1607 break; 1608 default: 1609 ret_val = igb_copper_link_setup_m88(hw); 1610 break; 1611 } 1612 break; 1613 case e1000_phy_igp_3: 1614 ret_val = igb_copper_link_setup_igp(hw); 1615 break; 1616 case e1000_phy_82580: 1617 ret_val = igb_copper_link_setup_82580(hw); 1618 break; 1619 default: 1620 ret_val = -E1000_ERR_PHY; 1621 break; 1622 } 1623 1624 if (ret_val) 1625 goto out; 1626 1627 ret_val = igb_setup_copper_link(hw); 1628 out: 1629 return ret_val; 1630 } 1631 1632 /** 1633 * igb_setup_serdes_link_82575 - Setup link for serdes 1634 * @hw: pointer to the HW structure 1635 * 1636 * Configure the physical coding sub-layer (PCS) link. The PCS link is 1637 * used on copper connections where the serialized gigabit media independent 1638 * interface (sgmii), or serdes fiber is being used. Configures the link 1639 * for auto-negotiation or forces speed/duplex. 1640 **/ 1641 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw) 1642 { 1643 u32 ctrl_ext, ctrl_reg, reg, anadv_reg; 1644 bool pcs_autoneg; 1645 s32 ret_val = 0; 1646 u16 data; 1647 1648 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1649 !igb_sgmii_active_82575(hw)) 1650 return ret_val; 1651 1652 1653 /* On the 82575, SerDes loopback mode persists until it is 1654 * explicitly turned off or a power cycle is performed. A read to 1655 * the register does not indicate its status. Therefore, we ensure 1656 * loopback mode is disabled during initialization. 1657 */ 1658 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1659 1660 /* power on the sfp cage if present and turn on I2C */ 1661 ctrl_ext = rd32(E1000_CTRL_EXT); 1662 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1663 ctrl_ext |= E1000_CTRL_I2C_ENA; 1664 wr32(E1000_CTRL_EXT, ctrl_ext); 1665 1666 ctrl_reg = rd32(E1000_CTRL); 1667 ctrl_reg |= E1000_CTRL_SLU; 1668 1669 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { 1670 /* set both sw defined pins */ 1671 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1672 1673 /* Set switch control to serdes energy detect */ 1674 reg = rd32(E1000_CONNSW); 1675 reg |= E1000_CONNSW_ENRGSRC; 1676 wr32(E1000_CONNSW, reg); 1677 } 1678 1679 reg = rd32(E1000_PCS_LCTL); 1680 1681 /* default pcs_autoneg to the same setting as mac autoneg */ 1682 pcs_autoneg = hw->mac.autoneg; 1683 1684 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1685 case E1000_CTRL_EXT_LINK_MODE_SGMII: 1686 /* sgmii mode lets the phy handle forcing speed/duplex */ 1687 pcs_autoneg = true; 1688 /* autoneg time out should be disabled for SGMII mode */ 1689 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1690 break; 1691 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1692 /* disable PCS autoneg and support parallel detect only */ 1693 pcs_autoneg = false; 1694 default: 1695 if (hw->mac.type == e1000_82575 || 1696 hw->mac.type == e1000_82576) { 1697 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data); 1698 if (ret_val) { 1699 hw_dbg(KERN_DEBUG "NVM Read Error\n\n"); 1700 return ret_val; 1701 } 1702 1703 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT) 1704 pcs_autoneg = false; 1705 } 1706 1707 /* non-SGMII modes only supports a speed of 1000/Full for the 1708 * link so it is best to just force the MAC and let the pcs 1709 * link either autoneg or be forced to 1000/Full 1710 */ 1711 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | 1712 E1000_CTRL_FD | E1000_CTRL_FRCDPX; 1713 1714 /* set speed of 1000/Full if speed/duplex is forced */ 1715 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1716 break; 1717 } 1718 1719 wr32(E1000_CTRL, ctrl_reg); 1720 1721 /* New SerDes mode allows for forcing speed or autonegotiating speed 1722 * at 1gb. Autoneg should be default set by most drivers. This is the 1723 * mode that will be compatible with older link partners and switches. 1724 * However, both are supported by the hardware and some drivers/tools. 1725 */ 1726 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1727 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1728 1729 if (pcs_autoneg) { 1730 /* Set PCS register for autoneg */ 1731 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1732 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1733 1734 /* Disable force flow control for autoneg */ 1735 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL; 1736 1737 /* Configure flow control advertisement for autoneg */ 1738 anadv_reg = rd32(E1000_PCS_ANADV); 1739 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE); 1740 switch (hw->fc.requested_mode) { 1741 case e1000_fc_full: 1742 case e1000_fc_rx_pause: 1743 anadv_reg |= E1000_TXCW_ASM_DIR; 1744 anadv_reg |= E1000_TXCW_PAUSE; 1745 break; 1746 case e1000_fc_tx_pause: 1747 anadv_reg |= E1000_TXCW_ASM_DIR; 1748 break; 1749 default: 1750 break; 1751 } 1752 wr32(E1000_PCS_ANADV, anadv_reg); 1753 1754 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); 1755 } else { 1756 /* Set PCS register for forced link */ 1757 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1758 1759 /* Force flow control for forced link */ 1760 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1761 1762 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); 1763 } 1764 1765 wr32(E1000_PCS_LCTL, reg); 1766 1767 if (!pcs_autoneg && !igb_sgmii_active_82575(hw)) 1768 igb_force_mac_fc(hw); 1769 1770 return ret_val; 1771 } 1772 1773 /** 1774 * igb_sgmii_active_82575 - Return sgmii state 1775 * @hw: pointer to the HW structure 1776 * 1777 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1778 * which can be enabled for use in the embedded applications. Simply 1779 * return the current state of the sgmii interface. 1780 **/ 1781 static bool igb_sgmii_active_82575(struct e1000_hw *hw) 1782 { 1783 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1784 return dev_spec->sgmii_active; 1785 } 1786 1787 /** 1788 * igb_reset_init_script_82575 - Inits HW defaults after reset 1789 * @hw: pointer to the HW structure 1790 * 1791 * Inits recommended HW defaults after a reset when there is no EEPROM 1792 * detected. This is only for the 82575. 1793 **/ 1794 static s32 igb_reset_init_script_82575(struct e1000_hw *hw) 1795 { 1796 if (hw->mac.type == e1000_82575) { 1797 hw_dbg("Running reset init script for 82575\n"); 1798 /* SerDes configuration via SERDESCTRL */ 1799 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C); 1800 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78); 1801 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23); 1802 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15); 1803 1804 /* CCM configuration via CCMCTL register */ 1805 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00); 1806 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00); 1807 1808 /* PCIe lanes configuration */ 1809 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC); 1810 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF); 1811 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05); 1812 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81); 1813 1814 /* PCIe PLL Configuration */ 1815 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47); 1816 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00); 1817 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00); 1818 } 1819 1820 return 0; 1821 } 1822 1823 /** 1824 * igb_read_mac_addr_82575 - Read device MAC address 1825 * @hw: pointer to the HW structure 1826 **/ 1827 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw) 1828 { 1829 s32 ret_val = 0; 1830 1831 /* If there's an alternate MAC address place it in RAR0 1832 * so that it will override the Si installed default perm 1833 * address. 1834 */ 1835 ret_val = igb_check_alt_mac_addr(hw); 1836 if (ret_val) 1837 goto out; 1838 1839 ret_val = igb_read_mac_addr(hw); 1840 1841 out: 1842 return ret_val; 1843 } 1844 1845 /** 1846 * igb_power_down_phy_copper_82575 - Remove link during PHY power down 1847 * @hw: pointer to the HW structure 1848 * 1849 * In the case of a PHY power down to save power, or to turn off link during a 1850 * driver unload, or wake on lan is not enabled, remove the link. 1851 **/ 1852 void igb_power_down_phy_copper_82575(struct e1000_hw *hw) 1853 { 1854 /* If the management interface is not enabled, then power down */ 1855 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw))) 1856 igb_power_down_phy_copper(hw); 1857 } 1858 1859 /** 1860 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters 1861 * @hw: pointer to the HW structure 1862 * 1863 * Clears the hardware counters by reading the counter registers. 1864 **/ 1865 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw) 1866 { 1867 igb_clear_hw_cntrs_base(hw); 1868 1869 rd32(E1000_PRC64); 1870 rd32(E1000_PRC127); 1871 rd32(E1000_PRC255); 1872 rd32(E1000_PRC511); 1873 rd32(E1000_PRC1023); 1874 rd32(E1000_PRC1522); 1875 rd32(E1000_PTC64); 1876 rd32(E1000_PTC127); 1877 rd32(E1000_PTC255); 1878 rd32(E1000_PTC511); 1879 rd32(E1000_PTC1023); 1880 rd32(E1000_PTC1522); 1881 1882 rd32(E1000_ALGNERRC); 1883 rd32(E1000_RXERRC); 1884 rd32(E1000_TNCRS); 1885 rd32(E1000_CEXTERR); 1886 rd32(E1000_TSCTC); 1887 rd32(E1000_TSCTFC); 1888 1889 rd32(E1000_MGTPRC); 1890 rd32(E1000_MGTPDC); 1891 rd32(E1000_MGTPTC); 1892 1893 rd32(E1000_IAC); 1894 rd32(E1000_ICRXOC); 1895 1896 rd32(E1000_ICRXPTC); 1897 rd32(E1000_ICRXATC); 1898 rd32(E1000_ICTXPTC); 1899 rd32(E1000_ICTXATC); 1900 rd32(E1000_ICTXQEC); 1901 rd32(E1000_ICTXQMTC); 1902 rd32(E1000_ICRXDMTC); 1903 1904 rd32(E1000_CBTMPC); 1905 rd32(E1000_HTDPMC); 1906 rd32(E1000_CBRMPC); 1907 rd32(E1000_RPTHC); 1908 rd32(E1000_HGPTC); 1909 rd32(E1000_HTCBDPC); 1910 rd32(E1000_HGORCL); 1911 rd32(E1000_HGORCH); 1912 rd32(E1000_HGOTCL); 1913 rd32(E1000_HGOTCH); 1914 rd32(E1000_LENERRS); 1915 1916 /* This register should not be read in copper configurations */ 1917 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1918 igb_sgmii_active_82575(hw)) 1919 rd32(E1000_SCVPC); 1920 } 1921 1922 /** 1923 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable 1924 * @hw: pointer to the HW structure 1925 * 1926 * After rx enable if manageability is enabled then there is likely some 1927 * bad data at the start of the fifo and possibly in the DMA fifo. This 1928 * function clears the fifos and flushes any packets that came in as rx was 1929 * being enabled. 1930 **/ 1931 void igb_rx_fifo_flush_82575(struct e1000_hw *hw) 1932 { 1933 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 1934 int i, ms_wait; 1935 1936 /* disable IPv6 options as per hardware errata */ 1937 rfctl = rd32(E1000_RFCTL); 1938 rfctl |= E1000_RFCTL_IPV6_EX_DIS; 1939 wr32(E1000_RFCTL, rfctl); 1940 1941 if (hw->mac.type != e1000_82575 || 1942 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 1943 return; 1944 1945 /* Disable all RX queues */ 1946 for (i = 0; i < 4; i++) { 1947 rxdctl[i] = rd32(E1000_RXDCTL(i)); 1948 wr32(E1000_RXDCTL(i), 1949 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 1950 } 1951 /* Poll all queues to verify they have shut down */ 1952 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 1953 usleep_range(1000, 2000); 1954 rx_enabled = 0; 1955 for (i = 0; i < 4; i++) 1956 rx_enabled |= rd32(E1000_RXDCTL(i)); 1957 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 1958 break; 1959 } 1960 1961 if (ms_wait == 10) 1962 hw_dbg("Queue disable timed out after 10ms\n"); 1963 1964 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 1965 * incoming packets are rejected. Set enable and wait 2ms so that 1966 * any packet that was coming in as RCTL.EN was set is flushed 1967 */ 1968 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 1969 1970 rlpml = rd32(E1000_RLPML); 1971 wr32(E1000_RLPML, 0); 1972 1973 rctl = rd32(E1000_RCTL); 1974 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 1975 temp_rctl |= E1000_RCTL_LPE; 1976 1977 wr32(E1000_RCTL, temp_rctl); 1978 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN); 1979 wrfl(); 1980 usleep_range(2000, 3000); 1981 1982 /* Enable RX queues that were previously enabled and restore our 1983 * previous state 1984 */ 1985 for (i = 0; i < 4; i++) 1986 wr32(E1000_RXDCTL(i), rxdctl[i]); 1987 wr32(E1000_RCTL, rctl); 1988 wrfl(); 1989 1990 wr32(E1000_RLPML, rlpml); 1991 wr32(E1000_RFCTL, rfctl); 1992 1993 /* Flush receive errors generated by workaround */ 1994 rd32(E1000_ROC); 1995 rd32(E1000_RNBC); 1996 rd32(E1000_MPC); 1997 } 1998 1999 /** 2000 * igb_set_pcie_completion_timeout - set pci-e completion timeout 2001 * @hw: pointer to the HW structure 2002 * 2003 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 2004 * however the hardware default for these parts is 500us to 1ms which is less 2005 * than the 10ms recommended by the pci-e spec. To address this we need to 2006 * increase the value to either 10ms to 200ms for capability version 1 config, 2007 * or 16ms to 55ms for version 2. 2008 **/ 2009 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw) 2010 { 2011 u32 gcr = rd32(E1000_GCR); 2012 s32 ret_val = 0; 2013 u16 pcie_devctl2; 2014 2015 /* only take action if timeout value is defaulted to 0 */ 2016 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 2017 goto out; 2018 2019 /* if capabilities version is type 1 we can write the 2020 * timeout of 10ms to 200ms through the GCR register 2021 */ 2022 if (!(gcr & E1000_GCR_CAP_VER2)) { 2023 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 2024 goto out; 2025 } 2026 2027 /* for version 2 capabilities we need to write the config space 2028 * directly in order to set the completion timeout value for 2029 * 16ms to 55ms 2030 */ 2031 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2032 &pcie_devctl2); 2033 if (ret_val) 2034 goto out; 2035 2036 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 2037 2038 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2039 &pcie_devctl2); 2040 out: 2041 /* disable completion timeout resend */ 2042 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 2043 2044 wr32(E1000_GCR, gcr); 2045 return ret_val; 2046 } 2047 2048 /** 2049 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing 2050 * @hw: pointer to the hardware struct 2051 * @enable: state to enter, either enabled or disabled 2052 * @pf: Physical Function pool - do not set anti-spoofing for the PF 2053 * 2054 * enables/disables L2 switch anti-spoofing functionality. 2055 **/ 2056 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) 2057 { 2058 u32 reg_val, reg_offset; 2059 2060 switch (hw->mac.type) { 2061 case e1000_82576: 2062 reg_offset = E1000_DTXSWC; 2063 break; 2064 case e1000_i350: 2065 case e1000_i354: 2066 reg_offset = E1000_TXSWC; 2067 break; 2068 default: 2069 return; 2070 } 2071 2072 reg_val = rd32(reg_offset); 2073 if (enable) { 2074 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK | 2075 E1000_DTXSWC_VLAN_SPOOF_MASK); 2076 /* The PF can spoof - it has to in order to 2077 * support emulation mode NICs 2078 */ 2079 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS)); 2080 } else { 2081 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | 2082 E1000_DTXSWC_VLAN_SPOOF_MASK); 2083 } 2084 wr32(reg_offset, reg_val); 2085 } 2086 2087 /** 2088 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback 2089 * @hw: pointer to the hardware struct 2090 * @enable: state to enter, either enabled or disabled 2091 * 2092 * enables/disables L2 switch loopback functionality. 2093 **/ 2094 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 2095 { 2096 u32 dtxswc; 2097 2098 switch (hw->mac.type) { 2099 case e1000_82576: 2100 dtxswc = rd32(E1000_DTXSWC); 2101 if (enable) 2102 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2103 else 2104 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2105 wr32(E1000_DTXSWC, dtxswc); 2106 break; 2107 case e1000_i354: 2108 case e1000_i350: 2109 dtxswc = rd32(E1000_TXSWC); 2110 if (enable) 2111 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2112 else 2113 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2114 wr32(E1000_TXSWC, dtxswc); 2115 break; 2116 default: 2117 /* Currently no other hardware supports loopback */ 2118 break; 2119 } 2120 2121 } 2122 2123 /** 2124 * igb_vmdq_set_replication_pf - enable or disable vmdq replication 2125 * @hw: pointer to the hardware struct 2126 * @enable: state to enter, either enabled or disabled 2127 * 2128 * enables/disables replication of packets across multiple pools. 2129 **/ 2130 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 2131 { 2132 u32 vt_ctl = rd32(E1000_VT_CTL); 2133 2134 if (enable) 2135 vt_ctl |= E1000_VT_CTL_VM_REPL_EN; 2136 else 2137 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; 2138 2139 wr32(E1000_VT_CTL, vt_ctl); 2140 } 2141 2142 /** 2143 * igb_read_phy_reg_82580 - Read 82580 MDI control register 2144 * @hw: pointer to the HW structure 2145 * @offset: register offset to be read 2146 * @data: pointer to the read data 2147 * 2148 * Reads the MDI control register in the PHY at offset and stores the 2149 * information read to data. 2150 **/ 2151 s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) 2152 { 2153 s32 ret_val; 2154 2155 ret_val = hw->phy.ops.acquire(hw); 2156 if (ret_val) 2157 goto out; 2158 2159 ret_val = igb_read_phy_reg_mdic(hw, offset, data); 2160 2161 hw->phy.ops.release(hw); 2162 2163 out: 2164 return ret_val; 2165 } 2166 2167 /** 2168 * igb_write_phy_reg_82580 - Write 82580 MDI control register 2169 * @hw: pointer to the HW structure 2170 * @offset: register offset to write to 2171 * @data: data to write to register at offset 2172 * 2173 * Writes data to MDI control register in the PHY at offset. 2174 **/ 2175 s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) 2176 { 2177 s32 ret_val; 2178 2179 2180 ret_val = hw->phy.ops.acquire(hw); 2181 if (ret_val) 2182 goto out; 2183 2184 ret_val = igb_write_phy_reg_mdic(hw, offset, data); 2185 2186 hw->phy.ops.release(hw); 2187 2188 out: 2189 return ret_val; 2190 } 2191 2192 /** 2193 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits 2194 * @hw: pointer to the HW structure 2195 * 2196 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on 2197 * the values found in the EEPROM. This addresses an issue in which these 2198 * bits are not restored from EEPROM after reset. 2199 **/ 2200 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw) 2201 { 2202 s32 ret_val = 0; 2203 u32 mdicnfg; 2204 u16 nvm_data = 0; 2205 2206 if (hw->mac.type != e1000_82580) 2207 goto out; 2208 if (!igb_sgmii_active_82575(hw)) 2209 goto out; 2210 2211 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2212 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2213 &nvm_data); 2214 if (ret_val) { 2215 hw_dbg("NVM Read Error\n"); 2216 goto out; 2217 } 2218 2219 mdicnfg = rd32(E1000_MDICNFG); 2220 if (nvm_data & NVM_WORD24_EXT_MDIO) 2221 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 2222 if (nvm_data & NVM_WORD24_COM_MDIO) 2223 mdicnfg |= E1000_MDICNFG_COM_MDIO; 2224 wr32(E1000_MDICNFG, mdicnfg); 2225 out: 2226 return ret_val; 2227 } 2228 2229 /** 2230 * igb_reset_hw_82580 - Reset hardware 2231 * @hw: pointer to the HW structure 2232 * 2233 * This resets function or entire device (all ports, etc.) 2234 * to a known state. 2235 **/ 2236 static s32 igb_reset_hw_82580(struct e1000_hw *hw) 2237 { 2238 s32 ret_val = 0; 2239 /* BH SW mailbox bit in SW_FW_SYNC */ 2240 u16 swmbsw_mask = E1000_SW_SYNCH_MB; 2241 u32 ctrl; 2242 bool global_device_reset = hw->dev_spec._82575.global_device_reset; 2243 2244 hw->dev_spec._82575.global_device_reset = false; 2245 2246 /* due to hw errata, global device reset doesn't always 2247 * work on 82580 2248 */ 2249 if (hw->mac.type == e1000_82580) 2250 global_device_reset = false; 2251 2252 /* Get current control state. */ 2253 ctrl = rd32(E1000_CTRL); 2254 2255 /* Prevent the PCI-E bus from sticking if there is no TLP connection 2256 * on the last TLP read/write transaction when MAC is reset. 2257 */ 2258 ret_val = igb_disable_pcie_master(hw); 2259 if (ret_val) 2260 hw_dbg("PCI-E Master disable polling has failed.\n"); 2261 2262 hw_dbg("Masking off all interrupts\n"); 2263 wr32(E1000_IMC, 0xffffffff); 2264 wr32(E1000_RCTL, 0); 2265 wr32(E1000_TCTL, E1000_TCTL_PSP); 2266 wrfl(); 2267 2268 usleep_range(10000, 11000); 2269 2270 /* Determine whether or not a global dev reset is requested */ 2271 if (global_device_reset && 2272 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask)) 2273 global_device_reset = false; 2274 2275 if (global_device_reset && 2276 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET)) 2277 ctrl |= E1000_CTRL_DEV_RST; 2278 else 2279 ctrl |= E1000_CTRL_RST; 2280 2281 wr32(E1000_CTRL, ctrl); 2282 wrfl(); 2283 2284 /* Add delay to insure DEV_RST has time to complete */ 2285 if (global_device_reset) 2286 usleep_range(5000, 6000); 2287 2288 ret_val = igb_get_auto_rd_done(hw); 2289 if (ret_val) { 2290 /* When auto config read does not complete, do not 2291 * return with an error. This can happen in situations 2292 * where there is no eeprom and prevents getting link. 2293 */ 2294 hw_dbg("Auto Read Done did not complete\n"); 2295 } 2296 2297 /* clear global device reset status bit */ 2298 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET); 2299 2300 /* Clear any pending interrupt events. */ 2301 wr32(E1000_IMC, 0xffffffff); 2302 rd32(E1000_ICR); 2303 2304 ret_val = igb_reset_mdicnfg_82580(hw); 2305 if (ret_val) 2306 hw_dbg("Could not reset MDICNFG based on EEPROM\n"); 2307 2308 /* Install any alternate MAC address into RAR0 */ 2309 ret_val = igb_check_alt_mac_addr(hw); 2310 2311 /* Release semaphore */ 2312 if (global_device_reset) 2313 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask); 2314 2315 return ret_val; 2316 } 2317 2318 /** 2319 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size 2320 * @data: data received by reading RXPBS register 2321 * 2322 * The 82580 uses a table based approach for packet buffer allocation sizes. 2323 * This function converts the retrieved value into the correct table value 2324 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 2325 * 0x0 36 72 144 1 2 4 8 16 2326 * 0x8 35 70 140 rsv rsv rsv rsv rsv 2327 */ 2328 u16 igb_rxpbs_adjust_82580(u32 data) 2329 { 2330 u16 ret_val = 0; 2331 2332 if (data < ARRAY_SIZE(e1000_82580_rxpbs_table)) 2333 ret_val = e1000_82580_rxpbs_table[data]; 2334 2335 return ret_val; 2336 } 2337 2338 /** 2339 * igb_validate_nvm_checksum_with_offset - Validate EEPROM 2340 * checksum 2341 * @hw: pointer to the HW structure 2342 * @offset: offset in words of the checksum protected region 2343 * 2344 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 2345 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 2346 **/ 2347 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw, 2348 u16 offset) 2349 { 2350 s32 ret_val = 0; 2351 u16 checksum = 0; 2352 u16 i, nvm_data; 2353 2354 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) { 2355 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2356 if (ret_val) { 2357 hw_dbg("NVM Read Error\n"); 2358 goto out; 2359 } 2360 checksum += nvm_data; 2361 } 2362 2363 if (checksum != (u16) NVM_SUM) { 2364 hw_dbg("NVM Checksum Invalid\n"); 2365 ret_val = -E1000_ERR_NVM; 2366 goto out; 2367 } 2368 2369 out: 2370 return ret_val; 2371 } 2372 2373 /** 2374 * igb_update_nvm_checksum_with_offset - Update EEPROM 2375 * checksum 2376 * @hw: pointer to the HW structure 2377 * @offset: offset in words of the checksum protected region 2378 * 2379 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 2380 * up to the checksum. Then calculates the EEPROM checksum and writes the 2381 * value to the EEPROM. 2382 **/ 2383 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2384 { 2385 s32 ret_val; 2386 u16 checksum = 0; 2387 u16 i, nvm_data; 2388 2389 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) { 2390 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2391 if (ret_val) { 2392 hw_dbg("NVM Read Error while updating checksum.\n"); 2393 goto out; 2394 } 2395 checksum += nvm_data; 2396 } 2397 checksum = (u16) NVM_SUM - checksum; 2398 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, 2399 &checksum); 2400 if (ret_val) 2401 hw_dbg("NVM Write Error while updating checksum.\n"); 2402 2403 out: 2404 return ret_val; 2405 } 2406 2407 /** 2408 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum 2409 * @hw: pointer to the HW structure 2410 * 2411 * Calculates the EEPROM section checksum by reading/adding each word of 2412 * the EEPROM and then verifies that the sum of the EEPROM is 2413 * equal to 0xBABA. 2414 **/ 2415 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw) 2416 { 2417 s32 ret_val = 0; 2418 u16 eeprom_regions_count = 1; 2419 u16 j, nvm_data; 2420 u16 nvm_offset; 2421 2422 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2423 if (ret_val) { 2424 hw_dbg("NVM Read Error\n"); 2425 goto out; 2426 } 2427 2428 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) { 2429 /* if checksums compatibility bit is set validate checksums 2430 * for all 4 ports. 2431 */ 2432 eeprom_regions_count = 4; 2433 } 2434 2435 for (j = 0; j < eeprom_regions_count; j++) { 2436 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2437 ret_val = igb_validate_nvm_checksum_with_offset(hw, 2438 nvm_offset); 2439 if (ret_val != 0) 2440 goto out; 2441 } 2442 2443 out: 2444 return ret_val; 2445 } 2446 2447 /** 2448 * igb_update_nvm_checksum_82580 - Update EEPROM checksum 2449 * @hw: pointer to the HW structure 2450 * 2451 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2452 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2453 * checksum and writes the value to the EEPROM. 2454 **/ 2455 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw) 2456 { 2457 s32 ret_val; 2458 u16 j, nvm_data; 2459 u16 nvm_offset; 2460 2461 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2462 if (ret_val) { 2463 hw_dbg("NVM Read Error while updating checksum compatibility bit.\n"); 2464 goto out; 2465 } 2466 2467 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) { 2468 /* set compatibility bit to validate checksums appropriately */ 2469 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK; 2470 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, 2471 &nvm_data); 2472 if (ret_val) { 2473 hw_dbg("NVM Write Error while updating checksum compatibility bit.\n"); 2474 goto out; 2475 } 2476 } 2477 2478 for (j = 0; j < 4; j++) { 2479 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2480 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset); 2481 if (ret_val) 2482 goto out; 2483 } 2484 2485 out: 2486 return ret_val; 2487 } 2488 2489 /** 2490 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum 2491 * @hw: pointer to the HW structure 2492 * 2493 * Calculates the EEPROM section checksum by reading/adding each word of 2494 * the EEPROM and then verifies that the sum of the EEPROM is 2495 * equal to 0xBABA. 2496 **/ 2497 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw) 2498 { 2499 s32 ret_val = 0; 2500 u16 j; 2501 u16 nvm_offset; 2502 2503 for (j = 0; j < 4; j++) { 2504 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2505 ret_val = igb_validate_nvm_checksum_with_offset(hw, 2506 nvm_offset); 2507 if (ret_val != 0) 2508 goto out; 2509 } 2510 2511 out: 2512 return ret_val; 2513 } 2514 2515 /** 2516 * igb_update_nvm_checksum_i350 - Update EEPROM checksum 2517 * @hw: pointer to the HW structure 2518 * 2519 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2520 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2521 * checksum and writes the value to the EEPROM. 2522 **/ 2523 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw) 2524 { 2525 s32 ret_val = 0; 2526 u16 j; 2527 u16 nvm_offset; 2528 2529 for (j = 0; j < 4; j++) { 2530 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2531 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset); 2532 if (ret_val != 0) 2533 goto out; 2534 } 2535 2536 out: 2537 return ret_val; 2538 } 2539 2540 /** 2541 * __igb_access_emi_reg - Read/write EMI register 2542 * @hw: pointer to the HW structure 2543 * @addr: EMI address to program 2544 * @data: pointer to value to read/write from/to the EMI address 2545 * @read: boolean flag to indicate read or write 2546 **/ 2547 static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address, 2548 u16 *data, bool read) 2549 { 2550 s32 ret_val = 0; 2551 2552 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address); 2553 if (ret_val) 2554 return ret_val; 2555 2556 if (read) 2557 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data); 2558 else 2559 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data); 2560 2561 return ret_val; 2562 } 2563 2564 /** 2565 * igb_read_emi_reg - Read Extended Management Interface register 2566 * @hw: pointer to the HW structure 2567 * @addr: EMI address to program 2568 * @data: value to be read from the EMI address 2569 **/ 2570 s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data) 2571 { 2572 return __igb_access_emi_reg(hw, addr, data, true); 2573 } 2574 2575 /** 2576 * igb_set_eee_i350 - Enable/disable EEE support 2577 * @hw: pointer to the HW structure 2578 * @adv1G: boolean flag enabling 1G EEE advertisement 2579 * @adv100m: boolean flag enabling 100M EEE advertisement 2580 * 2581 * Enable/disable EEE based on setting in dev_spec structure. 2582 * 2583 **/ 2584 s32 igb_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M) 2585 { 2586 u32 ipcnfg, eeer; 2587 2588 if ((hw->mac.type < e1000_i350) || 2589 (hw->phy.media_type != e1000_media_type_copper)) 2590 goto out; 2591 ipcnfg = rd32(E1000_IPCNFG); 2592 eeer = rd32(E1000_EEER); 2593 2594 /* enable or disable per user setting */ 2595 if (!(hw->dev_spec._82575.eee_disable)) { 2596 u32 eee_su = rd32(E1000_EEE_SU); 2597 2598 if (adv100M) 2599 ipcnfg |= E1000_IPCNFG_EEE_100M_AN; 2600 else 2601 ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN; 2602 2603 if (adv1G) 2604 ipcnfg |= E1000_IPCNFG_EEE_1G_AN; 2605 else 2606 ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN; 2607 2608 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 2609 E1000_EEER_LPI_FC); 2610 2611 /* This bit should not be set in normal operation. */ 2612 if (eee_su & E1000_EEE_SU_LPI_CLK_STP) 2613 hw_dbg("LPI Clock Stop Bit should not be set!\n"); 2614 2615 } else { 2616 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | 2617 E1000_IPCNFG_EEE_100M_AN); 2618 eeer &= ~(E1000_EEER_TX_LPI_EN | 2619 E1000_EEER_RX_LPI_EN | 2620 E1000_EEER_LPI_FC); 2621 } 2622 wr32(E1000_IPCNFG, ipcnfg); 2623 wr32(E1000_EEER, eeer); 2624 rd32(E1000_IPCNFG); 2625 rd32(E1000_EEER); 2626 out: 2627 2628 return 0; 2629 } 2630 2631 /** 2632 * igb_set_eee_i354 - Enable/disable EEE support 2633 * @hw: pointer to the HW structure 2634 * @adv1G: boolean flag enabling 1G EEE advertisement 2635 * @adv100m: boolean flag enabling 100M EEE advertisement 2636 * 2637 * Enable/disable EEE legacy mode based on setting in dev_spec structure. 2638 * 2639 **/ 2640 s32 igb_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M) 2641 { 2642 struct e1000_phy_info *phy = &hw->phy; 2643 s32 ret_val = 0; 2644 u16 phy_data; 2645 2646 if ((hw->phy.media_type != e1000_media_type_copper) || 2647 ((phy->id != M88E1543_E_PHY_ID) && 2648 (phy->id != M88E1512_E_PHY_ID))) 2649 goto out; 2650 2651 if (!hw->dev_spec._82575.eee_disable) { 2652 /* Switch to PHY page 18. */ 2653 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18); 2654 if (ret_val) 2655 goto out; 2656 2657 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1, 2658 &phy_data); 2659 if (ret_val) 2660 goto out; 2661 2662 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS; 2663 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1, 2664 phy_data); 2665 if (ret_val) 2666 goto out; 2667 2668 /* Return the PHY to page 0. */ 2669 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); 2670 if (ret_val) 2671 goto out; 2672 2673 /* Turn on EEE advertisement. */ 2674 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2675 E1000_EEE_ADV_DEV_I354, 2676 &phy_data); 2677 if (ret_val) 2678 goto out; 2679 2680 if (adv100M) 2681 phy_data |= E1000_EEE_ADV_100_SUPPORTED; 2682 else 2683 phy_data &= ~E1000_EEE_ADV_100_SUPPORTED; 2684 2685 if (adv1G) 2686 phy_data |= E1000_EEE_ADV_1000_SUPPORTED; 2687 else 2688 phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED; 2689 2690 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2691 E1000_EEE_ADV_DEV_I354, 2692 phy_data); 2693 } else { 2694 /* Turn off EEE advertisement. */ 2695 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2696 E1000_EEE_ADV_DEV_I354, 2697 &phy_data); 2698 if (ret_val) 2699 goto out; 2700 2701 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED | 2702 E1000_EEE_ADV_1000_SUPPORTED); 2703 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2704 E1000_EEE_ADV_DEV_I354, 2705 phy_data); 2706 } 2707 2708 out: 2709 return ret_val; 2710 } 2711 2712 /** 2713 * igb_get_eee_status_i354 - Get EEE status 2714 * @hw: pointer to the HW structure 2715 * @status: EEE status 2716 * 2717 * Get EEE status by guessing based on whether Tx or Rx LPI indications have 2718 * been received. 2719 **/ 2720 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status) 2721 { 2722 struct e1000_phy_info *phy = &hw->phy; 2723 s32 ret_val = 0; 2724 u16 phy_data; 2725 2726 /* Check if EEE is supported on this device. */ 2727 if ((hw->phy.media_type != e1000_media_type_copper) || 2728 ((phy->id != M88E1543_E_PHY_ID) && 2729 (phy->id != M88E1512_E_PHY_ID))) 2730 goto out; 2731 2732 ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354, 2733 E1000_PCS_STATUS_DEV_I354, 2734 &phy_data); 2735 if (ret_val) 2736 goto out; 2737 2738 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD | 2739 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false; 2740 2741 out: 2742 return ret_val; 2743 } 2744 2745 static const u8 e1000_emc_temp_data[4] = { 2746 E1000_EMC_INTERNAL_DATA, 2747 E1000_EMC_DIODE1_DATA, 2748 E1000_EMC_DIODE2_DATA, 2749 E1000_EMC_DIODE3_DATA 2750 }; 2751 static const u8 e1000_emc_therm_limit[4] = { 2752 E1000_EMC_INTERNAL_THERM_LIMIT, 2753 E1000_EMC_DIODE1_THERM_LIMIT, 2754 E1000_EMC_DIODE2_THERM_LIMIT, 2755 E1000_EMC_DIODE3_THERM_LIMIT 2756 }; 2757 2758 #ifdef CONFIG_IGB_HWMON 2759 /** 2760 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data 2761 * @hw: pointer to hardware structure 2762 * 2763 * Updates the temperatures in mac.thermal_sensor_data 2764 **/ 2765 static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw) 2766 { 2767 u16 ets_offset; 2768 u16 ets_cfg; 2769 u16 ets_sensor; 2770 u8 num_sensors; 2771 u8 sensor_index; 2772 u8 sensor_location; 2773 u8 i; 2774 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 2775 2776 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0)) 2777 return E1000_NOT_IMPLEMENTED; 2778 2779 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF); 2780 2781 /* Return the internal sensor only if ETS is unsupported */ 2782 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset); 2783 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) 2784 return 0; 2785 2786 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg); 2787 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT) 2788 != NVM_ETS_TYPE_EMC) 2789 return E1000_NOT_IMPLEMENTED; 2790 2791 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK); 2792 if (num_sensors > E1000_MAX_SENSORS) 2793 num_sensors = E1000_MAX_SENSORS; 2794 2795 for (i = 1; i < num_sensors; i++) { 2796 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor); 2797 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >> 2798 NVM_ETS_DATA_INDEX_SHIFT); 2799 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >> 2800 NVM_ETS_DATA_LOC_SHIFT); 2801 2802 if (sensor_location != 0) 2803 hw->phy.ops.read_i2c_byte(hw, 2804 e1000_emc_temp_data[sensor_index], 2805 E1000_I2C_THERMAL_SENSOR_ADDR, 2806 &data->sensor[i].temp); 2807 } 2808 return 0; 2809 } 2810 2811 /** 2812 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds 2813 * @hw: pointer to hardware structure 2814 * 2815 * Sets the thermal sensor thresholds according to the NVM map 2816 * and save off the threshold and location values into mac.thermal_sensor_data 2817 **/ 2818 static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw) 2819 { 2820 u16 ets_offset; 2821 u16 ets_cfg; 2822 u16 ets_sensor; 2823 u8 low_thresh_delta; 2824 u8 num_sensors; 2825 u8 sensor_index; 2826 u8 sensor_location; 2827 u8 therm_limit; 2828 u8 i; 2829 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 2830 2831 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0)) 2832 return E1000_NOT_IMPLEMENTED; 2833 2834 memset(data, 0, sizeof(struct e1000_thermal_sensor_data)); 2835 2836 data->sensor[0].location = 0x1; 2837 data->sensor[0].caution_thresh = 2838 (rd32(E1000_THHIGHTC) & 0xFF); 2839 data->sensor[0].max_op_thresh = 2840 (rd32(E1000_THLOWTC) & 0xFF); 2841 2842 /* Return the internal sensor only if ETS is unsupported */ 2843 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset); 2844 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) 2845 return 0; 2846 2847 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg); 2848 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT) 2849 != NVM_ETS_TYPE_EMC) 2850 return E1000_NOT_IMPLEMENTED; 2851 2852 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >> 2853 NVM_ETS_LTHRES_DELTA_SHIFT); 2854 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK); 2855 2856 for (i = 1; i <= num_sensors; i++) { 2857 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor); 2858 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >> 2859 NVM_ETS_DATA_INDEX_SHIFT); 2860 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >> 2861 NVM_ETS_DATA_LOC_SHIFT); 2862 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK; 2863 2864 hw->phy.ops.write_i2c_byte(hw, 2865 e1000_emc_therm_limit[sensor_index], 2866 E1000_I2C_THERMAL_SENSOR_ADDR, 2867 therm_limit); 2868 2869 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) { 2870 data->sensor[i].location = sensor_location; 2871 data->sensor[i].caution_thresh = therm_limit; 2872 data->sensor[i].max_op_thresh = therm_limit - 2873 low_thresh_delta; 2874 } 2875 } 2876 return 0; 2877 } 2878 2879 #endif 2880 static struct e1000_mac_operations e1000_mac_ops_82575 = { 2881 .init_hw = igb_init_hw_82575, 2882 .check_for_link = igb_check_for_link_82575, 2883 .rar_set = igb_rar_set, 2884 .read_mac_addr = igb_read_mac_addr_82575, 2885 .get_speed_and_duplex = igb_get_link_up_info_82575, 2886 #ifdef CONFIG_IGB_HWMON 2887 .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic, 2888 .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic, 2889 #endif 2890 }; 2891 2892 static struct e1000_phy_operations e1000_phy_ops_82575 = { 2893 .acquire = igb_acquire_phy_82575, 2894 .get_cfg_done = igb_get_cfg_done_82575, 2895 .release = igb_release_phy_82575, 2896 .write_i2c_byte = igb_write_i2c_byte, 2897 .read_i2c_byte = igb_read_i2c_byte, 2898 }; 2899 2900 static struct e1000_nvm_operations e1000_nvm_ops_82575 = { 2901 .acquire = igb_acquire_nvm_82575, 2902 .read = igb_read_nvm_eerd, 2903 .release = igb_release_nvm_82575, 2904 .write = igb_write_nvm_spi, 2905 }; 2906 2907 const struct e1000_info e1000_82575_info = { 2908 .get_invariants = igb_get_invariants_82575, 2909 .mac_ops = &e1000_mac_ops_82575, 2910 .phy_ops = &e1000_phy_ops_82575, 2911 .nvm_ops = &e1000_nvm_ops_82575, 2912 }; 2913 2914