1 /* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2015 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 /* e1000_82575 25 * e1000_82576 26 */ 27 28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 29 30 #include <linux/types.h> 31 #include <linux/if_ether.h> 32 #include <linux/i2c.h> 33 34 #include "e1000_mac.h" 35 #include "e1000_82575.h" 36 #include "e1000_i210.h" 37 #include "igb.h" 38 39 static s32 igb_get_invariants_82575(struct e1000_hw *); 40 static s32 igb_acquire_phy_82575(struct e1000_hw *); 41 static void igb_release_phy_82575(struct e1000_hw *); 42 static s32 igb_acquire_nvm_82575(struct e1000_hw *); 43 static void igb_release_nvm_82575(struct e1000_hw *); 44 static s32 igb_check_for_link_82575(struct e1000_hw *); 45 static s32 igb_get_cfg_done_82575(struct e1000_hw *); 46 static s32 igb_init_hw_82575(struct e1000_hw *); 47 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *); 48 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *); 49 static s32 igb_reset_hw_82575(struct e1000_hw *); 50 static s32 igb_reset_hw_82580(struct e1000_hw *); 51 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); 52 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool); 53 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool); 54 static s32 igb_setup_copper_link_82575(struct e1000_hw *); 55 static s32 igb_setup_serdes_link_82575(struct e1000_hw *); 56 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16); 57 static void igb_clear_hw_cntrs_82575(struct e1000_hw *); 58 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16); 59 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *, 60 u16 *); 61 static s32 igb_get_phy_id_82575(struct e1000_hw *); 62 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16); 63 static bool igb_sgmii_active_82575(struct e1000_hw *); 64 static s32 igb_reset_init_script_82575(struct e1000_hw *); 65 static s32 igb_read_mac_addr_82575(struct e1000_hw *); 66 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw); 67 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw); 68 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw); 69 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw); 70 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw); 71 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw); 72 static const u16 e1000_82580_rxpbs_table[] = { 73 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 }; 74 75 /* Due to a hw errata, if the host tries to configure the VFTA register 76 * while performing queries from the BMC or DMA, then the VFTA in some 77 * cases won't be written. 78 */ 79 80 /** 81 * igb_write_vfta_i350 - Write value to VLAN filter table 82 * @hw: pointer to the HW structure 83 * @offset: register offset in VLAN filter table 84 * @value: register value written to VLAN filter table 85 * 86 * Writes value at the given offset in the register array which stores 87 * the VLAN filter table. 88 **/ 89 static void igb_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value) 90 { 91 struct igb_adapter *adapter = hw->back; 92 int i; 93 94 for (i = 10; i--;) 95 array_wr32(E1000_VFTA, offset, value); 96 97 wrfl(); 98 adapter->shadow_vfta[offset] = value; 99 } 100 101 /** 102 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO 103 * @hw: pointer to the HW structure 104 * 105 * Called to determine if the I2C pins are being used for I2C or as an 106 * external MDIO interface since the two options are mutually exclusive. 107 **/ 108 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw) 109 { 110 u32 reg = 0; 111 bool ext_mdio = false; 112 113 switch (hw->mac.type) { 114 case e1000_82575: 115 case e1000_82576: 116 reg = rd32(E1000_MDIC); 117 ext_mdio = !!(reg & E1000_MDIC_DEST); 118 break; 119 case e1000_82580: 120 case e1000_i350: 121 case e1000_i354: 122 case e1000_i210: 123 case e1000_i211: 124 reg = rd32(E1000_MDICNFG); 125 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); 126 break; 127 default: 128 break; 129 } 130 return ext_mdio; 131 } 132 133 /** 134 * igb_check_for_link_media_swap - Check which M88E1112 interface linked 135 * @hw: pointer to the HW structure 136 * 137 * Poll the M88E1112 interfaces to see which interface achieved link. 138 */ 139 static s32 igb_check_for_link_media_swap(struct e1000_hw *hw) 140 { 141 struct e1000_phy_info *phy = &hw->phy; 142 s32 ret_val; 143 u16 data; 144 u8 port = 0; 145 146 /* Check the copper medium. */ 147 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 148 if (ret_val) 149 return ret_val; 150 151 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); 152 if (ret_val) 153 return ret_val; 154 155 if (data & E1000_M88E1112_STATUS_LINK) 156 port = E1000_MEDIA_PORT_COPPER; 157 158 /* Check the other medium. */ 159 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1); 160 if (ret_val) 161 return ret_val; 162 163 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); 164 if (ret_val) 165 return ret_val; 166 167 168 if (data & E1000_M88E1112_STATUS_LINK) 169 port = E1000_MEDIA_PORT_OTHER; 170 171 /* Determine if a swap needs to happen. */ 172 if (port && (hw->dev_spec._82575.media_port != port)) { 173 hw->dev_spec._82575.media_port = port; 174 hw->dev_spec._82575.media_changed = true; 175 } 176 177 if (port == E1000_MEDIA_PORT_COPPER) { 178 /* reset page to 0 */ 179 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 180 if (ret_val) 181 return ret_val; 182 igb_check_for_link_82575(hw); 183 } else { 184 igb_check_for_link_82575(hw); 185 /* reset page to 0 */ 186 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 187 if (ret_val) 188 return ret_val; 189 } 190 191 return 0; 192 } 193 194 /** 195 * igb_init_phy_params_82575 - Init PHY func ptrs. 196 * @hw: pointer to the HW structure 197 **/ 198 static s32 igb_init_phy_params_82575(struct e1000_hw *hw) 199 { 200 struct e1000_phy_info *phy = &hw->phy; 201 s32 ret_val = 0; 202 u32 ctrl_ext; 203 204 if (hw->phy.media_type != e1000_media_type_copper) { 205 phy->type = e1000_phy_none; 206 goto out; 207 } 208 209 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 210 phy->reset_delay_us = 100; 211 212 ctrl_ext = rd32(E1000_CTRL_EXT); 213 214 if (igb_sgmii_active_82575(hw)) { 215 phy->ops.reset = igb_phy_hw_reset_sgmii_82575; 216 ctrl_ext |= E1000_CTRL_I2C_ENA; 217 } else { 218 phy->ops.reset = igb_phy_hw_reset; 219 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 220 } 221 222 wr32(E1000_CTRL_EXT, ctrl_ext); 223 igb_reset_mdicnfg_82580(hw); 224 225 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) { 226 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575; 227 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575; 228 } else { 229 switch (hw->mac.type) { 230 case e1000_82580: 231 case e1000_i350: 232 case e1000_i354: 233 case e1000_i210: 234 case e1000_i211: 235 phy->ops.read_reg = igb_read_phy_reg_82580; 236 phy->ops.write_reg = igb_write_phy_reg_82580; 237 break; 238 default: 239 phy->ops.read_reg = igb_read_phy_reg_igp; 240 phy->ops.write_reg = igb_write_phy_reg_igp; 241 } 242 } 243 244 /* set lan id */ 245 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >> 246 E1000_STATUS_FUNC_SHIFT; 247 248 /* Make sure the PHY is in a good state. Several people have reported 249 * firmware leaving the PHY's page select register set to something 250 * other than the default of zero, which causes the PHY ID read to 251 * access something other than the intended register. 252 */ 253 ret_val = hw->phy.ops.reset(hw); 254 if (ret_val) { 255 hw_dbg("Error resetting the PHY.\n"); 256 goto out; 257 } 258 259 /* Set phy->phy_addr and phy->id. */ 260 igb_write_phy_reg_82580(hw, I347AT4_PAGE_SELECT, 0); 261 ret_val = igb_get_phy_id_82575(hw); 262 if (ret_val) 263 return ret_val; 264 265 /* Verify phy id and set remaining function pointers */ 266 switch (phy->id) { 267 case M88E1543_E_PHY_ID: 268 case M88E1512_E_PHY_ID: 269 case I347AT4_E_PHY_ID: 270 case M88E1112_E_PHY_ID: 271 case M88E1111_I_PHY_ID: 272 phy->type = e1000_phy_m88; 273 phy->ops.check_polarity = igb_check_polarity_m88; 274 phy->ops.get_phy_info = igb_get_phy_info_m88; 275 if (phy->id != M88E1111_I_PHY_ID) 276 phy->ops.get_cable_length = 277 igb_get_cable_length_m88_gen2; 278 else 279 phy->ops.get_cable_length = igb_get_cable_length_m88; 280 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; 281 /* Check if this PHY is configured for media swap. */ 282 if (phy->id == M88E1112_E_PHY_ID) { 283 u16 data; 284 285 ret_val = phy->ops.write_reg(hw, 286 E1000_M88E1112_PAGE_ADDR, 287 2); 288 if (ret_val) 289 goto out; 290 291 ret_val = phy->ops.read_reg(hw, 292 E1000_M88E1112_MAC_CTRL_1, 293 &data); 294 if (ret_val) 295 goto out; 296 297 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >> 298 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT; 299 if (data == E1000_M88E1112_AUTO_COPPER_SGMII || 300 data == E1000_M88E1112_AUTO_COPPER_BASEX) 301 hw->mac.ops.check_for_link = 302 igb_check_for_link_media_swap; 303 } 304 if (phy->id == M88E1512_E_PHY_ID) { 305 ret_val = igb_initialize_M88E1512_phy(hw); 306 if (ret_val) 307 goto out; 308 } 309 if (phy->id == M88E1543_E_PHY_ID) { 310 ret_val = igb_initialize_M88E1543_phy(hw); 311 if (ret_val) 312 goto out; 313 } 314 break; 315 case IGP03E1000_E_PHY_ID: 316 phy->type = e1000_phy_igp_3; 317 phy->ops.get_phy_info = igb_get_phy_info_igp; 318 phy->ops.get_cable_length = igb_get_cable_length_igp_2; 319 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp; 320 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575; 321 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state; 322 break; 323 case I82580_I_PHY_ID: 324 case I350_I_PHY_ID: 325 phy->type = e1000_phy_82580; 326 phy->ops.force_speed_duplex = 327 igb_phy_force_speed_duplex_82580; 328 phy->ops.get_cable_length = igb_get_cable_length_82580; 329 phy->ops.get_phy_info = igb_get_phy_info_82580; 330 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580; 331 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580; 332 break; 333 case I210_I_PHY_ID: 334 phy->type = e1000_phy_i210; 335 phy->ops.check_polarity = igb_check_polarity_m88; 336 phy->ops.get_cfg_done = igb_get_cfg_done_i210; 337 phy->ops.get_phy_info = igb_get_phy_info_m88; 338 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2; 339 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580; 340 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580; 341 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; 342 break; 343 case BCM54616_E_PHY_ID: 344 phy->type = e1000_phy_bcm54616; 345 break; 346 default: 347 ret_val = -E1000_ERR_PHY; 348 goto out; 349 } 350 351 out: 352 return ret_val; 353 } 354 355 /** 356 * igb_init_nvm_params_82575 - Init NVM func ptrs. 357 * @hw: pointer to the HW structure 358 **/ 359 static s32 igb_init_nvm_params_82575(struct e1000_hw *hw) 360 { 361 struct e1000_nvm_info *nvm = &hw->nvm; 362 u32 eecd = rd32(E1000_EECD); 363 u16 size; 364 365 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 366 E1000_EECD_SIZE_EX_SHIFT); 367 368 /* Added to a constant, "size" becomes the left-shift value 369 * for setting word_size. 370 */ 371 size += NVM_WORD_SIZE_BASE_SHIFT; 372 373 /* Just in case size is out of range, cap it to the largest 374 * EEPROM size supported 375 */ 376 if (size > 15) 377 size = 15; 378 379 nvm->word_size = BIT(size); 380 nvm->opcode_bits = 8; 381 nvm->delay_usec = 1; 382 383 switch (nvm->override) { 384 case e1000_nvm_override_spi_large: 385 nvm->page_size = 32; 386 nvm->address_bits = 16; 387 break; 388 case e1000_nvm_override_spi_small: 389 nvm->page_size = 8; 390 nvm->address_bits = 8; 391 break; 392 default: 393 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 394 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 395 16 : 8; 396 break; 397 } 398 if (nvm->word_size == BIT(15)) 399 nvm->page_size = 128; 400 401 nvm->type = e1000_nvm_eeprom_spi; 402 403 /* NVM Function Pointers */ 404 nvm->ops.acquire = igb_acquire_nvm_82575; 405 nvm->ops.release = igb_release_nvm_82575; 406 nvm->ops.write = igb_write_nvm_spi; 407 nvm->ops.validate = igb_validate_nvm_checksum; 408 nvm->ops.update = igb_update_nvm_checksum; 409 if (nvm->word_size < BIT(15)) 410 nvm->ops.read = igb_read_nvm_eerd; 411 else 412 nvm->ops.read = igb_read_nvm_spi; 413 414 /* override generic family function pointers for specific descendants */ 415 switch (hw->mac.type) { 416 case e1000_82580: 417 nvm->ops.validate = igb_validate_nvm_checksum_82580; 418 nvm->ops.update = igb_update_nvm_checksum_82580; 419 break; 420 case e1000_i354: 421 case e1000_i350: 422 nvm->ops.validate = igb_validate_nvm_checksum_i350; 423 nvm->ops.update = igb_update_nvm_checksum_i350; 424 break; 425 default: 426 break; 427 } 428 429 return 0; 430 } 431 432 /** 433 * igb_init_mac_params_82575 - Init MAC func ptrs. 434 * @hw: pointer to the HW structure 435 **/ 436 static s32 igb_init_mac_params_82575(struct e1000_hw *hw) 437 { 438 struct e1000_mac_info *mac = &hw->mac; 439 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 440 441 /* Set mta register count */ 442 mac->mta_reg_count = 128; 443 /* Set uta register count */ 444 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128; 445 /* Set rar entry count */ 446 switch (mac->type) { 447 case e1000_82576: 448 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 449 break; 450 case e1000_82580: 451 mac->rar_entry_count = E1000_RAR_ENTRIES_82580; 452 break; 453 case e1000_i350: 454 case e1000_i354: 455 mac->rar_entry_count = E1000_RAR_ENTRIES_I350; 456 break; 457 default: 458 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 459 break; 460 } 461 /* reset */ 462 if (mac->type >= e1000_82580) 463 mac->ops.reset_hw = igb_reset_hw_82580; 464 else 465 mac->ops.reset_hw = igb_reset_hw_82575; 466 467 if (mac->type >= e1000_i210) { 468 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210; 469 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210; 470 471 } else { 472 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575; 473 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575; 474 } 475 476 if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354)) 477 mac->ops.write_vfta = igb_write_vfta_i350; 478 else 479 mac->ops.write_vfta = igb_write_vfta; 480 481 /* Set if part includes ASF firmware */ 482 mac->asf_firmware_present = true; 483 /* Set if manageability features are enabled. */ 484 mac->arc_subsystem_valid = 485 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK) 486 ? true : false; 487 /* enable EEE on i350 parts and later parts */ 488 if (mac->type >= e1000_i350) 489 dev_spec->eee_disable = false; 490 else 491 dev_spec->eee_disable = true; 492 /* Allow a single clear of the SW semaphore on I210 and newer */ 493 if (mac->type >= e1000_i210) 494 dev_spec->clear_semaphore_once = true; 495 /* physical interface link setup */ 496 mac->ops.setup_physical_interface = 497 (hw->phy.media_type == e1000_media_type_copper) 498 ? igb_setup_copper_link_82575 499 : igb_setup_serdes_link_82575; 500 501 if (mac->type == e1000_82580) { 502 switch (hw->device_id) { 503 /* feature not supported on these id's */ 504 case E1000_DEV_ID_DH89XXCC_SGMII: 505 case E1000_DEV_ID_DH89XXCC_SERDES: 506 case E1000_DEV_ID_DH89XXCC_BACKPLANE: 507 case E1000_DEV_ID_DH89XXCC_SFP: 508 break; 509 default: 510 hw->dev_spec._82575.mas_capable = true; 511 break; 512 } 513 } 514 return 0; 515 } 516 517 /** 518 * igb_set_sfp_media_type_82575 - derives SFP module media type. 519 * @hw: pointer to the HW structure 520 * 521 * The media type is chosen based on SFP module. 522 * compatibility flags retrieved from SFP ID EEPROM. 523 **/ 524 static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw) 525 { 526 s32 ret_val = E1000_ERR_CONFIG; 527 u32 ctrl_ext = 0; 528 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 529 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags; 530 u8 tranceiver_type = 0; 531 s32 timeout = 3; 532 533 /* Turn I2C interface ON and power on sfp cage */ 534 ctrl_ext = rd32(E1000_CTRL_EXT); 535 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 536 wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); 537 538 wrfl(); 539 540 /* Read SFP module data */ 541 while (timeout) { 542 ret_val = igb_read_sfp_data_byte(hw, 543 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET), 544 &tranceiver_type); 545 if (ret_val == 0) 546 break; 547 msleep(100); 548 timeout--; 549 } 550 if (ret_val != 0) 551 goto out; 552 553 ret_val = igb_read_sfp_data_byte(hw, 554 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET), 555 (u8 *)eth_flags); 556 if (ret_val != 0) 557 goto out; 558 559 /* Check if there is some SFP module plugged and powered */ 560 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) || 561 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) { 562 dev_spec->module_plugged = true; 563 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) { 564 hw->phy.media_type = e1000_media_type_internal_serdes; 565 } else if (eth_flags->e100_base_fx) { 566 dev_spec->sgmii_active = true; 567 hw->phy.media_type = e1000_media_type_internal_serdes; 568 } else if (eth_flags->e1000_base_t) { 569 dev_spec->sgmii_active = true; 570 hw->phy.media_type = e1000_media_type_copper; 571 } else { 572 hw->phy.media_type = e1000_media_type_unknown; 573 hw_dbg("PHY module has not been recognized\n"); 574 goto out; 575 } 576 } else { 577 hw->phy.media_type = e1000_media_type_unknown; 578 } 579 ret_val = 0; 580 out: 581 /* Restore I2C interface setting */ 582 wr32(E1000_CTRL_EXT, ctrl_ext); 583 return ret_val; 584 } 585 586 static s32 igb_get_invariants_82575(struct e1000_hw *hw) 587 { 588 struct e1000_mac_info *mac = &hw->mac; 589 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 590 s32 ret_val; 591 u32 ctrl_ext = 0; 592 u32 link_mode = 0; 593 594 switch (hw->device_id) { 595 case E1000_DEV_ID_82575EB_COPPER: 596 case E1000_DEV_ID_82575EB_FIBER_SERDES: 597 case E1000_DEV_ID_82575GB_QUAD_COPPER: 598 mac->type = e1000_82575; 599 break; 600 case E1000_DEV_ID_82576: 601 case E1000_DEV_ID_82576_NS: 602 case E1000_DEV_ID_82576_NS_SERDES: 603 case E1000_DEV_ID_82576_FIBER: 604 case E1000_DEV_ID_82576_SERDES: 605 case E1000_DEV_ID_82576_QUAD_COPPER: 606 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 607 case E1000_DEV_ID_82576_SERDES_QUAD: 608 mac->type = e1000_82576; 609 break; 610 case E1000_DEV_ID_82580_COPPER: 611 case E1000_DEV_ID_82580_FIBER: 612 case E1000_DEV_ID_82580_QUAD_FIBER: 613 case E1000_DEV_ID_82580_SERDES: 614 case E1000_DEV_ID_82580_SGMII: 615 case E1000_DEV_ID_82580_COPPER_DUAL: 616 case E1000_DEV_ID_DH89XXCC_SGMII: 617 case E1000_DEV_ID_DH89XXCC_SERDES: 618 case E1000_DEV_ID_DH89XXCC_BACKPLANE: 619 case E1000_DEV_ID_DH89XXCC_SFP: 620 mac->type = e1000_82580; 621 break; 622 case E1000_DEV_ID_I350_COPPER: 623 case E1000_DEV_ID_I350_FIBER: 624 case E1000_DEV_ID_I350_SERDES: 625 case E1000_DEV_ID_I350_SGMII: 626 mac->type = e1000_i350; 627 break; 628 case E1000_DEV_ID_I210_COPPER: 629 case E1000_DEV_ID_I210_FIBER: 630 case E1000_DEV_ID_I210_SERDES: 631 case E1000_DEV_ID_I210_SGMII: 632 case E1000_DEV_ID_I210_COPPER_FLASHLESS: 633 case E1000_DEV_ID_I210_SERDES_FLASHLESS: 634 mac->type = e1000_i210; 635 break; 636 case E1000_DEV_ID_I211_COPPER: 637 mac->type = e1000_i211; 638 break; 639 case E1000_DEV_ID_I354_BACKPLANE_1GBPS: 640 case E1000_DEV_ID_I354_SGMII: 641 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS: 642 mac->type = e1000_i354; 643 break; 644 default: 645 return -E1000_ERR_MAC_INIT; 646 } 647 648 /* Set media type */ 649 /* The 82575 uses bits 22:23 for link mode. The mode can be changed 650 * based on the EEPROM. We cannot rely upon device ID. There 651 * is no distinguishable difference between fiber and internal 652 * SerDes mode on the 82575. There can be an external PHY attached 653 * on the SGMII interface. For this, we'll set sgmii_active to true. 654 */ 655 hw->phy.media_type = e1000_media_type_copper; 656 dev_spec->sgmii_active = false; 657 dev_spec->module_plugged = false; 658 659 ctrl_ext = rd32(E1000_CTRL_EXT); 660 661 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK; 662 switch (link_mode) { 663 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 664 hw->phy.media_type = e1000_media_type_internal_serdes; 665 break; 666 case E1000_CTRL_EXT_LINK_MODE_SGMII: 667 /* Get phy control interface type set (MDIO vs. I2C)*/ 668 if (igb_sgmii_uses_mdio_82575(hw)) { 669 hw->phy.media_type = e1000_media_type_copper; 670 dev_spec->sgmii_active = true; 671 break; 672 } 673 /* fall through for I2C based SGMII */ 674 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 675 /* read media type from SFP EEPROM */ 676 ret_val = igb_set_sfp_media_type_82575(hw); 677 if ((ret_val != 0) || 678 (hw->phy.media_type == e1000_media_type_unknown)) { 679 /* If media type was not identified then return media 680 * type defined by the CTRL_EXT settings. 681 */ 682 hw->phy.media_type = e1000_media_type_internal_serdes; 683 684 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) { 685 hw->phy.media_type = e1000_media_type_copper; 686 dev_spec->sgmii_active = true; 687 } 688 689 break; 690 } 691 692 /* do not change link mode for 100BaseFX */ 693 if (dev_spec->eth_flags.e100_base_fx) 694 break; 695 696 /* change current link mode setting */ 697 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 698 699 if (hw->phy.media_type == e1000_media_type_copper) 700 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII; 701 else 702 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 703 704 wr32(E1000_CTRL_EXT, ctrl_ext); 705 706 break; 707 default: 708 break; 709 } 710 711 /* mac initialization and operations */ 712 ret_val = igb_init_mac_params_82575(hw); 713 if (ret_val) 714 goto out; 715 716 /* NVM initialization */ 717 ret_val = igb_init_nvm_params_82575(hw); 718 switch (hw->mac.type) { 719 case e1000_i210: 720 case e1000_i211: 721 ret_val = igb_init_nvm_params_i210(hw); 722 break; 723 default: 724 break; 725 } 726 727 if (ret_val) 728 goto out; 729 730 /* if part supports SR-IOV then initialize mailbox parameters */ 731 switch (mac->type) { 732 case e1000_82576: 733 case e1000_i350: 734 igb_init_mbx_params_pf(hw); 735 break; 736 default: 737 break; 738 } 739 740 /* setup PHY parameters */ 741 ret_val = igb_init_phy_params_82575(hw); 742 743 out: 744 return ret_val; 745 } 746 747 /** 748 * igb_acquire_phy_82575 - Acquire rights to access PHY 749 * @hw: pointer to the HW structure 750 * 751 * Acquire access rights to the correct PHY. This is a 752 * function pointer entry point called by the api module. 753 **/ 754 static s32 igb_acquire_phy_82575(struct e1000_hw *hw) 755 { 756 u16 mask = E1000_SWFW_PHY0_SM; 757 758 if (hw->bus.func == E1000_FUNC_1) 759 mask = E1000_SWFW_PHY1_SM; 760 else if (hw->bus.func == E1000_FUNC_2) 761 mask = E1000_SWFW_PHY2_SM; 762 else if (hw->bus.func == E1000_FUNC_3) 763 mask = E1000_SWFW_PHY3_SM; 764 765 return hw->mac.ops.acquire_swfw_sync(hw, mask); 766 } 767 768 /** 769 * igb_release_phy_82575 - Release rights to access PHY 770 * @hw: pointer to the HW structure 771 * 772 * A wrapper to release access rights to the correct PHY. This is a 773 * function pointer entry point called by the api module. 774 **/ 775 static void igb_release_phy_82575(struct e1000_hw *hw) 776 { 777 u16 mask = E1000_SWFW_PHY0_SM; 778 779 if (hw->bus.func == E1000_FUNC_1) 780 mask = E1000_SWFW_PHY1_SM; 781 else if (hw->bus.func == E1000_FUNC_2) 782 mask = E1000_SWFW_PHY2_SM; 783 else if (hw->bus.func == E1000_FUNC_3) 784 mask = E1000_SWFW_PHY3_SM; 785 786 hw->mac.ops.release_swfw_sync(hw, mask); 787 } 788 789 /** 790 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 791 * @hw: pointer to the HW structure 792 * @offset: register offset to be read 793 * @data: pointer to the read data 794 * 795 * Reads the PHY register at offset using the serial gigabit media independent 796 * interface and stores the retrieved information in data. 797 **/ 798 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 799 u16 *data) 800 { 801 s32 ret_val = -E1000_ERR_PARAM; 802 803 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 804 hw_dbg("PHY Address %u is out of range\n", offset); 805 goto out; 806 } 807 808 ret_val = hw->phy.ops.acquire(hw); 809 if (ret_val) 810 goto out; 811 812 ret_val = igb_read_phy_reg_i2c(hw, offset, data); 813 814 hw->phy.ops.release(hw); 815 816 out: 817 return ret_val; 818 } 819 820 /** 821 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 822 * @hw: pointer to the HW structure 823 * @offset: register offset to write to 824 * @data: data to write at register offset 825 * 826 * Writes the data to PHY register at the offset using the serial gigabit 827 * media independent interface. 828 **/ 829 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 830 u16 data) 831 { 832 s32 ret_val = -E1000_ERR_PARAM; 833 834 835 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 836 hw_dbg("PHY Address %d is out of range\n", offset); 837 goto out; 838 } 839 840 ret_val = hw->phy.ops.acquire(hw); 841 if (ret_val) 842 goto out; 843 844 ret_val = igb_write_phy_reg_i2c(hw, offset, data); 845 846 hw->phy.ops.release(hw); 847 848 out: 849 return ret_val; 850 } 851 852 /** 853 * igb_get_phy_id_82575 - Retrieve PHY addr and id 854 * @hw: pointer to the HW structure 855 * 856 * Retrieves the PHY address and ID for both PHY's which do and do not use 857 * sgmi interface. 858 **/ 859 static s32 igb_get_phy_id_82575(struct e1000_hw *hw) 860 { 861 struct e1000_phy_info *phy = &hw->phy; 862 s32 ret_val = 0; 863 u16 phy_id; 864 u32 ctrl_ext; 865 u32 mdic; 866 867 /* Extra read required for some PHY's on i354 */ 868 if (hw->mac.type == e1000_i354) 869 igb_get_phy_id(hw); 870 871 /* For SGMII PHYs, we try the list of possible addresses until 872 * we find one that works. For non-SGMII PHYs 873 * (e.g. integrated copper PHYs), an address of 1 should 874 * work. The result of this function should mean phy->phy_addr 875 * and phy->id are set correctly. 876 */ 877 if (!(igb_sgmii_active_82575(hw))) { 878 phy->addr = 1; 879 ret_val = igb_get_phy_id(hw); 880 goto out; 881 } 882 883 if (igb_sgmii_uses_mdio_82575(hw)) { 884 switch (hw->mac.type) { 885 case e1000_82575: 886 case e1000_82576: 887 mdic = rd32(E1000_MDIC); 888 mdic &= E1000_MDIC_PHY_MASK; 889 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; 890 break; 891 case e1000_82580: 892 case e1000_i350: 893 case e1000_i354: 894 case e1000_i210: 895 case e1000_i211: 896 mdic = rd32(E1000_MDICNFG); 897 mdic &= E1000_MDICNFG_PHY_MASK; 898 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 899 break; 900 default: 901 ret_val = -E1000_ERR_PHY; 902 goto out; 903 } 904 ret_val = igb_get_phy_id(hw); 905 goto out; 906 } 907 908 /* Power on sgmii phy if it is disabled */ 909 ctrl_ext = rd32(E1000_CTRL_EXT); 910 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 911 wrfl(); 912 msleep(300); 913 914 /* The address field in the I2CCMD register is 3 bits and 0 is invalid. 915 * Therefore, we need to test 1-7 916 */ 917 for (phy->addr = 1; phy->addr < 8; phy->addr++) { 918 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 919 if (ret_val == 0) { 920 hw_dbg("Vendor ID 0x%08X read at address %u\n", 921 phy_id, phy->addr); 922 /* At the time of this writing, The M88 part is 923 * the only supported SGMII PHY product. 924 */ 925 if (phy_id == M88_VENDOR) 926 break; 927 } else { 928 hw_dbg("PHY address %u was unreadable\n", phy->addr); 929 } 930 } 931 932 /* A valid PHY type couldn't be found. */ 933 if (phy->addr == 8) { 934 phy->addr = 0; 935 ret_val = -E1000_ERR_PHY; 936 goto out; 937 } else { 938 ret_val = igb_get_phy_id(hw); 939 } 940 941 /* restore previous sfp cage power state */ 942 wr32(E1000_CTRL_EXT, ctrl_ext); 943 944 out: 945 return ret_val; 946 } 947 948 /** 949 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset 950 * @hw: pointer to the HW structure 951 * 952 * Resets the PHY using the serial gigabit media independent interface. 953 **/ 954 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 955 { 956 struct e1000_phy_info *phy = &hw->phy; 957 s32 ret_val; 958 959 /* This isn't a true "hard" reset, but is the only reset 960 * available to us at this time. 961 */ 962 963 hw_dbg("Soft resetting SGMII attached PHY...\n"); 964 965 /* SFP documentation requires the following to configure the SPF module 966 * to work on SGMII. No further documentation is given. 967 */ 968 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 969 if (ret_val) 970 goto out; 971 972 ret_val = igb_phy_sw_reset(hw); 973 if (ret_val) 974 goto out; 975 976 if (phy->id == M88E1512_E_PHY_ID) 977 ret_val = igb_initialize_M88E1512_phy(hw); 978 if (phy->id == M88E1543_E_PHY_ID) 979 ret_val = igb_initialize_M88E1543_phy(hw); 980 out: 981 return ret_val; 982 } 983 984 /** 985 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 986 * @hw: pointer to the HW structure 987 * @active: true to enable LPLU, false to disable 988 * 989 * Sets the LPLU D0 state according to the active flag. When 990 * activating LPLU this function also disables smart speed 991 * and vice versa. LPLU will not be activated unless the 992 * device autonegotiation advertisement meets standards of 993 * either 10 or 10/100 or 10/100/1000 at all duplexes. 994 * This is a function pointer entry point only called by 995 * PHY setup routines. 996 **/ 997 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 998 { 999 struct e1000_phy_info *phy = &hw->phy; 1000 s32 ret_val; 1001 u16 data; 1002 1003 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1004 if (ret_val) 1005 goto out; 1006 1007 if (active) { 1008 data |= IGP02E1000_PM_D0_LPLU; 1009 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1010 data); 1011 if (ret_val) 1012 goto out; 1013 1014 /* When LPLU is enabled, we should disable SmartSpeed */ 1015 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1016 &data); 1017 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1018 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1019 data); 1020 if (ret_val) 1021 goto out; 1022 } else { 1023 data &= ~IGP02E1000_PM_D0_LPLU; 1024 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1025 data); 1026 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1027 * during Dx states where the power conservation is most 1028 * important. During driver activity we should enable 1029 * SmartSpeed, so performance is maintained. 1030 */ 1031 if (phy->smart_speed == e1000_smart_speed_on) { 1032 ret_val = phy->ops.read_reg(hw, 1033 IGP01E1000_PHY_PORT_CONFIG, &data); 1034 if (ret_val) 1035 goto out; 1036 1037 data |= IGP01E1000_PSCFR_SMART_SPEED; 1038 ret_val = phy->ops.write_reg(hw, 1039 IGP01E1000_PHY_PORT_CONFIG, data); 1040 if (ret_val) 1041 goto out; 1042 } else if (phy->smart_speed == e1000_smart_speed_off) { 1043 ret_val = phy->ops.read_reg(hw, 1044 IGP01E1000_PHY_PORT_CONFIG, &data); 1045 if (ret_val) 1046 goto out; 1047 1048 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1049 ret_val = phy->ops.write_reg(hw, 1050 IGP01E1000_PHY_PORT_CONFIG, data); 1051 if (ret_val) 1052 goto out; 1053 } 1054 } 1055 1056 out: 1057 return ret_val; 1058 } 1059 1060 /** 1061 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state 1062 * @hw: pointer to the HW structure 1063 * @active: true to enable LPLU, false to disable 1064 * 1065 * Sets the LPLU D0 state according to the active flag. When 1066 * activating LPLU this function also disables smart speed 1067 * and vice versa. LPLU will not be activated unless the 1068 * device autonegotiation advertisement meets standards of 1069 * either 10 or 10/100 or 10/100/1000 at all duplexes. 1070 * This is a function pointer entry point only called by 1071 * PHY setup routines. 1072 **/ 1073 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) 1074 { 1075 struct e1000_phy_info *phy = &hw->phy; 1076 u16 data; 1077 1078 data = rd32(E1000_82580_PHY_POWER_MGMT); 1079 1080 if (active) { 1081 data |= E1000_82580_PM_D0_LPLU; 1082 1083 /* When LPLU is enabled, we should disable SmartSpeed */ 1084 data &= ~E1000_82580_PM_SPD; 1085 } else { 1086 data &= ~E1000_82580_PM_D0_LPLU; 1087 1088 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1089 * during Dx states where the power conservation is most 1090 * important. During driver activity we should enable 1091 * SmartSpeed, so performance is maintained. 1092 */ 1093 if (phy->smart_speed == e1000_smart_speed_on) 1094 data |= E1000_82580_PM_SPD; 1095 else if (phy->smart_speed == e1000_smart_speed_off) 1096 data &= ~E1000_82580_PM_SPD; } 1097 1098 wr32(E1000_82580_PHY_POWER_MGMT, data); 1099 return 0; 1100 } 1101 1102 /** 1103 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3 1104 * @hw: pointer to the HW structure 1105 * @active: boolean used to enable/disable lplu 1106 * 1107 * Success returns 0, Failure returns 1 1108 * 1109 * The low power link up (lplu) state is set to the power management level D3 1110 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1111 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1112 * is used during Dx states where the power conservation is most important. 1113 * During driver activity, SmartSpeed should be enabled so performance is 1114 * maintained. 1115 **/ 1116 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) 1117 { 1118 struct e1000_phy_info *phy = &hw->phy; 1119 u16 data; 1120 1121 data = rd32(E1000_82580_PHY_POWER_MGMT); 1122 1123 if (!active) { 1124 data &= ~E1000_82580_PM_D3_LPLU; 1125 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1126 * during Dx states where the power conservation is most 1127 * important. During driver activity we should enable 1128 * SmartSpeed, so performance is maintained. 1129 */ 1130 if (phy->smart_speed == e1000_smart_speed_on) 1131 data |= E1000_82580_PM_SPD; 1132 else if (phy->smart_speed == e1000_smart_speed_off) 1133 data &= ~E1000_82580_PM_SPD; 1134 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1135 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1136 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1137 data |= E1000_82580_PM_D3_LPLU; 1138 /* When LPLU is enabled, we should disable SmartSpeed */ 1139 data &= ~E1000_82580_PM_SPD; 1140 } 1141 1142 wr32(E1000_82580_PHY_POWER_MGMT, data); 1143 return 0; 1144 } 1145 1146 /** 1147 * igb_acquire_nvm_82575 - Request for access to EEPROM 1148 * @hw: pointer to the HW structure 1149 * 1150 * Acquire the necessary semaphores for exclusive access to the EEPROM. 1151 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 1152 * Return successful if access grant bit set, else clear the request for 1153 * EEPROM access and return -E1000_ERR_NVM (-1). 1154 **/ 1155 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw) 1156 { 1157 s32 ret_val; 1158 1159 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM); 1160 if (ret_val) 1161 goto out; 1162 1163 ret_val = igb_acquire_nvm(hw); 1164 1165 if (ret_val) 1166 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM); 1167 1168 out: 1169 return ret_val; 1170 } 1171 1172 /** 1173 * igb_release_nvm_82575 - Release exclusive access to EEPROM 1174 * @hw: pointer to the HW structure 1175 * 1176 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 1177 * then release the semaphores acquired. 1178 **/ 1179 static void igb_release_nvm_82575(struct e1000_hw *hw) 1180 { 1181 igb_release_nvm(hw); 1182 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM); 1183 } 1184 1185 /** 1186 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 1187 * @hw: pointer to the HW structure 1188 * @mask: specifies which semaphore to acquire 1189 * 1190 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 1191 * will also specify which port we're acquiring the lock for. 1192 **/ 1193 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1194 { 1195 u32 swfw_sync; 1196 u32 swmask = mask; 1197 u32 fwmask = mask << 16; 1198 s32 ret_val = 0; 1199 s32 i = 0, timeout = 200; 1200 1201 while (i < timeout) { 1202 if (igb_get_hw_semaphore(hw)) { 1203 ret_val = -E1000_ERR_SWFW_SYNC; 1204 goto out; 1205 } 1206 1207 swfw_sync = rd32(E1000_SW_FW_SYNC); 1208 if (!(swfw_sync & (fwmask | swmask))) 1209 break; 1210 1211 /* Firmware currently using resource (fwmask) 1212 * or other software thread using resource (swmask) 1213 */ 1214 igb_put_hw_semaphore(hw); 1215 mdelay(5); 1216 i++; 1217 } 1218 1219 if (i == timeout) { 1220 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1221 ret_val = -E1000_ERR_SWFW_SYNC; 1222 goto out; 1223 } 1224 1225 swfw_sync |= swmask; 1226 wr32(E1000_SW_FW_SYNC, swfw_sync); 1227 1228 igb_put_hw_semaphore(hw); 1229 1230 out: 1231 return ret_val; 1232 } 1233 1234 /** 1235 * igb_release_swfw_sync_82575 - Release SW/FW semaphore 1236 * @hw: pointer to the HW structure 1237 * @mask: specifies which semaphore to acquire 1238 * 1239 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 1240 * will also specify which port we're releasing the lock for. 1241 **/ 1242 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1243 { 1244 u32 swfw_sync; 1245 1246 while (igb_get_hw_semaphore(hw) != 0) 1247 ; /* Empty */ 1248 1249 swfw_sync = rd32(E1000_SW_FW_SYNC); 1250 swfw_sync &= ~mask; 1251 wr32(E1000_SW_FW_SYNC, swfw_sync); 1252 1253 igb_put_hw_semaphore(hw); 1254 } 1255 1256 /** 1257 * igb_get_cfg_done_82575 - Read config done bit 1258 * @hw: pointer to the HW structure 1259 * 1260 * Read the management control register for the config done bit for 1261 * completion status. NOTE: silicon which is EEPROM-less will fail trying 1262 * to read the config done bit, so an error is *ONLY* logged and returns 1263 * 0. If we were to return with error, EEPROM-less silicon 1264 * would not be able to be reset or change link. 1265 **/ 1266 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw) 1267 { 1268 s32 timeout = PHY_CFG_TIMEOUT; 1269 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 1270 1271 if (hw->bus.func == 1) 1272 mask = E1000_NVM_CFG_DONE_PORT_1; 1273 else if (hw->bus.func == E1000_FUNC_2) 1274 mask = E1000_NVM_CFG_DONE_PORT_2; 1275 else if (hw->bus.func == E1000_FUNC_3) 1276 mask = E1000_NVM_CFG_DONE_PORT_3; 1277 1278 while (timeout) { 1279 if (rd32(E1000_EEMNGCTL) & mask) 1280 break; 1281 usleep_range(1000, 2000); 1282 timeout--; 1283 } 1284 if (!timeout) 1285 hw_dbg("MNG configuration cycle has not completed.\n"); 1286 1287 /* If EEPROM is not marked present, init the PHY manually */ 1288 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) && 1289 (hw->phy.type == e1000_phy_igp_3)) 1290 igb_phy_init_script_igp3(hw); 1291 1292 return 0; 1293 } 1294 1295 /** 1296 * igb_get_link_up_info_82575 - Get link speed/duplex info 1297 * @hw: pointer to the HW structure 1298 * @speed: stores the current speed 1299 * @duplex: stores the current duplex 1300 * 1301 * This is a wrapper function, if using the serial gigabit media independent 1302 * interface, use PCS to retrieve the link speed and duplex information. 1303 * Otherwise, use the generic function to get the link speed and duplex info. 1304 **/ 1305 static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 1306 u16 *duplex) 1307 { 1308 s32 ret_val; 1309 1310 if (hw->phy.media_type != e1000_media_type_copper) 1311 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed, 1312 duplex); 1313 else 1314 ret_val = igb_get_speed_and_duplex_copper(hw, speed, 1315 duplex); 1316 1317 return ret_val; 1318 } 1319 1320 /** 1321 * igb_check_for_link_82575 - Check for link 1322 * @hw: pointer to the HW structure 1323 * 1324 * If sgmii is enabled, then use the pcs register to determine link, otherwise 1325 * use the generic interface for determining link. 1326 **/ 1327 static s32 igb_check_for_link_82575(struct e1000_hw *hw) 1328 { 1329 s32 ret_val; 1330 u16 speed, duplex; 1331 1332 if (hw->phy.media_type != e1000_media_type_copper) { 1333 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, 1334 &duplex); 1335 /* Use this flag to determine if link needs to be checked or 1336 * not. If we have link clear the flag so that we do not 1337 * continue to check for link. 1338 */ 1339 hw->mac.get_link_status = !hw->mac.serdes_has_link; 1340 1341 /* Configure Flow Control now that Auto-Neg has completed. 1342 * First, we need to restore the desired flow control 1343 * settings because we may have had to re-autoneg with a 1344 * different link partner. 1345 */ 1346 ret_val = igb_config_fc_after_link_up(hw); 1347 if (ret_val) 1348 hw_dbg("Error configuring flow control\n"); 1349 } else { 1350 ret_val = igb_check_for_copper_link(hw); 1351 } 1352 1353 return ret_val; 1354 } 1355 1356 /** 1357 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown 1358 * @hw: pointer to the HW structure 1359 **/ 1360 void igb_power_up_serdes_link_82575(struct e1000_hw *hw) 1361 { 1362 u32 reg; 1363 1364 1365 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1366 !igb_sgmii_active_82575(hw)) 1367 return; 1368 1369 /* Enable PCS to turn on link */ 1370 reg = rd32(E1000_PCS_CFG0); 1371 reg |= E1000_PCS_CFG_PCS_EN; 1372 wr32(E1000_PCS_CFG0, reg); 1373 1374 /* Power up the laser */ 1375 reg = rd32(E1000_CTRL_EXT); 1376 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1377 wr32(E1000_CTRL_EXT, reg); 1378 1379 /* flush the write to verify completion */ 1380 wrfl(); 1381 usleep_range(1000, 2000); 1382 } 1383 1384 /** 1385 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 1386 * @hw: pointer to the HW structure 1387 * @speed: stores the current speed 1388 * @duplex: stores the current duplex 1389 * 1390 * Using the physical coding sub-layer (PCS), retrieve the current speed and 1391 * duplex, then store the values in the pointers provided. 1392 **/ 1393 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, 1394 u16 *duplex) 1395 { 1396 struct e1000_mac_info *mac = &hw->mac; 1397 u32 pcs, status; 1398 1399 /* Set up defaults for the return values of this function */ 1400 mac->serdes_has_link = false; 1401 *speed = 0; 1402 *duplex = 0; 1403 1404 /* Read the PCS Status register for link state. For non-copper mode, 1405 * the status register is not accurate. The PCS status register is 1406 * used instead. 1407 */ 1408 pcs = rd32(E1000_PCS_LSTAT); 1409 1410 /* The link up bit determines when link is up on autoneg. The sync ok 1411 * gets set once both sides sync up and agree upon link. Stable link 1412 * can be determined by checking for both link up and link sync ok 1413 */ 1414 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 1415 mac->serdes_has_link = true; 1416 1417 /* Detect and store PCS speed */ 1418 if (pcs & E1000_PCS_LSTS_SPEED_1000) 1419 *speed = SPEED_1000; 1420 else if (pcs & E1000_PCS_LSTS_SPEED_100) 1421 *speed = SPEED_100; 1422 else 1423 *speed = SPEED_10; 1424 1425 /* Detect and store PCS duplex */ 1426 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) 1427 *duplex = FULL_DUPLEX; 1428 else 1429 *duplex = HALF_DUPLEX; 1430 1431 /* Check if it is an I354 2.5Gb backplane connection. */ 1432 if (mac->type == e1000_i354) { 1433 status = rd32(E1000_STATUS); 1434 if ((status & E1000_STATUS_2P5_SKU) && 1435 !(status & E1000_STATUS_2P5_SKU_OVER)) { 1436 *speed = SPEED_2500; 1437 *duplex = FULL_DUPLEX; 1438 hw_dbg("2500 Mbs, "); 1439 hw_dbg("Full Duplex\n"); 1440 } 1441 } 1442 1443 } 1444 1445 return 0; 1446 } 1447 1448 /** 1449 * igb_shutdown_serdes_link_82575 - Remove link during power down 1450 * @hw: pointer to the HW structure 1451 * 1452 * In the case of fiber serdes, shut down optics and PCS on driver unload 1453 * when management pass thru is not enabled. 1454 **/ 1455 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw) 1456 { 1457 u32 reg; 1458 1459 if (hw->phy.media_type != e1000_media_type_internal_serdes && 1460 igb_sgmii_active_82575(hw)) 1461 return; 1462 1463 if (!igb_enable_mng_pass_thru(hw)) { 1464 /* Disable PCS to turn off link */ 1465 reg = rd32(E1000_PCS_CFG0); 1466 reg &= ~E1000_PCS_CFG_PCS_EN; 1467 wr32(E1000_PCS_CFG0, reg); 1468 1469 /* shutdown the laser */ 1470 reg = rd32(E1000_CTRL_EXT); 1471 reg |= E1000_CTRL_EXT_SDP3_DATA; 1472 wr32(E1000_CTRL_EXT, reg); 1473 1474 /* flush the write to verify completion */ 1475 wrfl(); 1476 usleep_range(1000, 2000); 1477 } 1478 } 1479 1480 /** 1481 * igb_reset_hw_82575 - Reset hardware 1482 * @hw: pointer to the HW structure 1483 * 1484 * This resets the hardware into a known state. This is a 1485 * function pointer entry point called by the api module. 1486 **/ 1487 static s32 igb_reset_hw_82575(struct e1000_hw *hw) 1488 { 1489 u32 ctrl; 1490 s32 ret_val; 1491 1492 /* Prevent the PCI-E bus from sticking if there is no TLP connection 1493 * on the last TLP read/write transaction when MAC is reset. 1494 */ 1495 ret_val = igb_disable_pcie_master(hw); 1496 if (ret_val) 1497 hw_dbg("PCI-E Master disable polling has failed.\n"); 1498 1499 /* set the completion timeout for interface */ 1500 ret_val = igb_set_pcie_completion_timeout(hw); 1501 if (ret_val) 1502 hw_dbg("PCI-E Set completion timeout has failed.\n"); 1503 1504 hw_dbg("Masking off all interrupts\n"); 1505 wr32(E1000_IMC, 0xffffffff); 1506 1507 wr32(E1000_RCTL, 0); 1508 wr32(E1000_TCTL, E1000_TCTL_PSP); 1509 wrfl(); 1510 1511 usleep_range(10000, 20000); 1512 1513 ctrl = rd32(E1000_CTRL); 1514 1515 hw_dbg("Issuing a global reset to MAC\n"); 1516 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST); 1517 1518 ret_val = igb_get_auto_rd_done(hw); 1519 if (ret_val) { 1520 /* When auto config read does not complete, do not 1521 * return with an error. This can happen in situations 1522 * where there is no eeprom and prevents getting link. 1523 */ 1524 hw_dbg("Auto Read Done did not complete\n"); 1525 } 1526 1527 /* If EEPROM is not present, run manual init scripts */ 1528 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) 1529 igb_reset_init_script_82575(hw); 1530 1531 /* Clear any pending interrupt events. */ 1532 wr32(E1000_IMC, 0xffffffff); 1533 rd32(E1000_ICR); 1534 1535 /* Install any alternate MAC address into RAR0 */ 1536 ret_val = igb_check_alt_mac_addr(hw); 1537 1538 return ret_val; 1539 } 1540 1541 /** 1542 * igb_init_hw_82575 - Initialize hardware 1543 * @hw: pointer to the HW structure 1544 * 1545 * This inits the hardware readying it for operation. 1546 **/ 1547 static s32 igb_init_hw_82575(struct e1000_hw *hw) 1548 { 1549 struct e1000_mac_info *mac = &hw->mac; 1550 s32 ret_val; 1551 u16 i, rar_count = mac->rar_entry_count; 1552 1553 if ((hw->mac.type >= e1000_i210) && 1554 !(igb_get_flash_presence_i210(hw))) { 1555 ret_val = igb_pll_workaround_i210(hw); 1556 if (ret_val) 1557 return ret_val; 1558 } 1559 1560 /* Initialize identification LED */ 1561 ret_val = igb_id_led_init(hw); 1562 if (ret_val) { 1563 hw_dbg("Error initializing identification LED\n"); 1564 /* This is not fatal and we should not stop init due to this */ 1565 } 1566 1567 /* Disabling VLAN filtering */ 1568 hw_dbg("Initializing the IEEE VLAN\n"); 1569 igb_clear_vfta(hw); 1570 1571 /* Setup the receive address */ 1572 igb_init_rx_addrs(hw, rar_count); 1573 1574 /* Zero out the Multicast HASH table */ 1575 hw_dbg("Zeroing the MTA\n"); 1576 for (i = 0; i < mac->mta_reg_count; i++) 1577 array_wr32(E1000_MTA, i, 0); 1578 1579 /* Zero out the Unicast HASH table */ 1580 hw_dbg("Zeroing the UTA\n"); 1581 for (i = 0; i < mac->uta_reg_count; i++) 1582 array_wr32(E1000_UTA, i, 0); 1583 1584 /* Setup link and flow control */ 1585 ret_val = igb_setup_link(hw); 1586 1587 /* Clear all of the statistics registers (clear on read). It is 1588 * important that we do this after we have tried to establish link 1589 * because the symbol error count will increment wildly if there 1590 * is no link. 1591 */ 1592 igb_clear_hw_cntrs_82575(hw); 1593 return ret_val; 1594 } 1595 1596 /** 1597 * igb_setup_copper_link_82575 - Configure copper link settings 1598 * @hw: pointer to the HW structure 1599 * 1600 * Configures the link for auto-neg or forced speed and duplex. Then we check 1601 * for link, once link is established calls to configure collision distance 1602 * and flow control are called. 1603 **/ 1604 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw) 1605 { 1606 u32 ctrl; 1607 s32 ret_val; 1608 u32 phpm_reg; 1609 1610 ctrl = rd32(E1000_CTRL); 1611 ctrl |= E1000_CTRL_SLU; 1612 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1613 wr32(E1000_CTRL, ctrl); 1614 1615 /* Clear Go Link Disconnect bit on supported devices */ 1616 switch (hw->mac.type) { 1617 case e1000_82580: 1618 case e1000_i350: 1619 case e1000_i210: 1620 case e1000_i211: 1621 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT); 1622 phpm_reg &= ~E1000_82580_PM_GO_LINKD; 1623 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg); 1624 break; 1625 default: 1626 break; 1627 } 1628 1629 ret_val = igb_setup_serdes_link_82575(hw); 1630 if (ret_val) 1631 goto out; 1632 1633 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) { 1634 /* allow time for SFP cage time to power up phy */ 1635 msleep(300); 1636 1637 ret_val = hw->phy.ops.reset(hw); 1638 if (ret_val) { 1639 hw_dbg("Error resetting the PHY.\n"); 1640 goto out; 1641 } 1642 } 1643 switch (hw->phy.type) { 1644 case e1000_phy_i210: 1645 case e1000_phy_m88: 1646 switch (hw->phy.id) { 1647 case I347AT4_E_PHY_ID: 1648 case M88E1112_E_PHY_ID: 1649 case M88E1543_E_PHY_ID: 1650 case M88E1512_E_PHY_ID: 1651 case I210_I_PHY_ID: 1652 ret_val = igb_copper_link_setup_m88_gen2(hw); 1653 break; 1654 default: 1655 ret_val = igb_copper_link_setup_m88(hw); 1656 break; 1657 } 1658 break; 1659 case e1000_phy_igp_3: 1660 ret_val = igb_copper_link_setup_igp(hw); 1661 break; 1662 case e1000_phy_82580: 1663 ret_val = igb_copper_link_setup_82580(hw); 1664 break; 1665 case e1000_phy_bcm54616: 1666 ret_val = 0; 1667 break; 1668 default: 1669 ret_val = -E1000_ERR_PHY; 1670 break; 1671 } 1672 1673 if (ret_val) 1674 goto out; 1675 1676 ret_val = igb_setup_copper_link(hw); 1677 out: 1678 return ret_val; 1679 } 1680 1681 /** 1682 * igb_setup_serdes_link_82575 - Setup link for serdes 1683 * @hw: pointer to the HW structure 1684 * 1685 * Configure the physical coding sub-layer (PCS) link. The PCS link is 1686 * used on copper connections where the serialized gigabit media independent 1687 * interface (sgmii), or serdes fiber is being used. Configures the link 1688 * for auto-negotiation or forces speed/duplex. 1689 **/ 1690 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw) 1691 { 1692 u32 ctrl_ext, ctrl_reg, reg, anadv_reg; 1693 bool pcs_autoneg; 1694 s32 ret_val = 0; 1695 u16 data; 1696 1697 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1698 !igb_sgmii_active_82575(hw)) 1699 return ret_val; 1700 1701 1702 /* On the 82575, SerDes loopback mode persists until it is 1703 * explicitly turned off or a power cycle is performed. A read to 1704 * the register does not indicate its status. Therefore, we ensure 1705 * loopback mode is disabled during initialization. 1706 */ 1707 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1708 1709 /* power on the sfp cage if present and turn on I2C */ 1710 ctrl_ext = rd32(E1000_CTRL_EXT); 1711 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1712 ctrl_ext |= E1000_CTRL_I2C_ENA; 1713 wr32(E1000_CTRL_EXT, ctrl_ext); 1714 1715 ctrl_reg = rd32(E1000_CTRL); 1716 ctrl_reg |= E1000_CTRL_SLU; 1717 1718 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { 1719 /* set both sw defined pins */ 1720 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1721 1722 /* Set switch control to serdes energy detect */ 1723 reg = rd32(E1000_CONNSW); 1724 reg |= E1000_CONNSW_ENRGSRC; 1725 wr32(E1000_CONNSW, reg); 1726 } 1727 1728 reg = rd32(E1000_PCS_LCTL); 1729 1730 /* default pcs_autoneg to the same setting as mac autoneg */ 1731 pcs_autoneg = hw->mac.autoneg; 1732 1733 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1734 case E1000_CTRL_EXT_LINK_MODE_SGMII: 1735 /* sgmii mode lets the phy handle forcing speed/duplex */ 1736 pcs_autoneg = true; 1737 /* autoneg time out should be disabled for SGMII mode */ 1738 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1739 break; 1740 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1741 /* disable PCS autoneg and support parallel detect only */ 1742 pcs_autoneg = false; 1743 default: 1744 if (hw->mac.type == e1000_82575 || 1745 hw->mac.type == e1000_82576) { 1746 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data); 1747 if (ret_val) { 1748 hw_dbg(KERN_DEBUG "NVM Read Error\n\n"); 1749 return ret_val; 1750 } 1751 1752 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT) 1753 pcs_autoneg = false; 1754 } 1755 1756 /* non-SGMII modes only supports a speed of 1000/Full for the 1757 * link so it is best to just force the MAC and let the pcs 1758 * link either autoneg or be forced to 1000/Full 1759 */ 1760 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | 1761 E1000_CTRL_FD | E1000_CTRL_FRCDPX; 1762 1763 /* set speed of 1000/Full if speed/duplex is forced */ 1764 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1765 break; 1766 } 1767 1768 wr32(E1000_CTRL, ctrl_reg); 1769 1770 /* New SerDes mode allows for forcing speed or autonegotiating speed 1771 * at 1gb. Autoneg should be default set by most drivers. This is the 1772 * mode that will be compatible with older link partners and switches. 1773 * However, both are supported by the hardware and some drivers/tools. 1774 */ 1775 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1776 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1777 1778 if (pcs_autoneg) { 1779 /* Set PCS register for autoneg */ 1780 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1781 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1782 1783 /* Disable force flow control for autoneg */ 1784 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL; 1785 1786 /* Configure flow control advertisement for autoneg */ 1787 anadv_reg = rd32(E1000_PCS_ANADV); 1788 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE); 1789 switch (hw->fc.requested_mode) { 1790 case e1000_fc_full: 1791 case e1000_fc_rx_pause: 1792 anadv_reg |= E1000_TXCW_ASM_DIR; 1793 anadv_reg |= E1000_TXCW_PAUSE; 1794 break; 1795 case e1000_fc_tx_pause: 1796 anadv_reg |= E1000_TXCW_ASM_DIR; 1797 break; 1798 default: 1799 break; 1800 } 1801 wr32(E1000_PCS_ANADV, anadv_reg); 1802 1803 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); 1804 } else { 1805 /* Set PCS register for forced link */ 1806 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1807 1808 /* Force flow control for forced link */ 1809 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1810 1811 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); 1812 } 1813 1814 wr32(E1000_PCS_LCTL, reg); 1815 1816 if (!pcs_autoneg && !igb_sgmii_active_82575(hw)) 1817 igb_force_mac_fc(hw); 1818 1819 return ret_val; 1820 } 1821 1822 /** 1823 * igb_sgmii_active_82575 - Return sgmii state 1824 * @hw: pointer to the HW structure 1825 * 1826 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1827 * which can be enabled for use in the embedded applications. Simply 1828 * return the current state of the sgmii interface. 1829 **/ 1830 static bool igb_sgmii_active_82575(struct e1000_hw *hw) 1831 { 1832 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1833 return dev_spec->sgmii_active; 1834 } 1835 1836 /** 1837 * igb_reset_init_script_82575 - Inits HW defaults after reset 1838 * @hw: pointer to the HW structure 1839 * 1840 * Inits recommended HW defaults after a reset when there is no EEPROM 1841 * detected. This is only for the 82575. 1842 **/ 1843 static s32 igb_reset_init_script_82575(struct e1000_hw *hw) 1844 { 1845 if (hw->mac.type == e1000_82575) { 1846 hw_dbg("Running reset init script for 82575\n"); 1847 /* SerDes configuration via SERDESCTRL */ 1848 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C); 1849 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78); 1850 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23); 1851 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15); 1852 1853 /* CCM configuration via CCMCTL register */ 1854 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00); 1855 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00); 1856 1857 /* PCIe lanes configuration */ 1858 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC); 1859 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF); 1860 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05); 1861 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81); 1862 1863 /* PCIe PLL Configuration */ 1864 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47); 1865 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00); 1866 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00); 1867 } 1868 1869 return 0; 1870 } 1871 1872 /** 1873 * igb_read_mac_addr_82575 - Read device MAC address 1874 * @hw: pointer to the HW structure 1875 **/ 1876 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw) 1877 { 1878 s32 ret_val = 0; 1879 1880 /* If there's an alternate MAC address place it in RAR0 1881 * so that it will override the Si installed default perm 1882 * address. 1883 */ 1884 ret_val = igb_check_alt_mac_addr(hw); 1885 if (ret_val) 1886 goto out; 1887 1888 ret_val = igb_read_mac_addr(hw); 1889 1890 out: 1891 return ret_val; 1892 } 1893 1894 /** 1895 * igb_power_down_phy_copper_82575 - Remove link during PHY power down 1896 * @hw: pointer to the HW structure 1897 * 1898 * In the case of a PHY power down to save power, or to turn off link during a 1899 * driver unload, or wake on lan is not enabled, remove the link. 1900 **/ 1901 void igb_power_down_phy_copper_82575(struct e1000_hw *hw) 1902 { 1903 /* If the management interface is not enabled, then power down */ 1904 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw))) 1905 igb_power_down_phy_copper(hw); 1906 } 1907 1908 /** 1909 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters 1910 * @hw: pointer to the HW structure 1911 * 1912 * Clears the hardware counters by reading the counter registers. 1913 **/ 1914 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw) 1915 { 1916 igb_clear_hw_cntrs_base(hw); 1917 1918 rd32(E1000_PRC64); 1919 rd32(E1000_PRC127); 1920 rd32(E1000_PRC255); 1921 rd32(E1000_PRC511); 1922 rd32(E1000_PRC1023); 1923 rd32(E1000_PRC1522); 1924 rd32(E1000_PTC64); 1925 rd32(E1000_PTC127); 1926 rd32(E1000_PTC255); 1927 rd32(E1000_PTC511); 1928 rd32(E1000_PTC1023); 1929 rd32(E1000_PTC1522); 1930 1931 rd32(E1000_ALGNERRC); 1932 rd32(E1000_RXERRC); 1933 rd32(E1000_TNCRS); 1934 rd32(E1000_CEXTERR); 1935 rd32(E1000_TSCTC); 1936 rd32(E1000_TSCTFC); 1937 1938 rd32(E1000_MGTPRC); 1939 rd32(E1000_MGTPDC); 1940 rd32(E1000_MGTPTC); 1941 1942 rd32(E1000_IAC); 1943 rd32(E1000_ICRXOC); 1944 1945 rd32(E1000_ICRXPTC); 1946 rd32(E1000_ICRXATC); 1947 rd32(E1000_ICTXPTC); 1948 rd32(E1000_ICTXATC); 1949 rd32(E1000_ICTXQEC); 1950 rd32(E1000_ICTXQMTC); 1951 rd32(E1000_ICRXDMTC); 1952 1953 rd32(E1000_CBTMPC); 1954 rd32(E1000_HTDPMC); 1955 rd32(E1000_CBRMPC); 1956 rd32(E1000_RPTHC); 1957 rd32(E1000_HGPTC); 1958 rd32(E1000_HTCBDPC); 1959 rd32(E1000_HGORCL); 1960 rd32(E1000_HGORCH); 1961 rd32(E1000_HGOTCL); 1962 rd32(E1000_HGOTCH); 1963 rd32(E1000_LENERRS); 1964 1965 /* This register should not be read in copper configurations */ 1966 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1967 igb_sgmii_active_82575(hw)) 1968 rd32(E1000_SCVPC); 1969 } 1970 1971 /** 1972 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable 1973 * @hw: pointer to the HW structure 1974 * 1975 * After rx enable if manageability is enabled then there is likely some 1976 * bad data at the start of the fifo and possibly in the DMA fifo. This 1977 * function clears the fifos and flushes any packets that came in as rx was 1978 * being enabled. 1979 **/ 1980 void igb_rx_fifo_flush_82575(struct e1000_hw *hw) 1981 { 1982 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 1983 int i, ms_wait; 1984 1985 /* disable IPv6 options as per hardware errata */ 1986 rfctl = rd32(E1000_RFCTL); 1987 rfctl |= E1000_RFCTL_IPV6_EX_DIS; 1988 wr32(E1000_RFCTL, rfctl); 1989 1990 if (hw->mac.type != e1000_82575 || 1991 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 1992 return; 1993 1994 /* Disable all RX queues */ 1995 for (i = 0; i < 4; i++) { 1996 rxdctl[i] = rd32(E1000_RXDCTL(i)); 1997 wr32(E1000_RXDCTL(i), 1998 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 1999 } 2000 /* Poll all queues to verify they have shut down */ 2001 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 2002 usleep_range(1000, 2000); 2003 rx_enabled = 0; 2004 for (i = 0; i < 4; i++) 2005 rx_enabled |= rd32(E1000_RXDCTL(i)); 2006 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 2007 break; 2008 } 2009 2010 if (ms_wait == 10) 2011 hw_dbg("Queue disable timed out after 10ms\n"); 2012 2013 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 2014 * incoming packets are rejected. Set enable and wait 2ms so that 2015 * any packet that was coming in as RCTL.EN was set is flushed 2016 */ 2017 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 2018 2019 rlpml = rd32(E1000_RLPML); 2020 wr32(E1000_RLPML, 0); 2021 2022 rctl = rd32(E1000_RCTL); 2023 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 2024 temp_rctl |= E1000_RCTL_LPE; 2025 2026 wr32(E1000_RCTL, temp_rctl); 2027 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN); 2028 wrfl(); 2029 usleep_range(2000, 3000); 2030 2031 /* Enable RX queues that were previously enabled and restore our 2032 * previous state 2033 */ 2034 for (i = 0; i < 4; i++) 2035 wr32(E1000_RXDCTL(i), rxdctl[i]); 2036 wr32(E1000_RCTL, rctl); 2037 wrfl(); 2038 2039 wr32(E1000_RLPML, rlpml); 2040 wr32(E1000_RFCTL, rfctl); 2041 2042 /* Flush receive errors generated by workaround */ 2043 rd32(E1000_ROC); 2044 rd32(E1000_RNBC); 2045 rd32(E1000_MPC); 2046 } 2047 2048 /** 2049 * igb_set_pcie_completion_timeout - set pci-e completion timeout 2050 * @hw: pointer to the HW structure 2051 * 2052 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 2053 * however the hardware default for these parts is 500us to 1ms which is less 2054 * than the 10ms recommended by the pci-e spec. To address this we need to 2055 * increase the value to either 10ms to 200ms for capability version 1 config, 2056 * or 16ms to 55ms for version 2. 2057 **/ 2058 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw) 2059 { 2060 u32 gcr = rd32(E1000_GCR); 2061 s32 ret_val = 0; 2062 u16 pcie_devctl2; 2063 2064 /* only take action if timeout value is defaulted to 0 */ 2065 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 2066 goto out; 2067 2068 /* if capabilities version is type 1 we can write the 2069 * timeout of 10ms to 200ms through the GCR register 2070 */ 2071 if (!(gcr & E1000_GCR_CAP_VER2)) { 2072 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 2073 goto out; 2074 } 2075 2076 /* for version 2 capabilities we need to write the config space 2077 * directly in order to set the completion timeout value for 2078 * 16ms to 55ms 2079 */ 2080 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2081 &pcie_devctl2); 2082 if (ret_val) 2083 goto out; 2084 2085 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 2086 2087 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2088 &pcie_devctl2); 2089 out: 2090 /* disable completion timeout resend */ 2091 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 2092 2093 wr32(E1000_GCR, gcr); 2094 return ret_val; 2095 } 2096 2097 /** 2098 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing 2099 * @hw: pointer to the hardware struct 2100 * @enable: state to enter, either enabled or disabled 2101 * @pf: Physical Function pool - do not set anti-spoofing for the PF 2102 * 2103 * enables/disables L2 switch anti-spoofing functionality. 2104 **/ 2105 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) 2106 { 2107 u32 reg_val, reg_offset; 2108 2109 switch (hw->mac.type) { 2110 case e1000_82576: 2111 reg_offset = E1000_DTXSWC; 2112 break; 2113 case e1000_i350: 2114 case e1000_i354: 2115 reg_offset = E1000_TXSWC; 2116 break; 2117 default: 2118 return; 2119 } 2120 2121 reg_val = rd32(reg_offset); 2122 if (enable) { 2123 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK | 2124 E1000_DTXSWC_VLAN_SPOOF_MASK); 2125 /* The PF can spoof - it has to in order to 2126 * support emulation mode NICs 2127 */ 2128 reg_val ^= (BIT(pf) | BIT(pf + MAX_NUM_VFS)); 2129 } else { 2130 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | 2131 E1000_DTXSWC_VLAN_SPOOF_MASK); 2132 } 2133 wr32(reg_offset, reg_val); 2134 } 2135 2136 /** 2137 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback 2138 * @hw: pointer to the hardware struct 2139 * @enable: state to enter, either enabled or disabled 2140 * 2141 * enables/disables L2 switch loopback functionality. 2142 **/ 2143 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 2144 { 2145 u32 dtxswc; 2146 2147 switch (hw->mac.type) { 2148 case e1000_82576: 2149 dtxswc = rd32(E1000_DTXSWC); 2150 if (enable) 2151 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2152 else 2153 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2154 wr32(E1000_DTXSWC, dtxswc); 2155 break; 2156 case e1000_i354: 2157 case e1000_i350: 2158 dtxswc = rd32(E1000_TXSWC); 2159 if (enable) 2160 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2161 else 2162 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2163 wr32(E1000_TXSWC, dtxswc); 2164 break; 2165 default: 2166 /* Currently no other hardware supports loopback */ 2167 break; 2168 } 2169 2170 } 2171 2172 /** 2173 * igb_vmdq_set_replication_pf - enable or disable vmdq replication 2174 * @hw: pointer to the hardware struct 2175 * @enable: state to enter, either enabled or disabled 2176 * 2177 * enables/disables replication of packets across multiple pools. 2178 **/ 2179 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 2180 { 2181 u32 vt_ctl = rd32(E1000_VT_CTL); 2182 2183 if (enable) 2184 vt_ctl |= E1000_VT_CTL_VM_REPL_EN; 2185 else 2186 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; 2187 2188 wr32(E1000_VT_CTL, vt_ctl); 2189 } 2190 2191 /** 2192 * igb_read_phy_reg_82580 - Read 82580 MDI control register 2193 * @hw: pointer to the HW structure 2194 * @offset: register offset to be read 2195 * @data: pointer to the read data 2196 * 2197 * Reads the MDI control register in the PHY at offset and stores the 2198 * information read to data. 2199 **/ 2200 s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) 2201 { 2202 s32 ret_val; 2203 2204 ret_val = hw->phy.ops.acquire(hw); 2205 if (ret_val) 2206 goto out; 2207 2208 ret_val = igb_read_phy_reg_mdic(hw, offset, data); 2209 2210 hw->phy.ops.release(hw); 2211 2212 out: 2213 return ret_val; 2214 } 2215 2216 /** 2217 * igb_write_phy_reg_82580 - Write 82580 MDI control register 2218 * @hw: pointer to the HW structure 2219 * @offset: register offset to write to 2220 * @data: data to write to register at offset 2221 * 2222 * Writes data to MDI control register in the PHY at offset. 2223 **/ 2224 s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) 2225 { 2226 s32 ret_val; 2227 2228 2229 ret_val = hw->phy.ops.acquire(hw); 2230 if (ret_val) 2231 goto out; 2232 2233 ret_val = igb_write_phy_reg_mdic(hw, offset, data); 2234 2235 hw->phy.ops.release(hw); 2236 2237 out: 2238 return ret_val; 2239 } 2240 2241 /** 2242 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits 2243 * @hw: pointer to the HW structure 2244 * 2245 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on 2246 * the values found in the EEPROM. This addresses an issue in which these 2247 * bits are not restored from EEPROM after reset. 2248 **/ 2249 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw) 2250 { 2251 s32 ret_val = 0; 2252 u32 mdicnfg; 2253 u16 nvm_data = 0; 2254 2255 if (hw->mac.type != e1000_82580) 2256 goto out; 2257 if (!igb_sgmii_active_82575(hw)) 2258 goto out; 2259 2260 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2261 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2262 &nvm_data); 2263 if (ret_val) { 2264 hw_dbg("NVM Read Error\n"); 2265 goto out; 2266 } 2267 2268 mdicnfg = rd32(E1000_MDICNFG); 2269 if (nvm_data & NVM_WORD24_EXT_MDIO) 2270 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 2271 if (nvm_data & NVM_WORD24_COM_MDIO) 2272 mdicnfg |= E1000_MDICNFG_COM_MDIO; 2273 wr32(E1000_MDICNFG, mdicnfg); 2274 out: 2275 return ret_val; 2276 } 2277 2278 /** 2279 * igb_reset_hw_82580 - Reset hardware 2280 * @hw: pointer to the HW structure 2281 * 2282 * This resets function or entire device (all ports, etc.) 2283 * to a known state. 2284 **/ 2285 static s32 igb_reset_hw_82580(struct e1000_hw *hw) 2286 { 2287 s32 ret_val = 0; 2288 /* BH SW mailbox bit in SW_FW_SYNC */ 2289 u16 swmbsw_mask = E1000_SW_SYNCH_MB; 2290 u32 ctrl; 2291 bool global_device_reset = hw->dev_spec._82575.global_device_reset; 2292 2293 hw->dev_spec._82575.global_device_reset = false; 2294 2295 /* due to hw errata, global device reset doesn't always 2296 * work on 82580 2297 */ 2298 if (hw->mac.type == e1000_82580) 2299 global_device_reset = false; 2300 2301 /* Get current control state. */ 2302 ctrl = rd32(E1000_CTRL); 2303 2304 /* Prevent the PCI-E bus from sticking if there is no TLP connection 2305 * on the last TLP read/write transaction when MAC is reset. 2306 */ 2307 ret_val = igb_disable_pcie_master(hw); 2308 if (ret_val) 2309 hw_dbg("PCI-E Master disable polling has failed.\n"); 2310 2311 hw_dbg("Masking off all interrupts\n"); 2312 wr32(E1000_IMC, 0xffffffff); 2313 wr32(E1000_RCTL, 0); 2314 wr32(E1000_TCTL, E1000_TCTL_PSP); 2315 wrfl(); 2316 2317 usleep_range(10000, 11000); 2318 2319 /* Determine whether or not a global dev reset is requested */ 2320 if (global_device_reset && 2321 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask)) 2322 global_device_reset = false; 2323 2324 if (global_device_reset && 2325 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET)) 2326 ctrl |= E1000_CTRL_DEV_RST; 2327 else 2328 ctrl |= E1000_CTRL_RST; 2329 2330 wr32(E1000_CTRL, ctrl); 2331 wrfl(); 2332 2333 /* Add delay to insure DEV_RST has time to complete */ 2334 if (global_device_reset) 2335 usleep_range(5000, 6000); 2336 2337 ret_val = igb_get_auto_rd_done(hw); 2338 if (ret_val) { 2339 /* When auto config read does not complete, do not 2340 * return with an error. This can happen in situations 2341 * where there is no eeprom and prevents getting link. 2342 */ 2343 hw_dbg("Auto Read Done did not complete\n"); 2344 } 2345 2346 /* clear global device reset status bit */ 2347 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET); 2348 2349 /* Clear any pending interrupt events. */ 2350 wr32(E1000_IMC, 0xffffffff); 2351 rd32(E1000_ICR); 2352 2353 ret_val = igb_reset_mdicnfg_82580(hw); 2354 if (ret_val) 2355 hw_dbg("Could not reset MDICNFG based on EEPROM\n"); 2356 2357 /* Install any alternate MAC address into RAR0 */ 2358 ret_val = igb_check_alt_mac_addr(hw); 2359 2360 /* Release semaphore */ 2361 if (global_device_reset) 2362 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask); 2363 2364 return ret_val; 2365 } 2366 2367 /** 2368 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size 2369 * @data: data received by reading RXPBS register 2370 * 2371 * The 82580 uses a table based approach for packet buffer allocation sizes. 2372 * This function converts the retrieved value into the correct table value 2373 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 2374 * 0x0 36 72 144 1 2 4 8 16 2375 * 0x8 35 70 140 rsv rsv rsv rsv rsv 2376 */ 2377 u16 igb_rxpbs_adjust_82580(u32 data) 2378 { 2379 u16 ret_val = 0; 2380 2381 if (data < ARRAY_SIZE(e1000_82580_rxpbs_table)) 2382 ret_val = e1000_82580_rxpbs_table[data]; 2383 2384 return ret_val; 2385 } 2386 2387 /** 2388 * igb_validate_nvm_checksum_with_offset - Validate EEPROM 2389 * checksum 2390 * @hw: pointer to the HW structure 2391 * @offset: offset in words of the checksum protected region 2392 * 2393 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 2394 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 2395 **/ 2396 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw, 2397 u16 offset) 2398 { 2399 s32 ret_val = 0; 2400 u16 checksum = 0; 2401 u16 i, nvm_data; 2402 2403 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) { 2404 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2405 if (ret_val) { 2406 hw_dbg("NVM Read Error\n"); 2407 goto out; 2408 } 2409 checksum += nvm_data; 2410 } 2411 2412 if (checksum != (u16) NVM_SUM) { 2413 hw_dbg("NVM Checksum Invalid\n"); 2414 ret_val = -E1000_ERR_NVM; 2415 goto out; 2416 } 2417 2418 out: 2419 return ret_val; 2420 } 2421 2422 /** 2423 * igb_update_nvm_checksum_with_offset - Update EEPROM 2424 * checksum 2425 * @hw: pointer to the HW structure 2426 * @offset: offset in words of the checksum protected region 2427 * 2428 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 2429 * up to the checksum. Then calculates the EEPROM checksum and writes the 2430 * value to the EEPROM. 2431 **/ 2432 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2433 { 2434 s32 ret_val; 2435 u16 checksum = 0; 2436 u16 i, nvm_data; 2437 2438 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) { 2439 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2440 if (ret_val) { 2441 hw_dbg("NVM Read Error while updating checksum.\n"); 2442 goto out; 2443 } 2444 checksum += nvm_data; 2445 } 2446 checksum = (u16) NVM_SUM - checksum; 2447 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, 2448 &checksum); 2449 if (ret_val) 2450 hw_dbg("NVM Write Error while updating checksum.\n"); 2451 2452 out: 2453 return ret_val; 2454 } 2455 2456 /** 2457 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum 2458 * @hw: pointer to the HW structure 2459 * 2460 * Calculates the EEPROM section checksum by reading/adding each word of 2461 * the EEPROM and then verifies that the sum of the EEPROM is 2462 * equal to 0xBABA. 2463 **/ 2464 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw) 2465 { 2466 s32 ret_val = 0; 2467 u16 eeprom_regions_count = 1; 2468 u16 j, nvm_data; 2469 u16 nvm_offset; 2470 2471 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2472 if (ret_val) { 2473 hw_dbg("NVM Read Error\n"); 2474 goto out; 2475 } 2476 2477 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) { 2478 /* if checksums compatibility bit is set validate checksums 2479 * for all 4 ports. 2480 */ 2481 eeprom_regions_count = 4; 2482 } 2483 2484 for (j = 0; j < eeprom_regions_count; j++) { 2485 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2486 ret_val = igb_validate_nvm_checksum_with_offset(hw, 2487 nvm_offset); 2488 if (ret_val != 0) 2489 goto out; 2490 } 2491 2492 out: 2493 return ret_val; 2494 } 2495 2496 /** 2497 * igb_update_nvm_checksum_82580 - Update EEPROM checksum 2498 * @hw: pointer to the HW structure 2499 * 2500 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2501 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2502 * checksum and writes the value to the EEPROM. 2503 **/ 2504 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw) 2505 { 2506 s32 ret_val; 2507 u16 j, nvm_data; 2508 u16 nvm_offset; 2509 2510 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2511 if (ret_val) { 2512 hw_dbg("NVM Read Error while updating checksum compatibility bit.\n"); 2513 goto out; 2514 } 2515 2516 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) { 2517 /* set compatibility bit to validate checksums appropriately */ 2518 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK; 2519 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, 2520 &nvm_data); 2521 if (ret_val) { 2522 hw_dbg("NVM Write Error while updating checksum compatibility bit.\n"); 2523 goto out; 2524 } 2525 } 2526 2527 for (j = 0; j < 4; j++) { 2528 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2529 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset); 2530 if (ret_val) 2531 goto out; 2532 } 2533 2534 out: 2535 return ret_val; 2536 } 2537 2538 /** 2539 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum 2540 * @hw: pointer to the HW structure 2541 * 2542 * Calculates the EEPROM section checksum by reading/adding each word of 2543 * the EEPROM and then verifies that the sum of the EEPROM is 2544 * equal to 0xBABA. 2545 **/ 2546 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw) 2547 { 2548 s32 ret_val = 0; 2549 u16 j; 2550 u16 nvm_offset; 2551 2552 for (j = 0; j < 4; j++) { 2553 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2554 ret_val = igb_validate_nvm_checksum_with_offset(hw, 2555 nvm_offset); 2556 if (ret_val != 0) 2557 goto out; 2558 } 2559 2560 out: 2561 return ret_val; 2562 } 2563 2564 /** 2565 * igb_update_nvm_checksum_i350 - Update EEPROM checksum 2566 * @hw: pointer to the HW structure 2567 * 2568 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2569 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2570 * checksum and writes the value to the EEPROM. 2571 **/ 2572 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw) 2573 { 2574 s32 ret_val = 0; 2575 u16 j; 2576 u16 nvm_offset; 2577 2578 for (j = 0; j < 4; j++) { 2579 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2580 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset); 2581 if (ret_val != 0) 2582 goto out; 2583 } 2584 2585 out: 2586 return ret_val; 2587 } 2588 2589 /** 2590 * __igb_access_emi_reg - Read/write EMI register 2591 * @hw: pointer to the HW structure 2592 * @addr: EMI address to program 2593 * @data: pointer to value to read/write from/to the EMI address 2594 * @read: boolean flag to indicate read or write 2595 **/ 2596 static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address, 2597 u16 *data, bool read) 2598 { 2599 s32 ret_val = 0; 2600 2601 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address); 2602 if (ret_val) 2603 return ret_val; 2604 2605 if (read) 2606 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data); 2607 else 2608 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data); 2609 2610 return ret_val; 2611 } 2612 2613 /** 2614 * igb_read_emi_reg - Read Extended Management Interface register 2615 * @hw: pointer to the HW structure 2616 * @addr: EMI address to program 2617 * @data: value to be read from the EMI address 2618 **/ 2619 s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data) 2620 { 2621 return __igb_access_emi_reg(hw, addr, data, true); 2622 } 2623 2624 /** 2625 * igb_set_eee_i350 - Enable/disable EEE support 2626 * @hw: pointer to the HW structure 2627 * @adv1G: boolean flag enabling 1G EEE advertisement 2628 * @adv100m: boolean flag enabling 100M EEE advertisement 2629 * 2630 * Enable/disable EEE based on setting in dev_spec structure. 2631 * 2632 **/ 2633 s32 igb_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M) 2634 { 2635 u32 ipcnfg, eeer; 2636 2637 if ((hw->mac.type < e1000_i350) || 2638 (hw->phy.media_type != e1000_media_type_copper)) 2639 goto out; 2640 ipcnfg = rd32(E1000_IPCNFG); 2641 eeer = rd32(E1000_EEER); 2642 2643 /* enable or disable per user setting */ 2644 if (!(hw->dev_spec._82575.eee_disable)) { 2645 u32 eee_su = rd32(E1000_EEE_SU); 2646 2647 if (adv100M) 2648 ipcnfg |= E1000_IPCNFG_EEE_100M_AN; 2649 else 2650 ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN; 2651 2652 if (adv1G) 2653 ipcnfg |= E1000_IPCNFG_EEE_1G_AN; 2654 else 2655 ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN; 2656 2657 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 2658 E1000_EEER_LPI_FC); 2659 2660 /* This bit should not be set in normal operation. */ 2661 if (eee_su & E1000_EEE_SU_LPI_CLK_STP) 2662 hw_dbg("LPI Clock Stop Bit should not be set!\n"); 2663 2664 } else { 2665 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | 2666 E1000_IPCNFG_EEE_100M_AN); 2667 eeer &= ~(E1000_EEER_TX_LPI_EN | 2668 E1000_EEER_RX_LPI_EN | 2669 E1000_EEER_LPI_FC); 2670 } 2671 wr32(E1000_IPCNFG, ipcnfg); 2672 wr32(E1000_EEER, eeer); 2673 rd32(E1000_IPCNFG); 2674 rd32(E1000_EEER); 2675 out: 2676 2677 return 0; 2678 } 2679 2680 /** 2681 * igb_set_eee_i354 - Enable/disable EEE support 2682 * @hw: pointer to the HW structure 2683 * @adv1G: boolean flag enabling 1G EEE advertisement 2684 * @adv100m: boolean flag enabling 100M EEE advertisement 2685 * 2686 * Enable/disable EEE legacy mode based on setting in dev_spec structure. 2687 * 2688 **/ 2689 s32 igb_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M) 2690 { 2691 struct e1000_phy_info *phy = &hw->phy; 2692 s32 ret_val = 0; 2693 u16 phy_data; 2694 2695 if ((hw->phy.media_type != e1000_media_type_copper) || 2696 ((phy->id != M88E1543_E_PHY_ID) && 2697 (phy->id != M88E1512_E_PHY_ID))) 2698 goto out; 2699 2700 if (!hw->dev_spec._82575.eee_disable) { 2701 /* Switch to PHY page 18. */ 2702 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18); 2703 if (ret_val) 2704 goto out; 2705 2706 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1, 2707 &phy_data); 2708 if (ret_val) 2709 goto out; 2710 2711 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS; 2712 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1, 2713 phy_data); 2714 if (ret_val) 2715 goto out; 2716 2717 /* Return the PHY to page 0. */ 2718 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); 2719 if (ret_val) 2720 goto out; 2721 2722 /* Turn on EEE advertisement. */ 2723 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2724 E1000_EEE_ADV_DEV_I354, 2725 &phy_data); 2726 if (ret_val) 2727 goto out; 2728 2729 if (adv100M) 2730 phy_data |= E1000_EEE_ADV_100_SUPPORTED; 2731 else 2732 phy_data &= ~E1000_EEE_ADV_100_SUPPORTED; 2733 2734 if (adv1G) 2735 phy_data |= E1000_EEE_ADV_1000_SUPPORTED; 2736 else 2737 phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED; 2738 2739 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2740 E1000_EEE_ADV_DEV_I354, 2741 phy_data); 2742 } else { 2743 /* Turn off EEE advertisement. */ 2744 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2745 E1000_EEE_ADV_DEV_I354, 2746 &phy_data); 2747 if (ret_val) 2748 goto out; 2749 2750 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED | 2751 E1000_EEE_ADV_1000_SUPPORTED); 2752 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2753 E1000_EEE_ADV_DEV_I354, 2754 phy_data); 2755 } 2756 2757 out: 2758 return ret_val; 2759 } 2760 2761 /** 2762 * igb_get_eee_status_i354 - Get EEE status 2763 * @hw: pointer to the HW structure 2764 * @status: EEE status 2765 * 2766 * Get EEE status by guessing based on whether Tx or Rx LPI indications have 2767 * been received. 2768 **/ 2769 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status) 2770 { 2771 struct e1000_phy_info *phy = &hw->phy; 2772 s32 ret_val = 0; 2773 u16 phy_data; 2774 2775 /* Check if EEE is supported on this device. */ 2776 if ((hw->phy.media_type != e1000_media_type_copper) || 2777 ((phy->id != M88E1543_E_PHY_ID) && 2778 (phy->id != M88E1512_E_PHY_ID))) 2779 goto out; 2780 2781 ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354, 2782 E1000_PCS_STATUS_DEV_I354, 2783 &phy_data); 2784 if (ret_val) 2785 goto out; 2786 2787 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD | 2788 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false; 2789 2790 out: 2791 return ret_val; 2792 } 2793 2794 static const u8 e1000_emc_temp_data[4] = { 2795 E1000_EMC_INTERNAL_DATA, 2796 E1000_EMC_DIODE1_DATA, 2797 E1000_EMC_DIODE2_DATA, 2798 E1000_EMC_DIODE3_DATA 2799 }; 2800 static const u8 e1000_emc_therm_limit[4] = { 2801 E1000_EMC_INTERNAL_THERM_LIMIT, 2802 E1000_EMC_DIODE1_THERM_LIMIT, 2803 E1000_EMC_DIODE2_THERM_LIMIT, 2804 E1000_EMC_DIODE3_THERM_LIMIT 2805 }; 2806 2807 #ifdef CONFIG_IGB_HWMON 2808 /** 2809 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data 2810 * @hw: pointer to hardware structure 2811 * 2812 * Updates the temperatures in mac.thermal_sensor_data 2813 **/ 2814 static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw) 2815 { 2816 u16 ets_offset; 2817 u16 ets_cfg; 2818 u16 ets_sensor; 2819 u8 num_sensors; 2820 u8 sensor_index; 2821 u8 sensor_location; 2822 u8 i; 2823 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 2824 2825 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0)) 2826 return E1000_NOT_IMPLEMENTED; 2827 2828 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF); 2829 2830 /* Return the internal sensor only if ETS is unsupported */ 2831 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset); 2832 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) 2833 return 0; 2834 2835 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg); 2836 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT) 2837 != NVM_ETS_TYPE_EMC) 2838 return E1000_NOT_IMPLEMENTED; 2839 2840 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK); 2841 if (num_sensors > E1000_MAX_SENSORS) 2842 num_sensors = E1000_MAX_SENSORS; 2843 2844 for (i = 1; i < num_sensors; i++) { 2845 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor); 2846 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >> 2847 NVM_ETS_DATA_INDEX_SHIFT); 2848 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >> 2849 NVM_ETS_DATA_LOC_SHIFT); 2850 2851 if (sensor_location != 0) 2852 hw->phy.ops.read_i2c_byte(hw, 2853 e1000_emc_temp_data[sensor_index], 2854 E1000_I2C_THERMAL_SENSOR_ADDR, 2855 &data->sensor[i].temp); 2856 } 2857 return 0; 2858 } 2859 2860 /** 2861 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds 2862 * @hw: pointer to hardware structure 2863 * 2864 * Sets the thermal sensor thresholds according to the NVM map 2865 * and save off the threshold and location values into mac.thermal_sensor_data 2866 **/ 2867 static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw) 2868 { 2869 u16 ets_offset; 2870 u16 ets_cfg; 2871 u16 ets_sensor; 2872 u8 low_thresh_delta; 2873 u8 num_sensors; 2874 u8 sensor_index; 2875 u8 sensor_location; 2876 u8 therm_limit; 2877 u8 i; 2878 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 2879 2880 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0)) 2881 return E1000_NOT_IMPLEMENTED; 2882 2883 memset(data, 0, sizeof(struct e1000_thermal_sensor_data)); 2884 2885 data->sensor[0].location = 0x1; 2886 data->sensor[0].caution_thresh = 2887 (rd32(E1000_THHIGHTC) & 0xFF); 2888 data->sensor[0].max_op_thresh = 2889 (rd32(E1000_THLOWTC) & 0xFF); 2890 2891 /* Return the internal sensor only if ETS is unsupported */ 2892 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset); 2893 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) 2894 return 0; 2895 2896 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg); 2897 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT) 2898 != NVM_ETS_TYPE_EMC) 2899 return E1000_NOT_IMPLEMENTED; 2900 2901 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >> 2902 NVM_ETS_LTHRES_DELTA_SHIFT); 2903 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK); 2904 2905 for (i = 1; i <= num_sensors; i++) { 2906 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor); 2907 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >> 2908 NVM_ETS_DATA_INDEX_SHIFT); 2909 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >> 2910 NVM_ETS_DATA_LOC_SHIFT); 2911 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK; 2912 2913 hw->phy.ops.write_i2c_byte(hw, 2914 e1000_emc_therm_limit[sensor_index], 2915 E1000_I2C_THERMAL_SENSOR_ADDR, 2916 therm_limit); 2917 2918 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) { 2919 data->sensor[i].location = sensor_location; 2920 data->sensor[i].caution_thresh = therm_limit; 2921 data->sensor[i].max_op_thresh = therm_limit - 2922 low_thresh_delta; 2923 } 2924 } 2925 return 0; 2926 } 2927 2928 #endif 2929 static struct e1000_mac_operations e1000_mac_ops_82575 = { 2930 .init_hw = igb_init_hw_82575, 2931 .check_for_link = igb_check_for_link_82575, 2932 .rar_set = igb_rar_set, 2933 .read_mac_addr = igb_read_mac_addr_82575, 2934 .get_speed_and_duplex = igb_get_link_up_info_82575, 2935 #ifdef CONFIG_IGB_HWMON 2936 .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic, 2937 .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic, 2938 #endif 2939 }; 2940 2941 static const struct e1000_phy_operations e1000_phy_ops_82575 = { 2942 .acquire = igb_acquire_phy_82575, 2943 .get_cfg_done = igb_get_cfg_done_82575, 2944 .release = igb_release_phy_82575, 2945 .write_i2c_byte = igb_write_i2c_byte, 2946 .read_i2c_byte = igb_read_i2c_byte, 2947 }; 2948 2949 static struct e1000_nvm_operations e1000_nvm_ops_82575 = { 2950 .acquire = igb_acquire_nvm_82575, 2951 .read = igb_read_nvm_eerd, 2952 .release = igb_release_nvm_82575, 2953 .write = igb_write_nvm_spi, 2954 }; 2955 2956 const struct e1000_info e1000_82575_info = { 2957 .get_invariants = igb_get_invariants_82575, 2958 .mac_ops = &e1000_mac_ops_82575, 2959 .phy_ops = &e1000_phy_ops_82575, 2960 .nvm_ops = &e1000_nvm_ops_82575, 2961 }; 2962 2963