1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
3 
4 /* e1000_82575
5  * e1000_82576
6  */
7 
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9 
10 #include <linux/types.h>
11 #include <linux/if_ether.h>
12 #include <linux/i2c.h>
13 
14 #include "e1000_mac.h"
15 #include "e1000_82575.h"
16 #include "e1000_i210.h"
17 #include "igb.h"
18 
19 static s32  igb_get_invariants_82575(struct e1000_hw *);
20 static s32  igb_acquire_phy_82575(struct e1000_hw *);
21 static void igb_release_phy_82575(struct e1000_hw *);
22 static s32  igb_acquire_nvm_82575(struct e1000_hw *);
23 static void igb_release_nvm_82575(struct e1000_hw *);
24 static s32  igb_check_for_link_82575(struct e1000_hw *);
25 static s32  igb_get_cfg_done_82575(struct e1000_hw *);
26 static s32  igb_init_hw_82575(struct e1000_hw *);
27 static s32  igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
28 static s32  igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
29 static s32  igb_reset_hw_82575(struct e1000_hw *);
30 static s32  igb_reset_hw_82580(struct e1000_hw *);
31 static s32  igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
32 static s32  igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
33 static s32  igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
34 static s32  igb_setup_copper_link_82575(struct e1000_hw *);
35 static s32  igb_setup_serdes_link_82575(struct e1000_hw *);
36 static s32  igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
37 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
38 static s32  igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
39 static s32  igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
40 						 u16 *);
41 static s32  igb_get_phy_id_82575(struct e1000_hw *);
42 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
43 static bool igb_sgmii_active_82575(struct e1000_hw *);
44 static s32  igb_reset_init_script_82575(struct e1000_hw *);
45 static s32  igb_read_mac_addr_82575(struct e1000_hw *);
46 static s32  igb_set_pcie_completion_timeout(struct e1000_hw *hw);
47 static s32  igb_reset_mdicnfg_82580(struct e1000_hw *hw);
48 static s32  igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
49 static s32  igb_update_nvm_checksum_82580(struct e1000_hw *hw);
50 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
51 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
52 static const u16 e1000_82580_rxpbs_table[] = {
53 	36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
54 
55 /* Due to a hw errata, if the host tries to  configure the VFTA register
56  * while performing queries from the BMC or DMA, then the VFTA in some
57  * cases won't be written.
58  */
59 
60 /**
61  *  igb_write_vfta_i350 - Write value to VLAN filter table
62  *  @hw: pointer to the HW structure
63  *  @offset: register offset in VLAN filter table
64  *  @value: register value written to VLAN filter table
65  *
66  *  Writes value at the given offset in the register array which stores
67  *  the VLAN filter table.
68  **/
69 static void igb_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
70 {
71 	struct igb_adapter *adapter = hw->back;
72 	int i;
73 
74 	for (i = 10; i--;)
75 		array_wr32(E1000_VFTA, offset, value);
76 
77 	wrfl();
78 	adapter->shadow_vfta[offset] = value;
79 }
80 
81 /**
82  *  igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
83  *  @hw: pointer to the HW structure
84  *
85  *  Called to determine if the I2C pins are being used for I2C or as an
86  *  external MDIO interface since the two options are mutually exclusive.
87  **/
88 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
89 {
90 	u32 reg = 0;
91 	bool ext_mdio = false;
92 
93 	switch (hw->mac.type) {
94 	case e1000_82575:
95 	case e1000_82576:
96 		reg = rd32(E1000_MDIC);
97 		ext_mdio = !!(reg & E1000_MDIC_DEST);
98 		break;
99 	case e1000_82580:
100 	case e1000_i350:
101 	case e1000_i354:
102 	case e1000_i210:
103 	case e1000_i211:
104 		reg = rd32(E1000_MDICNFG);
105 		ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
106 		break;
107 	default:
108 		break;
109 	}
110 	return ext_mdio;
111 }
112 
113 /**
114  *  igb_check_for_link_media_swap - Check which M88E1112 interface linked
115  *  @hw: pointer to the HW structure
116  *
117  *  Poll the M88E1112 interfaces to see which interface achieved link.
118  */
119 static s32 igb_check_for_link_media_swap(struct e1000_hw *hw)
120 {
121 	struct e1000_phy_info *phy = &hw->phy;
122 	s32 ret_val;
123 	u16 data;
124 	u8 port = 0;
125 
126 	/* Check the copper medium. */
127 	ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
128 	if (ret_val)
129 		return ret_val;
130 
131 	ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
132 	if (ret_val)
133 		return ret_val;
134 
135 	if (data & E1000_M88E1112_STATUS_LINK)
136 		port = E1000_MEDIA_PORT_COPPER;
137 
138 	/* Check the other medium. */
139 	ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
140 	if (ret_val)
141 		return ret_val;
142 
143 	ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
144 	if (ret_val)
145 		return ret_val;
146 
147 
148 	if (data & E1000_M88E1112_STATUS_LINK)
149 		port = E1000_MEDIA_PORT_OTHER;
150 
151 	/* Determine if a swap needs to happen. */
152 	if (port && (hw->dev_spec._82575.media_port != port)) {
153 		hw->dev_spec._82575.media_port = port;
154 		hw->dev_spec._82575.media_changed = true;
155 	}
156 
157 	if (port == E1000_MEDIA_PORT_COPPER) {
158 		/* reset page to 0 */
159 		ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
160 		if (ret_val)
161 			return ret_val;
162 		igb_check_for_link_82575(hw);
163 	} else {
164 		igb_check_for_link_82575(hw);
165 		/* reset page to 0 */
166 		ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
167 		if (ret_val)
168 			return ret_val;
169 	}
170 
171 	return 0;
172 }
173 
174 /**
175  *  igb_init_phy_params_82575 - Init PHY func ptrs.
176  *  @hw: pointer to the HW structure
177  **/
178 static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
179 {
180 	struct e1000_phy_info *phy = &hw->phy;
181 	s32 ret_val = 0;
182 	u32 ctrl_ext;
183 
184 	if (hw->phy.media_type != e1000_media_type_copper) {
185 		phy->type = e1000_phy_none;
186 		goto out;
187 	}
188 
189 	phy->autoneg_mask	= AUTONEG_ADVERTISE_SPEED_DEFAULT;
190 	phy->reset_delay_us	= 100;
191 
192 	ctrl_ext = rd32(E1000_CTRL_EXT);
193 
194 	if (igb_sgmii_active_82575(hw)) {
195 		phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
196 		ctrl_ext |= E1000_CTRL_I2C_ENA;
197 	} else {
198 		phy->ops.reset = igb_phy_hw_reset;
199 		ctrl_ext &= ~E1000_CTRL_I2C_ENA;
200 	}
201 
202 	wr32(E1000_CTRL_EXT, ctrl_ext);
203 	igb_reset_mdicnfg_82580(hw);
204 
205 	if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
206 		phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
207 		phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
208 	} else {
209 		switch (hw->mac.type) {
210 		case e1000_82580:
211 		case e1000_i350:
212 		case e1000_i354:
213 		case e1000_i210:
214 		case e1000_i211:
215 			phy->ops.read_reg = igb_read_phy_reg_82580;
216 			phy->ops.write_reg = igb_write_phy_reg_82580;
217 			break;
218 		default:
219 			phy->ops.read_reg = igb_read_phy_reg_igp;
220 			phy->ops.write_reg = igb_write_phy_reg_igp;
221 		}
222 	}
223 
224 	/* set lan id */
225 	hw->bus.func = FIELD_GET(E1000_STATUS_FUNC_MASK, rd32(E1000_STATUS));
226 
227 	/* Set phy->phy_addr and phy->id. */
228 	ret_val = igb_get_phy_id_82575(hw);
229 	if (ret_val)
230 		return ret_val;
231 
232 	/* Verify phy id and set remaining function pointers */
233 	switch (phy->id) {
234 	case M88E1543_E_PHY_ID:
235 	case M88E1512_E_PHY_ID:
236 	case I347AT4_E_PHY_ID:
237 	case M88E1112_E_PHY_ID:
238 	case M88E1111_I_PHY_ID:
239 		phy->type		= e1000_phy_m88;
240 		phy->ops.check_polarity	= igb_check_polarity_m88;
241 		phy->ops.get_phy_info	= igb_get_phy_info_m88;
242 		if (phy->id != M88E1111_I_PHY_ID)
243 			phy->ops.get_cable_length =
244 					 igb_get_cable_length_m88_gen2;
245 		else
246 			phy->ops.get_cable_length = igb_get_cable_length_m88;
247 		phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
248 		/* Check if this PHY is configured for media swap. */
249 		if (phy->id == M88E1112_E_PHY_ID) {
250 			u16 data;
251 
252 			ret_val = phy->ops.write_reg(hw,
253 						     E1000_M88E1112_PAGE_ADDR,
254 						     2);
255 			if (ret_val)
256 				goto out;
257 
258 			ret_val = phy->ops.read_reg(hw,
259 						    E1000_M88E1112_MAC_CTRL_1,
260 						    &data);
261 			if (ret_val)
262 				goto out;
263 
264 			data = FIELD_GET(E1000_M88E1112_MAC_CTRL_1_MODE_MASK,
265 					 data);
266 			if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
267 			    data == E1000_M88E1112_AUTO_COPPER_BASEX)
268 				hw->mac.ops.check_for_link =
269 						igb_check_for_link_media_swap;
270 		}
271 		if (phy->id == M88E1512_E_PHY_ID) {
272 			ret_val = igb_initialize_M88E1512_phy(hw);
273 			if (ret_val)
274 				goto out;
275 		}
276 		if (phy->id == M88E1543_E_PHY_ID) {
277 			ret_val = igb_initialize_M88E1543_phy(hw);
278 			if (ret_val)
279 				goto out;
280 		}
281 		break;
282 	case IGP03E1000_E_PHY_ID:
283 		phy->type = e1000_phy_igp_3;
284 		phy->ops.get_phy_info = igb_get_phy_info_igp;
285 		phy->ops.get_cable_length = igb_get_cable_length_igp_2;
286 		phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
287 		phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
288 		phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
289 		break;
290 	case I82580_I_PHY_ID:
291 	case I350_I_PHY_ID:
292 		phy->type = e1000_phy_82580;
293 		phy->ops.force_speed_duplex =
294 					 igb_phy_force_speed_duplex_82580;
295 		phy->ops.get_cable_length = igb_get_cable_length_82580;
296 		phy->ops.get_phy_info = igb_get_phy_info_82580;
297 		phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
298 		phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
299 		break;
300 	case I210_I_PHY_ID:
301 		phy->type		= e1000_phy_i210;
302 		phy->ops.check_polarity	= igb_check_polarity_m88;
303 		phy->ops.get_cfg_done	= igb_get_cfg_done_i210;
304 		phy->ops.get_phy_info	= igb_get_phy_info_m88;
305 		phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
306 		phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
307 		phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
308 		phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
309 		break;
310 	case BCM54616_E_PHY_ID:
311 		phy->type = e1000_phy_bcm54616;
312 		break;
313 	default:
314 		ret_val = -E1000_ERR_PHY;
315 		goto out;
316 	}
317 
318 out:
319 	return ret_val;
320 }
321 
322 /**
323  *  igb_init_nvm_params_82575 - Init NVM func ptrs.
324  *  @hw: pointer to the HW structure
325  **/
326 static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
327 {
328 	struct e1000_nvm_info *nvm = &hw->nvm;
329 	u32 eecd = rd32(E1000_EECD);
330 	u16 size;
331 
332 	size = FIELD_GET(E1000_EECD_SIZE_EX_MASK, eecd);
333 
334 	/* Added to a constant, "size" becomes the left-shift value
335 	 * for setting word_size.
336 	 */
337 	size += NVM_WORD_SIZE_BASE_SHIFT;
338 
339 	/* Just in case size is out of range, cap it to the largest
340 	 * EEPROM size supported
341 	 */
342 	if (size > 15)
343 		size = 15;
344 
345 	nvm->word_size = BIT(size);
346 	nvm->opcode_bits = 8;
347 	nvm->delay_usec = 1;
348 
349 	switch (nvm->override) {
350 	case e1000_nvm_override_spi_large:
351 		nvm->page_size = 32;
352 		nvm->address_bits = 16;
353 		break;
354 	case e1000_nvm_override_spi_small:
355 		nvm->page_size = 8;
356 		nvm->address_bits = 8;
357 		break;
358 	default:
359 		nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
360 		nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
361 				    16 : 8;
362 		break;
363 	}
364 	if (nvm->word_size == BIT(15))
365 		nvm->page_size = 128;
366 
367 	nvm->type = e1000_nvm_eeprom_spi;
368 
369 	/* NVM Function Pointers */
370 	nvm->ops.acquire = igb_acquire_nvm_82575;
371 	nvm->ops.release = igb_release_nvm_82575;
372 	nvm->ops.write = igb_write_nvm_spi;
373 	nvm->ops.validate = igb_validate_nvm_checksum;
374 	nvm->ops.update = igb_update_nvm_checksum;
375 	if (nvm->word_size < BIT(15))
376 		nvm->ops.read = igb_read_nvm_eerd;
377 	else
378 		nvm->ops.read = igb_read_nvm_spi;
379 
380 	/* override generic family function pointers for specific descendants */
381 	switch (hw->mac.type) {
382 	case e1000_82580:
383 		nvm->ops.validate = igb_validate_nvm_checksum_82580;
384 		nvm->ops.update = igb_update_nvm_checksum_82580;
385 		break;
386 	case e1000_i354:
387 	case e1000_i350:
388 		nvm->ops.validate = igb_validate_nvm_checksum_i350;
389 		nvm->ops.update = igb_update_nvm_checksum_i350;
390 		break;
391 	default:
392 		break;
393 	}
394 
395 	return 0;
396 }
397 
398 /**
399  *  igb_init_mac_params_82575 - Init MAC func ptrs.
400  *  @hw: pointer to the HW structure
401  **/
402 static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
403 {
404 	struct e1000_mac_info *mac = &hw->mac;
405 	struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
406 
407 	/* Set mta register count */
408 	mac->mta_reg_count = 128;
409 	/* Set uta register count */
410 	mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
411 	/* Set rar entry count */
412 	switch (mac->type) {
413 	case e1000_82576:
414 		mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
415 		break;
416 	case e1000_82580:
417 		mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
418 		break;
419 	case e1000_i350:
420 	case e1000_i354:
421 		mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
422 		break;
423 	default:
424 		mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
425 		break;
426 	}
427 	/* reset */
428 	if (mac->type >= e1000_82580)
429 		mac->ops.reset_hw = igb_reset_hw_82580;
430 	else
431 		mac->ops.reset_hw = igb_reset_hw_82575;
432 
433 	if (mac->type >= e1000_i210) {
434 		mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
435 		mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
436 
437 	} else {
438 		mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
439 		mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
440 	}
441 
442 	if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
443 		mac->ops.write_vfta = igb_write_vfta_i350;
444 	else
445 		mac->ops.write_vfta = igb_write_vfta;
446 
447 	/* Set if part includes ASF firmware */
448 	mac->asf_firmware_present = true;
449 	/* Set if manageability features are enabled. */
450 	mac->arc_subsystem_valid =
451 		(rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
452 			? true : false;
453 	/* enable EEE on i350 parts and later parts */
454 	if (mac->type >= e1000_i350)
455 		dev_spec->eee_disable = false;
456 	else
457 		dev_spec->eee_disable = true;
458 	/* Allow a single clear of the SW semaphore on I210 and newer */
459 	if (mac->type >= e1000_i210)
460 		dev_spec->clear_semaphore_once = true;
461 	/* physical interface link setup */
462 	mac->ops.setup_physical_interface =
463 		(hw->phy.media_type == e1000_media_type_copper)
464 			? igb_setup_copper_link_82575
465 			: igb_setup_serdes_link_82575;
466 
467 	if (mac->type == e1000_82580 || mac->type == e1000_i350) {
468 		switch (hw->device_id) {
469 		/* feature not supported on these id's */
470 		case E1000_DEV_ID_DH89XXCC_SGMII:
471 		case E1000_DEV_ID_DH89XXCC_SERDES:
472 		case E1000_DEV_ID_DH89XXCC_BACKPLANE:
473 		case E1000_DEV_ID_DH89XXCC_SFP:
474 			break;
475 		default:
476 			hw->dev_spec._82575.mas_capable = true;
477 			break;
478 		}
479 	}
480 	return 0;
481 }
482 
483 /**
484  *  igb_set_sfp_media_type_82575 - derives SFP module media type.
485  *  @hw: pointer to the HW structure
486  *
487  *  The media type is chosen based on SFP module.
488  *  compatibility flags retrieved from SFP ID EEPROM.
489  **/
490 static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw)
491 {
492 	s32 ret_val = E1000_ERR_CONFIG;
493 	u32 ctrl_ext = 0;
494 	struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
495 	struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
496 	u8 tranceiver_type = 0;
497 	s32 timeout = 3;
498 
499 	/* Turn I2C interface ON and power on sfp cage */
500 	ctrl_ext = rd32(E1000_CTRL_EXT);
501 	ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
502 	wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
503 
504 	wrfl();
505 
506 	/* Read SFP module data */
507 	while (timeout) {
508 		ret_val = igb_read_sfp_data_byte(hw,
509 			E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
510 			&tranceiver_type);
511 		if (ret_val == 0)
512 			break;
513 		msleep(100);
514 		timeout--;
515 	}
516 	if (ret_val != 0)
517 		goto out;
518 
519 	ret_val = igb_read_sfp_data_byte(hw,
520 			E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
521 			(u8 *)eth_flags);
522 	if (ret_val != 0)
523 		goto out;
524 
525 	/* Check if there is some SFP module plugged and powered */
526 	if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
527 	    (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
528 		dev_spec->module_plugged = true;
529 		if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
530 			hw->phy.media_type = e1000_media_type_internal_serdes;
531 		} else if (eth_flags->e100_base_fx || eth_flags->e100_base_lx) {
532 			dev_spec->sgmii_active = true;
533 			hw->phy.media_type = e1000_media_type_internal_serdes;
534 		} else if (eth_flags->e1000_base_t) {
535 			dev_spec->sgmii_active = true;
536 			hw->phy.media_type = e1000_media_type_copper;
537 		} else {
538 			hw->phy.media_type = e1000_media_type_unknown;
539 			hw_dbg("PHY module has not been recognized\n");
540 			goto out;
541 		}
542 	} else {
543 		hw->phy.media_type = e1000_media_type_unknown;
544 	}
545 	ret_val = 0;
546 out:
547 	/* Restore I2C interface setting */
548 	wr32(E1000_CTRL_EXT, ctrl_ext);
549 	return ret_val;
550 }
551 
552 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
553 {
554 	struct e1000_mac_info *mac = &hw->mac;
555 	struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
556 	s32 ret_val;
557 	u32 ctrl_ext = 0;
558 	u32 link_mode = 0;
559 
560 	switch (hw->device_id) {
561 	case E1000_DEV_ID_82575EB_COPPER:
562 	case E1000_DEV_ID_82575EB_FIBER_SERDES:
563 	case E1000_DEV_ID_82575GB_QUAD_COPPER:
564 		mac->type = e1000_82575;
565 		break;
566 	case E1000_DEV_ID_82576:
567 	case E1000_DEV_ID_82576_NS:
568 	case E1000_DEV_ID_82576_NS_SERDES:
569 	case E1000_DEV_ID_82576_FIBER:
570 	case E1000_DEV_ID_82576_SERDES:
571 	case E1000_DEV_ID_82576_QUAD_COPPER:
572 	case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
573 	case E1000_DEV_ID_82576_SERDES_QUAD:
574 		mac->type = e1000_82576;
575 		break;
576 	case E1000_DEV_ID_82580_COPPER:
577 	case E1000_DEV_ID_82580_FIBER:
578 	case E1000_DEV_ID_82580_QUAD_FIBER:
579 	case E1000_DEV_ID_82580_SERDES:
580 	case E1000_DEV_ID_82580_SGMII:
581 	case E1000_DEV_ID_82580_COPPER_DUAL:
582 	case E1000_DEV_ID_DH89XXCC_SGMII:
583 	case E1000_DEV_ID_DH89XXCC_SERDES:
584 	case E1000_DEV_ID_DH89XXCC_BACKPLANE:
585 	case E1000_DEV_ID_DH89XXCC_SFP:
586 		mac->type = e1000_82580;
587 		break;
588 	case E1000_DEV_ID_I350_COPPER:
589 	case E1000_DEV_ID_I350_FIBER:
590 	case E1000_DEV_ID_I350_SERDES:
591 	case E1000_DEV_ID_I350_SGMII:
592 		mac->type = e1000_i350;
593 		break;
594 	case E1000_DEV_ID_I210_COPPER:
595 	case E1000_DEV_ID_I210_FIBER:
596 	case E1000_DEV_ID_I210_SERDES:
597 	case E1000_DEV_ID_I210_SGMII:
598 	case E1000_DEV_ID_I210_COPPER_FLASHLESS:
599 	case E1000_DEV_ID_I210_SERDES_FLASHLESS:
600 		mac->type = e1000_i210;
601 		break;
602 	case E1000_DEV_ID_I211_COPPER:
603 		mac->type = e1000_i211;
604 		break;
605 	case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
606 	case E1000_DEV_ID_I354_SGMII:
607 	case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
608 		mac->type = e1000_i354;
609 		break;
610 	default:
611 		return -E1000_ERR_MAC_INIT;
612 	}
613 
614 	/* Set media type */
615 	/* The 82575 uses bits 22:23 for link mode. The mode can be changed
616 	 * based on the EEPROM. We cannot rely upon device ID. There
617 	 * is no distinguishable difference between fiber and internal
618 	 * SerDes mode on the 82575. There can be an external PHY attached
619 	 * on the SGMII interface. For this, we'll set sgmii_active to true.
620 	 */
621 	hw->phy.media_type = e1000_media_type_copper;
622 	dev_spec->sgmii_active = false;
623 	dev_spec->module_plugged = false;
624 
625 	ctrl_ext = rd32(E1000_CTRL_EXT);
626 
627 	link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
628 	switch (link_mode) {
629 	case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
630 		hw->phy.media_type = e1000_media_type_internal_serdes;
631 		break;
632 	case E1000_CTRL_EXT_LINK_MODE_SGMII:
633 		/* Get phy control interface type set (MDIO vs. I2C)*/
634 		if (igb_sgmii_uses_mdio_82575(hw)) {
635 			hw->phy.media_type = e1000_media_type_copper;
636 			dev_spec->sgmii_active = true;
637 			break;
638 		}
639 		fallthrough; /* for I2C based SGMII */
640 	case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
641 		/* read media type from SFP EEPROM */
642 		ret_val = igb_set_sfp_media_type_82575(hw);
643 		if ((ret_val != 0) ||
644 		    (hw->phy.media_type == e1000_media_type_unknown)) {
645 			/* If media type was not identified then return media
646 			 * type defined by the CTRL_EXT settings.
647 			 */
648 			hw->phy.media_type = e1000_media_type_internal_serdes;
649 
650 			if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
651 				hw->phy.media_type = e1000_media_type_copper;
652 				dev_spec->sgmii_active = true;
653 			}
654 
655 			break;
656 		}
657 
658 		/* change current link mode setting */
659 		ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
660 
661 		if (dev_spec->sgmii_active)
662 			ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
663 		else
664 			ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
665 
666 		wr32(E1000_CTRL_EXT, ctrl_ext);
667 
668 		break;
669 	default:
670 		break;
671 	}
672 
673 	/* mac initialization and operations */
674 	ret_val = igb_init_mac_params_82575(hw);
675 	if (ret_val)
676 		goto out;
677 
678 	/* NVM initialization */
679 	ret_val = igb_init_nvm_params_82575(hw);
680 	switch (hw->mac.type) {
681 	case e1000_i210:
682 	case e1000_i211:
683 		ret_val = igb_init_nvm_params_i210(hw);
684 		break;
685 	default:
686 		break;
687 	}
688 
689 	if (ret_val)
690 		goto out;
691 
692 	/* if part supports SR-IOV then initialize mailbox parameters */
693 	switch (mac->type) {
694 	case e1000_82576:
695 	case e1000_i350:
696 		igb_init_mbx_params_pf(hw);
697 		break;
698 	default:
699 		break;
700 	}
701 
702 	/* setup PHY parameters */
703 	ret_val = igb_init_phy_params_82575(hw);
704 
705 out:
706 	return ret_val;
707 }
708 
709 /**
710  *  igb_acquire_phy_82575 - Acquire rights to access PHY
711  *  @hw: pointer to the HW structure
712  *
713  *  Acquire access rights to the correct PHY.  This is a
714  *  function pointer entry point called by the api module.
715  **/
716 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
717 {
718 	u16 mask = E1000_SWFW_PHY0_SM;
719 
720 	if (hw->bus.func == E1000_FUNC_1)
721 		mask = E1000_SWFW_PHY1_SM;
722 	else if (hw->bus.func == E1000_FUNC_2)
723 		mask = E1000_SWFW_PHY2_SM;
724 	else if (hw->bus.func == E1000_FUNC_3)
725 		mask = E1000_SWFW_PHY3_SM;
726 
727 	return hw->mac.ops.acquire_swfw_sync(hw, mask);
728 }
729 
730 /**
731  *  igb_release_phy_82575 - Release rights to access PHY
732  *  @hw: pointer to the HW structure
733  *
734  *  A wrapper to release access rights to the correct PHY.  This is a
735  *  function pointer entry point called by the api module.
736  **/
737 static void igb_release_phy_82575(struct e1000_hw *hw)
738 {
739 	u16 mask = E1000_SWFW_PHY0_SM;
740 
741 	if (hw->bus.func == E1000_FUNC_1)
742 		mask = E1000_SWFW_PHY1_SM;
743 	else if (hw->bus.func == E1000_FUNC_2)
744 		mask = E1000_SWFW_PHY2_SM;
745 	else if (hw->bus.func == E1000_FUNC_3)
746 		mask = E1000_SWFW_PHY3_SM;
747 
748 	hw->mac.ops.release_swfw_sync(hw, mask);
749 }
750 
751 /**
752  *  igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
753  *  @hw: pointer to the HW structure
754  *  @offset: register offset to be read
755  *  @data: pointer to the read data
756  *
757  *  Reads the PHY register at offset using the serial gigabit media independent
758  *  interface and stores the retrieved information in data.
759  **/
760 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
761 					  u16 *data)
762 {
763 	s32 ret_val = -E1000_ERR_PARAM;
764 
765 	if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
766 		hw_dbg("PHY Address %u is out of range\n", offset);
767 		goto out;
768 	}
769 
770 	ret_val = hw->phy.ops.acquire(hw);
771 	if (ret_val)
772 		goto out;
773 
774 	ret_val = igb_read_phy_reg_i2c(hw, offset, data);
775 
776 	hw->phy.ops.release(hw);
777 
778 out:
779 	return ret_val;
780 }
781 
782 /**
783  *  igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
784  *  @hw: pointer to the HW structure
785  *  @offset: register offset to write to
786  *  @data: data to write at register offset
787  *
788  *  Writes the data to PHY register at the offset using the serial gigabit
789  *  media independent interface.
790  **/
791 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
792 					   u16 data)
793 {
794 	s32 ret_val = -E1000_ERR_PARAM;
795 
796 
797 	if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
798 		hw_dbg("PHY Address %d is out of range\n", offset);
799 		goto out;
800 	}
801 
802 	ret_val = hw->phy.ops.acquire(hw);
803 	if (ret_val)
804 		goto out;
805 
806 	ret_val = igb_write_phy_reg_i2c(hw, offset, data);
807 
808 	hw->phy.ops.release(hw);
809 
810 out:
811 	return ret_val;
812 }
813 
814 /**
815  *  igb_get_phy_id_82575 - Retrieve PHY addr and id
816  *  @hw: pointer to the HW structure
817  *
818  *  Retrieves the PHY address and ID for both PHY's which do and do not use
819  *  sgmi interface.
820  **/
821 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
822 {
823 	struct e1000_phy_info *phy = &hw->phy;
824 	s32  ret_val = 0;
825 	u16 phy_id;
826 	u32 ctrl_ext;
827 	u32 mdic;
828 
829 	/* Extra read required for some PHY's on i354 */
830 	if (hw->mac.type == e1000_i354)
831 		igb_get_phy_id(hw);
832 
833 	/* For SGMII PHYs, we try the list of possible addresses until
834 	 * we find one that works.  For non-SGMII PHYs
835 	 * (e.g. integrated copper PHYs), an address of 1 should
836 	 * work.  The result of this function should mean phy->phy_addr
837 	 * and phy->id are set correctly.
838 	 */
839 	if (!(igb_sgmii_active_82575(hw))) {
840 		phy->addr = 1;
841 		ret_val = igb_get_phy_id(hw);
842 		goto out;
843 	}
844 
845 	if (igb_sgmii_uses_mdio_82575(hw)) {
846 		switch (hw->mac.type) {
847 		case e1000_82575:
848 		case e1000_82576:
849 			mdic = rd32(E1000_MDIC);
850 			mdic &= E1000_MDIC_PHY_MASK;
851 			phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
852 			break;
853 		case e1000_82580:
854 		case e1000_i350:
855 		case e1000_i354:
856 		case e1000_i210:
857 		case e1000_i211:
858 			mdic = rd32(E1000_MDICNFG);
859 			mdic &= E1000_MDICNFG_PHY_MASK;
860 			phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
861 			break;
862 		default:
863 			ret_val = -E1000_ERR_PHY;
864 			goto out;
865 		}
866 		ret_val = igb_get_phy_id(hw);
867 		goto out;
868 	}
869 
870 	/* Power on sgmii phy if it is disabled */
871 	ctrl_ext = rd32(E1000_CTRL_EXT);
872 	wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
873 	wrfl();
874 	msleep(300);
875 
876 	/* The address field in the I2CCMD register is 3 bits and 0 is invalid.
877 	 * Therefore, we need to test 1-7
878 	 */
879 	for (phy->addr = 1; phy->addr < 8; phy->addr++) {
880 		ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
881 		if (ret_val == 0) {
882 			hw_dbg("Vendor ID 0x%08X read at address %u\n",
883 			       phy_id, phy->addr);
884 			/* At the time of this writing, The M88 part is
885 			 * the only supported SGMII PHY product.
886 			 */
887 			if (phy_id == M88_VENDOR)
888 				break;
889 		} else {
890 			hw_dbg("PHY address %u was unreadable\n", phy->addr);
891 		}
892 	}
893 
894 	/* A valid PHY type couldn't be found. */
895 	if (phy->addr == 8) {
896 		phy->addr = 0;
897 		ret_val = -E1000_ERR_PHY;
898 		goto out;
899 	} else {
900 		ret_val = igb_get_phy_id(hw);
901 	}
902 
903 	/* restore previous sfp cage power state */
904 	wr32(E1000_CTRL_EXT, ctrl_ext);
905 
906 out:
907 	return ret_val;
908 }
909 
910 /**
911  *  igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
912  *  @hw: pointer to the HW structure
913  *
914  *  Resets the PHY using the serial gigabit media independent interface.
915  **/
916 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
917 {
918 	struct e1000_phy_info *phy = &hw->phy;
919 	s32 ret_val;
920 
921 	/* This isn't a true "hard" reset, but is the only reset
922 	 * available to us at this time.
923 	 */
924 
925 	hw_dbg("Soft resetting SGMII attached PHY...\n");
926 
927 	/* SFP documentation requires the following to configure the SPF module
928 	 * to work on SGMII.  No further documentation is given.
929 	 */
930 	ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
931 	if (ret_val)
932 		goto out;
933 
934 	ret_val = igb_phy_sw_reset(hw);
935 	if (ret_val)
936 		goto out;
937 
938 	if (phy->id == M88E1512_E_PHY_ID)
939 		ret_val = igb_initialize_M88E1512_phy(hw);
940 	if (phy->id == M88E1543_E_PHY_ID)
941 		ret_val = igb_initialize_M88E1543_phy(hw);
942 out:
943 	return ret_val;
944 }
945 
946 /**
947  *  igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
948  *  @hw: pointer to the HW structure
949  *  @active: true to enable LPLU, false to disable
950  *
951  *  Sets the LPLU D0 state according to the active flag.  When
952  *  activating LPLU this function also disables smart speed
953  *  and vice versa.  LPLU will not be activated unless the
954  *  device autonegotiation advertisement meets standards of
955  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
956  *  This is a function pointer entry point only called by
957  *  PHY setup routines.
958  **/
959 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
960 {
961 	struct e1000_phy_info *phy = &hw->phy;
962 	s32 ret_val;
963 	u16 data;
964 
965 	ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
966 	if (ret_val)
967 		goto out;
968 
969 	if (active) {
970 		data |= IGP02E1000_PM_D0_LPLU;
971 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
972 						 data);
973 		if (ret_val)
974 			goto out;
975 
976 		/* When LPLU is enabled, we should disable SmartSpeed */
977 		ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
978 						&data);
979 		data &= ~IGP01E1000_PSCFR_SMART_SPEED;
980 		ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
981 						 data);
982 		if (ret_val)
983 			goto out;
984 	} else {
985 		data &= ~IGP02E1000_PM_D0_LPLU;
986 		ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
987 						 data);
988 		/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
989 		 * during Dx states where the power conservation is most
990 		 * important.  During driver activity we should enable
991 		 * SmartSpeed, so performance is maintained.
992 		 */
993 		if (phy->smart_speed == e1000_smart_speed_on) {
994 			ret_val = phy->ops.read_reg(hw,
995 					IGP01E1000_PHY_PORT_CONFIG, &data);
996 			if (ret_val)
997 				goto out;
998 
999 			data |= IGP01E1000_PSCFR_SMART_SPEED;
1000 			ret_val = phy->ops.write_reg(hw,
1001 					IGP01E1000_PHY_PORT_CONFIG, data);
1002 			if (ret_val)
1003 				goto out;
1004 		} else if (phy->smart_speed == e1000_smart_speed_off) {
1005 			ret_val = phy->ops.read_reg(hw,
1006 					IGP01E1000_PHY_PORT_CONFIG, &data);
1007 			if (ret_val)
1008 				goto out;
1009 
1010 			data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1011 			ret_val = phy->ops.write_reg(hw,
1012 					IGP01E1000_PHY_PORT_CONFIG, data);
1013 			if (ret_val)
1014 				goto out;
1015 		}
1016 	}
1017 
1018 out:
1019 	return ret_val;
1020 }
1021 
1022 /**
1023  *  igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
1024  *  @hw: pointer to the HW structure
1025  *  @active: true to enable LPLU, false to disable
1026  *
1027  *  Sets the LPLU D0 state according to the active flag.  When
1028  *  activating LPLU this function also disables smart speed
1029  *  and vice versa.  LPLU will not be activated unless the
1030  *  device autonegotiation advertisement meets standards of
1031  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1032  *  This is a function pointer entry point only called by
1033  *  PHY setup routines.
1034  **/
1035 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
1036 {
1037 	struct e1000_phy_info *phy = &hw->phy;
1038 	u16 data;
1039 
1040 	data = rd32(E1000_82580_PHY_POWER_MGMT);
1041 
1042 	if (active) {
1043 		data |= E1000_82580_PM_D0_LPLU;
1044 
1045 		/* When LPLU is enabled, we should disable SmartSpeed */
1046 		data &= ~E1000_82580_PM_SPD;
1047 	} else {
1048 		data &= ~E1000_82580_PM_D0_LPLU;
1049 
1050 		/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1051 		 * during Dx states where the power conservation is most
1052 		 * important.  During driver activity we should enable
1053 		 * SmartSpeed, so performance is maintained.
1054 		 */
1055 		if (phy->smart_speed == e1000_smart_speed_on)
1056 			data |= E1000_82580_PM_SPD;
1057 		else if (phy->smart_speed == e1000_smart_speed_off)
1058 			data &= ~E1000_82580_PM_SPD; }
1059 
1060 	wr32(E1000_82580_PHY_POWER_MGMT, data);
1061 	return 0;
1062 }
1063 
1064 /**
1065  *  igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
1066  *  @hw: pointer to the HW structure
1067  *  @active: boolean used to enable/disable lplu
1068  *
1069  *  Success returns 0, Failure returns 1
1070  *
1071  *  The low power link up (lplu) state is set to the power management level D3
1072  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
1073  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
1074  *  is used during Dx states where the power conservation is most important.
1075  *  During driver activity, SmartSpeed should be enabled so performance is
1076  *  maintained.
1077  **/
1078 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
1079 {
1080 	struct e1000_phy_info *phy = &hw->phy;
1081 	u16 data;
1082 
1083 	data = rd32(E1000_82580_PHY_POWER_MGMT);
1084 
1085 	if (!active) {
1086 		data &= ~E1000_82580_PM_D3_LPLU;
1087 		/* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1088 		 * during Dx states where the power conservation is most
1089 		 * important.  During driver activity we should enable
1090 		 * SmartSpeed, so performance is maintained.
1091 		 */
1092 		if (phy->smart_speed == e1000_smart_speed_on)
1093 			data |= E1000_82580_PM_SPD;
1094 		else if (phy->smart_speed == e1000_smart_speed_off)
1095 			data &= ~E1000_82580_PM_SPD;
1096 	} else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1097 		   (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1098 		   (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1099 		data |= E1000_82580_PM_D3_LPLU;
1100 		/* When LPLU is enabled, we should disable SmartSpeed */
1101 		data &= ~E1000_82580_PM_SPD;
1102 	}
1103 
1104 	wr32(E1000_82580_PHY_POWER_MGMT, data);
1105 	return 0;
1106 }
1107 
1108 /**
1109  *  igb_acquire_nvm_82575 - Request for access to EEPROM
1110  *  @hw: pointer to the HW structure
1111  *
1112  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
1113  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
1114  *  Return successful if access grant bit set, else clear the request for
1115  *  EEPROM access and return -E1000_ERR_NVM (-1).
1116  **/
1117 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
1118 {
1119 	s32 ret_val;
1120 
1121 	ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
1122 	if (ret_val)
1123 		goto out;
1124 
1125 	ret_val = igb_acquire_nvm(hw);
1126 
1127 	if (ret_val)
1128 		hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1129 
1130 out:
1131 	return ret_val;
1132 }
1133 
1134 /**
1135  *  igb_release_nvm_82575 - Release exclusive access to EEPROM
1136  *  @hw: pointer to the HW structure
1137  *
1138  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
1139  *  then release the semaphores acquired.
1140  **/
1141 static void igb_release_nvm_82575(struct e1000_hw *hw)
1142 {
1143 	igb_release_nvm(hw);
1144 	hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1145 }
1146 
1147 /**
1148  *  igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1149  *  @hw: pointer to the HW structure
1150  *  @mask: specifies which semaphore to acquire
1151  *
1152  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
1153  *  will also specify which port we're acquiring the lock for.
1154  **/
1155 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1156 {
1157 	u32 swfw_sync;
1158 	u32 swmask = mask;
1159 	u32 fwmask = mask << 16;
1160 	s32 ret_val = 0;
1161 	s32 i = 0, timeout = 200;
1162 
1163 	while (i < timeout) {
1164 		if (igb_get_hw_semaphore(hw)) {
1165 			ret_val = -E1000_ERR_SWFW_SYNC;
1166 			goto out;
1167 		}
1168 
1169 		swfw_sync = rd32(E1000_SW_FW_SYNC);
1170 		if (!(swfw_sync & (fwmask | swmask)))
1171 			break;
1172 
1173 		/* Firmware currently using resource (fwmask)
1174 		 * or other software thread using resource (swmask)
1175 		 */
1176 		igb_put_hw_semaphore(hw);
1177 		mdelay(5);
1178 		i++;
1179 	}
1180 
1181 	if (i == timeout) {
1182 		hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
1183 		ret_val = -E1000_ERR_SWFW_SYNC;
1184 		goto out;
1185 	}
1186 
1187 	swfw_sync |= swmask;
1188 	wr32(E1000_SW_FW_SYNC, swfw_sync);
1189 
1190 	igb_put_hw_semaphore(hw);
1191 
1192 out:
1193 	return ret_val;
1194 }
1195 
1196 /**
1197  *  igb_release_swfw_sync_82575 - Release SW/FW semaphore
1198  *  @hw: pointer to the HW structure
1199  *  @mask: specifies which semaphore to acquire
1200  *
1201  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1202  *  will also specify which port we're releasing the lock for.
1203  **/
1204 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1205 {
1206 	u32 swfw_sync;
1207 
1208 	while (igb_get_hw_semaphore(hw) != 0)
1209 		; /* Empty */
1210 
1211 	swfw_sync = rd32(E1000_SW_FW_SYNC);
1212 	swfw_sync &= ~mask;
1213 	wr32(E1000_SW_FW_SYNC, swfw_sync);
1214 
1215 	igb_put_hw_semaphore(hw);
1216 }
1217 
1218 /**
1219  *  igb_get_cfg_done_82575 - Read config done bit
1220  *  @hw: pointer to the HW structure
1221  *
1222  *  Read the management control register for the config done bit for
1223  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1224  *  to read the config done bit, so an error is *ONLY* logged and returns
1225  *  0.  If we were to return with error, EEPROM-less silicon
1226  *  would not be able to be reset or change link.
1227  **/
1228 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1229 {
1230 	s32 timeout = PHY_CFG_TIMEOUT;
1231 	u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1232 
1233 	if (hw->bus.func == 1)
1234 		mask = E1000_NVM_CFG_DONE_PORT_1;
1235 	else if (hw->bus.func == E1000_FUNC_2)
1236 		mask = E1000_NVM_CFG_DONE_PORT_2;
1237 	else if (hw->bus.func == E1000_FUNC_3)
1238 		mask = E1000_NVM_CFG_DONE_PORT_3;
1239 
1240 	while (timeout) {
1241 		if (rd32(E1000_EEMNGCTL) & mask)
1242 			break;
1243 		usleep_range(1000, 2000);
1244 		timeout--;
1245 	}
1246 	if (!timeout)
1247 		hw_dbg("MNG configuration cycle has not completed.\n");
1248 
1249 	/* If EEPROM is not marked present, init the PHY manually */
1250 	if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1251 	    (hw->phy.type == e1000_phy_igp_3))
1252 		igb_phy_init_script_igp3(hw);
1253 
1254 	return 0;
1255 }
1256 
1257 /**
1258  *  igb_get_link_up_info_82575 - Get link speed/duplex info
1259  *  @hw: pointer to the HW structure
1260  *  @speed: stores the current speed
1261  *  @duplex: stores the current duplex
1262  *
1263  *  This is a wrapper function, if using the serial gigabit media independent
1264  *  interface, use PCS to retrieve the link speed and duplex information.
1265  *  Otherwise, use the generic function to get the link speed and duplex info.
1266  **/
1267 static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1268 					u16 *duplex)
1269 {
1270 	s32 ret_val;
1271 
1272 	if (hw->phy.media_type != e1000_media_type_copper)
1273 		ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed,
1274 							       duplex);
1275 	else
1276 		ret_val = igb_get_speed_and_duplex_copper(hw, speed,
1277 								    duplex);
1278 
1279 	return ret_val;
1280 }
1281 
1282 /**
1283  *  igb_check_for_link_82575 - Check for link
1284  *  @hw: pointer to the HW structure
1285  *
1286  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1287  *  use the generic interface for determining link.
1288  **/
1289 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1290 {
1291 	s32 ret_val;
1292 	u16 speed, duplex;
1293 
1294 	if (hw->phy.media_type != e1000_media_type_copper) {
1295 		ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
1296 							     &duplex);
1297 		/* Use this flag to determine if link needs to be checked or
1298 		 * not.  If  we have link clear the flag so that we do not
1299 		 * continue to check for link.
1300 		 */
1301 		hw->mac.get_link_status = !hw->mac.serdes_has_link;
1302 
1303 		/* Configure Flow Control now that Auto-Neg has completed.
1304 		 * First, we need to restore the desired flow control
1305 		 * settings because we may have had to re-autoneg with a
1306 		 * different link partner.
1307 		 */
1308 		ret_val = igb_config_fc_after_link_up(hw);
1309 		if (ret_val)
1310 			hw_dbg("Error configuring flow control\n");
1311 	} else {
1312 		ret_val = igb_check_for_copper_link(hw);
1313 	}
1314 
1315 	return ret_val;
1316 }
1317 
1318 /**
1319  *  igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1320  *  @hw: pointer to the HW structure
1321  **/
1322 void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1323 {
1324 	u32 reg;
1325 
1326 
1327 	if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1328 	    !igb_sgmii_active_82575(hw))
1329 		return;
1330 
1331 	/* Enable PCS to turn on link */
1332 	reg = rd32(E1000_PCS_CFG0);
1333 	reg |= E1000_PCS_CFG_PCS_EN;
1334 	wr32(E1000_PCS_CFG0, reg);
1335 
1336 	/* Power up the laser */
1337 	reg = rd32(E1000_CTRL_EXT);
1338 	reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1339 	wr32(E1000_CTRL_EXT, reg);
1340 
1341 	/* flush the write to verify completion */
1342 	wrfl();
1343 	usleep_range(1000, 2000);
1344 }
1345 
1346 /**
1347  *  igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1348  *  @hw: pointer to the HW structure
1349  *  @speed: stores the current speed
1350  *  @duplex: stores the current duplex
1351  *
1352  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1353  *  duplex, then store the values in the pointers provided.
1354  **/
1355 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1356 						u16 *duplex)
1357 {
1358 	struct e1000_mac_info *mac = &hw->mac;
1359 	u32 pcs, status;
1360 
1361 	/* Set up defaults for the return values of this function */
1362 	mac->serdes_has_link = false;
1363 	*speed = 0;
1364 	*duplex = 0;
1365 
1366 	/* Read the PCS Status register for link state. For non-copper mode,
1367 	 * the status register is not accurate. The PCS status register is
1368 	 * used instead.
1369 	 */
1370 	pcs = rd32(E1000_PCS_LSTAT);
1371 
1372 	/* The link up bit determines when link is up on autoneg. The sync ok
1373 	 * gets set once both sides sync up and agree upon link. Stable link
1374 	 * can be determined by checking for both link up and link sync ok
1375 	 */
1376 	if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1377 		mac->serdes_has_link = true;
1378 
1379 		/* Detect and store PCS speed */
1380 		if (pcs & E1000_PCS_LSTS_SPEED_1000)
1381 			*speed = SPEED_1000;
1382 		else if (pcs & E1000_PCS_LSTS_SPEED_100)
1383 			*speed = SPEED_100;
1384 		else
1385 			*speed = SPEED_10;
1386 
1387 		/* Detect and store PCS duplex */
1388 		if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1389 			*duplex = FULL_DUPLEX;
1390 		else
1391 			*duplex = HALF_DUPLEX;
1392 
1393 	/* Check if it is an I354 2.5Gb backplane connection. */
1394 		if (mac->type == e1000_i354) {
1395 			status = rd32(E1000_STATUS);
1396 			if ((status & E1000_STATUS_2P5_SKU) &&
1397 			    !(status & E1000_STATUS_2P5_SKU_OVER)) {
1398 				*speed = SPEED_2500;
1399 				*duplex = FULL_DUPLEX;
1400 				hw_dbg("2500 Mbs, ");
1401 				hw_dbg("Full Duplex\n");
1402 			}
1403 		}
1404 
1405 	}
1406 
1407 	return 0;
1408 }
1409 
1410 /**
1411  *  igb_shutdown_serdes_link_82575 - Remove link during power down
1412  *  @hw: pointer to the HW structure
1413  *
1414  *  In the case of fiber serdes, shut down optics and PCS on driver unload
1415  *  when management pass thru is not enabled.
1416  **/
1417 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
1418 {
1419 	u32 reg;
1420 
1421 	if (hw->phy.media_type != e1000_media_type_internal_serdes &&
1422 	    igb_sgmii_active_82575(hw))
1423 		return;
1424 
1425 	if (!igb_enable_mng_pass_thru(hw)) {
1426 		/* Disable PCS to turn off link */
1427 		reg = rd32(E1000_PCS_CFG0);
1428 		reg &= ~E1000_PCS_CFG_PCS_EN;
1429 		wr32(E1000_PCS_CFG0, reg);
1430 
1431 		/* shutdown the laser */
1432 		reg = rd32(E1000_CTRL_EXT);
1433 		reg |= E1000_CTRL_EXT_SDP3_DATA;
1434 		wr32(E1000_CTRL_EXT, reg);
1435 
1436 		/* flush the write to verify completion */
1437 		wrfl();
1438 		usleep_range(1000, 2000);
1439 	}
1440 }
1441 
1442 /**
1443  *  igb_reset_hw_82575 - Reset hardware
1444  *  @hw: pointer to the HW structure
1445  *
1446  *  This resets the hardware into a known state.  This is a
1447  *  function pointer entry point called by the api module.
1448  **/
1449 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1450 {
1451 	u32 ctrl;
1452 	s32 ret_val;
1453 
1454 	/* Prevent the PCI-E bus from sticking if there is no TLP connection
1455 	 * on the last TLP read/write transaction when MAC is reset.
1456 	 */
1457 	ret_val = igb_disable_pcie_master(hw);
1458 	if (ret_val)
1459 		hw_dbg("PCI-E Master disable polling has failed.\n");
1460 
1461 	/* set the completion timeout for interface */
1462 	ret_val = igb_set_pcie_completion_timeout(hw);
1463 	if (ret_val)
1464 		hw_dbg("PCI-E Set completion timeout has failed.\n");
1465 
1466 	hw_dbg("Masking off all interrupts\n");
1467 	wr32(E1000_IMC, 0xffffffff);
1468 
1469 	wr32(E1000_RCTL, 0);
1470 	wr32(E1000_TCTL, E1000_TCTL_PSP);
1471 	wrfl();
1472 
1473 	usleep_range(10000, 20000);
1474 
1475 	ctrl = rd32(E1000_CTRL);
1476 
1477 	hw_dbg("Issuing a global reset to MAC\n");
1478 	wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1479 
1480 	ret_val = igb_get_auto_rd_done(hw);
1481 	if (ret_val) {
1482 		/* When auto config read does not complete, do not
1483 		 * return with an error. This can happen in situations
1484 		 * where there is no eeprom and prevents getting link.
1485 		 */
1486 		hw_dbg("Auto Read Done did not complete\n");
1487 	}
1488 
1489 	/* If EEPROM is not present, run manual init scripts */
1490 	if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1491 		igb_reset_init_script_82575(hw);
1492 
1493 	/* Clear any pending interrupt events. */
1494 	wr32(E1000_IMC, 0xffffffff);
1495 	rd32(E1000_ICR);
1496 
1497 	/* Install any alternate MAC address into RAR0 */
1498 	ret_val = igb_check_alt_mac_addr(hw);
1499 
1500 	return ret_val;
1501 }
1502 
1503 /**
1504  *  igb_init_hw_82575 - Initialize hardware
1505  *  @hw: pointer to the HW structure
1506  *
1507  *  This inits the hardware readying it for operation.
1508  **/
1509 static s32 igb_init_hw_82575(struct e1000_hw *hw)
1510 {
1511 	struct e1000_mac_info *mac = &hw->mac;
1512 	s32 ret_val;
1513 	u16 i, rar_count = mac->rar_entry_count;
1514 
1515 	if ((hw->mac.type >= e1000_i210) &&
1516 	    !(igb_get_flash_presence_i210(hw))) {
1517 		ret_val = igb_pll_workaround_i210(hw);
1518 		if (ret_val)
1519 			return ret_val;
1520 	}
1521 
1522 	/* Initialize identification LED */
1523 	ret_val = igb_id_led_init(hw);
1524 	if (ret_val) {
1525 		hw_dbg("Error initializing identification LED\n");
1526 		/* This is not fatal and we should not stop init due to this */
1527 	}
1528 
1529 	/* Disabling VLAN filtering */
1530 	hw_dbg("Initializing the IEEE VLAN\n");
1531 	igb_clear_vfta(hw);
1532 
1533 	/* Setup the receive address */
1534 	igb_init_rx_addrs(hw, rar_count);
1535 
1536 	/* Zero out the Multicast HASH table */
1537 	hw_dbg("Zeroing the MTA\n");
1538 	for (i = 0; i < mac->mta_reg_count; i++)
1539 		array_wr32(E1000_MTA, i, 0);
1540 
1541 	/* Zero out the Unicast HASH table */
1542 	hw_dbg("Zeroing the UTA\n");
1543 	for (i = 0; i < mac->uta_reg_count; i++)
1544 		array_wr32(E1000_UTA, i, 0);
1545 
1546 	/* Setup link and flow control */
1547 	ret_val = igb_setup_link(hw);
1548 
1549 	/* Clear all of the statistics registers (clear on read).  It is
1550 	 * important that we do this after we have tried to establish link
1551 	 * because the symbol error count will increment wildly if there
1552 	 * is no link.
1553 	 */
1554 	igb_clear_hw_cntrs_82575(hw);
1555 	return ret_val;
1556 }
1557 
1558 /**
1559  *  igb_setup_copper_link_82575 - Configure copper link settings
1560  *  @hw: pointer to the HW structure
1561  *
1562  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1563  *  for link, once link is established calls to configure collision distance
1564  *  and flow control are called.
1565  **/
1566 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1567 {
1568 	u32 ctrl;
1569 	s32  ret_val;
1570 	u32 phpm_reg;
1571 
1572 	ctrl = rd32(E1000_CTRL);
1573 	ctrl |= E1000_CTRL_SLU;
1574 	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1575 	wr32(E1000_CTRL, ctrl);
1576 
1577 	/* Clear Go Link Disconnect bit on supported devices */
1578 	switch (hw->mac.type) {
1579 	case e1000_82580:
1580 	case e1000_i350:
1581 	case e1000_i210:
1582 	case e1000_i211:
1583 		phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1584 		phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1585 		wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1586 		break;
1587 	default:
1588 		break;
1589 	}
1590 
1591 	ret_val = igb_setup_serdes_link_82575(hw);
1592 	if (ret_val)
1593 		goto out;
1594 
1595 	if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1596 		/* allow time for SFP cage time to power up phy */
1597 		msleep(300);
1598 
1599 		ret_val = hw->phy.ops.reset(hw);
1600 		if (ret_val) {
1601 			hw_dbg("Error resetting the PHY.\n");
1602 			goto out;
1603 		}
1604 	}
1605 	switch (hw->phy.type) {
1606 	case e1000_phy_i210:
1607 	case e1000_phy_m88:
1608 		switch (hw->phy.id) {
1609 		case I347AT4_E_PHY_ID:
1610 		case M88E1112_E_PHY_ID:
1611 		case M88E1543_E_PHY_ID:
1612 		case M88E1512_E_PHY_ID:
1613 		case I210_I_PHY_ID:
1614 			ret_val = igb_copper_link_setup_m88_gen2(hw);
1615 			break;
1616 		default:
1617 			ret_val = igb_copper_link_setup_m88(hw);
1618 			break;
1619 		}
1620 		break;
1621 	case e1000_phy_igp_3:
1622 		ret_val = igb_copper_link_setup_igp(hw);
1623 		break;
1624 	case e1000_phy_82580:
1625 		ret_val = igb_copper_link_setup_82580(hw);
1626 		break;
1627 	case e1000_phy_bcm54616:
1628 		ret_val = 0;
1629 		break;
1630 	default:
1631 		ret_val = -E1000_ERR_PHY;
1632 		break;
1633 	}
1634 
1635 	if (ret_val)
1636 		goto out;
1637 
1638 	ret_val = igb_setup_copper_link(hw);
1639 out:
1640 	return ret_val;
1641 }
1642 
1643 /**
1644  *  igb_setup_serdes_link_82575 - Setup link for serdes
1645  *  @hw: pointer to the HW structure
1646  *
1647  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1648  *  used on copper connections where the serialized gigabit media independent
1649  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1650  *  for auto-negotiation or forces speed/duplex.
1651  **/
1652 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1653 {
1654 	u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1655 	bool pcs_autoneg;
1656 	s32 ret_val = 0;
1657 	u16 data;
1658 
1659 	if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1660 	    !igb_sgmii_active_82575(hw))
1661 		return ret_val;
1662 
1663 
1664 	/* On the 82575, SerDes loopback mode persists until it is
1665 	 * explicitly turned off or a power cycle is performed.  A read to
1666 	 * the register does not indicate its status.  Therefore, we ensure
1667 	 * loopback mode is disabled during initialization.
1668 	 */
1669 	wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1670 
1671 	/* power on the sfp cage if present and turn on I2C */
1672 	ctrl_ext = rd32(E1000_CTRL_EXT);
1673 	ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1674 	ctrl_ext |= E1000_CTRL_I2C_ENA;
1675 	wr32(E1000_CTRL_EXT, ctrl_ext);
1676 
1677 	ctrl_reg = rd32(E1000_CTRL);
1678 	ctrl_reg |= E1000_CTRL_SLU;
1679 
1680 	if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1681 		/* set both sw defined pins */
1682 		ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1683 
1684 		/* Set switch control to serdes energy detect */
1685 		reg = rd32(E1000_CONNSW);
1686 		reg |= E1000_CONNSW_ENRGSRC;
1687 		wr32(E1000_CONNSW, reg);
1688 	}
1689 
1690 	reg = rd32(E1000_PCS_LCTL);
1691 
1692 	/* default pcs_autoneg to the same setting as mac autoneg */
1693 	pcs_autoneg = hw->mac.autoneg;
1694 
1695 	switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1696 	case E1000_CTRL_EXT_LINK_MODE_SGMII:
1697 		/* sgmii mode lets the phy handle forcing speed/duplex */
1698 		pcs_autoneg = true;
1699 		/* autoneg time out should be disabled for SGMII mode */
1700 		reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1701 		break;
1702 	case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1703 		/* disable PCS autoneg and support parallel detect only */
1704 		pcs_autoneg = false;
1705 		fallthrough;
1706 	default:
1707 		if (hw->mac.type == e1000_82575 ||
1708 		    hw->mac.type == e1000_82576) {
1709 			ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1710 			if (ret_val) {
1711 				hw_dbg(KERN_DEBUG "NVM Read Error\n\n");
1712 				return ret_val;
1713 			}
1714 
1715 			if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1716 				pcs_autoneg = false;
1717 		}
1718 
1719 		/* non-SGMII modes only supports a speed of 1000/Full for the
1720 		 * link so it is best to just force the MAC and let the pcs
1721 		 * link either autoneg or be forced to 1000/Full
1722 		 */
1723 		ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1724 				E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1725 
1726 		/* set speed of 1000/Full if speed/duplex is forced */
1727 		reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1728 		break;
1729 	}
1730 
1731 	wr32(E1000_CTRL, ctrl_reg);
1732 
1733 	/* New SerDes mode allows for forcing speed or autonegotiating speed
1734 	 * at 1gb. Autoneg should be default set by most drivers. This is the
1735 	 * mode that will be compatible with older link partners and switches.
1736 	 * However, both are supported by the hardware and some drivers/tools.
1737 	 */
1738 	reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1739 		E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1740 
1741 	if (pcs_autoneg) {
1742 		/* Set PCS register for autoneg */
1743 		reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1744 		       E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1745 
1746 		/* Disable force flow control for autoneg */
1747 		reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1748 
1749 		/* Configure flow control advertisement for autoneg */
1750 		anadv_reg = rd32(E1000_PCS_ANADV);
1751 		anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1752 		switch (hw->fc.requested_mode) {
1753 		case e1000_fc_full:
1754 		case e1000_fc_rx_pause:
1755 			anadv_reg |= E1000_TXCW_ASM_DIR;
1756 			anadv_reg |= E1000_TXCW_PAUSE;
1757 			break;
1758 		case e1000_fc_tx_pause:
1759 			anadv_reg |= E1000_TXCW_ASM_DIR;
1760 			break;
1761 		default:
1762 			break;
1763 		}
1764 		wr32(E1000_PCS_ANADV, anadv_reg);
1765 
1766 		hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1767 	} else {
1768 		/* Set PCS register for forced link */
1769 		reg |= E1000_PCS_LCTL_FSD;        /* Force Speed */
1770 
1771 		/* Force flow control for forced link */
1772 		reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1773 
1774 		hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1775 	}
1776 
1777 	wr32(E1000_PCS_LCTL, reg);
1778 
1779 	if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
1780 		igb_force_mac_fc(hw);
1781 
1782 	return ret_val;
1783 }
1784 
1785 /**
1786  *  igb_sgmii_active_82575 - Return sgmii state
1787  *  @hw: pointer to the HW structure
1788  *
1789  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1790  *  which can be enabled for use in the embedded applications.  Simply
1791  *  return the current state of the sgmii interface.
1792  **/
1793 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1794 {
1795 	struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1796 	return dev_spec->sgmii_active;
1797 }
1798 
1799 /**
1800  *  igb_reset_init_script_82575 - Inits HW defaults after reset
1801  *  @hw: pointer to the HW structure
1802  *
1803  *  Inits recommended HW defaults after a reset when there is no EEPROM
1804  *  detected. This is only for the 82575.
1805  **/
1806 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1807 {
1808 	if (hw->mac.type == e1000_82575) {
1809 		hw_dbg("Running reset init script for 82575\n");
1810 		/* SerDes configuration via SERDESCTRL */
1811 		igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1812 		igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1813 		igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1814 		igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1815 
1816 		/* CCM configuration via CCMCTL register */
1817 		igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1818 		igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1819 
1820 		/* PCIe lanes configuration */
1821 		igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1822 		igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1823 		igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1824 		igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1825 
1826 		/* PCIe PLL Configuration */
1827 		igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1828 		igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1829 		igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1830 	}
1831 
1832 	return 0;
1833 }
1834 
1835 /**
1836  *  igb_read_mac_addr_82575 - Read device MAC address
1837  *  @hw: pointer to the HW structure
1838  **/
1839 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1840 {
1841 	s32 ret_val = 0;
1842 
1843 	/* If there's an alternate MAC address place it in RAR0
1844 	 * so that it will override the Si installed default perm
1845 	 * address.
1846 	 */
1847 	ret_val = igb_check_alt_mac_addr(hw);
1848 	if (ret_val)
1849 		goto out;
1850 
1851 	ret_val = igb_read_mac_addr(hw);
1852 
1853 out:
1854 	return ret_val;
1855 }
1856 
1857 /**
1858  * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1859  * @hw: pointer to the HW structure
1860  *
1861  * In the case of a PHY power down to save power, or to turn off link during a
1862  * driver unload, or wake on lan is not enabled, remove the link.
1863  **/
1864 void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1865 {
1866 	/* If the management interface is not enabled, then power down */
1867 	if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1868 		igb_power_down_phy_copper(hw);
1869 }
1870 
1871 /**
1872  *  igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1873  *  @hw: pointer to the HW structure
1874  *
1875  *  Clears the hardware counters by reading the counter registers.
1876  **/
1877 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1878 {
1879 	igb_clear_hw_cntrs_base(hw);
1880 
1881 	rd32(E1000_PRC64);
1882 	rd32(E1000_PRC127);
1883 	rd32(E1000_PRC255);
1884 	rd32(E1000_PRC511);
1885 	rd32(E1000_PRC1023);
1886 	rd32(E1000_PRC1522);
1887 	rd32(E1000_PTC64);
1888 	rd32(E1000_PTC127);
1889 	rd32(E1000_PTC255);
1890 	rd32(E1000_PTC511);
1891 	rd32(E1000_PTC1023);
1892 	rd32(E1000_PTC1522);
1893 
1894 	rd32(E1000_ALGNERRC);
1895 	rd32(E1000_RXERRC);
1896 	rd32(E1000_TNCRS);
1897 	rd32(E1000_CEXTERR);
1898 	rd32(E1000_TSCTC);
1899 	rd32(E1000_TSCTFC);
1900 
1901 	rd32(E1000_MGTPRC);
1902 	rd32(E1000_MGTPDC);
1903 	rd32(E1000_MGTPTC);
1904 
1905 	rd32(E1000_IAC);
1906 	rd32(E1000_ICRXOC);
1907 
1908 	rd32(E1000_ICRXPTC);
1909 	rd32(E1000_ICRXATC);
1910 	rd32(E1000_ICTXPTC);
1911 	rd32(E1000_ICTXATC);
1912 	rd32(E1000_ICTXQEC);
1913 	rd32(E1000_ICTXQMTC);
1914 	rd32(E1000_ICRXDMTC);
1915 
1916 	rd32(E1000_CBTMPC);
1917 	rd32(E1000_HTDPMC);
1918 	rd32(E1000_CBRMPC);
1919 	rd32(E1000_RPTHC);
1920 	rd32(E1000_HGPTC);
1921 	rd32(E1000_HTCBDPC);
1922 	rd32(E1000_HGORCL);
1923 	rd32(E1000_HGORCH);
1924 	rd32(E1000_HGOTCL);
1925 	rd32(E1000_HGOTCH);
1926 	rd32(E1000_LENERRS);
1927 
1928 	/* This register should not be read in copper configurations */
1929 	if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1930 	    igb_sgmii_active_82575(hw))
1931 		rd32(E1000_SCVPC);
1932 }
1933 
1934 /**
1935  *  igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1936  *  @hw: pointer to the HW structure
1937  *
1938  *  After rx enable if manageability is enabled then there is likely some
1939  *  bad data at the start of the fifo and possibly in the DMA fifo. This
1940  *  function clears the fifos and flushes any packets that came in as rx was
1941  *  being enabled.
1942  **/
1943 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1944 {
1945 	u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1946 	int i, ms_wait;
1947 
1948 	/* disable IPv6 options as per hardware errata */
1949 	rfctl = rd32(E1000_RFCTL);
1950 	rfctl |= E1000_RFCTL_IPV6_EX_DIS;
1951 	wr32(E1000_RFCTL, rfctl);
1952 
1953 	if (hw->mac.type != e1000_82575 ||
1954 	    !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1955 		return;
1956 
1957 	/* Disable all RX queues */
1958 	for (i = 0; i < 4; i++) {
1959 		rxdctl[i] = rd32(E1000_RXDCTL(i));
1960 		wr32(E1000_RXDCTL(i),
1961 		     rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1962 	}
1963 	/* Poll all queues to verify they have shut down */
1964 	for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1965 		usleep_range(1000, 2000);
1966 		rx_enabled = 0;
1967 		for (i = 0; i < 4; i++)
1968 			rx_enabled |= rd32(E1000_RXDCTL(i));
1969 		if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1970 			break;
1971 	}
1972 
1973 	if (ms_wait == 10)
1974 		hw_dbg("Queue disable timed out after 10ms\n");
1975 
1976 	/* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1977 	 * incoming packets are rejected.  Set enable and wait 2ms so that
1978 	 * any packet that was coming in as RCTL.EN was set is flushed
1979 	 */
1980 	wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1981 
1982 	rlpml = rd32(E1000_RLPML);
1983 	wr32(E1000_RLPML, 0);
1984 
1985 	rctl = rd32(E1000_RCTL);
1986 	temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1987 	temp_rctl |= E1000_RCTL_LPE;
1988 
1989 	wr32(E1000_RCTL, temp_rctl);
1990 	wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1991 	wrfl();
1992 	usleep_range(2000, 3000);
1993 
1994 	/* Enable RX queues that were previously enabled and restore our
1995 	 * previous state
1996 	 */
1997 	for (i = 0; i < 4; i++)
1998 		wr32(E1000_RXDCTL(i), rxdctl[i]);
1999 	wr32(E1000_RCTL, rctl);
2000 	wrfl();
2001 
2002 	wr32(E1000_RLPML, rlpml);
2003 	wr32(E1000_RFCTL, rfctl);
2004 
2005 	/* Flush receive errors generated by workaround */
2006 	rd32(E1000_ROC);
2007 	rd32(E1000_RNBC);
2008 	rd32(E1000_MPC);
2009 }
2010 
2011 /**
2012  *  igb_set_pcie_completion_timeout - set pci-e completion timeout
2013  *  @hw: pointer to the HW structure
2014  *
2015  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2016  *  however the hardware default for these parts is 500us to 1ms which is less
2017  *  than the 10ms recommended by the pci-e spec.  To address this we need to
2018  *  increase the value to either 10ms to 200ms for capability version 1 config,
2019  *  or 16ms to 55ms for version 2.
2020  **/
2021 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
2022 {
2023 	u32 gcr = rd32(E1000_GCR);
2024 	s32 ret_val = 0;
2025 	u16 pcie_devctl2;
2026 
2027 	/* only take action if timeout value is defaulted to 0 */
2028 	if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2029 		goto out;
2030 
2031 	/* if capabilities version is type 1 we can write the
2032 	 * timeout of 10ms to 200ms through the GCR register
2033 	 */
2034 	if (!(gcr & E1000_GCR_CAP_VER2)) {
2035 		gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2036 		goto out;
2037 	}
2038 
2039 	/* for version 2 capabilities we need to write the config space
2040 	 * directly in order to set the completion timeout value for
2041 	 * 16ms to 55ms
2042 	 */
2043 	ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2044 					&pcie_devctl2);
2045 	if (ret_val)
2046 		goto out;
2047 
2048 	pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2049 
2050 	ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2051 					 &pcie_devctl2);
2052 out:
2053 	/* disable completion timeout resend */
2054 	gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2055 
2056 	wr32(E1000_GCR, gcr);
2057 	return ret_val;
2058 }
2059 
2060 /**
2061  *  igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2062  *  @hw: pointer to the hardware struct
2063  *  @enable: state to enter, either enabled or disabled
2064  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
2065  *
2066  *  enables/disables L2 switch anti-spoofing functionality.
2067  **/
2068 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2069 {
2070 	u32 reg_val, reg_offset;
2071 
2072 	switch (hw->mac.type) {
2073 	case e1000_82576:
2074 		reg_offset = E1000_DTXSWC;
2075 		break;
2076 	case e1000_i350:
2077 	case e1000_i354:
2078 		reg_offset = E1000_TXSWC;
2079 		break;
2080 	default:
2081 		return;
2082 	}
2083 
2084 	reg_val = rd32(reg_offset);
2085 	if (enable) {
2086 		reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2087 			     E1000_DTXSWC_VLAN_SPOOF_MASK);
2088 		/* The PF can spoof - it has to in order to
2089 		 * support emulation mode NICs
2090 		 */
2091 		reg_val ^= (BIT(pf) | BIT(pf + MAX_NUM_VFS));
2092 	} else {
2093 		reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2094 			     E1000_DTXSWC_VLAN_SPOOF_MASK);
2095 	}
2096 	wr32(reg_offset, reg_val);
2097 }
2098 
2099 /**
2100  *  igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
2101  *  @hw: pointer to the hardware struct
2102  *  @enable: state to enter, either enabled or disabled
2103  *
2104  *  enables/disables L2 switch loopback functionality.
2105  **/
2106 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2107 {
2108 	u32 dtxswc;
2109 
2110 	switch (hw->mac.type) {
2111 	case e1000_82576:
2112 		dtxswc = rd32(E1000_DTXSWC);
2113 		if (enable)
2114 			dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2115 		else
2116 			dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2117 		wr32(E1000_DTXSWC, dtxswc);
2118 		break;
2119 	case e1000_i354:
2120 	case e1000_i350:
2121 		dtxswc = rd32(E1000_TXSWC);
2122 		if (enable)
2123 			dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2124 		else
2125 			dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2126 		wr32(E1000_TXSWC, dtxswc);
2127 		break;
2128 	default:
2129 		/* Currently no other hardware supports loopback */
2130 		break;
2131 	}
2132 
2133 }
2134 
2135 /**
2136  *  igb_vmdq_set_replication_pf - enable or disable vmdq replication
2137  *  @hw: pointer to the hardware struct
2138  *  @enable: state to enter, either enabled or disabled
2139  *
2140  *  enables/disables replication of packets across multiple pools.
2141  **/
2142 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2143 {
2144 	u32 vt_ctl = rd32(E1000_VT_CTL);
2145 
2146 	if (enable)
2147 		vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2148 	else
2149 		vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2150 
2151 	wr32(E1000_VT_CTL, vt_ctl);
2152 }
2153 
2154 /**
2155  *  igb_read_phy_reg_82580 - Read 82580 MDI control register
2156  *  @hw: pointer to the HW structure
2157  *  @offset: register offset to be read
2158  *  @data: pointer to the read data
2159  *
2160  *  Reads the MDI control register in the PHY at offset and stores the
2161  *  information read to data.
2162  **/
2163 s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2164 {
2165 	s32 ret_val;
2166 
2167 	ret_val = hw->phy.ops.acquire(hw);
2168 	if (ret_val)
2169 		goto out;
2170 
2171 	ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2172 
2173 	hw->phy.ops.release(hw);
2174 
2175 out:
2176 	return ret_val;
2177 }
2178 
2179 /**
2180  *  igb_write_phy_reg_82580 - Write 82580 MDI control register
2181  *  @hw: pointer to the HW structure
2182  *  @offset: register offset to write to
2183  *  @data: data to write to register at offset
2184  *
2185  *  Writes data to MDI control register in the PHY at offset.
2186  **/
2187 s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2188 {
2189 	s32 ret_val;
2190 
2191 
2192 	ret_val = hw->phy.ops.acquire(hw);
2193 	if (ret_val)
2194 		goto out;
2195 
2196 	ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2197 
2198 	hw->phy.ops.release(hw);
2199 
2200 out:
2201 	return ret_val;
2202 }
2203 
2204 /**
2205  *  igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2206  *  @hw: pointer to the HW structure
2207  *
2208  *  This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2209  *  the values found in the EEPROM.  This addresses an issue in which these
2210  *  bits are not restored from EEPROM after reset.
2211  **/
2212 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
2213 {
2214 	s32 ret_val = 0;
2215 	u32 mdicnfg;
2216 	u16 nvm_data = 0;
2217 
2218 	if (hw->mac.type != e1000_82580)
2219 		goto out;
2220 	if (!igb_sgmii_active_82575(hw))
2221 		goto out;
2222 
2223 	ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2224 				   NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2225 				   &nvm_data);
2226 	if (ret_val) {
2227 		hw_dbg("NVM Read Error\n");
2228 		goto out;
2229 	}
2230 
2231 	mdicnfg = rd32(E1000_MDICNFG);
2232 	if (nvm_data & NVM_WORD24_EXT_MDIO)
2233 		mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2234 	if (nvm_data & NVM_WORD24_COM_MDIO)
2235 		mdicnfg |= E1000_MDICNFG_COM_MDIO;
2236 	wr32(E1000_MDICNFG, mdicnfg);
2237 out:
2238 	return ret_val;
2239 }
2240 
2241 /**
2242  *  igb_reset_hw_82580 - Reset hardware
2243  *  @hw: pointer to the HW structure
2244  *
2245  *  This resets function or entire device (all ports, etc.)
2246  *  to a known state.
2247  **/
2248 static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2249 {
2250 	s32 ret_val = 0;
2251 	/* BH SW mailbox bit in SW_FW_SYNC */
2252 	u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2253 	u32 ctrl;
2254 	bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2255 
2256 	hw->dev_spec._82575.global_device_reset = false;
2257 
2258 	/* due to hw errata, global device reset doesn't always
2259 	 * work on 82580
2260 	 */
2261 	if (hw->mac.type == e1000_82580)
2262 		global_device_reset = false;
2263 
2264 	/* Get current control state. */
2265 	ctrl = rd32(E1000_CTRL);
2266 
2267 	/* Prevent the PCI-E bus from sticking if there is no TLP connection
2268 	 * on the last TLP read/write transaction when MAC is reset.
2269 	 */
2270 	ret_val = igb_disable_pcie_master(hw);
2271 	if (ret_val)
2272 		hw_dbg("PCI-E Master disable polling has failed.\n");
2273 
2274 	hw_dbg("Masking off all interrupts\n");
2275 	wr32(E1000_IMC, 0xffffffff);
2276 	wr32(E1000_RCTL, 0);
2277 	wr32(E1000_TCTL, E1000_TCTL_PSP);
2278 	wrfl();
2279 
2280 	usleep_range(10000, 11000);
2281 
2282 	/* Determine whether or not a global dev reset is requested */
2283 	if (global_device_reset &&
2284 		hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
2285 			global_device_reset = false;
2286 
2287 	if (global_device_reset &&
2288 		!(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2289 		ctrl |= E1000_CTRL_DEV_RST;
2290 	else
2291 		ctrl |= E1000_CTRL_RST;
2292 
2293 	wr32(E1000_CTRL, ctrl);
2294 	wrfl();
2295 
2296 	/* Add delay to insure DEV_RST has time to complete */
2297 	if (global_device_reset)
2298 		usleep_range(5000, 6000);
2299 
2300 	ret_val = igb_get_auto_rd_done(hw);
2301 	if (ret_val) {
2302 		/* When auto config read does not complete, do not
2303 		 * return with an error. This can happen in situations
2304 		 * where there is no eeprom and prevents getting link.
2305 		 */
2306 		hw_dbg("Auto Read Done did not complete\n");
2307 	}
2308 
2309 	/* clear global device reset status bit */
2310 	wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2311 
2312 	/* Clear any pending interrupt events. */
2313 	wr32(E1000_IMC, 0xffffffff);
2314 	rd32(E1000_ICR);
2315 
2316 	ret_val = igb_reset_mdicnfg_82580(hw);
2317 	if (ret_val)
2318 		hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2319 
2320 	/* Install any alternate MAC address into RAR0 */
2321 	ret_val = igb_check_alt_mac_addr(hw);
2322 
2323 	/* Release semaphore */
2324 	if (global_device_reset)
2325 		hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2326 
2327 	return ret_val;
2328 }
2329 
2330 /**
2331  *  igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2332  *  @data: data received by reading RXPBS register
2333  *
2334  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2335  *  This function converts the retrieved value into the correct table value
2336  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2337  *  0x0 36  72 144   1   2   4   8  16
2338  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2339  */
2340 u16 igb_rxpbs_adjust_82580(u32 data)
2341 {
2342 	u16 ret_val = 0;
2343 
2344 	if (data < ARRAY_SIZE(e1000_82580_rxpbs_table))
2345 		ret_val = e1000_82580_rxpbs_table[data];
2346 
2347 	return ret_val;
2348 }
2349 
2350 /**
2351  *  igb_validate_nvm_checksum_with_offset - Validate EEPROM
2352  *  checksum
2353  *  @hw: pointer to the HW structure
2354  *  @offset: offset in words of the checksum protected region
2355  *
2356  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2357  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2358  **/
2359 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2360 						 u16 offset)
2361 {
2362 	s32 ret_val = 0;
2363 	u16 checksum = 0;
2364 	u16 i, nvm_data;
2365 
2366 	for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2367 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2368 		if (ret_val) {
2369 			hw_dbg("NVM Read Error\n");
2370 			goto out;
2371 		}
2372 		checksum += nvm_data;
2373 	}
2374 
2375 	if (checksum != (u16) NVM_SUM) {
2376 		hw_dbg("NVM Checksum Invalid\n");
2377 		ret_val = -E1000_ERR_NVM;
2378 		goto out;
2379 	}
2380 
2381 out:
2382 	return ret_val;
2383 }
2384 
2385 /**
2386  *  igb_update_nvm_checksum_with_offset - Update EEPROM
2387  *  checksum
2388  *  @hw: pointer to the HW structure
2389  *  @offset: offset in words of the checksum protected region
2390  *
2391  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2392  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2393  *  value to the EEPROM.
2394  **/
2395 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2396 {
2397 	s32 ret_val;
2398 	u16 checksum = 0;
2399 	u16 i, nvm_data;
2400 
2401 	for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2402 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2403 		if (ret_val) {
2404 			hw_dbg("NVM Read Error while updating checksum.\n");
2405 			goto out;
2406 		}
2407 		checksum += nvm_data;
2408 	}
2409 	checksum = (u16) NVM_SUM - checksum;
2410 	ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2411 				&checksum);
2412 	if (ret_val)
2413 		hw_dbg("NVM Write Error while updating checksum.\n");
2414 
2415 out:
2416 	return ret_val;
2417 }
2418 
2419 /**
2420  *  igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2421  *  @hw: pointer to the HW structure
2422  *
2423  *  Calculates the EEPROM section checksum by reading/adding each word of
2424  *  the EEPROM and then verifies that the sum of the EEPROM is
2425  *  equal to 0xBABA.
2426  **/
2427 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2428 {
2429 	s32 ret_val = 0;
2430 	u16 eeprom_regions_count = 1;
2431 	u16 j, nvm_data;
2432 	u16 nvm_offset;
2433 
2434 	ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2435 	if (ret_val) {
2436 		hw_dbg("NVM Read Error\n");
2437 		goto out;
2438 	}
2439 
2440 	if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2441 		/* if checksums compatibility bit is set validate checksums
2442 		 * for all 4 ports.
2443 		 */
2444 		eeprom_regions_count = 4;
2445 	}
2446 
2447 	for (j = 0; j < eeprom_regions_count; j++) {
2448 		nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2449 		ret_val = igb_validate_nvm_checksum_with_offset(hw,
2450 								nvm_offset);
2451 		if (ret_val != 0)
2452 			goto out;
2453 	}
2454 
2455 out:
2456 	return ret_val;
2457 }
2458 
2459 /**
2460  *  igb_update_nvm_checksum_82580 - Update EEPROM checksum
2461  *  @hw: pointer to the HW structure
2462  *
2463  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2464  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2465  *  checksum and writes the value to the EEPROM.
2466  **/
2467 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2468 {
2469 	s32 ret_val;
2470 	u16 j, nvm_data;
2471 	u16 nvm_offset;
2472 
2473 	ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2474 	if (ret_val) {
2475 		hw_dbg("NVM Read Error while updating checksum compatibility bit.\n");
2476 		goto out;
2477 	}
2478 
2479 	if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2480 		/* set compatibility bit to validate checksums appropriately */
2481 		nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2482 		ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2483 					&nvm_data);
2484 		if (ret_val) {
2485 			hw_dbg("NVM Write Error while updating checksum compatibility bit.\n");
2486 			goto out;
2487 		}
2488 	}
2489 
2490 	for (j = 0; j < 4; j++) {
2491 		nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2492 		ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2493 		if (ret_val)
2494 			goto out;
2495 	}
2496 
2497 out:
2498 	return ret_val;
2499 }
2500 
2501 /**
2502  *  igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2503  *  @hw: pointer to the HW structure
2504  *
2505  *  Calculates the EEPROM section checksum by reading/adding each word of
2506  *  the EEPROM and then verifies that the sum of the EEPROM is
2507  *  equal to 0xBABA.
2508  **/
2509 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2510 {
2511 	s32 ret_val = 0;
2512 	u16 j;
2513 	u16 nvm_offset;
2514 
2515 	for (j = 0; j < 4; j++) {
2516 		nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2517 		ret_val = igb_validate_nvm_checksum_with_offset(hw,
2518 								nvm_offset);
2519 		if (ret_val != 0)
2520 			goto out;
2521 	}
2522 
2523 out:
2524 	return ret_val;
2525 }
2526 
2527 /**
2528  *  igb_update_nvm_checksum_i350 - Update EEPROM checksum
2529  *  @hw: pointer to the HW structure
2530  *
2531  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2532  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2533  *  checksum and writes the value to the EEPROM.
2534  **/
2535 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2536 {
2537 	s32 ret_val = 0;
2538 	u16 j;
2539 	u16 nvm_offset;
2540 
2541 	for (j = 0; j < 4; j++) {
2542 		nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2543 		ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2544 		if (ret_val != 0)
2545 			goto out;
2546 	}
2547 
2548 out:
2549 	return ret_val;
2550 }
2551 
2552 /**
2553  *  __igb_access_emi_reg - Read/write EMI register
2554  *  @hw: pointer to the HW structure
2555  *  @address: EMI address to program
2556  *  @data: pointer to value to read/write from/to the EMI address
2557  *  @read: boolean flag to indicate read or write
2558  **/
2559 static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
2560 				  u16 *data, bool read)
2561 {
2562 	s32 ret_val = 0;
2563 
2564 	ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2565 	if (ret_val)
2566 		return ret_val;
2567 
2568 	if (read)
2569 		ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2570 	else
2571 		ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2572 
2573 	return ret_val;
2574 }
2575 
2576 /**
2577  *  igb_read_emi_reg - Read Extended Management Interface register
2578  *  @hw: pointer to the HW structure
2579  *  @addr: EMI address to program
2580  *  @data: value to be read from the EMI address
2581  **/
2582 s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2583 {
2584 	return __igb_access_emi_reg(hw, addr, data, true);
2585 }
2586 
2587 /**
2588  *  igb_set_eee_i350 - Enable/disable EEE support
2589  *  @hw: pointer to the HW structure
2590  *  @adv1G: boolean flag enabling 1G EEE advertisement
2591  *  @adv100M: boolean flag enabling 100M EEE advertisement
2592  *
2593  *  Enable/disable EEE based on setting in dev_spec structure.
2594  *
2595  **/
2596 s32 igb_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
2597 {
2598 	u32 ipcnfg, eeer;
2599 
2600 	if ((hw->mac.type < e1000_i350) ||
2601 	    (hw->phy.media_type != e1000_media_type_copper))
2602 		goto out;
2603 	ipcnfg = rd32(E1000_IPCNFG);
2604 	eeer = rd32(E1000_EEER);
2605 
2606 	/* enable or disable per user setting */
2607 	if (!(hw->dev_spec._82575.eee_disable)) {
2608 		u32 eee_su = rd32(E1000_EEE_SU);
2609 
2610 		if (adv100M)
2611 			ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
2612 		else
2613 			ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
2614 
2615 		if (adv1G)
2616 			ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
2617 		else
2618 			ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
2619 
2620 		eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2621 			E1000_EEER_LPI_FC);
2622 
2623 		/* This bit should not be set in normal operation. */
2624 		if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2625 			hw_dbg("LPI Clock Stop Bit should not be set!\n");
2626 
2627 	} else {
2628 		ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2629 			E1000_IPCNFG_EEE_100M_AN);
2630 		eeer &= ~(E1000_EEER_TX_LPI_EN |
2631 			E1000_EEER_RX_LPI_EN |
2632 			E1000_EEER_LPI_FC);
2633 	}
2634 	wr32(E1000_IPCNFG, ipcnfg);
2635 	wr32(E1000_EEER, eeer);
2636 	rd32(E1000_IPCNFG);
2637 	rd32(E1000_EEER);
2638 out:
2639 
2640 	return 0;
2641 }
2642 
2643 /**
2644  *  igb_set_eee_i354 - Enable/disable EEE support
2645  *  @hw: pointer to the HW structure
2646  *  @adv1G: boolean flag enabling 1G EEE advertisement
2647  *  @adv100M: boolean flag enabling 100M EEE advertisement
2648  *
2649  *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
2650  *
2651  **/
2652 s32 igb_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
2653 {
2654 	struct e1000_phy_info *phy = &hw->phy;
2655 	s32 ret_val = 0;
2656 	u16 phy_data;
2657 
2658 	if ((hw->phy.media_type != e1000_media_type_copper) ||
2659 	    ((phy->id != M88E1543_E_PHY_ID) &&
2660 	     (phy->id != M88E1512_E_PHY_ID)))
2661 		goto out;
2662 
2663 	if (!hw->dev_spec._82575.eee_disable) {
2664 		/* Switch to PHY page 18. */
2665 		ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2666 		if (ret_val)
2667 			goto out;
2668 
2669 		ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2670 					    &phy_data);
2671 		if (ret_val)
2672 			goto out;
2673 
2674 		phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2675 		ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2676 					     phy_data);
2677 		if (ret_val)
2678 			goto out;
2679 
2680 		/* Return the PHY to page 0. */
2681 		ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2682 		if (ret_val)
2683 			goto out;
2684 
2685 		/* Turn on EEE advertisement. */
2686 		ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2687 					     E1000_EEE_ADV_DEV_I354,
2688 					     &phy_data);
2689 		if (ret_val)
2690 			goto out;
2691 
2692 		if (adv100M)
2693 			phy_data |= E1000_EEE_ADV_100_SUPPORTED;
2694 		else
2695 			phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
2696 
2697 		if (adv1G)
2698 			phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
2699 		else
2700 			phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
2701 
2702 		ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2703 						E1000_EEE_ADV_DEV_I354,
2704 						phy_data);
2705 	} else {
2706 		/* Turn off EEE advertisement. */
2707 		ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2708 					     E1000_EEE_ADV_DEV_I354,
2709 					     &phy_data);
2710 		if (ret_val)
2711 			goto out;
2712 
2713 		phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2714 			      E1000_EEE_ADV_1000_SUPPORTED);
2715 		ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2716 					      E1000_EEE_ADV_DEV_I354,
2717 					      phy_data);
2718 	}
2719 
2720 out:
2721 	return ret_val;
2722 }
2723 
2724 /**
2725  *  igb_get_eee_status_i354 - Get EEE status
2726  *  @hw: pointer to the HW structure
2727  *  @status: EEE status
2728  *
2729  *  Get EEE status by guessing based on whether Tx or Rx LPI indications have
2730  *  been received.
2731  **/
2732 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2733 {
2734 	struct e1000_phy_info *phy = &hw->phy;
2735 	s32 ret_val = 0;
2736 	u16 phy_data;
2737 
2738 	/* Check if EEE is supported on this device. */
2739 	if ((hw->phy.media_type != e1000_media_type_copper) ||
2740 	    ((phy->id != M88E1543_E_PHY_ID) &&
2741 	     (phy->id != M88E1512_E_PHY_ID)))
2742 		goto out;
2743 
2744 	ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2745 				     E1000_PCS_STATUS_DEV_I354,
2746 				     &phy_data);
2747 	if (ret_val)
2748 		goto out;
2749 
2750 	*status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2751 			      E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2752 
2753 out:
2754 	return ret_val;
2755 }
2756 
2757 #ifdef CONFIG_IGB_HWMON
2758 static const u8 e1000_emc_temp_data[4] = {
2759 	E1000_EMC_INTERNAL_DATA,
2760 	E1000_EMC_DIODE1_DATA,
2761 	E1000_EMC_DIODE2_DATA,
2762 	E1000_EMC_DIODE3_DATA
2763 };
2764 static const u8 e1000_emc_therm_limit[4] = {
2765 	E1000_EMC_INTERNAL_THERM_LIMIT,
2766 	E1000_EMC_DIODE1_THERM_LIMIT,
2767 	E1000_EMC_DIODE2_THERM_LIMIT,
2768 	E1000_EMC_DIODE3_THERM_LIMIT
2769 };
2770 
2771 /**
2772  *  igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2773  *  @hw: pointer to hardware structure
2774  *
2775  *  Updates the temperatures in mac.thermal_sensor_data
2776  **/
2777 static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2778 {
2779 	u16 ets_offset;
2780 	u16 ets_cfg;
2781 	u16 ets_sensor;
2782 	u8  num_sensors;
2783 	u8  sensor_index;
2784 	u8  sensor_location;
2785 	u8  i;
2786 	struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2787 
2788 	if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2789 		return E1000_NOT_IMPLEMENTED;
2790 
2791 	data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2792 
2793 	/* Return the internal sensor only if ETS is unsupported */
2794 	hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2795 	if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2796 		return 0;
2797 
2798 	hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2799 	if (FIELD_GET(NVM_ETS_TYPE_MASK, ets_cfg)
2800 	    != NVM_ETS_TYPE_EMC)
2801 		return E1000_NOT_IMPLEMENTED;
2802 
2803 	num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2804 	if (num_sensors > E1000_MAX_SENSORS)
2805 		num_sensors = E1000_MAX_SENSORS;
2806 
2807 	for (i = 1; i < num_sensors; i++) {
2808 		hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2809 		sensor_index = FIELD_GET(NVM_ETS_DATA_INDEX_MASK, ets_sensor);
2810 		sensor_location = FIELD_GET(NVM_ETS_DATA_LOC_MASK, ets_sensor);
2811 
2812 		if (sensor_location != 0)
2813 			hw->phy.ops.read_i2c_byte(hw,
2814 					e1000_emc_temp_data[sensor_index],
2815 					E1000_I2C_THERMAL_SENSOR_ADDR,
2816 					&data->sensor[i].temp);
2817 	}
2818 	return 0;
2819 }
2820 
2821 /**
2822  *  igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2823  *  @hw: pointer to hardware structure
2824  *
2825  *  Sets the thermal sensor thresholds according to the NVM map
2826  *  and save off the threshold and location values into mac.thermal_sensor_data
2827  **/
2828 static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2829 {
2830 	u16 ets_offset;
2831 	u16 ets_cfg;
2832 	u16 ets_sensor;
2833 	u8  low_thresh_delta;
2834 	u8  num_sensors;
2835 	u8  sensor_index;
2836 	u8  sensor_location;
2837 	u8  therm_limit;
2838 	u8  i;
2839 	struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2840 
2841 	if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2842 		return E1000_NOT_IMPLEMENTED;
2843 
2844 	memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2845 
2846 	data->sensor[0].location = 0x1;
2847 	data->sensor[0].caution_thresh =
2848 		(rd32(E1000_THHIGHTC) & 0xFF);
2849 	data->sensor[0].max_op_thresh =
2850 		(rd32(E1000_THLOWTC) & 0xFF);
2851 
2852 	/* Return the internal sensor only if ETS is unsupported */
2853 	hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2854 	if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2855 		return 0;
2856 
2857 	hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2858 	if (FIELD_GET(NVM_ETS_TYPE_MASK, ets_cfg)
2859 	    != NVM_ETS_TYPE_EMC)
2860 		return E1000_NOT_IMPLEMENTED;
2861 
2862 	low_thresh_delta = FIELD_GET(NVM_ETS_LTHRES_DELTA_MASK, ets_cfg);
2863 	num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2864 
2865 	for (i = 1; i <= num_sensors; i++) {
2866 		hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2867 		sensor_index = FIELD_GET(NVM_ETS_DATA_INDEX_MASK, ets_sensor);
2868 		sensor_location = FIELD_GET(NVM_ETS_DATA_LOC_MASK, ets_sensor);
2869 		therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2870 
2871 		hw->phy.ops.write_i2c_byte(hw,
2872 			e1000_emc_therm_limit[sensor_index],
2873 			E1000_I2C_THERMAL_SENSOR_ADDR,
2874 			therm_limit);
2875 
2876 		if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2877 			data->sensor[i].location = sensor_location;
2878 			data->sensor[i].caution_thresh = therm_limit;
2879 			data->sensor[i].max_op_thresh = therm_limit -
2880 							low_thresh_delta;
2881 		}
2882 	}
2883 	return 0;
2884 }
2885 
2886 #endif
2887 static struct e1000_mac_operations e1000_mac_ops_82575 = {
2888 	.init_hw              = igb_init_hw_82575,
2889 	.check_for_link       = igb_check_for_link_82575,
2890 	.rar_set              = igb_rar_set,
2891 	.read_mac_addr        = igb_read_mac_addr_82575,
2892 	.get_speed_and_duplex = igb_get_link_up_info_82575,
2893 #ifdef CONFIG_IGB_HWMON
2894 	.get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2895 	.init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2896 #endif
2897 };
2898 
2899 static const struct e1000_phy_operations e1000_phy_ops_82575 = {
2900 	.acquire              = igb_acquire_phy_82575,
2901 	.get_cfg_done         = igb_get_cfg_done_82575,
2902 	.release              = igb_release_phy_82575,
2903 	.write_i2c_byte       = igb_write_i2c_byte,
2904 	.read_i2c_byte        = igb_read_i2c_byte,
2905 };
2906 
2907 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
2908 	.acquire              = igb_acquire_nvm_82575,
2909 	.read                 = igb_read_nvm_eerd,
2910 	.release              = igb_release_nvm_82575,
2911 	.write                = igb_write_nvm_spi,
2912 };
2913 
2914 const struct e1000_info e1000_82575_info = {
2915 	.get_invariants = igb_get_invariants_82575,
2916 	.mac_ops = &e1000_mac_ops_82575,
2917 	.phy_ops = &e1000_phy_ops_82575,
2918 	.nvm_ops = &e1000_nvm_ops_82575,
2919 };
2920 
2921