1 /* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2015 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24 /* e1000_82575 25 * e1000_82576 26 */ 27 28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 29 30 #include <linux/types.h> 31 #include <linux/if_ether.h> 32 #include <linux/i2c.h> 33 34 #include "e1000_mac.h" 35 #include "e1000_82575.h" 36 #include "e1000_i210.h" 37 #include "igb.h" 38 39 static s32 igb_get_invariants_82575(struct e1000_hw *); 40 static s32 igb_acquire_phy_82575(struct e1000_hw *); 41 static void igb_release_phy_82575(struct e1000_hw *); 42 static s32 igb_acquire_nvm_82575(struct e1000_hw *); 43 static void igb_release_nvm_82575(struct e1000_hw *); 44 static s32 igb_check_for_link_82575(struct e1000_hw *); 45 static s32 igb_get_cfg_done_82575(struct e1000_hw *); 46 static s32 igb_init_hw_82575(struct e1000_hw *); 47 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *); 48 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *); 49 static s32 igb_reset_hw_82575(struct e1000_hw *); 50 static s32 igb_reset_hw_82580(struct e1000_hw *); 51 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); 52 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *, bool); 53 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *, bool); 54 static s32 igb_setup_copper_link_82575(struct e1000_hw *); 55 static s32 igb_setup_serdes_link_82575(struct e1000_hw *); 56 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16); 57 static void igb_clear_hw_cntrs_82575(struct e1000_hw *); 58 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16); 59 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *, 60 u16 *); 61 static s32 igb_get_phy_id_82575(struct e1000_hw *); 62 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16); 63 static bool igb_sgmii_active_82575(struct e1000_hw *); 64 static s32 igb_reset_init_script_82575(struct e1000_hw *); 65 static s32 igb_read_mac_addr_82575(struct e1000_hw *); 66 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw); 67 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw); 68 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw); 69 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw); 70 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw); 71 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw); 72 static const u16 e1000_82580_rxpbs_table[] = { 73 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 }; 74 75 /* Due to a hw errata, if the host tries to configure the VFTA register 76 * while performing queries from the BMC or DMA, then the VFTA in some 77 * cases won't be written. 78 */ 79 80 /** 81 * igb_write_vfta_i350 - Write value to VLAN filter table 82 * @hw: pointer to the HW structure 83 * @offset: register offset in VLAN filter table 84 * @value: register value written to VLAN filter table 85 * 86 * Writes value at the given offset in the register array which stores 87 * the VLAN filter table. 88 **/ 89 static void igb_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value) 90 { 91 struct igb_adapter *adapter = hw->back; 92 int i; 93 94 for (i = 10; i--;) 95 array_wr32(E1000_VFTA, offset, value); 96 97 wrfl(); 98 adapter->shadow_vfta[offset] = value; 99 } 100 101 /** 102 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO 103 * @hw: pointer to the HW structure 104 * 105 * Called to determine if the I2C pins are being used for I2C or as an 106 * external MDIO interface since the two options are mutually exclusive. 107 **/ 108 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw) 109 { 110 u32 reg = 0; 111 bool ext_mdio = false; 112 113 switch (hw->mac.type) { 114 case e1000_82575: 115 case e1000_82576: 116 reg = rd32(E1000_MDIC); 117 ext_mdio = !!(reg & E1000_MDIC_DEST); 118 break; 119 case e1000_82580: 120 case e1000_i350: 121 case e1000_i354: 122 case e1000_i210: 123 case e1000_i211: 124 reg = rd32(E1000_MDICNFG); 125 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); 126 break; 127 default: 128 break; 129 } 130 return ext_mdio; 131 } 132 133 /** 134 * igb_check_for_link_media_swap - Check which M88E1112 interface linked 135 * @hw: pointer to the HW structure 136 * 137 * Poll the M88E1112 interfaces to see which interface achieved link. 138 */ 139 static s32 igb_check_for_link_media_swap(struct e1000_hw *hw) 140 { 141 struct e1000_phy_info *phy = &hw->phy; 142 s32 ret_val; 143 u16 data; 144 u8 port = 0; 145 146 /* Check the copper medium. */ 147 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 148 if (ret_val) 149 return ret_val; 150 151 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); 152 if (ret_val) 153 return ret_val; 154 155 if (data & E1000_M88E1112_STATUS_LINK) 156 port = E1000_MEDIA_PORT_COPPER; 157 158 /* Check the other medium. */ 159 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1); 160 if (ret_val) 161 return ret_val; 162 163 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data); 164 if (ret_val) 165 return ret_val; 166 167 168 if (data & E1000_M88E1112_STATUS_LINK) 169 port = E1000_MEDIA_PORT_OTHER; 170 171 /* Determine if a swap needs to happen. */ 172 if (port && (hw->dev_spec._82575.media_port != port)) { 173 hw->dev_spec._82575.media_port = port; 174 hw->dev_spec._82575.media_changed = true; 175 } 176 177 if (port == E1000_MEDIA_PORT_COPPER) { 178 /* reset page to 0 */ 179 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 180 if (ret_val) 181 return ret_val; 182 igb_check_for_link_82575(hw); 183 } else { 184 igb_check_for_link_82575(hw); 185 /* reset page to 0 */ 186 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0); 187 if (ret_val) 188 return ret_val; 189 } 190 191 return 0; 192 } 193 194 /** 195 * igb_init_phy_params_82575 - Init PHY func ptrs. 196 * @hw: pointer to the HW structure 197 **/ 198 static s32 igb_init_phy_params_82575(struct e1000_hw *hw) 199 { 200 struct e1000_phy_info *phy = &hw->phy; 201 s32 ret_val = 0; 202 u32 ctrl_ext; 203 204 if (hw->phy.media_type != e1000_media_type_copper) { 205 phy->type = e1000_phy_none; 206 goto out; 207 } 208 209 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 210 phy->reset_delay_us = 100; 211 212 ctrl_ext = rd32(E1000_CTRL_EXT); 213 214 if (igb_sgmii_active_82575(hw)) { 215 phy->ops.reset = igb_phy_hw_reset_sgmii_82575; 216 ctrl_ext |= E1000_CTRL_I2C_ENA; 217 } else { 218 phy->ops.reset = igb_phy_hw_reset; 219 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 220 } 221 222 wr32(E1000_CTRL_EXT, ctrl_ext); 223 igb_reset_mdicnfg_82580(hw); 224 225 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) { 226 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575; 227 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575; 228 } else { 229 switch (hw->mac.type) { 230 case e1000_82580: 231 case e1000_i350: 232 case e1000_i354: 233 case e1000_i210: 234 case e1000_i211: 235 phy->ops.read_reg = igb_read_phy_reg_82580; 236 phy->ops.write_reg = igb_write_phy_reg_82580; 237 break; 238 default: 239 phy->ops.read_reg = igb_read_phy_reg_igp; 240 phy->ops.write_reg = igb_write_phy_reg_igp; 241 } 242 } 243 244 /* set lan id */ 245 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >> 246 E1000_STATUS_FUNC_SHIFT; 247 248 /* Make sure the PHY is in a good state. Several people have reported 249 * firmware leaving the PHY's page select register set to something 250 * other than the default of zero, which causes the PHY ID read to 251 * access something other than the intended register. 252 */ 253 ret_val = hw->phy.ops.reset(hw); 254 if (ret_val) { 255 hw_dbg("Error resetting the PHY.\n"); 256 goto out; 257 } 258 259 /* Set phy->phy_addr and phy->id. */ 260 ret_val = igb_get_phy_id_82575(hw); 261 if (ret_val) 262 return ret_val; 263 264 /* Verify phy id and set remaining function pointers */ 265 switch (phy->id) { 266 case M88E1543_E_PHY_ID: 267 case M88E1512_E_PHY_ID: 268 case I347AT4_E_PHY_ID: 269 case M88E1112_E_PHY_ID: 270 case M88E1111_I_PHY_ID: 271 phy->type = e1000_phy_m88; 272 phy->ops.check_polarity = igb_check_polarity_m88; 273 phy->ops.get_phy_info = igb_get_phy_info_m88; 274 if (phy->id != M88E1111_I_PHY_ID) 275 phy->ops.get_cable_length = 276 igb_get_cable_length_m88_gen2; 277 else 278 phy->ops.get_cable_length = igb_get_cable_length_m88; 279 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; 280 /* Check if this PHY is configured for media swap. */ 281 if (phy->id == M88E1112_E_PHY_ID) { 282 u16 data; 283 284 ret_val = phy->ops.write_reg(hw, 285 E1000_M88E1112_PAGE_ADDR, 286 2); 287 if (ret_val) 288 goto out; 289 290 ret_val = phy->ops.read_reg(hw, 291 E1000_M88E1112_MAC_CTRL_1, 292 &data); 293 if (ret_val) 294 goto out; 295 296 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >> 297 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT; 298 if (data == E1000_M88E1112_AUTO_COPPER_SGMII || 299 data == E1000_M88E1112_AUTO_COPPER_BASEX) 300 hw->mac.ops.check_for_link = 301 igb_check_for_link_media_swap; 302 } 303 if (phy->id == M88E1512_E_PHY_ID) { 304 ret_val = igb_initialize_M88E1512_phy(hw); 305 if (ret_val) 306 goto out; 307 } 308 if (phy->id == M88E1543_E_PHY_ID) { 309 ret_val = igb_initialize_M88E1543_phy(hw); 310 if (ret_val) 311 goto out; 312 } 313 break; 314 case IGP03E1000_E_PHY_ID: 315 phy->type = e1000_phy_igp_3; 316 phy->ops.get_phy_info = igb_get_phy_info_igp; 317 phy->ops.get_cable_length = igb_get_cable_length_igp_2; 318 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp; 319 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575; 320 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state; 321 break; 322 case I82580_I_PHY_ID: 323 case I350_I_PHY_ID: 324 phy->type = e1000_phy_82580; 325 phy->ops.force_speed_duplex = 326 igb_phy_force_speed_duplex_82580; 327 phy->ops.get_cable_length = igb_get_cable_length_82580; 328 phy->ops.get_phy_info = igb_get_phy_info_82580; 329 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580; 330 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580; 331 break; 332 case I210_I_PHY_ID: 333 phy->type = e1000_phy_i210; 334 phy->ops.check_polarity = igb_check_polarity_m88; 335 phy->ops.get_cfg_done = igb_get_cfg_done_i210; 336 phy->ops.get_phy_info = igb_get_phy_info_m88; 337 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2; 338 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580; 339 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580; 340 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; 341 break; 342 default: 343 ret_val = -E1000_ERR_PHY; 344 goto out; 345 } 346 347 out: 348 return ret_val; 349 } 350 351 /** 352 * igb_init_nvm_params_82575 - Init NVM func ptrs. 353 * @hw: pointer to the HW structure 354 **/ 355 static s32 igb_init_nvm_params_82575(struct e1000_hw *hw) 356 { 357 struct e1000_nvm_info *nvm = &hw->nvm; 358 u32 eecd = rd32(E1000_EECD); 359 u16 size; 360 361 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 362 E1000_EECD_SIZE_EX_SHIFT); 363 364 /* Added to a constant, "size" becomes the left-shift value 365 * for setting word_size. 366 */ 367 size += NVM_WORD_SIZE_BASE_SHIFT; 368 369 /* Just in case size is out of range, cap it to the largest 370 * EEPROM size supported 371 */ 372 if (size > 15) 373 size = 15; 374 375 nvm->word_size = BIT(size); 376 nvm->opcode_bits = 8; 377 nvm->delay_usec = 1; 378 379 switch (nvm->override) { 380 case e1000_nvm_override_spi_large: 381 nvm->page_size = 32; 382 nvm->address_bits = 16; 383 break; 384 case e1000_nvm_override_spi_small: 385 nvm->page_size = 8; 386 nvm->address_bits = 8; 387 break; 388 default: 389 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 390 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 391 16 : 8; 392 break; 393 } 394 if (nvm->word_size == BIT(15)) 395 nvm->page_size = 128; 396 397 nvm->type = e1000_nvm_eeprom_spi; 398 399 /* NVM Function Pointers */ 400 nvm->ops.acquire = igb_acquire_nvm_82575; 401 nvm->ops.release = igb_release_nvm_82575; 402 nvm->ops.write = igb_write_nvm_spi; 403 nvm->ops.validate = igb_validate_nvm_checksum; 404 nvm->ops.update = igb_update_nvm_checksum; 405 if (nvm->word_size < BIT(15)) 406 nvm->ops.read = igb_read_nvm_eerd; 407 else 408 nvm->ops.read = igb_read_nvm_spi; 409 410 /* override generic family function pointers for specific descendants */ 411 switch (hw->mac.type) { 412 case e1000_82580: 413 nvm->ops.validate = igb_validate_nvm_checksum_82580; 414 nvm->ops.update = igb_update_nvm_checksum_82580; 415 break; 416 case e1000_i354: 417 case e1000_i350: 418 nvm->ops.validate = igb_validate_nvm_checksum_i350; 419 nvm->ops.update = igb_update_nvm_checksum_i350; 420 break; 421 default: 422 break; 423 } 424 425 return 0; 426 } 427 428 /** 429 * igb_init_mac_params_82575 - Init MAC func ptrs. 430 * @hw: pointer to the HW structure 431 **/ 432 static s32 igb_init_mac_params_82575(struct e1000_hw *hw) 433 { 434 struct e1000_mac_info *mac = &hw->mac; 435 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 436 437 /* Set mta register count */ 438 mac->mta_reg_count = 128; 439 /* Set uta register count */ 440 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128; 441 /* Set rar entry count */ 442 switch (mac->type) { 443 case e1000_82576: 444 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 445 break; 446 case e1000_82580: 447 mac->rar_entry_count = E1000_RAR_ENTRIES_82580; 448 break; 449 case e1000_i350: 450 case e1000_i354: 451 mac->rar_entry_count = E1000_RAR_ENTRIES_I350; 452 break; 453 default: 454 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 455 break; 456 } 457 /* reset */ 458 if (mac->type >= e1000_82580) 459 mac->ops.reset_hw = igb_reset_hw_82580; 460 else 461 mac->ops.reset_hw = igb_reset_hw_82575; 462 463 if (mac->type >= e1000_i210) { 464 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210; 465 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210; 466 467 } else { 468 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575; 469 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575; 470 } 471 472 if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354)) 473 mac->ops.write_vfta = igb_write_vfta_i350; 474 else 475 mac->ops.write_vfta = igb_write_vfta; 476 477 /* Set if part includes ASF firmware */ 478 mac->asf_firmware_present = true; 479 /* Set if manageability features are enabled. */ 480 mac->arc_subsystem_valid = 481 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK) 482 ? true : false; 483 /* enable EEE on i350 parts and later parts */ 484 if (mac->type >= e1000_i350) 485 dev_spec->eee_disable = false; 486 else 487 dev_spec->eee_disable = true; 488 /* Allow a single clear of the SW semaphore on I210 and newer */ 489 if (mac->type >= e1000_i210) 490 dev_spec->clear_semaphore_once = true; 491 /* physical interface link setup */ 492 mac->ops.setup_physical_interface = 493 (hw->phy.media_type == e1000_media_type_copper) 494 ? igb_setup_copper_link_82575 495 : igb_setup_serdes_link_82575; 496 497 if (mac->type == e1000_82580) { 498 switch (hw->device_id) { 499 /* feature not supported on these id's */ 500 case E1000_DEV_ID_DH89XXCC_SGMII: 501 case E1000_DEV_ID_DH89XXCC_SERDES: 502 case E1000_DEV_ID_DH89XXCC_BACKPLANE: 503 case E1000_DEV_ID_DH89XXCC_SFP: 504 break; 505 default: 506 hw->dev_spec._82575.mas_capable = true; 507 break; 508 } 509 } 510 return 0; 511 } 512 513 /** 514 * igb_set_sfp_media_type_82575 - derives SFP module media type. 515 * @hw: pointer to the HW structure 516 * 517 * The media type is chosen based on SFP module. 518 * compatibility flags retrieved from SFP ID EEPROM. 519 **/ 520 static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw) 521 { 522 s32 ret_val = E1000_ERR_CONFIG; 523 u32 ctrl_ext = 0; 524 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 525 struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags; 526 u8 tranceiver_type = 0; 527 s32 timeout = 3; 528 529 /* Turn I2C interface ON and power on sfp cage */ 530 ctrl_ext = rd32(E1000_CTRL_EXT); 531 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 532 wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA); 533 534 wrfl(); 535 536 /* Read SFP module data */ 537 while (timeout) { 538 ret_val = igb_read_sfp_data_byte(hw, 539 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET), 540 &tranceiver_type); 541 if (ret_val == 0) 542 break; 543 msleep(100); 544 timeout--; 545 } 546 if (ret_val != 0) 547 goto out; 548 549 ret_val = igb_read_sfp_data_byte(hw, 550 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET), 551 (u8 *)eth_flags); 552 if (ret_val != 0) 553 goto out; 554 555 /* Check if there is some SFP module plugged and powered */ 556 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) || 557 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) { 558 dev_spec->module_plugged = true; 559 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) { 560 hw->phy.media_type = e1000_media_type_internal_serdes; 561 } else if (eth_flags->e100_base_fx) { 562 dev_spec->sgmii_active = true; 563 hw->phy.media_type = e1000_media_type_internal_serdes; 564 } else if (eth_flags->e1000_base_t) { 565 dev_spec->sgmii_active = true; 566 hw->phy.media_type = e1000_media_type_copper; 567 } else { 568 hw->phy.media_type = e1000_media_type_unknown; 569 hw_dbg("PHY module has not been recognized\n"); 570 goto out; 571 } 572 } else { 573 hw->phy.media_type = e1000_media_type_unknown; 574 } 575 ret_val = 0; 576 out: 577 /* Restore I2C interface setting */ 578 wr32(E1000_CTRL_EXT, ctrl_ext); 579 return ret_val; 580 } 581 582 static s32 igb_get_invariants_82575(struct e1000_hw *hw) 583 { 584 struct e1000_mac_info *mac = &hw->mac; 585 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 586 s32 ret_val; 587 u32 ctrl_ext = 0; 588 u32 link_mode = 0; 589 590 switch (hw->device_id) { 591 case E1000_DEV_ID_82575EB_COPPER: 592 case E1000_DEV_ID_82575EB_FIBER_SERDES: 593 case E1000_DEV_ID_82575GB_QUAD_COPPER: 594 mac->type = e1000_82575; 595 break; 596 case E1000_DEV_ID_82576: 597 case E1000_DEV_ID_82576_NS: 598 case E1000_DEV_ID_82576_NS_SERDES: 599 case E1000_DEV_ID_82576_FIBER: 600 case E1000_DEV_ID_82576_SERDES: 601 case E1000_DEV_ID_82576_QUAD_COPPER: 602 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 603 case E1000_DEV_ID_82576_SERDES_QUAD: 604 mac->type = e1000_82576; 605 break; 606 case E1000_DEV_ID_82580_COPPER: 607 case E1000_DEV_ID_82580_FIBER: 608 case E1000_DEV_ID_82580_QUAD_FIBER: 609 case E1000_DEV_ID_82580_SERDES: 610 case E1000_DEV_ID_82580_SGMII: 611 case E1000_DEV_ID_82580_COPPER_DUAL: 612 case E1000_DEV_ID_DH89XXCC_SGMII: 613 case E1000_DEV_ID_DH89XXCC_SERDES: 614 case E1000_DEV_ID_DH89XXCC_BACKPLANE: 615 case E1000_DEV_ID_DH89XXCC_SFP: 616 mac->type = e1000_82580; 617 break; 618 case E1000_DEV_ID_I350_COPPER: 619 case E1000_DEV_ID_I350_FIBER: 620 case E1000_DEV_ID_I350_SERDES: 621 case E1000_DEV_ID_I350_SGMII: 622 mac->type = e1000_i350; 623 break; 624 case E1000_DEV_ID_I210_COPPER: 625 case E1000_DEV_ID_I210_FIBER: 626 case E1000_DEV_ID_I210_SERDES: 627 case E1000_DEV_ID_I210_SGMII: 628 case E1000_DEV_ID_I210_COPPER_FLASHLESS: 629 case E1000_DEV_ID_I210_SERDES_FLASHLESS: 630 mac->type = e1000_i210; 631 break; 632 case E1000_DEV_ID_I211_COPPER: 633 mac->type = e1000_i211; 634 break; 635 case E1000_DEV_ID_I354_BACKPLANE_1GBPS: 636 case E1000_DEV_ID_I354_SGMII: 637 case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS: 638 mac->type = e1000_i354; 639 break; 640 default: 641 return -E1000_ERR_MAC_INIT; 642 } 643 644 /* Set media type */ 645 /* The 82575 uses bits 22:23 for link mode. The mode can be changed 646 * based on the EEPROM. We cannot rely upon device ID. There 647 * is no distinguishable difference between fiber and internal 648 * SerDes mode on the 82575. There can be an external PHY attached 649 * on the SGMII interface. For this, we'll set sgmii_active to true. 650 */ 651 hw->phy.media_type = e1000_media_type_copper; 652 dev_spec->sgmii_active = false; 653 dev_spec->module_plugged = false; 654 655 ctrl_ext = rd32(E1000_CTRL_EXT); 656 657 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK; 658 switch (link_mode) { 659 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 660 hw->phy.media_type = e1000_media_type_internal_serdes; 661 break; 662 case E1000_CTRL_EXT_LINK_MODE_SGMII: 663 /* Get phy control interface type set (MDIO vs. I2C)*/ 664 if (igb_sgmii_uses_mdio_82575(hw)) { 665 hw->phy.media_type = e1000_media_type_copper; 666 dev_spec->sgmii_active = true; 667 break; 668 } 669 /* fall through for I2C based SGMII */ 670 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 671 /* read media type from SFP EEPROM */ 672 ret_val = igb_set_sfp_media_type_82575(hw); 673 if ((ret_val != 0) || 674 (hw->phy.media_type == e1000_media_type_unknown)) { 675 /* If media type was not identified then return media 676 * type defined by the CTRL_EXT settings. 677 */ 678 hw->phy.media_type = e1000_media_type_internal_serdes; 679 680 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) { 681 hw->phy.media_type = e1000_media_type_copper; 682 dev_spec->sgmii_active = true; 683 } 684 685 break; 686 } 687 688 /* do not change link mode for 100BaseFX */ 689 if (dev_spec->eth_flags.e100_base_fx) 690 break; 691 692 /* change current link mode setting */ 693 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 694 695 if (hw->phy.media_type == e1000_media_type_copper) 696 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII; 697 else 698 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 699 700 wr32(E1000_CTRL_EXT, ctrl_ext); 701 702 break; 703 default: 704 break; 705 } 706 707 /* mac initialization and operations */ 708 ret_val = igb_init_mac_params_82575(hw); 709 if (ret_val) 710 goto out; 711 712 /* NVM initialization */ 713 ret_val = igb_init_nvm_params_82575(hw); 714 switch (hw->mac.type) { 715 case e1000_i210: 716 case e1000_i211: 717 ret_val = igb_init_nvm_params_i210(hw); 718 break; 719 default: 720 break; 721 } 722 723 if (ret_val) 724 goto out; 725 726 /* if part supports SR-IOV then initialize mailbox parameters */ 727 switch (mac->type) { 728 case e1000_82576: 729 case e1000_i350: 730 igb_init_mbx_params_pf(hw); 731 break; 732 default: 733 break; 734 } 735 736 /* setup PHY parameters */ 737 ret_val = igb_init_phy_params_82575(hw); 738 739 out: 740 return ret_val; 741 } 742 743 /** 744 * igb_acquire_phy_82575 - Acquire rights to access PHY 745 * @hw: pointer to the HW structure 746 * 747 * Acquire access rights to the correct PHY. This is a 748 * function pointer entry point called by the api module. 749 **/ 750 static s32 igb_acquire_phy_82575(struct e1000_hw *hw) 751 { 752 u16 mask = E1000_SWFW_PHY0_SM; 753 754 if (hw->bus.func == E1000_FUNC_1) 755 mask = E1000_SWFW_PHY1_SM; 756 else if (hw->bus.func == E1000_FUNC_2) 757 mask = E1000_SWFW_PHY2_SM; 758 else if (hw->bus.func == E1000_FUNC_3) 759 mask = E1000_SWFW_PHY3_SM; 760 761 return hw->mac.ops.acquire_swfw_sync(hw, mask); 762 } 763 764 /** 765 * igb_release_phy_82575 - Release rights to access PHY 766 * @hw: pointer to the HW structure 767 * 768 * A wrapper to release access rights to the correct PHY. This is a 769 * function pointer entry point called by the api module. 770 **/ 771 static void igb_release_phy_82575(struct e1000_hw *hw) 772 { 773 u16 mask = E1000_SWFW_PHY0_SM; 774 775 if (hw->bus.func == E1000_FUNC_1) 776 mask = E1000_SWFW_PHY1_SM; 777 else if (hw->bus.func == E1000_FUNC_2) 778 mask = E1000_SWFW_PHY2_SM; 779 else if (hw->bus.func == E1000_FUNC_3) 780 mask = E1000_SWFW_PHY3_SM; 781 782 hw->mac.ops.release_swfw_sync(hw, mask); 783 } 784 785 /** 786 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 787 * @hw: pointer to the HW structure 788 * @offset: register offset to be read 789 * @data: pointer to the read data 790 * 791 * Reads the PHY register at offset using the serial gigabit media independent 792 * interface and stores the retrieved information in data. 793 **/ 794 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 795 u16 *data) 796 { 797 s32 ret_val = -E1000_ERR_PARAM; 798 799 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 800 hw_dbg("PHY Address %u is out of range\n", offset); 801 goto out; 802 } 803 804 ret_val = hw->phy.ops.acquire(hw); 805 if (ret_val) 806 goto out; 807 808 ret_val = igb_read_phy_reg_i2c(hw, offset, data); 809 810 hw->phy.ops.release(hw); 811 812 out: 813 return ret_val; 814 } 815 816 /** 817 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 818 * @hw: pointer to the HW structure 819 * @offset: register offset to write to 820 * @data: data to write at register offset 821 * 822 * Writes the data to PHY register at the offset using the serial gigabit 823 * media independent interface. 824 **/ 825 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 826 u16 data) 827 { 828 s32 ret_val = -E1000_ERR_PARAM; 829 830 831 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 832 hw_dbg("PHY Address %d is out of range\n", offset); 833 goto out; 834 } 835 836 ret_val = hw->phy.ops.acquire(hw); 837 if (ret_val) 838 goto out; 839 840 ret_val = igb_write_phy_reg_i2c(hw, offset, data); 841 842 hw->phy.ops.release(hw); 843 844 out: 845 return ret_val; 846 } 847 848 /** 849 * igb_get_phy_id_82575 - Retrieve PHY addr and id 850 * @hw: pointer to the HW structure 851 * 852 * Retrieves the PHY address and ID for both PHY's which do and do not use 853 * sgmi interface. 854 **/ 855 static s32 igb_get_phy_id_82575(struct e1000_hw *hw) 856 { 857 struct e1000_phy_info *phy = &hw->phy; 858 s32 ret_val = 0; 859 u16 phy_id; 860 u32 ctrl_ext; 861 u32 mdic; 862 863 /* Extra read required for some PHY's on i354 */ 864 if (hw->mac.type == e1000_i354) 865 igb_get_phy_id(hw); 866 867 /* For SGMII PHYs, we try the list of possible addresses until 868 * we find one that works. For non-SGMII PHYs 869 * (e.g. integrated copper PHYs), an address of 1 should 870 * work. The result of this function should mean phy->phy_addr 871 * and phy->id are set correctly. 872 */ 873 if (!(igb_sgmii_active_82575(hw))) { 874 phy->addr = 1; 875 ret_val = igb_get_phy_id(hw); 876 goto out; 877 } 878 879 if (igb_sgmii_uses_mdio_82575(hw)) { 880 switch (hw->mac.type) { 881 case e1000_82575: 882 case e1000_82576: 883 mdic = rd32(E1000_MDIC); 884 mdic &= E1000_MDIC_PHY_MASK; 885 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; 886 break; 887 case e1000_82580: 888 case e1000_i350: 889 case e1000_i354: 890 case e1000_i210: 891 case e1000_i211: 892 mdic = rd32(E1000_MDICNFG); 893 mdic &= E1000_MDICNFG_PHY_MASK; 894 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 895 break; 896 default: 897 ret_val = -E1000_ERR_PHY; 898 goto out; 899 } 900 ret_val = igb_get_phy_id(hw); 901 goto out; 902 } 903 904 /* Power on sgmii phy if it is disabled */ 905 ctrl_ext = rd32(E1000_CTRL_EXT); 906 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 907 wrfl(); 908 msleep(300); 909 910 /* The address field in the I2CCMD register is 3 bits and 0 is invalid. 911 * Therefore, we need to test 1-7 912 */ 913 for (phy->addr = 1; phy->addr < 8; phy->addr++) { 914 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 915 if (ret_val == 0) { 916 hw_dbg("Vendor ID 0x%08X read at address %u\n", 917 phy_id, phy->addr); 918 /* At the time of this writing, The M88 part is 919 * the only supported SGMII PHY product. 920 */ 921 if (phy_id == M88_VENDOR) 922 break; 923 } else { 924 hw_dbg("PHY address %u was unreadable\n", phy->addr); 925 } 926 } 927 928 /* A valid PHY type couldn't be found. */ 929 if (phy->addr == 8) { 930 phy->addr = 0; 931 ret_val = -E1000_ERR_PHY; 932 goto out; 933 } else { 934 ret_val = igb_get_phy_id(hw); 935 } 936 937 /* restore previous sfp cage power state */ 938 wr32(E1000_CTRL_EXT, ctrl_ext); 939 940 out: 941 return ret_val; 942 } 943 944 /** 945 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset 946 * @hw: pointer to the HW structure 947 * 948 * Resets the PHY using the serial gigabit media independent interface. 949 **/ 950 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 951 { 952 struct e1000_phy_info *phy = &hw->phy; 953 s32 ret_val; 954 955 /* This isn't a true "hard" reset, but is the only reset 956 * available to us at this time. 957 */ 958 959 hw_dbg("Soft resetting SGMII attached PHY...\n"); 960 961 /* SFP documentation requires the following to configure the SPF module 962 * to work on SGMII. No further documentation is given. 963 */ 964 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 965 if (ret_val) 966 goto out; 967 968 ret_val = igb_phy_sw_reset(hw); 969 if (ret_val) 970 goto out; 971 972 if (phy->id == M88E1512_E_PHY_ID) 973 ret_val = igb_initialize_M88E1512_phy(hw); 974 if (phy->id == M88E1543_E_PHY_ID) 975 ret_val = igb_initialize_M88E1543_phy(hw); 976 out: 977 return ret_val; 978 } 979 980 /** 981 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 982 * @hw: pointer to the HW structure 983 * @active: true to enable LPLU, false to disable 984 * 985 * Sets the LPLU D0 state according to the active flag. When 986 * activating LPLU this function also disables smart speed 987 * and vice versa. LPLU will not be activated unless the 988 * device autonegotiation advertisement meets standards of 989 * either 10 or 10/100 or 10/100/1000 at all duplexes. 990 * This is a function pointer entry point only called by 991 * PHY setup routines. 992 **/ 993 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 994 { 995 struct e1000_phy_info *phy = &hw->phy; 996 s32 ret_val; 997 u16 data; 998 999 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 1000 if (ret_val) 1001 goto out; 1002 1003 if (active) { 1004 data |= IGP02E1000_PM_D0_LPLU; 1005 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1006 data); 1007 if (ret_val) 1008 goto out; 1009 1010 /* When LPLU is enabled, we should disable SmartSpeed */ 1011 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1012 &data); 1013 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1014 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 1015 data); 1016 if (ret_val) 1017 goto out; 1018 } else { 1019 data &= ~IGP02E1000_PM_D0_LPLU; 1020 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 1021 data); 1022 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1023 * during Dx states where the power conservation is most 1024 * important. During driver activity we should enable 1025 * SmartSpeed, so performance is maintained. 1026 */ 1027 if (phy->smart_speed == e1000_smart_speed_on) { 1028 ret_val = phy->ops.read_reg(hw, 1029 IGP01E1000_PHY_PORT_CONFIG, &data); 1030 if (ret_val) 1031 goto out; 1032 1033 data |= IGP01E1000_PSCFR_SMART_SPEED; 1034 ret_val = phy->ops.write_reg(hw, 1035 IGP01E1000_PHY_PORT_CONFIG, data); 1036 if (ret_val) 1037 goto out; 1038 } else if (phy->smart_speed == e1000_smart_speed_off) { 1039 ret_val = phy->ops.read_reg(hw, 1040 IGP01E1000_PHY_PORT_CONFIG, &data); 1041 if (ret_val) 1042 goto out; 1043 1044 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1045 ret_val = phy->ops.write_reg(hw, 1046 IGP01E1000_PHY_PORT_CONFIG, data); 1047 if (ret_val) 1048 goto out; 1049 } 1050 } 1051 1052 out: 1053 return ret_val; 1054 } 1055 1056 /** 1057 * igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state 1058 * @hw: pointer to the HW structure 1059 * @active: true to enable LPLU, false to disable 1060 * 1061 * Sets the LPLU D0 state according to the active flag. When 1062 * activating LPLU this function also disables smart speed 1063 * and vice versa. LPLU will not be activated unless the 1064 * device autonegotiation advertisement meets standards of 1065 * either 10 or 10/100 or 10/100/1000 at all duplexes. 1066 * This is a function pointer entry point only called by 1067 * PHY setup routines. 1068 **/ 1069 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active) 1070 { 1071 struct e1000_phy_info *phy = &hw->phy; 1072 u16 data; 1073 1074 data = rd32(E1000_82580_PHY_POWER_MGMT); 1075 1076 if (active) { 1077 data |= E1000_82580_PM_D0_LPLU; 1078 1079 /* When LPLU is enabled, we should disable SmartSpeed */ 1080 data &= ~E1000_82580_PM_SPD; 1081 } else { 1082 data &= ~E1000_82580_PM_D0_LPLU; 1083 1084 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1085 * during Dx states where the power conservation is most 1086 * important. During driver activity we should enable 1087 * SmartSpeed, so performance is maintained. 1088 */ 1089 if (phy->smart_speed == e1000_smart_speed_on) 1090 data |= E1000_82580_PM_SPD; 1091 else if (phy->smart_speed == e1000_smart_speed_off) 1092 data &= ~E1000_82580_PM_SPD; } 1093 1094 wr32(E1000_82580_PHY_POWER_MGMT, data); 1095 return 0; 1096 } 1097 1098 /** 1099 * igb_set_d3_lplu_state_82580 - Sets low power link up state for D3 1100 * @hw: pointer to the HW structure 1101 * @active: boolean used to enable/disable lplu 1102 * 1103 * Success returns 0, Failure returns 1 1104 * 1105 * The low power link up (lplu) state is set to the power management level D3 1106 * and SmartSpeed is disabled when active is true, else clear lplu for D3 1107 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 1108 * is used during Dx states where the power conservation is most important. 1109 * During driver activity, SmartSpeed should be enabled so performance is 1110 * maintained. 1111 **/ 1112 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active) 1113 { 1114 struct e1000_phy_info *phy = &hw->phy; 1115 u16 data; 1116 1117 data = rd32(E1000_82580_PHY_POWER_MGMT); 1118 1119 if (!active) { 1120 data &= ~E1000_82580_PM_D3_LPLU; 1121 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 1122 * during Dx states where the power conservation is most 1123 * important. During driver activity we should enable 1124 * SmartSpeed, so performance is maintained. 1125 */ 1126 if (phy->smart_speed == e1000_smart_speed_on) 1127 data |= E1000_82580_PM_SPD; 1128 else if (phy->smart_speed == e1000_smart_speed_off) 1129 data &= ~E1000_82580_PM_SPD; 1130 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1131 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1132 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1133 data |= E1000_82580_PM_D3_LPLU; 1134 /* When LPLU is enabled, we should disable SmartSpeed */ 1135 data &= ~E1000_82580_PM_SPD; 1136 } 1137 1138 wr32(E1000_82580_PHY_POWER_MGMT, data); 1139 return 0; 1140 } 1141 1142 /** 1143 * igb_acquire_nvm_82575 - Request for access to EEPROM 1144 * @hw: pointer to the HW structure 1145 * 1146 * Acquire the necessary semaphores for exclusive access to the EEPROM. 1147 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 1148 * Return successful if access grant bit set, else clear the request for 1149 * EEPROM access and return -E1000_ERR_NVM (-1). 1150 **/ 1151 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw) 1152 { 1153 s32 ret_val; 1154 1155 ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM); 1156 if (ret_val) 1157 goto out; 1158 1159 ret_val = igb_acquire_nvm(hw); 1160 1161 if (ret_val) 1162 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM); 1163 1164 out: 1165 return ret_val; 1166 } 1167 1168 /** 1169 * igb_release_nvm_82575 - Release exclusive access to EEPROM 1170 * @hw: pointer to the HW structure 1171 * 1172 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 1173 * then release the semaphores acquired. 1174 **/ 1175 static void igb_release_nvm_82575(struct e1000_hw *hw) 1176 { 1177 igb_release_nvm(hw); 1178 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM); 1179 } 1180 1181 /** 1182 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 1183 * @hw: pointer to the HW structure 1184 * @mask: specifies which semaphore to acquire 1185 * 1186 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 1187 * will also specify which port we're acquiring the lock for. 1188 **/ 1189 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1190 { 1191 u32 swfw_sync; 1192 u32 swmask = mask; 1193 u32 fwmask = mask << 16; 1194 s32 ret_val = 0; 1195 s32 i = 0, timeout = 200; 1196 1197 while (i < timeout) { 1198 if (igb_get_hw_semaphore(hw)) { 1199 ret_val = -E1000_ERR_SWFW_SYNC; 1200 goto out; 1201 } 1202 1203 swfw_sync = rd32(E1000_SW_FW_SYNC); 1204 if (!(swfw_sync & (fwmask | swmask))) 1205 break; 1206 1207 /* Firmware currently using resource (fwmask) 1208 * or other software thread using resource (swmask) 1209 */ 1210 igb_put_hw_semaphore(hw); 1211 mdelay(5); 1212 i++; 1213 } 1214 1215 if (i == timeout) { 1216 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); 1217 ret_val = -E1000_ERR_SWFW_SYNC; 1218 goto out; 1219 } 1220 1221 swfw_sync |= swmask; 1222 wr32(E1000_SW_FW_SYNC, swfw_sync); 1223 1224 igb_put_hw_semaphore(hw); 1225 1226 out: 1227 return ret_val; 1228 } 1229 1230 /** 1231 * igb_release_swfw_sync_82575 - Release SW/FW semaphore 1232 * @hw: pointer to the HW structure 1233 * @mask: specifies which semaphore to acquire 1234 * 1235 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 1236 * will also specify which port we're releasing the lock for. 1237 **/ 1238 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 1239 { 1240 u32 swfw_sync; 1241 1242 while (igb_get_hw_semaphore(hw) != 0) 1243 ; /* Empty */ 1244 1245 swfw_sync = rd32(E1000_SW_FW_SYNC); 1246 swfw_sync &= ~mask; 1247 wr32(E1000_SW_FW_SYNC, swfw_sync); 1248 1249 igb_put_hw_semaphore(hw); 1250 } 1251 1252 /** 1253 * igb_get_cfg_done_82575 - Read config done bit 1254 * @hw: pointer to the HW structure 1255 * 1256 * Read the management control register for the config done bit for 1257 * completion status. NOTE: silicon which is EEPROM-less will fail trying 1258 * to read the config done bit, so an error is *ONLY* logged and returns 1259 * 0. If we were to return with error, EEPROM-less silicon 1260 * would not be able to be reset or change link. 1261 **/ 1262 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw) 1263 { 1264 s32 timeout = PHY_CFG_TIMEOUT; 1265 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 1266 1267 if (hw->bus.func == 1) 1268 mask = E1000_NVM_CFG_DONE_PORT_1; 1269 else if (hw->bus.func == E1000_FUNC_2) 1270 mask = E1000_NVM_CFG_DONE_PORT_2; 1271 else if (hw->bus.func == E1000_FUNC_3) 1272 mask = E1000_NVM_CFG_DONE_PORT_3; 1273 1274 while (timeout) { 1275 if (rd32(E1000_EEMNGCTL) & mask) 1276 break; 1277 usleep_range(1000, 2000); 1278 timeout--; 1279 } 1280 if (!timeout) 1281 hw_dbg("MNG configuration cycle has not completed.\n"); 1282 1283 /* If EEPROM is not marked present, init the PHY manually */ 1284 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) && 1285 (hw->phy.type == e1000_phy_igp_3)) 1286 igb_phy_init_script_igp3(hw); 1287 1288 return 0; 1289 } 1290 1291 /** 1292 * igb_get_link_up_info_82575 - Get link speed/duplex info 1293 * @hw: pointer to the HW structure 1294 * @speed: stores the current speed 1295 * @duplex: stores the current duplex 1296 * 1297 * This is a wrapper function, if using the serial gigabit media independent 1298 * interface, use PCS to retrieve the link speed and duplex information. 1299 * Otherwise, use the generic function to get the link speed and duplex info. 1300 **/ 1301 static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed, 1302 u16 *duplex) 1303 { 1304 s32 ret_val; 1305 1306 if (hw->phy.media_type != e1000_media_type_copper) 1307 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed, 1308 duplex); 1309 else 1310 ret_val = igb_get_speed_and_duplex_copper(hw, speed, 1311 duplex); 1312 1313 return ret_val; 1314 } 1315 1316 /** 1317 * igb_check_for_link_82575 - Check for link 1318 * @hw: pointer to the HW structure 1319 * 1320 * If sgmii is enabled, then use the pcs register to determine link, otherwise 1321 * use the generic interface for determining link. 1322 **/ 1323 static s32 igb_check_for_link_82575(struct e1000_hw *hw) 1324 { 1325 s32 ret_val; 1326 u16 speed, duplex; 1327 1328 if (hw->phy.media_type != e1000_media_type_copper) { 1329 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, 1330 &duplex); 1331 /* Use this flag to determine if link needs to be checked or 1332 * not. If we have link clear the flag so that we do not 1333 * continue to check for link. 1334 */ 1335 hw->mac.get_link_status = !hw->mac.serdes_has_link; 1336 1337 /* Configure Flow Control now that Auto-Neg has completed. 1338 * First, we need to restore the desired flow control 1339 * settings because we may have had to re-autoneg with a 1340 * different link partner. 1341 */ 1342 ret_val = igb_config_fc_after_link_up(hw); 1343 if (ret_val) 1344 hw_dbg("Error configuring flow control\n"); 1345 } else { 1346 ret_val = igb_check_for_copper_link(hw); 1347 } 1348 1349 return ret_val; 1350 } 1351 1352 /** 1353 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown 1354 * @hw: pointer to the HW structure 1355 **/ 1356 void igb_power_up_serdes_link_82575(struct e1000_hw *hw) 1357 { 1358 u32 reg; 1359 1360 1361 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1362 !igb_sgmii_active_82575(hw)) 1363 return; 1364 1365 /* Enable PCS to turn on link */ 1366 reg = rd32(E1000_PCS_CFG0); 1367 reg |= E1000_PCS_CFG_PCS_EN; 1368 wr32(E1000_PCS_CFG0, reg); 1369 1370 /* Power up the laser */ 1371 reg = rd32(E1000_CTRL_EXT); 1372 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 1373 wr32(E1000_CTRL_EXT, reg); 1374 1375 /* flush the write to verify completion */ 1376 wrfl(); 1377 usleep_range(1000, 2000); 1378 } 1379 1380 /** 1381 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 1382 * @hw: pointer to the HW structure 1383 * @speed: stores the current speed 1384 * @duplex: stores the current duplex 1385 * 1386 * Using the physical coding sub-layer (PCS), retrieve the current speed and 1387 * duplex, then store the values in the pointers provided. 1388 **/ 1389 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, 1390 u16 *duplex) 1391 { 1392 struct e1000_mac_info *mac = &hw->mac; 1393 u32 pcs, status; 1394 1395 /* Set up defaults for the return values of this function */ 1396 mac->serdes_has_link = false; 1397 *speed = 0; 1398 *duplex = 0; 1399 1400 /* Read the PCS Status register for link state. For non-copper mode, 1401 * the status register is not accurate. The PCS status register is 1402 * used instead. 1403 */ 1404 pcs = rd32(E1000_PCS_LSTAT); 1405 1406 /* The link up bit determines when link is up on autoneg. The sync ok 1407 * gets set once both sides sync up and agree upon link. Stable link 1408 * can be determined by checking for both link up and link sync ok 1409 */ 1410 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 1411 mac->serdes_has_link = true; 1412 1413 /* Detect and store PCS speed */ 1414 if (pcs & E1000_PCS_LSTS_SPEED_1000) 1415 *speed = SPEED_1000; 1416 else if (pcs & E1000_PCS_LSTS_SPEED_100) 1417 *speed = SPEED_100; 1418 else 1419 *speed = SPEED_10; 1420 1421 /* Detect and store PCS duplex */ 1422 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) 1423 *duplex = FULL_DUPLEX; 1424 else 1425 *duplex = HALF_DUPLEX; 1426 1427 /* Check if it is an I354 2.5Gb backplane connection. */ 1428 if (mac->type == e1000_i354) { 1429 status = rd32(E1000_STATUS); 1430 if ((status & E1000_STATUS_2P5_SKU) && 1431 !(status & E1000_STATUS_2P5_SKU_OVER)) { 1432 *speed = SPEED_2500; 1433 *duplex = FULL_DUPLEX; 1434 hw_dbg("2500 Mbs, "); 1435 hw_dbg("Full Duplex\n"); 1436 } 1437 } 1438 1439 } 1440 1441 return 0; 1442 } 1443 1444 /** 1445 * igb_shutdown_serdes_link_82575 - Remove link during power down 1446 * @hw: pointer to the HW structure 1447 * 1448 * In the case of fiber serdes, shut down optics and PCS on driver unload 1449 * when management pass thru is not enabled. 1450 **/ 1451 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw) 1452 { 1453 u32 reg; 1454 1455 if (hw->phy.media_type != e1000_media_type_internal_serdes && 1456 igb_sgmii_active_82575(hw)) 1457 return; 1458 1459 if (!igb_enable_mng_pass_thru(hw)) { 1460 /* Disable PCS to turn off link */ 1461 reg = rd32(E1000_PCS_CFG0); 1462 reg &= ~E1000_PCS_CFG_PCS_EN; 1463 wr32(E1000_PCS_CFG0, reg); 1464 1465 /* shutdown the laser */ 1466 reg = rd32(E1000_CTRL_EXT); 1467 reg |= E1000_CTRL_EXT_SDP3_DATA; 1468 wr32(E1000_CTRL_EXT, reg); 1469 1470 /* flush the write to verify completion */ 1471 wrfl(); 1472 usleep_range(1000, 2000); 1473 } 1474 } 1475 1476 /** 1477 * igb_reset_hw_82575 - Reset hardware 1478 * @hw: pointer to the HW structure 1479 * 1480 * This resets the hardware into a known state. This is a 1481 * function pointer entry point called by the api module. 1482 **/ 1483 static s32 igb_reset_hw_82575(struct e1000_hw *hw) 1484 { 1485 u32 ctrl; 1486 s32 ret_val; 1487 1488 /* Prevent the PCI-E bus from sticking if there is no TLP connection 1489 * on the last TLP read/write transaction when MAC is reset. 1490 */ 1491 ret_val = igb_disable_pcie_master(hw); 1492 if (ret_val) 1493 hw_dbg("PCI-E Master disable polling has failed.\n"); 1494 1495 /* set the completion timeout for interface */ 1496 ret_val = igb_set_pcie_completion_timeout(hw); 1497 if (ret_val) 1498 hw_dbg("PCI-E Set completion timeout has failed.\n"); 1499 1500 hw_dbg("Masking off all interrupts\n"); 1501 wr32(E1000_IMC, 0xffffffff); 1502 1503 wr32(E1000_RCTL, 0); 1504 wr32(E1000_TCTL, E1000_TCTL_PSP); 1505 wrfl(); 1506 1507 usleep_range(10000, 20000); 1508 1509 ctrl = rd32(E1000_CTRL); 1510 1511 hw_dbg("Issuing a global reset to MAC\n"); 1512 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST); 1513 1514 ret_val = igb_get_auto_rd_done(hw); 1515 if (ret_val) { 1516 /* When auto config read does not complete, do not 1517 * return with an error. This can happen in situations 1518 * where there is no eeprom and prevents getting link. 1519 */ 1520 hw_dbg("Auto Read Done did not complete\n"); 1521 } 1522 1523 /* If EEPROM is not present, run manual init scripts */ 1524 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) 1525 igb_reset_init_script_82575(hw); 1526 1527 /* Clear any pending interrupt events. */ 1528 wr32(E1000_IMC, 0xffffffff); 1529 rd32(E1000_ICR); 1530 1531 /* Install any alternate MAC address into RAR0 */ 1532 ret_val = igb_check_alt_mac_addr(hw); 1533 1534 return ret_val; 1535 } 1536 1537 /** 1538 * igb_init_hw_82575 - Initialize hardware 1539 * @hw: pointer to the HW structure 1540 * 1541 * This inits the hardware readying it for operation. 1542 **/ 1543 static s32 igb_init_hw_82575(struct e1000_hw *hw) 1544 { 1545 struct e1000_mac_info *mac = &hw->mac; 1546 s32 ret_val; 1547 u16 i, rar_count = mac->rar_entry_count; 1548 1549 if ((hw->mac.type >= e1000_i210) && 1550 !(igb_get_flash_presence_i210(hw))) { 1551 ret_val = igb_pll_workaround_i210(hw); 1552 if (ret_val) 1553 return ret_val; 1554 } 1555 1556 /* Initialize identification LED */ 1557 ret_val = igb_id_led_init(hw); 1558 if (ret_val) { 1559 hw_dbg("Error initializing identification LED\n"); 1560 /* This is not fatal and we should not stop init due to this */ 1561 } 1562 1563 /* Disabling VLAN filtering */ 1564 hw_dbg("Initializing the IEEE VLAN\n"); 1565 igb_clear_vfta(hw); 1566 1567 /* Setup the receive address */ 1568 igb_init_rx_addrs(hw, rar_count); 1569 1570 /* Zero out the Multicast HASH table */ 1571 hw_dbg("Zeroing the MTA\n"); 1572 for (i = 0; i < mac->mta_reg_count; i++) 1573 array_wr32(E1000_MTA, i, 0); 1574 1575 /* Zero out the Unicast HASH table */ 1576 hw_dbg("Zeroing the UTA\n"); 1577 for (i = 0; i < mac->uta_reg_count; i++) 1578 array_wr32(E1000_UTA, i, 0); 1579 1580 /* Setup link and flow control */ 1581 ret_val = igb_setup_link(hw); 1582 1583 /* Clear all of the statistics registers (clear on read). It is 1584 * important that we do this after we have tried to establish link 1585 * because the symbol error count will increment wildly if there 1586 * is no link. 1587 */ 1588 igb_clear_hw_cntrs_82575(hw); 1589 return ret_val; 1590 } 1591 1592 /** 1593 * igb_setup_copper_link_82575 - Configure copper link settings 1594 * @hw: pointer to the HW structure 1595 * 1596 * Configures the link for auto-neg or forced speed and duplex. Then we check 1597 * for link, once link is established calls to configure collision distance 1598 * and flow control are called. 1599 **/ 1600 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw) 1601 { 1602 u32 ctrl; 1603 s32 ret_val; 1604 u32 phpm_reg; 1605 1606 ctrl = rd32(E1000_CTRL); 1607 ctrl |= E1000_CTRL_SLU; 1608 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1609 wr32(E1000_CTRL, ctrl); 1610 1611 /* Clear Go Link Disconnect bit on supported devices */ 1612 switch (hw->mac.type) { 1613 case e1000_82580: 1614 case e1000_i350: 1615 case e1000_i210: 1616 case e1000_i211: 1617 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT); 1618 phpm_reg &= ~E1000_82580_PM_GO_LINKD; 1619 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg); 1620 break; 1621 default: 1622 break; 1623 } 1624 1625 ret_val = igb_setup_serdes_link_82575(hw); 1626 if (ret_val) 1627 goto out; 1628 1629 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) { 1630 /* allow time for SFP cage time to power up phy */ 1631 msleep(300); 1632 1633 ret_val = hw->phy.ops.reset(hw); 1634 if (ret_val) { 1635 hw_dbg("Error resetting the PHY.\n"); 1636 goto out; 1637 } 1638 } 1639 switch (hw->phy.type) { 1640 case e1000_phy_i210: 1641 case e1000_phy_m88: 1642 switch (hw->phy.id) { 1643 case I347AT4_E_PHY_ID: 1644 case M88E1112_E_PHY_ID: 1645 case M88E1543_E_PHY_ID: 1646 case M88E1512_E_PHY_ID: 1647 case I210_I_PHY_ID: 1648 ret_val = igb_copper_link_setup_m88_gen2(hw); 1649 break; 1650 default: 1651 ret_val = igb_copper_link_setup_m88(hw); 1652 break; 1653 } 1654 break; 1655 case e1000_phy_igp_3: 1656 ret_val = igb_copper_link_setup_igp(hw); 1657 break; 1658 case e1000_phy_82580: 1659 ret_val = igb_copper_link_setup_82580(hw); 1660 break; 1661 default: 1662 ret_val = -E1000_ERR_PHY; 1663 break; 1664 } 1665 1666 if (ret_val) 1667 goto out; 1668 1669 ret_val = igb_setup_copper_link(hw); 1670 out: 1671 return ret_val; 1672 } 1673 1674 /** 1675 * igb_setup_serdes_link_82575 - Setup link for serdes 1676 * @hw: pointer to the HW structure 1677 * 1678 * Configure the physical coding sub-layer (PCS) link. The PCS link is 1679 * used on copper connections where the serialized gigabit media independent 1680 * interface (sgmii), or serdes fiber is being used. Configures the link 1681 * for auto-negotiation or forces speed/duplex. 1682 **/ 1683 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw) 1684 { 1685 u32 ctrl_ext, ctrl_reg, reg, anadv_reg; 1686 bool pcs_autoneg; 1687 s32 ret_val = 0; 1688 u16 data; 1689 1690 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1691 !igb_sgmii_active_82575(hw)) 1692 return ret_val; 1693 1694 1695 /* On the 82575, SerDes loopback mode persists until it is 1696 * explicitly turned off or a power cycle is performed. A read to 1697 * the register does not indicate its status. Therefore, we ensure 1698 * loopback mode is disabled during initialization. 1699 */ 1700 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1701 1702 /* power on the sfp cage if present and turn on I2C */ 1703 ctrl_ext = rd32(E1000_CTRL_EXT); 1704 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1705 ctrl_ext |= E1000_CTRL_I2C_ENA; 1706 wr32(E1000_CTRL_EXT, ctrl_ext); 1707 1708 ctrl_reg = rd32(E1000_CTRL); 1709 ctrl_reg |= E1000_CTRL_SLU; 1710 1711 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { 1712 /* set both sw defined pins */ 1713 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1714 1715 /* Set switch control to serdes energy detect */ 1716 reg = rd32(E1000_CONNSW); 1717 reg |= E1000_CONNSW_ENRGSRC; 1718 wr32(E1000_CONNSW, reg); 1719 } 1720 1721 reg = rd32(E1000_PCS_LCTL); 1722 1723 /* default pcs_autoneg to the same setting as mac autoneg */ 1724 pcs_autoneg = hw->mac.autoneg; 1725 1726 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1727 case E1000_CTRL_EXT_LINK_MODE_SGMII: 1728 /* sgmii mode lets the phy handle forcing speed/duplex */ 1729 pcs_autoneg = true; 1730 /* autoneg time out should be disabled for SGMII mode */ 1731 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1732 break; 1733 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1734 /* disable PCS autoneg and support parallel detect only */ 1735 pcs_autoneg = false; 1736 default: 1737 if (hw->mac.type == e1000_82575 || 1738 hw->mac.type == e1000_82576) { 1739 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data); 1740 if (ret_val) { 1741 hw_dbg(KERN_DEBUG "NVM Read Error\n\n"); 1742 return ret_val; 1743 } 1744 1745 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT) 1746 pcs_autoneg = false; 1747 } 1748 1749 /* non-SGMII modes only supports a speed of 1000/Full for the 1750 * link so it is best to just force the MAC and let the pcs 1751 * link either autoneg or be forced to 1000/Full 1752 */ 1753 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | 1754 E1000_CTRL_FD | E1000_CTRL_FRCDPX; 1755 1756 /* set speed of 1000/Full if speed/duplex is forced */ 1757 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1758 break; 1759 } 1760 1761 wr32(E1000_CTRL, ctrl_reg); 1762 1763 /* New SerDes mode allows for forcing speed or autonegotiating speed 1764 * at 1gb. Autoneg should be default set by most drivers. This is the 1765 * mode that will be compatible with older link partners and switches. 1766 * However, both are supported by the hardware and some drivers/tools. 1767 */ 1768 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1769 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1770 1771 if (pcs_autoneg) { 1772 /* Set PCS register for autoneg */ 1773 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1774 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1775 1776 /* Disable force flow control for autoneg */ 1777 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL; 1778 1779 /* Configure flow control advertisement for autoneg */ 1780 anadv_reg = rd32(E1000_PCS_ANADV); 1781 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE); 1782 switch (hw->fc.requested_mode) { 1783 case e1000_fc_full: 1784 case e1000_fc_rx_pause: 1785 anadv_reg |= E1000_TXCW_ASM_DIR; 1786 anadv_reg |= E1000_TXCW_PAUSE; 1787 break; 1788 case e1000_fc_tx_pause: 1789 anadv_reg |= E1000_TXCW_ASM_DIR; 1790 break; 1791 default: 1792 break; 1793 } 1794 wr32(E1000_PCS_ANADV, anadv_reg); 1795 1796 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); 1797 } else { 1798 /* Set PCS register for forced link */ 1799 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1800 1801 /* Force flow control for forced link */ 1802 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1803 1804 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); 1805 } 1806 1807 wr32(E1000_PCS_LCTL, reg); 1808 1809 if (!pcs_autoneg && !igb_sgmii_active_82575(hw)) 1810 igb_force_mac_fc(hw); 1811 1812 return ret_val; 1813 } 1814 1815 /** 1816 * igb_sgmii_active_82575 - Return sgmii state 1817 * @hw: pointer to the HW structure 1818 * 1819 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1820 * which can be enabled for use in the embedded applications. Simply 1821 * return the current state of the sgmii interface. 1822 **/ 1823 static bool igb_sgmii_active_82575(struct e1000_hw *hw) 1824 { 1825 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1826 return dev_spec->sgmii_active; 1827 } 1828 1829 /** 1830 * igb_reset_init_script_82575 - Inits HW defaults after reset 1831 * @hw: pointer to the HW structure 1832 * 1833 * Inits recommended HW defaults after a reset when there is no EEPROM 1834 * detected. This is only for the 82575. 1835 **/ 1836 static s32 igb_reset_init_script_82575(struct e1000_hw *hw) 1837 { 1838 if (hw->mac.type == e1000_82575) { 1839 hw_dbg("Running reset init script for 82575\n"); 1840 /* SerDes configuration via SERDESCTRL */ 1841 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C); 1842 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78); 1843 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23); 1844 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15); 1845 1846 /* CCM configuration via CCMCTL register */ 1847 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00); 1848 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00); 1849 1850 /* PCIe lanes configuration */ 1851 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC); 1852 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF); 1853 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05); 1854 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81); 1855 1856 /* PCIe PLL Configuration */ 1857 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47); 1858 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00); 1859 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00); 1860 } 1861 1862 return 0; 1863 } 1864 1865 /** 1866 * igb_read_mac_addr_82575 - Read device MAC address 1867 * @hw: pointer to the HW structure 1868 **/ 1869 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw) 1870 { 1871 s32 ret_val = 0; 1872 1873 /* If there's an alternate MAC address place it in RAR0 1874 * so that it will override the Si installed default perm 1875 * address. 1876 */ 1877 ret_val = igb_check_alt_mac_addr(hw); 1878 if (ret_val) 1879 goto out; 1880 1881 ret_val = igb_read_mac_addr(hw); 1882 1883 out: 1884 return ret_val; 1885 } 1886 1887 /** 1888 * igb_power_down_phy_copper_82575 - Remove link during PHY power down 1889 * @hw: pointer to the HW structure 1890 * 1891 * In the case of a PHY power down to save power, or to turn off link during a 1892 * driver unload, or wake on lan is not enabled, remove the link. 1893 **/ 1894 void igb_power_down_phy_copper_82575(struct e1000_hw *hw) 1895 { 1896 /* If the management interface is not enabled, then power down */ 1897 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw))) 1898 igb_power_down_phy_copper(hw); 1899 } 1900 1901 /** 1902 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters 1903 * @hw: pointer to the HW structure 1904 * 1905 * Clears the hardware counters by reading the counter registers. 1906 **/ 1907 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw) 1908 { 1909 igb_clear_hw_cntrs_base(hw); 1910 1911 rd32(E1000_PRC64); 1912 rd32(E1000_PRC127); 1913 rd32(E1000_PRC255); 1914 rd32(E1000_PRC511); 1915 rd32(E1000_PRC1023); 1916 rd32(E1000_PRC1522); 1917 rd32(E1000_PTC64); 1918 rd32(E1000_PTC127); 1919 rd32(E1000_PTC255); 1920 rd32(E1000_PTC511); 1921 rd32(E1000_PTC1023); 1922 rd32(E1000_PTC1522); 1923 1924 rd32(E1000_ALGNERRC); 1925 rd32(E1000_RXERRC); 1926 rd32(E1000_TNCRS); 1927 rd32(E1000_CEXTERR); 1928 rd32(E1000_TSCTC); 1929 rd32(E1000_TSCTFC); 1930 1931 rd32(E1000_MGTPRC); 1932 rd32(E1000_MGTPDC); 1933 rd32(E1000_MGTPTC); 1934 1935 rd32(E1000_IAC); 1936 rd32(E1000_ICRXOC); 1937 1938 rd32(E1000_ICRXPTC); 1939 rd32(E1000_ICRXATC); 1940 rd32(E1000_ICTXPTC); 1941 rd32(E1000_ICTXATC); 1942 rd32(E1000_ICTXQEC); 1943 rd32(E1000_ICTXQMTC); 1944 rd32(E1000_ICRXDMTC); 1945 1946 rd32(E1000_CBTMPC); 1947 rd32(E1000_HTDPMC); 1948 rd32(E1000_CBRMPC); 1949 rd32(E1000_RPTHC); 1950 rd32(E1000_HGPTC); 1951 rd32(E1000_HTCBDPC); 1952 rd32(E1000_HGORCL); 1953 rd32(E1000_HGORCH); 1954 rd32(E1000_HGOTCL); 1955 rd32(E1000_HGOTCH); 1956 rd32(E1000_LENERRS); 1957 1958 /* This register should not be read in copper configurations */ 1959 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1960 igb_sgmii_active_82575(hw)) 1961 rd32(E1000_SCVPC); 1962 } 1963 1964 /** 1965 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable 1966 * @hw: pointer to the HW structure 1967 * 1968 * After rx enable if manageability is enabled then there is likely some 1969 * bad data at the start of the fifo and possibly in the DMA fifo. This 1970 * function clears the fifos and flushes any packets that came in as rx was 1971 * being enabled. 1972 **/ 1973 void igb_rx_fifo_flush_82575(struct e1000_hw *hw) 1974 { 1975 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 1976 int i, ms_wait; 1977 1978 /* disable IPv6 options as per hardware errata */ 1979 rfctl = rd32(E1000_RFCTL); 1980 rfctl |= E1000_RFCTL_IPV6_EX_DIS; 1981 wr32(E1000_RFCTL, rfctl); 1982 1983 if (hw->mac.type != e1000_82575 || 1984 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 1985 return; 1986 1987 /* Disable all RX queues */ 1988 for (i = 0; i < 4; i++) { 1989 rxdctl[i] = rd32(E1000_RXDCTL(i)); 1990 wr32(E1000_RXDCTL(i), 1991 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 1992 } 1993 /* Poll all queues to verify they have shut down */ 1994 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 1995 usleep_range(1000, 2000); 1996 rx_enabled = 0; 1997 for (i = 0; i < 4; i++) 1998 rx_enabled |= rd32(E1000_RXDCTL(i)); 1999 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 2000 break; 2001 } 2002 2003 if (ms_wait == 10) 2004 hw_dbg("Queue disable timed out after 10ms\n"); 2005 2006 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 2007 * incoming packets are rejected. Set enable and wait 2ms so that 2008 * any packet that was coming in as RCTL.EN was set is flushed 2009 */ 2010 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 2011 2012 rlpml = rd32(E1000_RLPML); 2013 wr32(E1000_RLPML, 0); 2014 2015 rctl = rd32(E1000_RCTL); 2016 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 2017 temp_rctl |= E1000_RCTL_LPE; 2018 2019 wr32(E1000_RCTL, temp_rctl); 2020 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN); 2021 wrfl(); 2022 usleep_range(2000, 3000); 2023 2024 /* Enable RX queues that were previously enabled and restore our 2025 * previous state 2026 */ 2027 for (i = 0; i < 4; i++) 2028 wr32(E1000_RXDCTL(i), rxdctl[i]); 2029 wr32(E1000_RCTL, rctl); 2030 wrfl(); 2031 2032 wr32(E1000_RLPML, rlpml); 2033 wr32(E1000_RFCTL, rfctl); 2034 2035 /* Flush receive errors generated by workaround */ 2036 rd32(E1000_ROC); 2037 rd32(E1000_RNBC); 2038 rd32(E1000_MPC); 2039 } 2040 2041 /** 2042 * igb_set_pcie_completion_timeout - set pci-e completion timeout 2043 * @hw: pointer to the HW structure 2044 * 2045 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 2046 * however the hardware default for these parts is 500us to 1ms which is less 2047 * than the 10ms recommended by the pci-e spec. To address this we need to 2048 * increase the value to either 10ms to 200ms for capability version 1 config, 2049 * or 16ms to 55ms for version 2. 2050 **/ 2051 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw) 2052 { 2053 u32 gcr = rd32(E1000_GCR); 2054 s32 ret_val = 0; 2055 u16 pcie_devctl2; 2056 2057 /* only take action if timeout value is defaulted to 0 */ 2058 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 2059 goto out; 2060 2061 /* if capabilities version is type 1 we can write the 2062 * timeout of 10ms to 200ms through the GCR register 2063 */ 2064 if (!(gcr & E1000_GCR_CAP_VER2)) { 2065 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 2066 goto out; 2067 } 2068 2069 /* for version 2 capabilities we need to write the config space 2070 * directly in order to set the completion timeout value for 2071 * 16ms to 55ms 2072 */ 2073 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2074 &pcie_devctl2); 2075 if (ret_val) 2076 goto out; 2077 2078 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 2079 2080 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 2081 &pcie_devctl2); 2082 out: 2083 /* disable completion timeout resend */ 2084 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 2085 2086 wr32(E1000_GCR, gcr); 2087 return ret_val; 2088 } 2089 2090 /** 2091 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing 2092 * @hw: pointer to the hardware struct 2093 * @enable: state to enter, either enabled or disabled 2094 * @pf: Physical Function pool - do not set anti-spoofing for the PF 2095 * 2096 * enables/disables L2 switch anti-spoofing functionality. 2097 **/ 2098 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) 2099 { 2100 u32 reg_val, reg_offset; 2101 2102 switch (hw->mac.type) { 2103 case e1000_82576: 2104 reg_offset = E1000_DTXSWC; 2105 break; 2106 case e1000_i350: 2107 case e1000_i354: 2108 reg_offset = E1000_TXSWC; 2109 break; 2110 default: 2111 return; 2112 } 2113 2114 reg_val = rd32(reg_offset); 2115 if (enable) { 2116 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK | 2117 E1000_DTXSWC_VLAN_SPOOF_MASK); 2118 /* The PF can spoof - it has to in order to 2119 * support emulation mode NICs 2120 */ 2121 reg_val ^= (BIT(pf) | BIT(pf + MAX_NUM_VFS)); 2122 } else { 2123 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | 2124 E1000_DTXSWC_VLAN_SPOOF_MASK); 2125 } 2126 wr32(reg_offset, reg_val); 2127 } 2128 2129 /** 2130 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback 2131 * @hw: pointer to the hardware struct 2132 * @enable: state to enter, either enabled or disabled 2133 * 2134 * enables/disables L2 switch loopback functionality. 2135 **/ 2136 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 2137 { 2138 u32 dtxswc; 2139 2140 switch (hw->mac.type) { 2141 case e1000_82576: 2142 dtxswc = rd32(E1000_DTXSWC); 2143 if (enable) 2144 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2145 else 2146 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2147 wr32(E1000_DTXSWC, dtxswc); 2148 break; 2149 case e1000_i354: 2150 case e1000_i350: 2151 dtxswc = rd32(E1000_TXSWC); 2152 if (enable) 2153 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2154 else 2155 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 2156 wr32(E1000_TXSWC, dtxswc); 2157 break; 2158 default: 2159 /* Currently no other hardware supports loopback */ 2160 break; 2161 } 2162 2163 } 2164 2165 /** 2166 * igb_vmdq_set_replication_pf - enable or disable vmdq replication 2167 * @hw: pointer to the hardware struct 2168 * @enable: state to enter, either enabled or disabled 2169 * 2170 * enables/disables replication of packets across multiple pools. 2171 **/ 2172 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 2173 { 2174 u32 vt_ctl = rd32(E1000_VT_CTL); 2175 2176 if (enable) 2177 vt_ctl |= E1000_VT_CTL_VM_REPL_EN; 2178 else 2179 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; 2180 2181 wr32(E1000_VT_CTL, vt_ctl); 2182 } 2183 2184 /** 2185 * igb_read_phy_reg_82580 - Read 82580 MDI control register 2186 * @hw: pointer to the HW structure 2187 * @offset: register offset to be read 2188 * @data: pointer to the read data 2189 * 2190 * Reads the MDI control register in the PHY at offset and stores the 2191 * information read to data. 2192 **/ 2193 s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) 2194 { 2195 s32 ret_val; 2196 2197 ret_val = hw->phy.ops.acquire(hw); 2198 if (ret_val) 2199 goto out; 2200 2201 ret_val = igb_read_phy_reg_mdic(hw, offset, data); 2202 2203 hw->phy.ops.release(hw); 2204 2205 out: 2206 return ret_val; 2207 } 2208 2209 /** 2210 * igb_write_phy_reg_82580 - Write 82580 MDI control register 2211 * @hw: pointer to the HW structure 2212 * @offset: register offset to write to 2213 * @data: data to write to register at offset 2214 * 2215 * Writes data to MDI control register in the PHY at offset. 2216 **/ 2217 s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) 2218 { 2219 s32 ret_val; 2220 2221 2222 ret_val = hw->phy.ops.acquire(hw); 2223 if (ret_val) 2224 goto out; 2225 2226 ret_val = igb_write_phy_reg_mdic(hw, offset, data); 2227 2228 hw->phy.ops.release(hw); 2229 2230 out: 2231 return ret_val; 2232 } 2233 2234 /** 2235 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits 2236 * @hw: pointer to the HW structure 2237 * 2238 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on 2239 * the values found in the EEPROM. This addresses an issue in which these 2240 * bits are not restored from EEPROM after reset. 2241 **/ 2242 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw) 2243 { 2244 s32 ret_val = 0; 2245 u32 mdicnfg; 2246 u16 nvm_data = 0; 2247 2248 if (hw->mac.type != e1000_82580) 2249 goto out; 2250 if (!igb_sgmii_active_82575(hw)) 2251 goto out; 2252 2253 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2254 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2255 &nvm_data); 2256 if (ret_val) { 2257 hw_dbg("NVM Read Error\n"); 2258 goto out; 2259 } 2260 2261 mdicnfg = rd32(E1000_MDICNFG); 2262 if (nvm_data & NVM_WORD24_EXT_MDIO) 2263 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 2264 if (nvm_data & NVM_WORD24_COM_MDIO) 2265 mdicnfg |= E1000_MDICNFG_COM_MDIO; 2266 wr32(E1000_MDICNFG, mdicnfg); 2267 out: 2268 return ret_val; 2269 } 2270 2271 /** 2272 * igb_reset_hw_82580 - Reset hardware 2273 * @hw: pointer to the HW structure 2274 * 2275 * This resets function or entire device (all ports, etc.) 2276 * to a known state. 2277 **/ 2278 static s32 igb_reset_hw_82580(struct e1000_hw *hw) 2279 { 2280 s32 ret_val = 0; 2281 /* BH SW mailbox bit in SW_FW_SYNC */ 2282 u16 swmbsw_mask = E1000_SW_SYNCH_MB; 2283 u32 ctrl; 2284 bool global_device_reset = hw->dev_spec._82575.global_device_reset; 2285 2286 hw->dev_spec._82575.global_device_reset = false; 2287 2288 /* due to hw errata, global device reset doesn't always 2289 * work on 82580 2290 */ 2291 if (hw->mac.type == e1000_82580) 2292 global_device_reset = false; 2293 2294 /* Get current control state. */ 2295 ctrl = rd32(E1000_CTRL); 2296 2297 /* Prevent the PCI-E bus from sticking if there is no TLP connection 2298 * on the last TLP read/write transaction when MAC is reset. 2299 */ 2300 ret_val = igb_disable_pcie_master(hw); 2301 if (ret_val) 2302 hw_dbg("PCI-E Master disable polling has failed.\n"); 2303 2304 hw_dbg("Masking off all interrupts\n"); 2305 wr32(E1000_IMC, 0xffffffff); 2306 wr32(E1000_RCTL, 0); 2307 wr32(E1000_TCTL, E1000_TCTL_PSP); 2308 wrfl(); 2309 2310 usleep_range(10000, 11000); 2311 2312 /* Determine whether or not a global dev reset is requested */ 2313 if (global_device_reset && 2314 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask)) 2315 global_device_reset = false; 2316 2317 if (global_device_reset && 2318 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET)) 2319 ctrl |= E1000_CTRL_DEV_RST; 2320 else 2321 ctrl |= E1000_CTRL_RST; 2322 2323 wr32(E1000_CTRL, ctrl); 2324 wrfl(); 2325 2326 /* Add delay to insure DEV_RST has time to complete */ 2327 if (global_device_reset) 2328 usleep_range(5000, 6000); 2329 2330 ret_val = igb_get_auto_rd_done(hw); 2331 if (ret_val) { 2332 /* When auto config read does not complete, do not 2333 * return with an error. This can happen in situations 2334 * where there is no eeprom and prevents getting link. 2335 */ 2336 hw_dbg("Auto Read Done did not complete\n"); 2337 } 2338 2339 /* clear global device reset status bit */ 2340 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET); 2341 2342 /* Clear any pending interrupt events. */ 2343 wr32(E1000_IMC, 0xffffffff); 2344 rd32(E1000_ICR); 2345 2346 ret_val = igb_reset_mdicnfg_82580(hw); 2347 if (ret_val) 2348 hw_dbg("Could not reset MDICNFG based on EEPROM\n"); 2349 2350 /* Install any alternate MAC address into RAR0 */ 2351 ret_val = igb_check_alt_mac_addr(hw); 2352 2353 /* Release semaphore */ 2354 if (global_device_reset) 2355 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask); 2356 2357 return ret_val; 2358 } 2359 2360 /** 2361 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size 2362 * @data: data received by reading RXPBS register 2363 * 2364 * The 82580 uses a table based approach for packet buffer allocation sizes. 2365 * This function converts the retrieved value into the correct table value 2366 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 2367 * 0x0 36 72 144 1 2 4 8 16 2368 * 0x8 35 70 140 rsv rsv rsv rsv rsv 2369 */ 2370 u16 igb_rxpbs_adjust_82580(u32 data) 2371 { 2372 u16 ret_val = 0; 2373 2374 if (data < ARRAY_SIZE(e1000_82580_rxpbs_table)) 2375 ret_val = e1000_82580_rxpbs_table[data]; 2376 2377 return ret_val; 2378 } 2379 2380 /** 2381 * igb_validate_nvm_checksum_with_offset - Validate EEPROM 2382 * checksum 2383 * @hw: pointer to the HW structure 2384 * @offset: offset in words of the checksum protected region 2385 * 2386 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 2387 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 2388 **/ 2389 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw, 2390 u16 offset) 2391 { 2392 s32 ret_val = 0; 2393 u16 checksum = 0; 2394 u16 i, nvm_data; 2395 2396 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) { 2397 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2398 if (ret_val) { 2399 hw_dbg("NVM Read Error\n"); 2400 goto out; 2401 } 2402 checksum += nvm_data; 2403 } 2404 2405 if (checksum != (u16) NVM_SUM) { 2406 hw_dbg("NVM Checksum Invalid\n"); 2407 ret_val = -E1000_ERR_NVM; 2408 goto out; 2409 } 2410 2411 out: 2412 return ret_val; 2413 } 2414 2415 /** 2416 * igb_update_nvm_checksum_with_offset - Update EEPROM 2417 * checksum 2418 * @hw: pointer to the HW structure 2419 * @offset: offset in words of the checksum protected region 2420 * 2421 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 2422 * up to the checksum. Then calculates the EEPROM checksum and writes the 2423 * value to the EEPROM. 2424 **/ 2425 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 2426 { 2427 s32 ret_val; 2428 u16 checksum = 0; 2429 u16 i, nvm_data; 2430 2431 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) { 2432 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 2433 if (ret_val) { 2434 hw_dbg("NVM Read Error while updating checksum.\n"); 2435 goto out; 2436 } 2437 checksum += nvm_data; 2438 } 2439 checksum = (u16) NVM_SUM - checksum; 2440 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, 2441 &checksum); 2442 if (ret_val) 2443 hw_dbg("NVM Write Error while updating checksum.\n"); 2444 2445 out: 2446 return ret_val; 2447 } 2448 2449 /** 2450 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum 2451 * @hw: pointer to the HW structure 2452 * 2453 * Calculates the EEPROM section checksum by reading/adding each word of 2454 * the EEPROM and then verifies that the sum of the EEPROM is 2455 * equal to 0xBABA. 2456 **/ 2457 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw) 2458 { 2459 s32 ret_val = 0; 2460 u16 eeprom_regions_count = 1; 2461 u16 j, nvm_data; 2462 u16 nvm_offset; 2463 2464 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2465 if (ret_val) { 2466 hw_dbg("NVM Read Error\n"); 2467 goto out; 2468 } 2469 2470 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) { 2471 /* if checksums compatibility bit is set validate checksums 2472 * for all 4 ports. 2473 */ 2474 eeprom_regions_count = 4; 2475 } 2476 2477 for (j = 0; j < eeprom_regions_count; j++) { 2478 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2479 ret_val = igb_validate_nvm_checksum_with_offset(hw, 2480 nvm_offset); 2481 if (ret_val != 0) 2482 goto out; 2483 } 2484 2485 out: 2486 return ret_val; 2487 } 2488 2489 /** 2490 * igb_update_nvm_checksum_82580 - Update EEPROM checksum 2491 * @hw: pointer to the HW structure 2492 * 2493 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2494 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2495 * checksum and writes the value to the EEPROM. 2496 **/ 2497 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw) 2498 { 2499 s32 ret_val; 2500 u16 j, nvm_data; 2501 u16 nvm_offset; 2502 2503 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 2504 if (ret_val) { 2505 hw_dbg("NVM Read Error while updating checksum compatibility bit.\n"); 2506 goto out; 2507 } 2508 2509 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) { 2510 /* set compatibility bit to validate checksums appropriately */ 2511 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK; 2512 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, 2513 &nvm_data); 2514 if (ret_val) { 2515 hw_dbg("NVM Write Error while updating checksum compatibility bit.\n"); 2516 goto out; 2517 } 2518 } 2519 2520 for (j = 0; j < 4; j++) { 2521 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2522 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset); 2523 if (ret_val) 2524 goto out; 2525 } 2526 2527 out: 2528 return ret_val; 2529 } 2530 2531 /** 2532 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum 2533 * @hw: pointer to the HW structure 2534 * 2535 * Calculates the EEPROM section checksum by reading/adding each word of 2536 * the EEPROM and then verifies that the sum of the EEPROM is 2537 * equal to 0xBABA. 2538 **/ 2539 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw) 2540 { 2541 s32 ret_val = 0; 2542 u16 j; 2543 u16 nvm_offset; 2544 2545 for (j = 0; j < 4; j++) { 2546 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2547 ret_val = igb_validate_nvm_checksum_with_offset(hw, 2548 nvm_offset); 2549 if (ret_val != 0) 2550 goto out; 2551 } 2552 2553 out: 2554 return ret_val; 2555 } 2556 2557 /** 2558 * igb_update_nvm_checksum_i350 - Update EEPROM checksum 2559 * @hw: pointer to the HW structure 2560 * 2561 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2562 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2563 * checksum and writes the value to the EEPROM. 2564 **/ 2565 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw) 2566 { 2567 s32 ret_val = 0; 2568 u16 j; 2569 u16 nvm_offset; 2570 2571 for (j = 0; j < 4; j++) { 2572 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2573 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset); 2574 if (ret_val != 0) 2575 goto out; 2576 } 2577 2578 out: 2579 return ret_val; 2580 } 2581 2582 /** 2583 * __igb_access_emi_reg - Read/write EMI register 2584 * @hw: pointer to the HW structure 2585 * @addr: EMI address to program 2586 * @data: pointer to value to read/write from/to the EMI address 2587 * @read: boolean flag to indicate read or write 2588 **/ 2589 static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address, 2590 u16 *data, bool read) 2591 { 2592 s32 ret_val = 0; 2593 2594 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address); 2595 if (ret_val) 2596 return ret_val; 2597 2598 if (read) 2599 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data); 2600 else 2601 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data); 2602 2603 return ret_val; 2604 } 2605 2606 /** 2607 * igb_read_emi_reg - Read Extended Management Interface register 2608 * @hw: pointer to the HW structure 2609 * @addr: EMI address to program 2610 * @data: value to be read from the EMI address 2611 **/ 2612 s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data) 2613 { 2614 return __igb_access_emi_reg(hw, addr, data, true); 2615 } 2616 2617 /** 2618 * igb_set_eee_i350 - Enable/disable EEE support 2619 * @hw: pointer to the HW structure 2620 * @adv1G: boolean flag enabling 1G EEE advertisement 2621 * @adv100m: boolean flag enabling 100M EEE advertisement 2622 * 2623 * Enable/disable EEE based on setting in dev_spec structure. 2624 * 2625 **/ 2626 s32 igb_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M) 2627 { 2628 u32 ipcnfg, eeer; 2629 2630 if ((hw->mac.type < e1000_i350) || 2631 (hw->phy.media_type != e1000_media_type_copper)) 2632 goto out; 2633 ipcnfg = rd32(E1000_IPCNFG); 2634 eeer = rd32(E1000_EEER); 2635 2636 /* enable or disable per user setting */ 2637 if (!(hw->dev_spec._82575.eee_disable)) { 2638 u32 eee_su = rd32(E1000_EEE_SU); 2639 2640 if (adv100M) 2641 ipcnfg |= E1000_IPCNFG_EEE_100M_AN; 2642 else 2643 ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN; 2644 2645 if (adv1G) 2646 ipcnfg |= E1000_IPCNFG_EEE_1G_AN; 2647 else 2648 ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN; 2649 2650 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN | 2651 E1000_EEER_LPI_FC); 2652 2653 /* This bit should not be set in normal operation. */ 2654 if (eee_su & E1000_EEE_SU_LPI_CLK_STP) 2655 hw_dbg("LPI Clock Stop Bit should not be set!\n"); 2656 2657 } else { 2658 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | 2659 E1000_IPCNFG_EEE_100M_AN); 2660 eeer &= ~(E1000_EEER_TX_LPI_EN | 2661 E1000_EEER_RX_LPI_EN | 2662 E1000_EEER_LPI_FC); 2663 } 2664 wr32(E1000_IPCNFG, ipcnfg); 2665 wr32(E1000_EEER, eeer); 2666 rd32(E1000_IPCNFG); 2667 rd32(E1000_EEER); 2668 out: 2669 2670 return 0; 2671 } 2672 2673 /** 2674 * igb_set_eee_i354 - Enable/disable EEE support 2675 * @hw: pointer to the HW structure 2676 * @adv1G: boolean flag enabling 1G EEE advertisement 2677 * @adv100m: boolean flag enabling 100M EEE advertisement 2678 * 2679 * Enable/disable EEE legacy mode based on setting in dev_spec structure. 2680 * 2681 **/ 2682 s32 igb_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M) 2683 { 2684 struct e1000_phy_info *phy = &hw->phy; 2685 s32 ret_val = 0; 2686 u16 phy_data; 2687 2688 if ((hw->phy.media_type != e1000_media_type_copper) || 2689 ((phy->id != M88E1543_E_PHY_ID) && 2690 (phy->id != M88E1512_E_PHY_ID))) 2691 goto out; 2692 2693 if (!hw->dev_spec._82575.eee_disable) { 2694 /* Switch to PHY page 18. */ 2695 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18); 2696 if (ret_val) 2697 goto out; 2698 2699 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1, 2700 &phy_data); 2701 if (ret_val) 2702 goto out; 2703 2704 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS; 2705 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1, 2706 phy_data); 2707 if (ret_val) 2708 goto out; 2709 2710 /* Return the PHY to page 0. */ 2711 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0); 2712 if (ret_val) 2713 goto out; 2714 2715 /* Turn on EEE advertisement. */ 2716 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2717 E1000_EEE_ADV_DEV_I354, 2718 &phy_data); 2719 if (ret_val) 2720 goto out; 2721 2722 if (adv100M) 2723 phy_data |= E1000_EEE_ADV_100_SUPPORTED; 2724 else 2725 phy_data &= ~E1000_EEE_ADV_100_SUPPORTED; 2726 2727 if (adv1G) 2728 phy_data |= E1000_EEE_ADV_1000_SUPPORTED; 2729 else 2730 phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED; 2731 2732 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2733 E1000_EEE_ADV_DEV_I354, 2734 phy_data); 2735 } else { 2736 /* Turn off EEE advertisement. */ 2737 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2738 E1000_EEE_ADV_DEV_I354, 2739 &phy_data); 2740 if (ret_val) 2741 goto out; 2742 2743 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED | 2744 E1000_EEE_ADV_1000_SUPPORTED); 2745 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354, 2746 E1000_EEE_ADV_DEV_I354, 2747 phy_data); 2748 } 2749 2750 out: 2751 return ret_val; 2752 } 2753 2754 /** 2755 * igb_get_eee_status_i354 - Get EEE status 2756 * @hw: pointer to the HW structure 2757 * @status: EEE status 2758 * 2759 * Get EEE status by guessing based on whether Tx or Rx LPI indications have 2760 * been received. 2761 **/ 2762 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status) 2763 { 2764 struct e1000_phy_info *phy = &hw->phy; 2765 s32 ret_val = 0; 2766 u16 phy_data; 2767 2768 /* Check if EEE is supported on this device. */ 2769 if ((hw->phy.media_type != e1000_media_type_copper) || 2770 ((phy->id != M88E1543_E_PHY_ID) && 2771 (phy->id != M88E1512_E_PHY_ID))) 2772 goto out; 2773 2774 ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354, 2775 E1000_PCS_STATUS_DEV_I354, 2776 &phy_data); 2777 if (ret_val) 2778 goto out; 2779 2780 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD | 2781 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false; 2782 2783 out: 2784 return ret_val; 2785 } 2786 2787 static const u8 e1000_emc_temp_data[4] = { 2788 E1000_EMC_INTERNAL_DATA, 2789 E1000_EMC_DIODE1_DATA, 2790 E1000_EMC_DIODE2_DATA, 2791 E1000_EMC_DIODE3_DATA 2792 }; 2793 static const u8 e1000_emc_therm_limit[4] = { 2794 E1000_EMC_INTERNAL_THERM_LIMIT, 2795 E1000_EMC_DIODE1_THERM_LIMIT, 2796 E1000_EMC_DIODE2_THERM_LIMIT, 2797 E1000_EMC_DIODE3_THERM_LIMIT 2798 }; 2799 2800 #ifdef CONFIG_IGB_HWMON 2801 /** 2802 * igb_get_thermal_sensor_data_generic - Gathers thermal sensor data 2803 * @hw: pointer to hardware structure 2804 * 2805 * Updates the temperatures in mac.thermal_sensor_data 2806 **/ 2807 static s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw) 2808 { 2809 u16 ets_offset; 2810 u16 ets_cfg; 2811 u16 ets_sensor; 2812 u8 num_sensors; 2813 u8 sensor_index; 2814 u8 sensor_location; 2815 u8 i; 2816 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 2817 2818 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0)) 2819 return E1000_NOT_IMPLEMENTED; 2820 2821 data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF); 2822 2823 /* Return the internal sensor only if ETS is unsupported */ 2824 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset); 2825 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) 2826 return 0; 2827 2828 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg); 2829 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT) 2830 != NVM_ETS_TYPE_EMC) 2831 return E1000_NOT_IMPLEMENTED; 2832 2833 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK); 2834 if (num_sensors > E1000_MAX_SENSORS) 2835 num_sensors = E1000_MAX_SENSORS; 2836 2837 for (i = 1; i < num_sensors; i++) { 2838 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor); 2839 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >> 2840 NVM_ETS_DATA_INDEX_SHIFT); 2841 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >> 2842 NVM_ETS_DATA_LOC_SHIFT); 2843 2844 if (sensor_location != 0) 2845 hw->phy.ops.read_i2c_byte(hw, 2846 e1000_emc_temp_data[sensor_index], 2847 E1000_I2C_THERMAL_SENSOR_ADDR, 2848 &data->sensor[i].temp); 2849 } 2850 return 0; 2851 } 2852 2853 /** 2854 * igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds 2855 * @hw: pointer to hardware structure 2856 * 2857 * Sets the thermal sensor thresholds according to the NVM map 2858 * and save off the threshold and location values into mac.thermal_sensor_data 2859 **/ 2860 static s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw) 2861 { 2862 u16 ets_offset; 2863 u16 ets_cfg; 2864 u16 ets_sensor; 2865 u8 low_thresh_delta; 2866 u8 num_sensors; 2867 u8 sensor_index; 2868 u8 sensor_location; 2869 u8 therm_limit; 2870 u8 i; 2871 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data; 2872 2873 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0)) 2874 return E1000_NOT_IMPLEMENTED; 2875 2876 memset(data, 0, sizeof(struct e1000_thermal_sensor_data)); 2877 2878 data->sensor[0].location = 0x1; 2879 data->sensor[0].caution_thresh = 2880 (rd32(E1000_THHIGHTC) & 0xFF); 2881 data->sensor[0].max_op_thresh = 2882 (rd32(E1000_THLOWTC) & 0xFF); 2883 2884 /* Return the internal sensor only if ETS is unsupported */ 2885 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset); 2886 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) 2887 return 0; 2888 2889 hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg); 2890 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT) 2891 != NVM_ETS_TYPE_EMC) 2892 return E1000_NOT_IMPLEMENTED; 2893 2894 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >> 2895 NVM_ETS_LTHRES_DELTA_SHIFT); 2896 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK); 2897 2898 for (i = 1; i <= num_sensors; i++) { 2899 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor); 2900 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >> 2901 NVM_ETS_DATA_INDEX_SHIFT); 2902 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >> 2903 NVM_ETS_DATA_LOC_SHIFT); 2904 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK; 2905 2906 hw->phy.ops.write_i2c_byte(hw, 2907 e1000_emc_therm_limit[sensor_index], 2908 E1000_I2C_THERMAL_SENSOR_ADDR, 2909 therm_limit); 2910 2911 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) { 2912 data->sensor[i].location = sensor_location; 2913 data->sensor[i].caution_thresh = therm_limit; 2914 data->sensor[i].max_op_thresh = therm_limit - 2915 low_thresh_delta; 2916 } 2917 } 2918 return 0; 2919 } 2920 2921 #endif 2922 static struct e1000_mac_operations e1000_mac_ops_82575 = { 2923 .init_hw = igb_init_hw_82575, 2924 .check_for_link = igb_check_for_link_82575, 2925 .rar_set = igb_rar_set, 2926 .read_mac_addr = igb_read_mac_addr_82575, 2927 .get_speed_and_duplex = igb_get_link_up_info_82575, 2928 #ifdef CONFIG_IGB_HWMON 2929 .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic, 2930 .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic, 2931 #endif 2932 }; 2933 2934 static const struct e1000_phy_operations e1000_phy_ops_82575 = { 2935 .acquire = igb_acquire_phy_82575, 2936 .get_cfg_done = igb_get_cfg_done_82575, 2937 .release = igb_release_phy_82575, 2938 .write_i2c_byte = igb_write_i2c_byte, 2939 .read_i2c_byte = igb_read_i2c_byte, 2940 }; 2941 2942 static struct e1000_nvm_operations e1000_nvm_ops_82575 = { 2943 .acquire = igb_acquire_nvm_82575, 2944 .read = igb_read_nvm_eerd, 2945 .release = igb_release_nvm_82575, 2946 .write = igb_write_nvm_spi, 2947 }; 2948 2949 const struct e1000_info e1000_82575_info = { 2950 .get_invariants = igb_get_invariants_82575, 2951 .mac_ops = &e1000_mac_ops_82575, 2952 .phy_ops = &e1000_phy_ops_82575, 2953 .nvm_ops = &e1000_nvm_ops_82575, 2954 }; 2955 2956