1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_TYPE_H_ 5 #define _ICE_TYPE_H_ 6 7 #define ICE_BYTES_PER_WORD 2 8 #define ICE_BYTES_PER_DWORD 4 9 10 #include "ice_status.h" 11 #include "ice_hw_autogen.h" 12 #include "ice_osdep.h" 13 #include "ice_controlq.h" 14 #include "ice_lan_tx_rx.h" 15 #include "ice_flex_type.h" 16 #include "ice_protocol_type.h" 17 18 static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc) 19 { 20 return test_bit(tc, &bitmap); 21 } 22 23 static inline u64 round_up_64bit(u64 a, u32 b) 24 { 25 return div64_long(((a) + (b) / 2), (b)); 26 } 27 28 static inline u32 ice_round_to_num(u32 N, u32 R) 29 { 30 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) : 31 ((((N) + (R) - 1) / (R)) * (R))); 32 } 33 34 /* Driver always calls main vsi_handle first */ 35 #define ICE_MAIN_VSI_HANDLE 0 36 37 /* debug masks - set these bits in hw->debug_mask to control output */ 38 #define ICE_DBG_INIT BIT_ULL(1) 39 #define ICE_DBG_FW_LOG BIT_ULL(3) 40 #define ICE_DBG_LINK BIT_ULL(4) 41 #define ICE_DBG_PHY BIT_ULL(5) 42 #define ICE_DBG_QCTX BIT_ULL(6) 43 #define ICE_DBG_NVM BIT_ULL(7) 44 #define ICE_DBG_LAN BIT_ULL(8) 45 #define ICE_DBG_FLOW BIT_ULL(9) 46 #define ICE_DBG_SW BIT_ULL(13) 47 #define ICE_DBG_SCHED BIT_ULL(14) 48 #define ICE_DBG_PKG BIT_ULL(16) 49 #define ICE_DBG_RES BIT_ULL(17) 50 #define ICE_DBG_AQ_MSG BIT_ULL(24) 51 #define ICE_DBG_AQ_DESC BIT_ULL(25) 52 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26) 53 #define ICE_DBG_AQ_CMD BIT_ULL(27) 54 #define ICE_DBG_USER BIT_ULL(31) 55 56 enum ice_aq_res_ids { 57 ICE_NVM_RES_ID = 1, 58 ICE_SPD_RES_ID, 59 ICE_CHANGE_LOCK_RES_ID, 60 ICE_GLOBAL_CFG_LOCK_RES_ID 61 }; 62 63 /* FW update timeout definitions are in milliseconds */ 64 #define ICE_NVM_TIMEOUT 180000 65 #define ICE_CHANGE_LOCK_TIMEOUT 1000 66 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000 67 68 enum ice_aq_res_access_type { 69 ICE_RES_READ = 1, 70 ICE_RES_WRITE 71 }; 72 73 struct ice_driver_ver { 74 u8 major_ver; 75 u8 minor_ver; 76 u8 build_ver; 77 u8 subbuild_ver; 78 u8 driver_string[32]; 79 }; 80 81 enum ice_fc_mode { 82 ICE_FC_NONE = 0, 83 ICE_FC_RX_PAUSE, 84 ICE_FC_TX_PAUSE, 85 ICE_FC_FULL, 86 ICE_FC_PFC, 87 ICE_FC_DFLT 88 }; 89 90 enum ice_phy_cache_mode { 91 ICE_FC_MODE = 0, 92 ICE_SPEED_MODE, 93 ICE_FEC_MODE 94 }; 95 96 enum ice_fec_mode { 97 ICE_FEC_NONE = 0, 98 ICE_FEC_RS, 99 ICE_FEC_BASER, 100 ICE_FEC_AUTO 101 }; 102 103 struct ice_phy_cache_mode_data { 104 union { 105 enum ice_fec_mode curr_user_fec_req; 106 enum ice_fc_mode curr_user_fc_req; 107 u16 curr_user_speed_req; 108 } data; 109 }; 110 111 enum ice_set_fc_aq_failures { 112 ICE_SET_FC_AQ_FAIL_NONE = 0, 113 ICE_SET_FC_AQ_FAIL_GET, 114 ICE_SET_FC_AQ_FAIL_SET, 115 ICE_SET_FC_AQ_FAIL_UPDATE 116 }; 117 118 /* Various MAC types */ 119 enum ice_mac_type { 120 ICE_MAC_UNKNOWN = 0, 121 ICE_MAC_E810, 122 ICE_MAC_GENERIC, 123 }; 124 125 /* Media Types */ 126 enum ice_media_type { 127 ICE_MEDIA_UNKNOWN = 0, 128 ICE_MEDIA_FIBER, 129 ICE_MEDIA_BASET, 130 ICE_MEDIA_BACKPLANE, 131 ICE_MEDIA_DA, 132 }; 133 134 enum ice_vsi_type { 135 ICE_VSI_PF = 0, 136 ICE_VSI_VF = 1, 137 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */ 138 ICE_VSI_LB = 6, 139 }; 140 141 struct ice_link_status { 142 /* Refer to ice_aq_phy_type for bits definition */ 143 u64 phy_type_low; 144 u64 phy_type_high; 145 u8 topo_media_conflict; 146 u16 max_frame_size; 147 u16 link_speed; 148 u16 req_speeds; 149 u8 lse_ena; /* Link Status Event notification */ 150 u8 link_info; 151 u8 an_info; 152 u8 ext_info; 153 u8 fec_info; 154 u8 pacing; 155 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of 156 * ice_aqc_get_phy_caps structure 157 */ 158 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 159 }; 160 161 /* Different reset sources for which a disable queue AQ call has to be made in 162 * order to clean the Tx scheduler as a part of the reset 163 */ 164 enum ice_disq_rst_src { 165 ICE_NO_RESET = 0, 166 ICE_VM_RESET, 167 ICE_VF_RESET, 168 }; 169 170 /* PHY info such as phy_type, etc... */ 171 struct ice_phy_info { 172 struct ice_link_status link_info; 173 struct ice_link_status link_info_old; 174 u64 phy_type_low; 175 u64 phy_type_high; 176 enum ice_media_type media_type; 177 u8 get_link_info; 178 /* Please refer to struct ice_aqc_get_link_status_data to get 179 * detail of enable bit in curr_user_speed_req 180 */ 181 u16 curr_user_speed_req; 182 enum ice_fec_mode curr_user_fec_req; 183 enum ice_fc_mode curr_user_fc_req; 184 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg; 185 }; 186 187 /* protocol enumeration for filters */ 188 enum ice_fltr_ptype { 189 /* NONE - used for undef/error */ 190 ICE_FLTR_PTYPE_NONF_NONE = 0, 191 ICE_FLTR_PTYPE_NONF_IPV4_UDP, 192 ICE_FLTR_PTYPE_NONF_IPV4_TCP, 193 ICE_FLTR_PTYPE_NONF_IPV4_SCTP, 194 ICE_FLTR_PTYPE_NONF_IPV4_OTHER, 195 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP, 196 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP, 197 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP, 198 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER, 199 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER, 200 ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3, 201 ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3, 202 ICE_FLTR_PTYPE_NONF_IPV4_ESP, 203 ICE_FLTR_PTYPE_NONF_IPV6_ESP, 204 ICE_FLTR_PTYPE_NONF_IPV4_AH, 205 ICE_FLTR_PTYPE_NONF_IPV6_AH, 206 ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP, 207 ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP, 208 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE, 209 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION, 210 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE, 211 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION, 212 ICE_FLTR_PTYPE_NON_IP_L2, 213 ICE_FLTR_PTYPE_FRAG_IPV4, 214 ICE_FLTR_PTYPE_NONF_IPV6_UDP, 215 ICE_FLTR_PTYPE_NONF_IPV6_TCP, 216 ICE_FLTR_PTYPE_NONF_IPV6_SCTP, 217 ICE_FLTR_PTYPE_NONF_IPV6_OTHER, 218 ICE_FLTR_PTYPE_MAX, 219 }; 220 221 enum ice_fd_hw_seg { 222 ICE_FD_HW_SEG_NON_TUN = 0, 223 ICE_FD_HW_SEG_TUN, 224 ICE_FD_HW_SEG_MAX, 225 }; 226 227 /* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */ 228 #define ICE_MAX_FDIR_VSI_PER_FILTER 2 229 230 struct ice_fd_hw_prof { 231 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX]; 232 int cnt; 233 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX]; 234 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER]; 235 }; 236 237 /* Common HW capabilities for SW use */ 238 struct ice_hw_common_caps { 239 u32 valid_functions; 240 /* DCB capabilities */ 241 u32 active_tc_bitmap; 242 u32 maxtc; 243 244 /* Tx/Rx queues */ 245 u16 num_rxq; /* Number/Total Rx queues */ 246 u16 rxq_first_id; /* First queue ID for Rx queues */ 247 u16 num_txq; /* Number/Total Tx queues */ 248 u16 txq_first_id; /* First queue ID for Tx queues */ 249 250 /* MSI-X vectors */ 251 u16 num_msix_vectors; 252 u16 msix_vector_first_id; 253 254 /* Max MTU for function or device */ 255 u16 max_mtu; 256 257 /* Virtualization support */ 258 u8 sr_iov_1_1; /* SR-IOV enabled */ 259 260 /* RSS related capabilities */ 261 u16 rss_table_size; /* 512 for PFs and 64 for VFs */ 262 u8 rss_table_entry_width; /* RSS Entry width in bits */ 263 264 u8 dcb; 265 266 bool nvm_update_pending_nvm; 267 bool nvm_update_pending_orom; 268 bool nvm_update_pending_netlist; 269 #define ICE_NVM_PENDING_NVM_IMAGE BIT(0) 270 #define ICE_NVM_PENDING_OROM BIT(1) 271 #define ICE_NVM_PENDING_NETLIST BIT(2) 272 bool nvm_unified_update; 273 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) 274 }; 275 276 /* Function specific capabilities */ 277 struct ice_hw_func_caps { 278 struct ice_hw_common_caps common_cap; 279 u32 num_allocd_vfs; /* Number of allocated VFs */ 280 u32 vf_base_id; /* Logical ID of the first VF */ 281 u32 guar_num_vsi; 282 u32 fd_fltr_guar; /* Number of filters guaranteed */ 283 u32 fd_fltr_best_effort; /* Number of best effort filters */ 284 }; 285 286 /* Device wide capabilities */ 287 struct ice_hw_dev_caps { 288 struct ice_hw_common_caps common_cap; 289 u32 num_vfs_exposed; /* Total number of VFs exposed */ 290 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ 291 u32 num_flow_director_fltr; /* Number of FD filters available */ 292 u32 num_funcs; 293 }; 294 295 /* MAC info */ 296 struct ice_mac_info { 297 u8 lan_addr[ETH_ALEN]; 298 u8 perm_addr[ETH_ALEN]; 299 }; 300 301 /* Reset types used to determine which kind of reset was requested. These 302 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register. 303 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register 304 * because its reset source is different than the other types listed. 305 */ 306 enum ice_reset_req { 307 ICE_RESET_POR = 0, 308 ICE_RESET_INVAL = 0, 309 ICE_RESET_CORER = 1, 310 ICE_RESET_GLOBR = 2, 311 ICE_RESET_EMPR = 3, 312 ICE_RESET_PFR = 4, 313 }; 314 315 /* Bus parameters */ 316 struct ice_bus_info { 317 u16 device; 318 u8 func; 319 }; 320 321 /* Flow control (FC) parameters */ 322 struct ice_fc_info { 323 enum ice_fc_mode current_mode; /* FC mode in effect */ 324 enum ice_fc_mode req_mode; /* FC mode requested by caller */ 325 }; 326 327 /* Option ROM version information */ 328 struct ice_orom_info { 329 u8 major; /* Major version of OROM */ 330 u8 patch; /* Patch version of OROM */ 331 u16 build; /* Build version of OROM */ 332 }; 333 334 /* NVM version information */ 335 struct ice_nvm_info { 336 u32 eetrack; 337 u8 major; 338 u8 minor; 339 }; 340 341 /* netlist version information */ 342 struct ice_netlist_info { 343 u32 major; /* major high/low */ 344 u32 minor; /* minor high/low */ 345 u32 type; /* type high/low */ 346 u32 rev; /* revision high/low */ 347 u32 hash; /* SHA-1 hash word */ 348 u16 cust_ver; /* customer version */ 349 }; 350 351 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules 352 * of the flash image. 353 */ 354 enum ice_flash_bank { 355 ICE_INVALID_FLASH_BANK, 356 ICE_1ST_FLASH_BANK, 357 ICE_2ND_FLASH_BANK, 358 }; 359 360 /* Enumeration of which flash bank is desired to read from, either the active 361 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from 362 * code which just wants to read the active or inactive flash bank. 363 */ 364 enum ice_bank_select { 365 ICE_ACTIVE_FLASH_BANK, 366 ICE_INACTIVE_FLASH_BANK, 367 }; 368 369 /* information for accessing NVM, OROM, and Netlist flash banks */ 370 struct ice_bank_info { 371 u32 nvm_ptr; /* Pointer to 1st NVM bank */ 372 u32 nvm_size; /* Size of NVM bank */ 373 u32 orom_ptr; /* Pointer to 1st OROM bank */ 374 u32 orom_size; /* Size of OROM bank */ 375 u32 netlist_ptr; /* Pointer to 1st Netlist bank */ 376 u32 netlist_size; /* Size of Netlist bank */ 377 enum ice_flash_bank nvm_bank; /* Active NVM bank */ 378 enum ice_flash_bank orom_bank; /* Active OROM bank */ 379 enum ice_flash_bank netlist_bank; /* Active Netlist bank */ 380 }; 381 382 /* Flash Chip Information */ 383 struct ice_flash_info { 384 struct ice_orom_info orom; /* Option ROM version info */ 385 struct ice_nvm_info nvm; /* NVM version information */ 386 struct ice_netlist_info netlist;/* Netlist version info */ 387 struct ice_bank_info banks; /* Flash Bank information */ 388 u16 sr_words; /* Shadow RAM size in words */ 389 u32 flash_size; /* Size of available flash in bytes */ 390 u8 blank_nvm_mode; /* is NVM empty (no FW present) */ 391 }; 392 393 struct ice_link_default_override_tlv { 394 u8 options; 395 #define ICE_LINK_OVERRIDE_OPT_M 0x3F 396 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0) 397 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1) 398 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2) 399 #define ICE_LINK_OVERRIDE_EN BIT(3) 400 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4) 401 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5) 402 u8 phy_config; 403 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8 404 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S) 405 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3 406 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6) 407 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7) 408 u8 fec_options; 409 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF 410 u8 rsvd1; 411 u64 phy_type_low; 412 u64 phy_type_high; 413 }; 414 415 #define ICE_NVM_VER_LEN 32 416 417 /* Max number of port to queue branches w.r.t topology */ 418 #define ICE_MAX_TRAFFIC_CLASS 8 419 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS 420 421 #define ice_for_each_traffic_class(_i) \ 422 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++) 423 424 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects 425 * to driver defined policy for default aggregator 426 */ 427 #define ICE_INVAL_TEID 0xFFFFFFFF 428 #define ICE_DFLT_AGG_ID 0 429 430 struct ice_sched_node { 431 struct ice_sched_node *parent; 432 struct ice_sched_node *sibling; /* next sibling in the same layer */ 433 struct ice_sched_node **children; 434 struct ice_aqc_txsched_elem_data info; 435 u32 agg_id; /* aggregator group ID */ 436 u16 vsi_handle; 437 u8 in_use; /* suspended or in use */ 438 u8 tx_sched_layer; /* Logical Layer (1-9) */ 439 u8 num_children; 440 u8 tc_num; 441 u8 owner; 442 #define ICE_SCHED_NODE_OWNER_LAN 0 443 }; 444 445 /* Access Macros for Tx Sched Elements data */ 446 #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid) 447 448 /* The aggregator type determines if identifier is for a VSI group, 449 * aggregator group, aggregator of queues, or queue group. 450 */ 451 enum ice_agg_type { 452 ICE_AGG_TYPE_UNKNOWN = 0, 453 ICE_AGG_TYPE_VSI, 454 ICE_AGG_TYPE_AGG, /* aggregator */ 455 ICE_AGG_TYPE_Q, 456 ICE_AGG_TYPE_QG 457 }; 458 459 /* Rate limit types */ 460 enum ice_rl_type { 461 ICE_UNKNOWN_BW = 0, 462 ICE_MIN_BW, /* for CIR profile */ 463 ICE_MAX_BW, /* for EIR profile */ 464 ICE_SHARED_BW /* for shared profile */ 465 }; 466 467 #define ICE_SCHED_MIN_BW 500 /* in Kbps */ 468 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */ 469 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */ 470 #define ICE_SCHED_DFLT_RL_PROF_ID 0 471 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF 472 #define ICE_SCHED_DFLT_BW_WT 4 473 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF 474 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */ 475 476 /* Data structure for saving BW information */ 477 enum ice_bw_type { 478 ICE_BW_TYPE_PRIO, 479 ICE_BW_TYPE_CIR, 480 ICE_BW_TYPE_CIR_WT, 481 ICE_BW_TYPE_EIR, 482 ICE_BW_TYPE_EIR_WT, 483 ICE_BW_TYPE_SHARED, 484 ICE_BW_TYPE_CNT /* This must be last */ 485 }; 486 487 struct ice_bw { 488 u32 bw; 489 u16 bw_alloc; 490 }; 491 492 struct ice_bw_type_info { 493 DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT); 494 u8 generic; 495 struct ice_bw cir_bw; 496 struct ice_bw eir_bw; 497 u32 shared_bw; 498 }; 499 500 /* VSI queue context structure for given TC */ 501 struct ice_q_ctx { 502 u16 q_handle; 503 u32 q_teid; 504 /* bw_t_info saves queue BW information */ 505 struct ice_bw_type_info bw_t_info; 506 }; 507 508 /* VSI type list entry to locate corresponding VSI/aggregator nodes */ 509 struct ice_sched_vsi_info { 510 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS]; 511 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS]; 512 struct list_head list_entry; 513 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS]; 514 }; 515 516 /* driver defines the policy */ 517 struct ice_sched_tx_policy { 518 u16 max_num_vsis; 519 u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS]; 520 u8 rdma_ena; 521 }; 522 523 /* CEE or IEEE 802.1Qaz ETS Configuration data */ 524 struct ice_dcb_ets_cfg { 525 u8 willing; 526 u8 cbs; 527 u8 maxtcs; 528 u8 prio_table[ICE_MAX_TRAFFIC_CLASS]; 529 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS]; 530 u8 tsatable[ICE_MAX_TRAFFIC_CLASS]; 531 }; 532 533 /* CEE or IEEE 802.1Qaz PFC Configuration data */ 534 struct ice_dcb_pfc_cfg { 535 u8 willing; 536 u8 mbc; 537 u8 pfccap; 538 u8 pfcena; 539 }; 540 541 /* CEE or IEEE 802.1Qaz Application Priority data */ 542 struct ice_dcb_app_priority_table { 543 u16 prot_id; 544 u8 priority; 545 u8 selector; 546 }; 547 548 #define ICE_MAX_USER_PRIORITY 8 549 #define ICE_DCBX_MAX_APPS 32 550 #define ICE_LLDPDU_SIZE 1500 551 #define ICE_TLV_STATUS_OPER 0x1 552 #define ICE_TLV_STATUS_SYNC 0x2 553 #define ICE_TLV_STATUS_ERR 0x4 554 #define ICE_APP_PROT_ID_ISCSI_860 0x035c 555 #define ICE_APP_SEL_ETHTYPE 0x1 556 #define ICE_APP_SEL_TCPIP 0x2 557 #define ICE_CEE_APP_SEL_ETHTYPE 0x0 558 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134 559 #define ICE_CEE_APP_SEL_TCPIP 0x1 560 561 struct ice_dcbx_cfg { 562 u32 numapps; 563 u32 tlv_status; /* CEE mode TLV status */ 564 struct ice_dcb_ets_cfg etscfg; 565 struct ice_dcb_ets_cfg etsrec; 566 struct ice_dcb_pfc_cfg pfc; 567 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS]; 568 u8 dcbx_mode; 569 #define ICE_DCBX_MODE_CEE 0x1 570 #define ICE_DCBX_MODE_IEEE 0x2 571 u8 app_mode; 572 #define ICE_DCBX_APPS_NON_WILLING 0x1 573 }; 574 575 struct ice_qos_cfg { 576 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */ 577 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */ 578 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */ 579 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */ 580 u8 is_sw_lldp : 1; 581 }; 582 583 struct ice_port_info { 584 struct ice_sched_node *root; /* Root Node per Port */ 585 struct ice_hw *hw; /* back pointer to HW instance */ 586 u32 last_node_teid; /* scheduler last node info */ 587 u16 sw_id; /* Initial switch ID belongs to port */ 588 u16 pf_vf_num; 589 u8 port_state; 590 #define ICE_SCHED_PORT_STATE_INIT 0x0 591 #define ICE_SCHED_PORT_STATE_READY 0x1 592 u8 lport; 593 #define ICE_LPORT_MASK 0xff 594 u16 dflt_tx_vsi_rule_id; 595 u16 dflt_tx_vsi_num; 596 u16 dflt_rx_vsi_rule_id; 597 u16 dflt_rx_vsi_num; 598 struct ice_fc_info fc; 599 struct ice_mac_info mac; 600 struct ice_phy_info phy; 601 struct mutex sched_lock; /* protect access to TXSched tree */ 602 struct ice_sched_node * 603 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM]; 604 /* List contain profile ID(s) and other params per layer */ 605 struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 606 struct ice_qos_cfg qos_cfg; 607 u8 is_vf:1; 608 }; 609 610 struct ice_switch_info { 611 struct list_head vsi_list_map_head; 612 struct ice_sw_recipe *recp_list; 613 }; 614 615 /* FW logging configuration */ 616 struct ice_fw_log_evnt { 617 u8 cfg : 4; /* New event enables to configure */ 618 u8 cur : 4; /* Current/active event enables */ 619 }; 620 621 struct ice_fw_log_cfg { 622 u8 cq_en : 1; /* FW logging is enabled via the control queue */ 623 u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */ 624 u8 actv_evnts; /* Cumulation of currently enabled log events */ 625 626 #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S) 627 #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S) 628 #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S) 629 #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S) 630 struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX]; 631 }; 632 633 /* Enum defining the different states of the mailbox snapshot in the 634 * PF-VF mailbox overflow detection algorithm. The snapshot can be in 635 * states: 636 * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot 637 * within the mailbox buffer. 638 * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot 639 * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the 640 * mailbox and mark any VFs sending more messages than the threshold limit set. 641 * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF. 642 */ 643 enum ice_mbx_snapshot_state { 644 ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0, 645 ICE_MAL_VF_DETECT_STATE_TRAVERSE, 646 ICE_MAL_VF_DETECT_STATE_DETECT, 647 ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF, 648 }; 649 650 /* Structure to hold information of the static snapshot and the mailbox 651 * buffer data used to generate and track the snapshot. 652 * 1. state: the state of the mailbox snapshot in the malicious VF 653 * detection state handler ice_mbx_vf_state_handler() 654 * 2. head: head of the mailbox snapshot in a circular mailbox buffer 655 * 3. tail: tail of the mailbox snapshot in a circular mailbox buffer 656 * 4. num_iterations: number of messages traversed in circular mailbox buffer 657 * 5. num_msg_proc: number of messages processed in mailbox 658 * 6. num_pending_arq: number of pending asynchronous messages 659 * 7. max_num_msgs_mbx: maximum messages in mailbox for currently 660 * serviced work item or interrupt. 661 */ 662 struct ice_mbx_snap_buffer_data { 663 enum ice_mbx_snapshot_state state; 664 u32 head; 665 u32 tail; 666 u32 num_iterations; 667 u16 num_msg_proc; 668 u16 num_pending_arq; 669 u16 max_num_msgs_mbx; 670 }; 671 672 /* Structure to track messages sent by VFs on mailbox: 673 * 1. vf_cntr: a counter array of VFs to track the number of 674 * asynchronous messages sent by each VF 675 * 2. vfcntr_len: number of entries in VF counter array 676 */ 677 struct ice_mbx_vf_counter { 678 u32 *vf_cntr; 679 u32 vfcntr_len; 680 }; 681 682 /* Structure to hold data relevant to the captured static snapshot 683 * of the PF-VF mailbox. 684 */ 685 struct ice_mbx_snapshot { 686 struct ice_mbx_snap_buffer_data mbx_buf; 687 struct ice_mbx_vf_counter mbx_vf; 688 }; 689 690 /* Structure to hold data to be used for capturing or updating a 691 * static snapshot. 692 * 1. num_msg_proc: number of messages processed in mailbox 693 * 2. num_pending_arq: number of pending asynchronous messages 694 * 3. max_num_msgs_mbx: maximum messages in mailbox for currently 695 * serviced work item or interrupt. 696 * 4. async_watermark_val: An upper threshold set by caller to determine 697 * if the pending arq count is large enough to assume that there is 698 * the possibility of a mailicious VF. 699 */ 700 struct ice_mbx_data { 701 u16 num_msg_proc; 702 u16 num_pending_arq; 703 u16 max_num_msgs_mbx; 704 u16 async_watermark_val; 705 }; 706 707 /* Port hardware description */ 708 struct ice_hw { 709 u8 __iomem *hw_addr; 710 void *back; 711 struct ice_aqc_layer_props *layer_info; 712 struct ice_port_info *port_info; 713 /* PSM clock frequency for calculating RL profile params */ 714 u32 psm_clk_freq; 715 u64 debug_mask; /* bitmap for debug mask */ 716 enum ice_mac_type mac_type; 717 718 u16 fd_ctr_base; /* FD counter base index */ 719 720 /* pci info */ 721 u16 device_id; 722 u16 vendor_id; 723 u16 subsystem_device_id; 724 u16 subsystem_vendor_id; 725 u8 revision_id; 726 727 u8 pf_id; /* device profile info */ 728 729 u16 max_burst_size; /* driver sets this value */ 730 731 /* Tx Scheduler values */ 732 u8 num_tx_sched_layers; 733 u8 num_tx_sched_phys_layers; 734 u8 flattened_layers; 735 u8 max_cgds; 736 u8 sw_entry_point_layer; 737 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 738 struct list_head agg_list; /* lists all aggregator */ 739 740 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI]; 741 u8 evb_veb; /* true for VEB, false for VEPA */ 742 u8 reset_ongoing; /* true if HW is in reset, false otherwise */ 743 struct ice_bus_info bus; 744 struct ice_flash_info flash; 745 struct ice_hw_dev_caps dev_caps; /* device capabilities */ 746 struct ice_hw_func_caps func_caps; /* function capabilities */ 747 748 struct ice_switch_info *switch_info; /* switch filter lists */ 749 750 /* Control Queue info */ 751 struct ice_ctl_q_info adminq; 752 struct ice_ctl_q_info mailboxq; 753 754 u8 api_branch; /* API branch version */ 755 u8 api_maj_ver; /* API major version */ 756 u8 api_min_ver; /* API minor version */ 757 u8 api_patch; /* API patch version */ 758 u8 fw_branch; /* firmware branch version */ 759 u8 fw_maj_ver; /* firmware major version */ 760 u8 fw_min_ver; /* firmware minor version */ 761 u8 fw_patch; /* firmware patch version */ 762 u32 fw_build; /* firmware build number */ 763 764 struct ice_fw_log_cfg fw_log; 765 766 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL 767 * register. Used for determining the ITR/INTRL granularity during 768 * initialization. 769 */ 770 #define ICE_MAX_AGG_BW_200G 0x0 771 #define ICE_MAX_AGG_BW_100G 0X1 772 #define ICE_MAX_AGG_BW_50G 0x2 773 #define ICE_MAX_AGG_BW_25G 0x3 774 /* ITR granularity for different speeds */ 775 #define ICE_ITR_GRAN_ABOVE_25 2 776 #define ICE_ITR_GRAN_MAX_25 4 777 /* ITR granularity in 1 us */ 778 u8 itr_gran; 779 /* INTRL granularity for different speeds */ 780 #define ICE_INTRL_GRAN_ABOVE_25 4 781 #define ICE_INTRL_GRAN_MAX_25 8 782 /* INTRL granularity in 1 us */ 783 u8 intrl_gran; 784 785 u8 ucast_shared; /* true if VSIs can share unicast addr */ 786 787 /* Active package version (currently active) */ 788 struct ice_pkg_ver active_pkg_ver; 789 u32 active_track_id; 790 u8 active_pkg_name[ICE_PKG_NAME_SIZE]; 791 u8 active_pkg_in_nvm; 792 793 enum ice_aq_err pkg_dwnld_status; 794 795 /* Driver's package ver - (from the Ice Metadata section) */ 796 struct ice_pkg_ver pkg_ver; 797 u8 pkg_name[ICE_PKG_NAME_SIZE]; 798 799 /* Driver's Ice segment format version and ID (from the Ice seg) */ 800 struct ice_pkg_ver ice_seg_fmt_ver; 801 u8 ice_seg_id[ICE_SEG_ID_SIZE]; 802 803 /* Pointer to the ice segment */ 804 struct ice_seg *seg; 805 806 /* Pointer to allocated copy of pkg memory */ 807 u8 *pkg_copy; 808 u32 pkg_size; 809 810 /* tunneling info */ 811 struct mutex tnl_lock; 812 struct ice_tunnel_table tnl; 813 814 struct udp_tunnel_nic_shared udp_tunnel_shared; 815 struct udp_tunnel_nic_info udp_tunnel_nic; 816 817 /* HW block tables */ 818 struct ice_blk_info blk[ICE_BLK_COUNT]; 819 struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */ 820 struct list_head fl_profs[ICE_BLK_COUNT]; 821 822 /* Flow Director filter info */ 823 int fdir_active_fltr; 824 825 struct mutex fdir_fltr_lock; /* protect Flow Director */ 826 struct list_head fdir_list_head; 827 828 /* Book-keeping of side-band filter count per flow-type. 829 * This is used to detect and handle input set changes for 830 * respective flow-type. 831 */ 832 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX]; 833 834 struct ice_fd_hw_prof **fdir_prof; 835 DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX); 836 struct mutex rss_locks; /* protect RSS configuration */ 837 struct list_head rss_list_head; 838 struct ice_mbx_snapshot mbx_snapshot; 839 }; 840 841 /* Statistics collected by each port, VSI, VEB, and S-channel */ 842 struct ice_eth_stats { 843 u64 rx_bytes; /* gorc */ 844 u64 rx_unicast; /* uprc */ 845 u64 rx_multicast; /* mprc */ 846 u64 rx_broadcast; /* bprc */ 847 u64 rx_discards; /* rdpc */ 848 u64 rx_unknown_protocol; /* rupp */ 849 u64 tx_bytes; /* gotc */ 850 u64 tx_unicast; /* uptc */ 851 u64 tx_multicast; /* mptc */ 852 u64 tx_broadcast; /* bptc */ 853 u64 tx_discards; /* tdpc */ 854 u64 tx_errors; /* tepc */ 855 }; 856 857 #define ICE_MAX_UP 8 858 859 /* Statistics collected by the MAC */ 860 struct ice_hw_port_stats { 861 /* eth stats collected by the port */ 862 struct ice_eth_stats eth; 863 /* additional port specific stats */ 864 u64 tx_dropped_link_down; /* tdold */ 865 u64 crc_errors; /* crcerrs */ 866 u64 illegal_bytes; /* illerrc */ 867 u64 error_bytes; /* errbc */ 868 u64 mac_local_faults; /* mlfc */ 869 u64 mac_remote_faults; /* mrfc */ 870 u64 rx_len_errors; /* rlec */ 871 u64 link_xon_rx; /* lxonrxc */ 872 u64 link_xoff_rx; /* lxoffrxc */ 873 u64 link_xon_tx; /* lxontxc */ 874 u64 link_xoff_tx; /* lxofftxc */ 875 u64 priority_xon_rx[8]; /* pxonrxc[8] */ 876 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 877 u64 priority_xon_tx[8]; /* pxontxc[8] */ 878 u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 879 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 880 u64 rx_size_64; /* prc64 */ 881 u64 rx_size_127; /* prc127 */ 882 u64 rx_size_255; /* prc255 */ 883 u64 rx_size_511; /* prc511 */ 884 u64 rx_size_1023; /* prc1023 */ 885 u64 rx_size_1522; /* prc1522 */ 886 u64 rx_size_big; /* prc9522 */ 887 u64 rx_undersize; /* ruc */ 888 u64 rx_fragments; /* rfc */ 889 u64 rx_oversize; /* roc */ 890 u64 rx_jabber; /* rjc */ 891 u64 tx_size_64; /* ptc64 */ 892 u64 tx_size_127; /* ptc127 */ 893 u64 tx_size_255; /* ptc255 */ 894 u64 tx_size_511; /* ptc511 */ 895 u64 tx_size_1023; /* ptc1023 */ 896 u64 tx_size_1522; /* ptc1522 */ 897 u64 tx_size_big; /* ptc9522 */ 898 /* flow director stats */ 899 u32 fd_sb_status; 900 u64 fd_sb_match; 901 }; 902 903 struct ice_aq_get_set_rss_lut_params { 904 u16 vsi_handle; /* software VSI handle */ 905 u16 lut_size; /* size of the LUT buffer */ 906 u8 lut_type; /* type of the LUT (i.e. VSI, PF, Global) */ 907 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */ 908 u8 global_lut_id; /* only valid when lut_type is global */ 909 }; 910 911 /* Checksum and Shadow RAM pointers */ 912 #define ICE_SR_NVM_CTRL_WORD 0x00 913 #define ICE_SR_BOOT_CFG_PTR 0x132 914 #define ICE_SR_NVM_WOL_CFG 0x19 915 #define ICE_NVM_OROM_VER_OFF 0x02 916 #define ICE_SR_PBA_BLOCK_PTR 0x16 917 #define ICE_SR_NVM_DEV_STARTER_VER 0x18 918 #define ICE_SR_NVM_EETRACK_LO 0x2D 919 #define ICE_SR_NVM_EETRACK_HI 0x2E 920 #define ICE_NVM_VER_LO_SHIFT 0 921 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT) 922 #define ICE_NVM_VER_HI_SHIFT 12 923 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT) 924 #define ICE_OROM_VER_PATCH_SHIFT 0 925 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT) 926 #define ICE_OROM_VER_BUILD_SHIFT 8 927 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT) 928 #define ICE_OROM_VER_SHIFT 24 929 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT) 930 #define ICE_SR_PFA_PTR 0x40 931 #define ICE_SR_1ST_NVM_BANK_PTR 0x42 932 #define ICE_SR_NVM_BANK_SIZE 0x43 933 #define ICE_SR_1ST_OROM_BANK_PTR 0x44 934 #define ICE_SR_OROM_BANK_SIZE 0x45 935 #define ICE_SR_NETLIST_BANK_PTR 0x46 936 #define ICE_SR_NETLIST_BANK_SIZE 0x47 937 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800 938 939 /* CSS Header words */ 940 #define ICE_NVM_CSS_SREV_L 0x14 941 #define ICE_NVM_CSS_SREV_H 0x15 942 943 /* Length of CSS header section in words */ 944 #define ICE_CSS_HEADER_LENGTH 330 945 946 /* Offset of Shadow RAM copy in the NVM bank area. */ 947 #define ICE_NVM_SR_COPY_WORD_OFFSET roundup(ICE_CSS_HEADER_LENGTH, 32) 948 949 /* Size in bytes of Option ROM trailer */ 950 #define ICE_NVM_OROM_TRAILER_LENGTH (2 * ICE_CSS_HEADER_LENGTH) 951 952 /* The Link Topology Netlist section is stored as a series of words. It is 953 * stored in the NVM as a TLV, with the first two words containing the type 954 * and length. 955 */ 956 #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B 957 #define ICE_NETLIST_TYPE_OFFSET 0x0000 958 #define ICE_NETLIST_LEN_OFFSET 0x0001 959 960 /* The Link Topology section follows the TLV header. When reading the netlist 961 * using ice_read_netlist_module, we need to account for the 2-word TLV 962 * header. 963 */ 964 #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2) 965 966 #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000) 967 #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001) 968 969 #define ICE_LINK_TOPO_NODE_COUNT_M ICE_M(0x3FF, 0) 970 971 /* The Netlist ID Block is located after all of the Link Topology nodes. */ 972 #define ICE_NETLIST_ID_BLK_SIZE 0x30 973 #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n)) 974 975 /* netlist ID block field offsets (word offsets) */ 976 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02 977 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03 978 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04 979 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05 980 #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06 981 #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07 982 #define ICE_NETLIST_ID_BLK_REV_LOW 0x08 983 #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09 984 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n)) 985 #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F 986 987 /* Auxiliary field, mask, and shift definition for Shadow RAM and NVM Flash */ 988 #define ICE_SR_CTRL_WORD_1_S 0x06 989 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S) 990 #define ICE_SR_CTRL_WORD_VALID 0x1 991 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3) 992 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4) 993 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5) 994 995 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15) 996 997 /* Link override related */ 998 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10 999 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4 1000 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2 1001 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1 1002 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2 1003 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1 1004 #define ICE_FW_API_LINK_OVERRIDE_MIN 5 1005 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2 1006 1007 #define ICE_SR_WORDS_IN_1KB 512 1008 1009 /* Hash redirection LUT for VSI - maximum array size */ 1010 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4) 1011 1012 /* AQ API version for LLDP_FILTER_CONTROL */ 1013 #define ICE_FW_API_LLDP_FLTR_MAJ 1 1014 #define ICE_FW_API_LLDP_FLTR_MIN 7 1015 #define ICE_FW_API_LLDP_FLTR_PATCH 1 1016 1017 /* AQ API version for report default configuration */ 1018 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1 1019 #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7 1020 #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3 1021 1022 #endif /* _ICE_TYPE_H_ */ 1023