1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_TYPE_H_ 5 #define _ICE_TYPE_H_ 6 7 #define ICE_BYTES_PER_WORD 2 8 #define ICE_BYTES_PER_DWORD 4 9 #define ICE_CHNL_MAX_TC 16 10 11 #include "ice_hw_autogen.h" 12 #include "ice_devids.h" 13 #include "ice_osdep.h" 14 #include "ice_controlq.h" 15 #include "ice_lan_tx_rx.h" 16 #include "ice_flex_type.h" 17 #include "ice_protocol_type.h" 18 #include "ice_sbq_cmd.h" 19 #include "ice_vlan_mode.h" 20 21 static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc) 22 { 23 return test_bit(tc, &bitmap); 24 } 25 26 static inline u64 round_up_64bit(u64 a, u32 b) 27 { 28 return div64_long(((a) + (b) / 2), (b)); 29 } 30 31 static inline u32 ice_round_to_num(u32 N, u32 R) 32 { 33 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) : 34 ((((N) + (R) - 1) / (R)) * (R))); 35 } 36 37 /* Driver always calls main vsi_handle first */ 38 #define ICE_MAIN_VSI_HANDLE 0 39 40 /* debug masks - set these bits in hw->debug_mask to control output */ 41 #define ICE_DBG_INIT BIT_ULL(1) 42 #define ICE_DBG_FW_LOG BIT_ULL(3) 43 #define ICE_DBG_LINK BIT_ULL(4) 44 #define ICE_DBG_PHY BIT_ULL(5) 45 #define ICE_DBG_QCTX BIT_ULL(6) 46 #define ICE_DBG_NVM BIT_ULL(7) 47 #define ICE_DBG_LAN BIT_ULL(8) 48 #define ICE_DBG_FLOW BIT_ULL(9) 49 #define ICE_DBG_SW BIT_ULL(13) 50 #define ICE_DBG_SCHED BIT_ULL(14) 51 #define ICE_DBG_RDMA BIT_ULL(15) 52 #define ICE_DBG_PKG BIT_ULL(16) 53 #define ICE_DBG_RES BIT_ULL(17) 54 #define ICE_DBG_PTP BIT_ULL(19) 55 #define ICE_DBG_AQ_MSG BIT_ULL(24) 56 #define ICE_DBG_AQ_DESC BIT_ULL(25) 57 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26) 58 #define ICE_DBG_AQ_CMD BIT_ULL(27) 59 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \ 60 ICE_DBG_AQ_DESC | \ 61 ICE_DBG_AQ_DESC_BUF | \ 62 ICE_DBG_AQ_CMD) 63 64 #define ICE_DBG_USER BIT_ULL(31) 65 66 enum ice_aq_res_ids { 67 ICE_NVM_RES_ID = 1, 68 ICE_SPD_RES_ID, 69 ICE_CHANGE_LOCK_RES_ID, 70 ICE_GLOBAL_CFG_LOCK_RES_ID 71 }; 72 73 /* FW update timeout definitions are in milliseconds */ 74 #define ICE_NVM_TIMEOUT 180000 75 #define ICE_CHANGE_LOCK_TIMEOUT 1000 76 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 5000 77 78 enum ice_aq_res_access_type { 79 ICE_RES_READ = 1, 80 ICE_RES_WRITE 81 }; 82 83 struct ice_driver_ver { 84 u8 major_ver; 85 u8 minor_ver; 86 u8 build_ver; 87 u8 subbuild_ver; 88 u8 driver_string[32]; 89 }; 90 91 enum ice_fc_mode { 92 ICE_FC_NONE = 0, 93 ICE_FC_RX_PAUSE, 94 ICE_FC_TX_PAUSE, 95 ICE_FC_FULL, 96 ICE_FC_PFC, 97 ICE_FC_DFLT 98 }; 99 100 enum ice_phy_cache_mode { 101 ICE_FC_MODE = 0, 102 ICE_SPEED_MODE, 103 ICE_FEC_MODE 104 }; 105 106 enum ice_fec_mode { 107 ICE_FEC_NONE = 0, 108 ICE_FEC_RS, 109 ICE_FEC_BASER, 110 ICE_FEC_AUTO 111 }; 112 113 struct ice_phy_cache_mode_data { 114 union { 115 enum ice_fec_mode curr_user_fec_req; 116 enum ice_fc_mode curr_user_fc_req; 117 u16 curr_user_speed_req; 118 } data; 119 }; 120 121 enum ice_set_fc_aq_failures { 122 ICE_SET_FC_AQ_FAIL_NONE = 0, 123 ICE_SET_FC_AQ_FAIL_GET, 124 ICE_SET_FC_AQ_FAIL_SET, 125 ICE_SET_FC_AQ_FAIL_UPDATE 126 }; 127 128 /* Various MAC types */ 129 enum ice_mac_type { 130 ICE_MAC_UNKNOWN = 0, 131 ICE_MAC_E810, 132 ICE_MAC_GENERIC, 133 }; 134 135 /* Media Types */ 136 enum ice_media_type { 137 ICE_MEDIA_UNKNOWN = 0, 138 ICE_MEDIA_FIBER, 139 ICE_MEDIA_BASET, 140 ICE_MEDIA_BACKPLANE, 141 ICE_MEDIA_DA, 142 }; 143 144 enum ice_vsi_type { 145 ICE_VSI_PF = 0, 146 ICE_VSI_VF = 1, 147 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */ 148 ICE_VSI_CHNL = 4, 149 ICE_VSI_LB = 6, 150 ICE_VSI_SWITCHDEV_CTRL = 7, 151 }; 152 153 struct ice_link_status { 154 /* Refer to ice_aq_phy_type for bits definition */ 155 u64 phy_type_low; 156 u64 phy_type_high; 157 u8 topo_media_conflict; 158 u16 max_frame_size; 159 u16 link_speed; 160 u16 req_speeds; 161 u8 link_cfg_err; 162 u8 lse_ena; /* Link Status Event notification */ 163 u8 link_info; 164 u8 an_info; 165 u8 ext_info; 166 u8 fec_info; 167 u8 pacing; 168 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of 169 * ice_aqc_get_phy_caps structure 170 */ 171 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 172 }; 173 174 /* Different reset sources for which a disable queue AQ call has to be made in 175 * order to clean the Tx scheduler as a part of the reset 176 */ 177 enum ice_disq_rst_src { 178 ICE_NO_RESET = 0, 179 ICE_VM_RESET, 180 ICE_VF_RESET, 181 }; 182 183 /* PHY info such as phy_type, etc... */ 184 struct ice_phy_info { 185 struct ice_link_status link_info; 186 struct ice_link_status link_info_old; 187 u64 phy_type_low; 188 u64 phy_type_high; 189 enum ice_media_type media_type; 190 u8 get_link_info; 191 /* Please refer to struct ice_aqc_get_link_status_data to get 192 * detail of enable bit in curr_user_speed_req 193 */ 194 u16 curr_user_speed_req; 195 enum ice_fec_mode curr_user_fec_req; 196 enum ice_fc_mode curr_user_fc_req; 197 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg; 198 }; 199 200 /* protocol enumeration for filters */ 201 enum ice_fltr_ptype { 202 /* NONE - used for undef/error */ 203 ICE_FLTR_PTYPE_NONF_NONE = 0, 204 ICE_FLTR_PTYPE_NONF_IPV4_UDP, 205 ICE_FLTR_PTYPE_NONF_IPV4_TCP, 206 ICE_FLTR_PTYPE_NONF_IPV4_SCTP, 207 ICE_FLTR_PTYPE_NONF_IPV4_OTHER, 208 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP, 209 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP, 210 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP, 211 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER, 212 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER, 213 ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3, 214 ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3, 215 ICE_FLTR_PTYPE_NONF_IPV4_ESP, 216 ICE_FLTR_PTYPE_NONF_IPV6_ESP, 217 ICE_FLTR_PTYPE_NONF_IPV4_AH, 218 ICE_FLTR_PTYPE_NONF_IPV6_AH, 219 ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP, 220 ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP, 221 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE, 222 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION, 223 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE, 224 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION, 225 ICE_FLTR_PTYPE_NON_IP_L2, 226 ICE_FLTR_PTYPE_FRAG_IPV4, 227 ICE_FLTR_PTYPE_NONF_IPV6_UDP, 228 ICE_FLTR_PTYPE_NONF_IPV6_TCP, 229 ICE_FLTR_PTYPE_NONF_IPV6_SCTP, 230 ICE_FLTR_PTYPE_NONF_IPV6_OTHER, 231 ICE_FLTR_PTYPE_MAX, 232 }; 233 234 enum ice_fd_hw_seg { 235 ICE_FD_HW_SEG_NON_TUN = 0, 236 ICE_FD_HW_SEG_TUN, 237 ICE_FD_HW_SEG_MAX, 238 }; 239 240 /* 1 ICE_VSI_PF + 1 ICE_VSI_CTRL + ICE_CHNL_MAX_TC */ 241 #define ICE_MAX_FDIR_VSI_PER_FILTER (2 + ICE_CHNL_MAX_TC) 242 243 struct ice_fd_hw_prof { 244 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX]; 245 int cnt; 246 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX]; 247 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER]; 248 }; 249 250 /* Common HW capabilities for SW use */ 251 struct ice_hw_common_caps { 252 u32 valid_functions; 253 /* DCB capabilities */ 254 u32 active_tc_bitmap; 255 u32 maxtc; 256 257 /* Tx/Rx queues */ 258 u16 num_rxq; /* Number/Total Rx queues */ 259 u16 rxq_first_id; /* First queue ID for Rx queues */ 260 u16 num_txq; /* Number/Total Tx queues */ 261 u16 txq_first_id; /* First queue ID for Tx queues */ 262 263 /* MSI-X vectors */ 264 u16 num_msix_vectors; 265 u16 msix_vector_first_id; 266 267 /* Max MTU for function or device */ 268 u16 max_mtu; 269 270 /* Virtualization support */ 271 u8 sr_iov_1_1; /* SR-IOV enabled */ 272 273 /* RSS related capabilities */ 274 u16 rss_table_size; /* 512 for PFs and 64 for VFs */ 275 u8 rss_table_entry_width; /* RSS Entry width in bits */ 276 277 u8 dcb; 278 u8 ieee_1588; 279 u8 rdma; 280 281 bool nvm_update_pending_nvm; 282 bool nvm_update_pending_orom; 283 bool nvm_update_pending_netlist; 284 #define ICE_NVM_PENDING_NVM_IMAGE BIT(0) 285 #define ICE_NVM_PENDING_OROM BIT(1) 286 #define ICE_NVM_PENDING_NETLIST BIT(2) 287 bool nvm_unified_update; 288 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) 289 /* PCIe reset avoidance */ 290 bool pcie_reset_avoidance; 291 /* Post update reset restriction */ 292 bool reset_restrict_support; 293 }; 294 295 /* IEEE 1588 TIME_SYNC specific info */ 296 /* Function specific definitions */ 297 #define ICE_TS_FUNC_ENA_M BIT(0) 298 #define ICE_TS_SRC_TMR_OWND_M BIT(1) 299 #define ICE_TS_TMR_ENA_M BIT(2) 300 #define ICE_TS_TMR_IDX_OWND_S 4 301 #define ICE_TS_TMR_IDX_OWND_M BIT(4) 302 #define ICE_TS_CLK_FREQ_S 16 303 #define ICE_TS_CLK_FREQ_M ICE_M(0x7, ICE_TS_CLK_FREQ_S) 304 #define ICE_TS_CLK_SRC_S 20 305 #define ICE_TS_CLK_SRC_M BIT(20) 306 #define ICE_TS_TMR_IDX_ASSOC_S 24 307 #define ICE_TS_TMR_IDX_ASSOC_M BIT(24) 308 309 /* TIME_REF clock rate specification */ 310 enum ice_time_ref_freq { 311 ICE_TIME_REF_FREQ_25_000 = 0, 312 ICE_TIME_REF_FREQ_122_880 = 1, 313 ICE_TIME_REF_FREQ_125_000 = 2, 314 ICE_TIME_REF_FREQ_153_600 = 3, 315 ICE_TIME_REF_FREQ_156_250 = 4, 316 ICE_TIME_REF_FREQ_245_760 = 5, 317 318 NUM_ICE_TIME_REF_FREQ 319 }; 320 321 /* Clock source specification */ 322 enum ice_clk_src { 323 ICE_CLK_SRC_TCX0 = 0, /* Temperature compensated oscillator */ 324 ICE_CLK_SRC_TIME_REF = 1, /* Use TIME_REF reference clock */ 325 326 NUM_ICE_CLK_SRC 327 }; 328 329 struct ice_ts_func_info { 330 /* Function specific info */ 331 enum ice_time_ref_freq time_ref; 332 u8 clk_freq; 333 u8 clk_src; 334 u8 tmr_index_assoc; 335 u8 ena; 336 u8 tmr_index_owned; 337 u8 src_tmr_owned; 338 u8 tmr_ena; 339 }; 340 341 /* Device specific definitions */ 342 #define ICE_TS_TMR0_OWNR_M 0x7 343 #define ICE_TS_TMR0_OWND_M BIT(3) 344 #define ICE_TS_TMR1_OWNR_S 4 345 #define ICE_TS_TMR1_OWNR_M ICE_M(0x7, ICE_TS_TMR1_OWNR_S) 346 #define ICE_TS_TMR1_OWND_M BIT(7) 347 #define ICE_TS_DEV_ENA_M BIT(24) 348 #define ICE_TS_TMR0_ENA_M BIT(25) 349 #define ICE_TS_TMR1_ENA_M BIT(26) 350 #define ICE_TS_LL_TX_TS_READ_M BIT(28) 351 352 struct ice_ts_dev_info { 353 /* Device specific info */ 354 u32 ena_ports; 355 u32 tmr_own_map; 356 u32 tmr0_owner; 357 u32 tmr1_owner; 358 u8 tmr0_owned; 359 u8 tmr1_owned; 360 u8 ena; 361 u8 tmr0_ena; 362 u8 tmr1_ena; 363 u8 ts_ll_read; 364 }; 365 366 /* Function specific capabilities */ 367 struct ice_hw_func_caps { 368 struct ice_hw_common_caps common_cap; 369 u32 num_allocd_vfs; /* Number of allocated VFs */ 370 u32 vf_base_id; /* Logical ID of the first VF */ 371 u32 guar_num_vsi; 372 u32 fd_fltr_guar; /* Number of filters guaranteed */ 373 u32 fd_fltr_best_effort; /* Number of best effort filters */ 374 struct ice_ts_func_info ts_func_info; 375 }; 376 377 /* Device wide capabilities */ 378 struct ice_hw_dev_caps { 379 struct ice_hw_common_caps common_cap; 380 u32 num_vfs_exposed; /* Total number of VFs exposed */ 381 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ 382 u32 num_flow_director_fltr; /* Number of FD filters available */ 383 struct ice_ts_dev_info ts_dev_info; 384 u32 num_funcs; 385 }; 386 387 /* MAC info */ 388 struct ice_mac_info { 389 u8 lan_addr[ETH_ALEN]; 390 u8 perm_addr[ETH_ALEN]; 391 }; 392 393 /* Reset types used to determine which kind of reset was requested. These 394 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register. 395 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register 396 * because its reset source is different than the other types listed. 397 */ 398 enum ice_reset_req { 399 ICE_RESET_POR = 0, 400 ICE_RESET_INVAL = 0, 401 ICE_RESET_CORER = 1, 402 ICE_RESET_GLOBR = 2, 403 ICE_RESET_EMPR = 3, 404 ICE_RESET_PFR = 4, 405 }; 406 407 /* Bus parameters */ 408 struct ice_bus_info { 409 u16 device; 410 u8 func; 411 }; 412 413 /* Flow control (FC) parameters */ 414 struct ice_fc_info { 415 enum ice_fc_mode current_mode; /* FC mode in effect */ 416 enum ice_fc_mode req_mode; /* FC mode requested by caller */ 417 }; 418 419 /* Option ROM version information */ 420 struct ice_orom_info { 421 u8 major; /* Major version of OROM */ 422 u8 patch; /* Patch version of OROM */ 423 u16 build; /* Build version of OROM */ 424 }; 425 426 /* NVM version information */ 427 struct ice_nvm_info { 428 u32 eetrack; 429 u8 major; 430 u8 minor; 431 }; 432 433 /* netlist version information */ 434 struct ice_netlist_info { 435 u32 major; /* major high/low */ 436 u32 minor; /* minor high/low */ 437 u32 type; /* type high/low */ 438 u32 rev; /* revision high/low */ 439 u32 hash; /* SHA-1 hash word */ 440 u16 cust_ver; /* customer version */ 441 }; 442 443 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules 444 * of the flash image. 445 */ 446 enum ice_flash_bank { 447 ICE_INVALID_FLASH_BANK, 448 ICE_1ST_FLASH_BANK, 449 ICE_2ND_FLASH_BANK, 450 }; 451 452 /* Enumeration of which flash bank is desired to read from, either the active 453 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from 454 * code which just wants to read the active or inactive flash bank. 455 */ 456 enum ice_bank_select { 457 ICE_ACTIVE_FLASH_BANK, 458 ICE_INACTIVE_FLASH_BANK, 459 }; 460 461 /* information for accessing NVM, OROM, and Netlist flash banks */ 462 struct ice_bank_info { 463 u32 nvm_ptr; /* Pointer to 1st NVM bank */ 464 u32 nvm_size; /* Size of NVM bank */ 465 u32 orom_ptr; /* Pointer to 1st OROM bank */ 466 u32 orom_size; /* Size of OROM bank */ 467 u32 netlist_ptr; /* Pointer to 1st Netlist bank */ 468 u32 netlist_size; /* Size of Netlist bank */ 469 enum ice_flash_bank nvm_bank; /* Active NVM bank */ 470 enum ice_flash_bank orom_bank; /* Active OROM bank */ 471 enum ice_flash_bank netlist_bank; /* Active Netlist bank */ 472 }; 473 474 /* Flash Chip Information */ 475 struct ice_flash_info { 476 struct ice_orom_info orom; /* Option ROM version info */ 477 struct ice_nvm_info nvm; /* NVM version information */ 478 struct ice_netlist_info netlist;/* Netlist version info */ 479 struct ice_bank_info banks; /* Flash Bank information */ 480 u16 sr_words; /* Shadow RAM size in words */ 481 u32 flash_size; /* Size of available flash in bytes */ 482 u8 blank_nvm_mode; /* is NVM empty (no FW present) */ 483 }; 484 485 struct ice_link_default_override_tlv { 486 u8 options; 487 #define ICE_LINK_OVERRIDE_OPT_M 0x3F 488 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0) 489 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1) 490 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2) 491 #define ICE_LINK_OVERRIDE_EN BIT(3) 492 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4) 493 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5) 494 u8 phy_config; 495 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8 496 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S) 497 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3 498 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6) 499 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7) 500 u8 fec_options; 501 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF 502 u8 rsvd1; 503 u64 phy_type_low; 504 u64 phy_type_high; 505 }; 506 507 #define ICE_NVM_VER_LEN 32 508 509 /* Max number of port to queue branches w.r.t topology */ 510 #define ICE_MAX_TRAFFIC_CLASS 8 511 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS 512 513 #define ice_for_each_traffic_class(_i) \ 514 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++) 515 516 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects 517 * to driver defined policy for default aggregator 518 */ 519 #define ICE_INVAL_TEID 0xFFFFFFFF 520 #define ICE_DFLT_AGG_ID 0 521 522 struct ice_sched_node { 523 struct ice_sched_node *parent; 524 struct ice_sched_node *sibling; /* next sibling in the same layer */ 525 struct ice_sched_node **children; 526 struct ice_aqc_txsched_elem_data info; 527 char *name; 528 struct devlink_rate *rate_node; 529 u64 tx_max; 530 u64 tx_share; 531 u32 agg_id; /* aggregator group ID */ 532 u32 id; 533 u32 tx_priority; 534 u32 tx_weight; 535 u16 vsi_handle; 536 u8 in_use; /* suspended or in use */ 537 u8 tx_sched_layer; /* Logical Layer (1-9) */ 538 u8 num_children; 539 u8 tc_num; 540 u8 owner; 541 #define ICE_SCHED_NODE_OWNER_LAN 0 542 #define ICE_SCHED_NODE_OWNER_RDMA 2 543 }; 544 545 /* Access Macros for Tx Sched Elements data */ 546 #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid) 547 548 /* The aggregator type determines if identifier is for a VSI group, 549 * aggregator group, aggregator of queues, or queue group. 550 */ 551 enum ice_agg_type { 552 ICE_AGG_TYPE_UNKNOWN = 0, 553 ICE_AGG_TYPE_VSI, 554 ICE_AGG_TYPE_AGG, /* aggregator */ 555 ICE_AGG_TYPE_Q, 556 ICE_AGG_TYPE_QG 557 }; 558 559 /* Rate limit types */ 560 enum ice_rl_type { 561 ICE_UNKNOWN_BW = 0, 562 ICE_MIN_BW, /* for CIR profile */ 563 ICE_MAX_BW, /* for EIR profile */ 564 ICE_SHARED_BW /* for shared profile */ 565 }; 566 567 #define ICE_SCHED_MIN_BW 500 /* in Kbps */ 568 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */ 569 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */ 570 #define ICE_SCHED_DFLT_RL_PROF_ID 0 571 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF 572 #define ICE_SCHED_DFLT_BW_WT 4 573 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF 574 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */ 575 576 #define ICE_MAX_PORT_PER_PCI_DEV 8 577 578 /* Data structure for saving BW information */ 579 enum ice_bw_type { 580 ICE_BW_TYPE_PRIO, 581 ICE_BW_TYPE_CIR, 582 ICE_BW_TYPE_CIR_WT, 583 ICE_BW_TYPE_EIR, 584 ICE_BW_TYPE_EIR_WT, 585 ICE_BW_TYPE_SHARED, 586 ICE_BW_TYPE_CNT /* This must be last */ 587 }; 588 589 struct ice_bw { 590 u32 bw; 591 u16 bw_alloc; 592 }; 593 594 struct ice_bw_type_info { 595 DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT); 596 u8 generic; 597 struct ice_bw cir_bw; 598 struct ice_bw eir_bw; 599 u32 shared_bw; 600 }; 601 602 /* VSI queue context structure for given TC */ 603 struct ice_q_ctx { 604 u16 q_handle; 605 u32 q_teid; 606 /* bw_t_info saves queue BW information */ 607 struct ice_bw_type_info bw_t_info; 608 }; 609 610 /* VSI type list entry to locate corresponding VSI/aggregator nodes */ 611 struct ice_sched_vsi_info { 612 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS]; 613 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS]; 614 struct list_head list_entry; 615 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS]; 616 u16 max_rdmaq[ICE_MAX_TRAFFIC_CLASS]; 617 /* bw_t_info saves VSI BW information */ 618 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS]; 619 }; 620 621 /* driver defines the policy */ 622 struct ice_sched_tx_policy { 623 u16 max_num_vsis; 624 u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS]; 625 u8 rdma_ena; 626 }; 627 628 /* CEE or IEEE 802.1Qaz ETS Configuration data */ 629 struct ice_dcb_ets_cfg { 630 u8 willing; 631 u8 cbs; 632 u8 maxtcs; 633 u8 prio_table[ICE_MAX_TRAFFIC_CLASS]; 634 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS]; 635 u8 tsatable[ICE_MAX_TRAFFIC_CLASS]; 636 }; 637 638 /* CEE or IEEE 802.1Qaz PFC Configuration data */ 639 struct ice_dcb_pfc_cfg { 640 u8 willing; 641 u8 mbc; 642 u8 pfccap; 643 u8 pfcena; 644 }; 645 646 /* CEE or IEEE 802.1Qaz Application Priority data */ 647 struct ice_dcb_app_priority_table { 648 u16 prot_id; 649 u8 priority; 650 u8 selector; 651 }; 652 653 #define ICE_MAX_USER_PRIORITY 8 654 #define ICE_DCBX_MAX_APPS 64 655 #define ICE_DSCP_NUM_VAL 64 656 #define ICE_LLDPDU_SIZE 1500 657 #define ICE_TLV_STATUS_OPER 0x1 658 #define ICE_TLV_STATUS_SYNC 0x2 659 #define ICE_TLV_STATUS_ERR 0x4 660 #define ICE_APP_PROT_ID_ISCSI_860 0x035c 661 #define ICE_APP_SEL_ETHTYPE 0x1 662 #define ICE_APP_SEL_TCPIP 0x2 663 #define ICE_CEE_APP_SEL_ETHTYPE 0x0 664 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134 665 #define ICE_CEE_APP_SEL_TCPIP 0x1 666 667 struct ice_dcbx_cfg { 668 u32 numapps; 669 u32 tlv_status; /* CEE mode TLV status */ 670 struct ice_dcb_ets_cfg etscfg; 671 struct ice_dcb_ets_cfg etsrec; 672 struct ice_dcb_pfc_cfg pfc; 673 #define ICE_QOS_MODE_VLAN 0x0 674 #define ICE_QOS_MODE_DSCP 0x1 675 u8 pfc_mode; 676 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS]; 677 /* when DSCP mapping defined by user set its bit to 1 */ 678 DECLARE_BITMAP(dscp_mapped, ICE_DSCP_NUM_VAL); 679 /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */ 680 u8 dscp_map[ICE_DSCP_NUM_VAL]; 681 u8 dcbx_mode; 682 #define ICE_DCBX_MODE_CEE 0x1 683 #define ICE_DCBX_MODE_IEEE 0x2 684 u8 app_mode; 685 #define ICE_DCBX_APPS_NON_WILLING 0x1 686 }; 687 688 struct ice_qos_cfg { 689 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */ 690 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */ 691 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */ 692 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */ 693 u8 is_sw_lldp : 1; 694 }; 695 696 struct ice_port_info { 697 struct ice_sched_node *root; /* Root Node per Port */ 698 struct ice_hw *hw; /* back pointer to HW instance */ 699 u32 last_node_teid; /* scheduler last node info */ 700 u16 sw_id; /* Initial switch ID belongs to port */ 701 u16 pf_vf_num; 702 u8 port_state; 703 #define ICE_SCHED_PORT_STATE_INIT 0x0 704 #define ICE_SCHED_PORT_STATE_READY 0x1 705 u8 lport; 706 #define ICE_LPORT_MASK 0xff 707 struct ice_fc_info fc; 708 struct ice_mac_info mac; 709 struct ice_phy_info phy; 710 struct mutex sched_lock; /* protect access to TXSched tree */ 711 struct ice_sched_node * 712 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM]; 713 /* List contain profile ID(s) and other params per layer */ 714 struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 715 struct ice_qos_cfg qos_cfg; 716 struct xarray sched_node_ids; 717 u8 is_vf:1; 718 u8 is_custom_tx_enabled:1; 719 }; 720 721 struct ice_switch_info { 722 struct list_head vsi_list_map_head; 723 struct ice_sw_recipe *recp_list; 724 u16 prof_res_bm_init; 725 u16 max_used_prof_index; 726 727 DECLARE_BITMAP(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS); 728 }; 729 730 /* FW logging configuration */ 731 struct ice_fw_log_evnt { 732 u8 cfg : 4; /* New event enables to configure */ 733 u8 cur : 4; /* Current/active event enables */ 734 }; 735 736 struct ice_fw_log_cfg { 737 u8 cq_en : 1; /* FW logging is enabled via the control queue */ 738 u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */ 739 u8 actv_evnts; /* Cumulation of currently enabled log events */ 740 741 #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S) 742 #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S) 743 #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S) 744 #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S) 745 struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX]; 746 }; 747 748 /* Enum defining the different states of the mailbox snapshot in the 749 * PF-VF mailbox overflow detection algorithm. The snapshot can be in 750 * states: 751 * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot 752 * within the mailbox buffer. 753 * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot 754 * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the 755 * mailbox and mark any VFs sending more messages than the threshold limit set. 756 * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF. 757 */ 758 enum ice_mbx_snapshot_state { 759 ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0, 760 ICE_MAL_VF_DETECT_STATE_TRAVERSE, 761 ICE_MAL_VF_DETECT_STATE_DETECT, 762 ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF, 763 }; 764 765 /* Structure to hold information of the static snapshot and the mailbox 766 * buffer data used to generate and track the snapshot. 767 * 1. state: the state of the mailbox snapshot in the malicious VF 768 * detection state handler ice_mbx_vf_state_handler() 769 * 2. head: head of the mailbox snapshot in a circular mailbox buffer 770 * 3. tail: tail of the mailbox snapshot in a circular mailbox buffer 771 * 4. num_iterations: number of messages traversed in circular mailbox buffer 772 * 5. num_msg_proc: number of messages processed in mailbox 773 * 6. num_pending_arq: number of pending asynchronous messages 774 * 7. max_num_msgs_mbx: maximum messages in mailbox for currently 775 * serviced work item or interrupt. 776 */ 777 struct ice_mbx_snap_buffer_data { 778 enum ice_mbx_snapshot_state state; 779 u32 head; 780 u32 tail; 781 u32 num_iterations; 782 u16 num_msg_proc; 783 u16 num_pending_arq; 784 u16 max_num_msgs_mbx; 785 }; 786 787 /* Structure to track messages sent by VFs on mailbox: 788 * 1. vf_cntr: a counter array of VFs to track the number of 789 * asynchronous messages sent by each VF 790 * 2. vfcntr_len: number of entries in VF counter array 791 */ 792 struct ice_mbx_vf_counter { 793 u32 *vf_cntr; 794 u32 vfcntr_len; 795 }; 796 797 /* Structure to hold data relevant to the captured static snapshot 798 * of the PF-VF mailbox. 799 */ 800 struct ice_mbx_snapshot { 801 struct ice_mbx_snap_buffer_data mbx_buf; 802 struct ice_mbx_vf_counter mbx_vf; 803 }; 804 805 /* Structure to hold data to be used for capturing or updating a 806 * static snapshot. 807 * 1. num_msg_proc: number of messages processed in mailbox 808 * 2. num_pending_arq: number of pending asynchronous messages 809 * 3. max_num_msgs_mbx: maximum messages in mailbox for currently 810 * serviced work item or interrupt. 811 * 4. async_watermark_val: An upper threshold set by caller to determine 812 * if the pending arq count is large enough to assume that there is 813 * the possibility of a mailicious VF. 814 */ 815 struct ice_mbx_data { 816 u16 num_msg_proc; 817 u16 num_pending_arq; 818 u16 max_num_msgs_mbx; 819 u16 async_watermark_val; 820 }; 821 822 /* Port hardware description */ 823 struct ice_hw { 824 u8 __iomem *hw_addr; 825 void *back; 826 struct ice_aqc_layer_props *layer_info; 827 struct ice_port_info *port_info; 828 /* PSM clock frequency for calculating RL profile params */ 829 u32 psm_clk_freq; 830 u64 debug_mask; /* bitmap for debug mask */ 831 enum ice_mac_type mac_type; 832 833 u16 fd_ctr_base; /* FD counter base index */ 834 835 /* pci info */ 836 u16 device_id; 837 u16 vendor_id; 838 u16 subsystem_device_id; 839 u16 subsystem_vendor_id; 840 u8 revision_id; 841 842 u8 pf_id; /* device profile info */ 843 844 u16 max_burst_size; /* driver sets this value */ 845 846 /* Tx Scheduler values */ 847 u8 num_tx_sched_layers; 848 u8 num_tx_sched_phys_layers; 849 u8 flattened_layers; 850 u8 max_cgds; 851 u8 sw_entry_point_layer; 852 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 853 struct list_head agg_list; /* lists all aggregator */ 854 855 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI]; 856 u8 evb_veb; /* true for VEB, false for VEPA */ 857 u8 reset_ongoing; /* true if HW is in reset, false otherwise */ 858 struct ice_bus_info bus; 859 struct ice_flash_info flash; 860 struct ice_hw_dev_caps dev_caps; /* device capabilities */ 861 struct ice_hw_func_caps func_caps; /* function capabilities */ 862 863 struct ice_switch_info *switch_info; /* switch filter lists */ 864 865 /* Control Queue info */ 866 struct ice_ctl_q_info adminq; 867 struct ice_ctl_q_info sbq; 868 struct ice_ctl_q_info mailboxq; 869 870 u8 api_branch; /* API branch version */ 871 u8 api_maj_ver; /* API major version */ 872 u8 api_min_ver; /* API minor version */ 873 u8 api_patch; /* API patch version */ 874 u8 fw_branch; /* firmware branch version */ 875 u8 fw_maj_ver; /* firmware major version */ 876 u8 fw_min_ver; /* firmware minor version */ 877 u8 fw_patch; /* firmware patch version */ 878 u32 fw_build; /* firmware build number */ 879 880 struct ice_fw_log_cfg fw_log; 881 882 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL 883 * register. Used for determining the ITR/INTRL granularity during 884 * initialization. 885 */ 886 #define ICE_MAX_AGG_BW_200G 0x0 887 #define ICE_MAX_AGG_BW_100G 0X1 888 #define ICE_MAX_AGG_BW_50G 0x2 889 #define ICE_MAX_AGG_BW_25G 0x3 890 /* ITR granularity for different speeds */ 891 #define ICE_ITR_GRAN_ABOVE_25 2 892 #define ICE_ITR_GRAN_MAX_25 4 893 /* ITR granularity in 1 us */ 894 u8 itr_gran; 895 /* INTRL granularity for different speeds */ 896 #define ICE_INTRL_GRAN_ABOVE_25 4 897 #define ICE_INTRL_GRAN_MAX_25 8 898 /* INTRL granularity in 1 us */ 899 u8 intrl_gran; 900 901 #define ICE_PHY_PER_NAC 1 902 #define ICE_MAX_QUAD 2 903 #define ICE_NUM_QUAD_TYPE 2 904 #define ICE_PORTS_PER_QUAD 4 905 #define ICE_PHY_0_LAST_QUAD 1 906 #define ICE_PORTS_PER_PHY 8 907 #define ICE_NUM_EXTERNAL_PORTS ICE_PORTS_PER_PHY 908 909 /* Active package version (currently active) */ 910 struct ice_pkg_ver active_pkg_ver; 911 u32 active_track_id; 912 u8 active_pkg_name[ICE_PKG_NAME_SIZE]; 913 u8 active_pkg_in_nvm; 914 915 /* Driver's package ver - (from the Ice Metadata section) */ 916 struct ice_pkg_ver pkg_ver; 917 u8 pkg_name[ICE_PKG_NAME_SIZE]; 918 919 /* Driver's Ice segment format version and ID (from the Ice seg) */ 920 struct ice_pkg_ver ice_seg_fmt_ver; 921 u8 ice_seg_id[ICE_SEG_ID_SIZE]; 922 923 /* Pointer to the ice segment */ 924 struct ice_seg *seg; 925 926 /* Pointer to allocated copy of pkg memory */ 927 u8 *pkg_copy; 928 u32 pkg_size; 929 930 /* tunneling info */ 931 struct mutex tnl_lock; 932 struct ice_tunnel_table tnl; 933 934 struct udp_tunnel_nic_shared udp_tunnel_shared; 935 struct udp_tunnel_nic_info udp_tunnel_nic; 936 937 /* dvm boost update information */ 938 struct ice_dvm_table dvm_upd; 939 940 /* HW block tables */ 941 struct ice_blk_info blk[ICE_BLK_COUNT]; 942 struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */ 943 struct list_head fl_profs[ICE_BLK_COUNT]; 944 945 /* Flow Director filter info */ 946 int fdir_active_fltr; 947 948 struct mutex fdir_fltr_lock; /* protect Flow Director */ 949 struct list_head fdir_list_head; 950 951 /* Book-keeping of side-band filter count per flow-type. 952 * This is used to detect and handle input set changes for 953 * respective flow-type. 954 */ 955 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX]; 956 957 struct ice_fd_hw_prof **fdir_prof; 958 DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX); 959 struct mutex rss_locks; /* protect RSS configuration */ 960 struct list_head rss_list_head; 961 struct ice_mbx_snapshot mbx_snapshot; 962 DECLARE_BITMAP(hw_ptype, ICE_FLOW_PTYPE_MAX); 963 u8 dvm_ena; 964 u16 io_expander_handle; 965 }; 966 967 /* Statistics collected by each port, VSI, VEB, and S-channel */ 968 struct ice_eth_stats { 969 u64 rx_bytes; /* gorc */ 970 u64 rx_unicast; /* uprc */ 971 u64 rx_multicast; /* mprc */ 972 u64 rx_broadcast; /* bprc */ 973 u64 rx_discards; /* rdpc */ 974 u64 rx_unknown_protocol; /* rupp */ 975 u64 tx_bytes; /* gotc */ 976 u64 tx_unicast; /* uptc */ 977 u64 tx_multicast; /* mptc */ 978 u64 tx_broadcast; /* bptc */ 979 u64 tx_discards; /* tdpc */ 980 u64 tx_errors; /* tepc */ 981 }; 982 983 #define ICE_MAX_UP 8 984 985 /* Statistics collected by the MAC */ 986 struct ice_hw_port_stats { 987 /* eth stats collected by the port */ 988 struct ice_eth_stats eth; 989 /* additional port specific stats */ 990 u64 tx_dropped_link_down; /* tdold */ 991 u64 crc_errors; /* crcerrs */ 992 u64 illegal_bytes; /* illerrc */ 993 u64 error_bytes; /* errbc */ 994 u64 mac_local_faults; /* mlfc */ 995 u64 mac_remote_faults; /* mrfc */ 996 u64 rx_len_errors; /* rlec */ 997 u64 link_xon_rx; /* lxonrxc */ 998 u64 link_xoff_rx; /* lxoffrxc */ 999 u64 link_xon_tx; /* lxontxc */ 1000 u64 link_xoff_tx; /* lxofftxc */ 1001 u64 priority_xon_rx[8]; /* pxonrxc[8] */ 1002 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 1003 u64 priority_xon_tx[8]; /* pxontxc[8] */ 1004 u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 1005 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 1006 u64 rx_size_64; /* prc64 */ 1007 u64 rx_size_127; /* prc127 */ 1008 u64 rx_size_255; /* prc255 */ 1009 u64 rx_size_511; /* prc511 */ 1010 u64 rx_size_1023; /* prc1023 */ 1011 u64 rx_size_1522; /* prc1522 */ 1012 u64 rx_size_big; /* prc9522 */ 1013 u64 rx_undersize; /* ruc */ 1014 u64 rx_fragments; /* rfc */ 1015 u64 rx_oversize; /* roc */ 1016 u64 rx_jabber; /* rjc */ 1017 u64 tx_size_64; /* ptc64 */ 1018 u64 tx_size_127; /* ptc127 */ 1019 u64 tx_size_255; /* ptc255 */ 1020 u64 tx_size_511; /* ptc511 */ 1021 u64 tx_size_1023; /* ptc1023 */ 1022 u64 tx_size_1522; /* ptc1522 */ 1023 u64 tx_size_big; /* ptc9522 */ 1024 /* flow director stats */ 1025 u32 fd_sb_status; 1026 u64 fd_sb_match; 1027 }; 1028 1029 enum ice_sw_fwd_act_type { 1030 ICE_FWD_TO_VSI = 0, 1031 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */ 1032 ICE_FWD_TO_Q, 1033 ICE_FWD_TO_QGRP, 1034 ICE_DROP_PACKET, 1035 ICE_INVAL_ACT 1036 }; 1037 1038 struct ice_aq_get_set_rss_lut_params { 1039 u16 vsi_handle; /* software VSI handle */ 1040 u16 lut_size; /* size of the LUT buffer */ 1041 u8 lut_type; /* type of the LUT (i.e. VSI, PF, Global) */ 1042 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */ 1043 u8 global_lut_id; /* only valid when lut_type is global */ 1044 }; 1045 1046 /* Checksum and Shadow RAM pointers */ 1047 #define ICE_SR_NVM_CTRL_WORD 0x00 1048 #define ICE_SR_BOOT_CFG_PTR 0x132 1049 #define ICE_SR_NVM_WOL_CFG 0x19 1050 #define ICE_NVM_OROM_VER_OFF 0x02 1051 #define ICE_SR_PBA_BLOCK_PTR 0x16 1052 #define ICE_SR_NVM_DEV_STARTER_VER 0x18 1053 #define ICE_SR_NVM_EETRACK_LO 0x2D 1054 #define ICE_SR_NVM_EETRACK_HI 0x2E 1055 #define ICE_NVM_VER_LO_SHIFT 0 1056 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT) 1057 #define ICE_NVM_VER_HI_SHIFT 12 1058 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT) 1059 #define ICE_OROM_VER_PATCH_SHIFT 0 1060 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT) 1061 #define ICE_OROM_VER_BUILD_SHIFT 8 1062 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT) 1063 #define ICE_OROM_VER_SHIFT 24 1064 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT) 1065 #define ICE_SR_PFA_PTR 0x40 1066 #define ICE_SR_1ST_NVM_BANK_PTR 0x42 1067 #define ICE_SR_NVM_BANK_SIZE 0x43 1068 #define ICE_SR_1ST_OROM_BANK_PTR 0x44 1069 #define ICE_SR_OROM_BANK_SIZE 0x45 1070 #define ICE_SR_NETLIST_BANK_PTR 0x46 1071 #define ICE_SR_NETLIST_BANK_SIZE 0x47 1072 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800 1073 1074 /* CSS Header words */ 1075 #define ICE_NVM_CSS_SREV_L 0x14 1076 #define ICE_NVM_CSS_SREV_H 0x15 1077 1078 /* Length of CSS header section in words */ 1079 #define ICE_CSS_HEADER_LENGTH 330 1080 1081 /* Offset of Shadow RAM copy in the NVM bank area. */ 1082 #define ICE_NVM_SR_COPY_WORD_OFFSET roundup(ICE_CSS_HEADER_LENGTH, 32) 1083 1084 /* Size in bytes of Option ROM trailer */ 1085 #define ICE_NVM_OROM_TRAILER_LENGTH (2 * ICE_CSS_HEADER_LENGTH) 1086 1087 /* The Link Topology Netlist section is stored as a series of words. It is 1088 * stored in the NVM as a TLV, with the first two words containing the type 1089 * and length. 1090 */ 1091 #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B 1092 #define ICE_NETLIST_TYPE_OFFSET 0x0000 1093 #define ICE_NETLIST_LEN_OFFSET 0x0001 1094 1095 /* The Link Topology section follows the TLV header. When reading the netlist 1096 * using ice_read_netlist_module, we need to account for the 2-word TLV 1097 * header. 1098 */ 1099 #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2) 1100 1101 #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000) 1102 #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001) 1103 1104 #define ICE_LINK_TOPO_NODE_COUNT_M ICE_M(0x3FF, 0) 1105 1106 /* The Netlist ID Block is located after all of the Link Topology nodes. */ 1107 #define ICE_NETLIST_ID_BLK_SIZE 0x30 1108 #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n)) 1109 1110 /* netlist ID block field offsets (word offsets) */ 1111 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02 1112 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03 1113 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04 1114 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05 1115 #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06 1116 #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07 1117 #define ICE_NETLIST_ID_BLK_REV_LOW 0x08 1118 #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09 1119 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n)) 1120 #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F 1121 1122 /* Auxiliary field, mask, and shift definition for Shadow RAM and NVM Flash */ 1123 #define ICE_SR_CTRL_WORD_1_S 0x06 1124 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S) 1125 #define ICE_SR_CTRL_WORD_VALID 0x1 1126 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3) 1127 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4) 1128 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5) 1129 1130 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15) 1131 1132 /* Link override related */ 1133 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10 1134 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4 1135 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2 1136 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1 1137 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2 1138 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1 1139 #define ICE_FW_API_LINK_OVERRIDE_MIN 5 1140 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2 1141 1142 #define ICE_SR_WORDS_IN_1KB 512 1143 1144 /* Hash redirection LUT for VSI - maximum array size */ 1145 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4) 1146 1147 /* AQ API version for LLDP_FILTER_CONTROL */ 1148 #define ICE_FW_API_LLDP_FLTR_MAJ 1 1149 #define ICE_FW_API_LLDP_FLTR_MIN 7 1150 #define ICE_FW_API_LLDP_FLTR_PATCH 1 1151 1152 /* AQ API version for report default configuration */ 1153 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1 1154 #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7 1155 #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3 1156 1157 #endif /* _ICE_TYPE_H_ */ 1158