1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_TYPE_H_ 5 #define _ICE_TYPE_H_ 6 7 #define ICE_BYTES_PER_WORD 2 8 #define ICE_BYTES_PER_DWORD 4 9 10 #include "ice_status.h" 11 #include "ice_hw_autogen.h" 12 #include "ice_osdep.h" 13 #include "ice_controlq.h" 14 #include "ice_lan_tx_rx.h" 15 #include "ice_flex_type.h" 16 #include "ice_protocol_type.h" 17 #include "ice_sbq_cmd.h" 18 19 static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc) 20 { 21 return test_bit(tc, &bitmap); 22 } 23 24 static inline u64 round_up_64bit(u64 a, u32 b) 25 { 26 return div64_long(((a) + (b) / 2), (b)); 27 } 28 29 static inline u32 ice_round_to_num(u32 N, u32 R) 30 { 31 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) : 32 ((((N) + (R) - 1) / (R)) * (R))); 33 } 34 35 /* Driver always calls main vsi_handle first */ 36 #define ICE_MAIN_VSI_HANDLE 0 37 38 /* debug masks - set these bits in hw->debug_mask to control output */ 39 #define ICE_DBG_INIT BIT_ULL(1) 40 #define ICE_DBG_FW_LOG BIT_ULL(3) 41 #define ICE_DBG_LINK BIT_ULL(4) 42 #define ICE_DBG_PHY BIT_ULL(5) 43 #define ICE_DBG_QCTX BIT_ULL(6) 44 #define ICE_DBG_NVM BIT_ULL(7) 45 #define ICE_DBG_LAN BIT_ULL(8) 46 #define ICE_DBG_FLOW BIT_ULL(9) 47 #define ICE_DBG_SW BIT_ULL(13) 48 #define ICE_DBG_SCHED BIT_ULL(14) 49 #define ICE_DBG_RDMA BIT_ULL(15) 50 #define ICE_DBG_PKG BIT_ULL(16) 51 #define ICE_DBG_RES BIT_ULL(17) 52 #define ICE_DBG_PTP BIT_ULL(19) 53 #define ICE_DBG_AQ_MSG BIT_ULL(24) 54 #define ICE_DBG_AQ_DESC BIT_ULL(25) 55 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26) 56 #define ICE_DBG_AQ_CMD BIT_ULL(27) 57 #define ICE_DBG_USER BIT_ULL(31) 58 59 enum ice_aq_res_ids { 60 ICE_NVM_RES_ID = 1, 61 ICE_SPD_RES_ID, 62 ICE_CHANGE_LOCK_RES_ID, 63 ICE_GLOBAL_CFG_LOCK_RES_ID 64 }; 65 66 /* FW update timeout definitions are in milliseconds */ 67 #define ICE_NVM_TIMEOUT 180000 68 #define ICE_CHANGE_LOCK_TIMEOUT 1000 69 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 5000 70 71 enum ice_aq_res_access_type { 72 ICE_RES_READ = 1, 73 ICE_RES_WRITE 74 }; 75 76 struct ice_driver_ver { 77 u8 major_ver; 78 u8 minor_ver; 79 u8 build_ver; 80 u8 subbuild_ver; 81 u8 driver_string[32]; 82 }; 83 84 enum ice_fc_mode { 85 ICE_FC_NONE = 0, 86 ICE_FC_RX_PAUSE, 87 ICE_FC_TX_PAUSE, 88 ICE_FC_FULL, 89 ICE_FC_PFC, 90 ICE_FC_DFLT 91 }; 92 93 enum ice_phy_cache_mode { 94 ICE_FC_MODE = 0, 95 ICE_SPEED_MODE, 96 ICE_FEC_MODE 97 }; 98 99 enum ice_fec_mode { 100 ICE_FEC_NONE = 0, 101 ICE_FEC_RS, 102 ICE_FEC_BASER, 103 ICE_FEC_AUTO 104 }; 105 106 struct ice_phy_cache_mode_data { 107 union { 108 enum ice_fec_mode curr_user_fec_req; 109 enum ice_fc_mode curr_user_fc_req; 110 u16 curr_user_speed_req; 111 } data; 112 }; 113 114 enum ice_set_fc_aq_failures { 115 ICE_SET_FC_AQ_FAIL_NONE = 0, 116 ICE_SET_FC_AQ_FAIL_GET, 117 ICE_SET_FC_AQ_FAIL_SET, 118 ICE_SET_FC_AQ_FAIL_UPDATE 119 }; 120 121 /* Various MAC types */ 122 enum ice_mac_type { 123 ICE_MAC_UNKNOWN = 0, 124 ICE_MAC_E810, 125 ICE_MAC_GENERIC, 126 }; 127 128 /* Media Types */ 129 enum ice_media_type { 130 ICE_MEDIA_UNKNOWN = 0, 131 ICE_MEDIA_FIBER, 132 ICE_MEDIA_BASET, 133 ICE_MEDIA_BACKPLANE, 134 ICE_MEDIA_DA, 135 }; 136 137 enum ice_vsi_type { 138 ICE_VSI_PF = 0, 139 ICE_VSI_VF = 1, 140 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */ 141 ICE_VSI_CHNL = 4, 142 ICE_VSI_LB = 6, 143 ICE_VSI_SWITCHDEV_CTRL = 7, 144 }; 145 146 struct ice_link_status { 147 /* Refer to ice_aq_phy_type for bits definition */ 148 u64 phy_type_low; 149 u64 phy_type_high; 150 u8 topo_media_conflict; 151 u16 max_frame_size; 152 u16 link_speed; 153 u16 req_speeds; 154 u8 link_cfg_err; 155 u8 lse_ena; /* Link Status Event notification */ 156 u8 link_info; 157 u8 an_info; 158 u8 ext_info; 159 u8 fec_info; 160 u8 pacing; 161 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of 162 * ice_aqc_get_phy_caps structure 163 */ 164 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 165 }; 166 167 /* Different reset sources for which a disable queue AQ call has to be made in 168 * order to clean the Tx scheduler as a part of the reset 169 */ 170 enum ice_disq_rst_src { 171 ICE_NO_RESET = 0, 172 ICE_VM_RESET, 173 ICE_VF_RESET, 174 }; 175 176 /* PHY info such as phy_type, etc... */ 177 struct ice_phy_info { 178 struct ice_link_status link_info; 179 struct ice_link_status link_info_old; 180 u64 phy_type_low; 181 u64 phy_type_high; 182 enum ice_media_type media_type; 183 u8 get_link_info; 184 /* Please refer to struct ice_aqc_get_link_status_data to get 185 * detail of enable bit in curr_user_speed_req 186 */ 187 u16 curr_user_speed_req; 188 enum ice_fec_mode curr_user_fec_req; 189 enum ice_fc_mode curr_user_fc_req; 190 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg; 191 }; 192 193 /* protocol enumeration for filters */ 194 enum ice_fltr_ptype { 195 /* NONE - used for undef/error */ 196 ICE_FLTR_PTYPE_NONF_NONE = 0, 197 ICE_FLTR_PTYPE_NONF_IPV4_UDP, 198 ICE_FLTR_PTYPE_NONF_IPV4_TCP, 199 ICE_FLTR_PTYPE_NONF_IPV4_SCTP, 200 ICE_FLTR_PTYPE_NONF_IPV4_OTHER, 201 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP, 202 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP, 203 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP, 204 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER, 205 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER, 206 ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3, 207 ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3, 208 ICE_FLTR_PTYPE_NONF_IPV4_ESP, 209 ICE_FLTR_PTYPE_NONF_IPV6_ESP, 210 ICE_FLTR_PTYPE_NONF_IPV4_AH, 211 ICE_FLTR_PTYPE_NONF_IPV6_AH, 212 ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP, 213 ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP, 214 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE, 215 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION, 216 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE, 217 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION, 218 ICE_FLTR_PTYPE_NON_IP_L2, 219 ICE_FLTR_PTYPE_FRAG_IPV4, 220 ICE_FLTR_PTYPE_NONF_IPV6_UDP, 221 ICE_FLTR_PTYPE_NONF_IPV6_TCP, 222 ICE_FLTR_PTYPE_NONF_IPV6_SCTP, 223 ICE_FLTR_PTYPE_NONF_IPV6_OTHER, 224 ICE_FLTR_PTYPE_MAX, 225 }; 226 227 enum ice_fd_hw_seg { 228 ICE_FD_HW_SEG_NON_TUN = 0, 229 ICE_FD_HW_SEG_TUN, 230 ICE_FD_HW_SEG_MAX, 231 }; 232 233 /* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */ 234 #define ICE_MAX_FDIR_VSI_PER_FILTER 2 235 236 struct ice_fd_hw_prof { 237 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX]; 238 int cnt; 239 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX]; 240 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER]; 241 }; 242 243 /* Common HW capabilities for SW use */ 244 struct ice_hw_common_caps { 245 u32 valid_functions; 246 /* DCB capabilities */ 247 u32 active_tc_bitmap; 248 u32 maxtc; 249 250 /* Tx/Rx queues */ 251 u16 num_rxq; /* Number/Total Rx queues */ 252 u16 rxq_first_id; /* First queue ID for Rx queues */ 253 u16 num_txq; /* Number/Total Tx queues */ 254 u16 txq_first_id; /* First queue ID for Tx queues */ 255 256 /* MSI-X vectors */ 257 u16 num_msix_vectors; 258 u16 msix_vector_first_id; 259 260 /* Max MTU for function or device */ 261 u16 max_mtu; 262 263 /* Virtualization support */ 264 u8 sr_iov_1_1; /* SR-IOV enabled */ 265 266 /* RSS related capabilities */ 267 u16 rss_table_size; /* 512 for PFs and 64 for VFs */ 268 u8 rss_table_entry_width; /* RSS Entry width in bits */ 269 270 u8 dcb; 271 u8 ieee_1588; 272 u8 rdma; 273 274 bool nvm_update_pending_nvm; 275 bool nvm_update_pending_orom; 276 bool nvm_update_pending_netlist; 277 #define ICE_NVM_PENDING_NVM_IMAGE BIT(0) 278 #define ICE_NVM_PENDING_OROM BIT(1) 279 #define ICE_NVM_PENDING_NETLIST BIT(2) 280 bool nvm_unified_update; 281 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) 282 }; 283 284 /* IEEE 1588 TIME_SYNC specific info */ 285 /* Function specific definitions */ 286 #define ICE_TS_FUNC_ENA_M BIT(0) 287 #define ICE_TS_SRC_TMR_OWND_M BIT(1) 288 #define ICE_TS_TMR_ENA_M BIT(2) 289 #define ICE_TS_TMR_IDX_OWND_S 4 290 #define ICE_TS_TMR_IDX_OWND_M BIT(4) 291 #define ICE_TS_CLK_FREQ_S 16 292 #define ICE_TS_CLK_FREQ_M ICE_M(0x7, ICE_TS_CLK_FREQ_S) 293 #define ICE_TS_CLK_SRC_S 20 294 #define ICE_TS_CLK_SRC_M BIT(20) 295 #define ICE_TS_TMR_IDX_ASSOC_S 24 296 #define ICE_TS_TMR_IDX_ASSOC_M BIT(24) 297 298 struct ice_ts_func_info { 299 /* Function specific info */ 300 u32 clk_freq; 301 u8 clk_src; 302 u8 tmr_index_assoc; 303 u8 ena; 304 u8 tmr_index_owned; 305 u8 src_tmr_owned; 306 u8 tmr_ena; 307 }; 308 309 /* Device specific definitions */ 310 #define ICE_TS_TMR0_OWNR_M 0x7 311 #define ICE_TS_TMR0_OWND_M BIT(3) 312 #define ICE_TS_TMR1_OWNR_S 4 313 #define ICE_TS_TMR1_OWNR_M ICE_M(0x7, ICE_TS_TMR1_OWNR_S) 314 #define ICE_TS_TMR1_OWND_M BIT(7) 315 #define ICE_TS_DEV_ENA_M BIT(24) 316 #define ICE_TS_TMR0_ENA_M BIT(25) 317 #define ICE_TS_TMR1_ENA_M BIT(26) 318 319 struct ice_ts_dev_info { 320 /* Device specific info */ 321 u32 ena_ports; 322 u32 tmr_own_map; 323 u32 tmr0_owner; 324 u32 tmr1_owner; 325 u8 tmr0_owned; 326 u8 tmr1_owned; 327 u8 ena; 328 u8 tmr0_ena; 329 u8 tmr1_ena; 330 }; 331 332 /* Function specific capabilities */ 333 struct ice_hw_func_caps { 334 struct ice_hw_common_caps common_cap; 335 u32 num_allocd_vfs; /* Number of allocated VFs */ 336 u32 vf_base_id; /* Logical ID of the first VF */ 337 u32 guar_num_vsi; 338 u32 fd_fltr_guar; /* Number of filters guaranteed */ 339 u32 fd_fltr_best_effort; /* Number of best effort filters */ 340 struct ice_ts_func_info ts_func_info; 341 }; 342 343 /* Device wide capabilities */ 344 struct ice_hw_dev_caps { 345 struct ice_hw_common_caps common_cap; 346 u32 num_vfs_exposed; /* Total number of VFs exposed */ 347 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ 348 u32 num_flow_director_fltr; /* Number of FD filters available */ 349 struct ice_ts_dev_info ts_dev_info; 350 u32 num_funcs; 351 }; 352 353 /* MAC info */ 354 struct ice_mac_info { 355 u8 lan_addr[ETH_ALEN]; 356 u8 perm_addr[ETH_ALEN]; 357 }; 358 359 /* Reset types used to determine which kind of reset was requested. These 360 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register. 361 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register 362 * because its reset source is different than the other types listed. 363 */ 364 enum ice_reset_req { 365 ICE_RESET_POR = 0, 366 ICE_RESET_INVAL = 0, 367 ICE_RESET_CORER = 1, 368 ICE_RESET_GLOBR = 2, 369 ICE_RESET_EMPR = 3, 370 ICE_RESET_PFR = 4, 371 }; 372 373 /* Bus parameters */ 374 struct ice_bus_info { 375 u16 device; 376 u8 func; 377 }; 378 379 /* Flow control (FC) parameters */ 380 struct ice_fc_info { 381 enum ice_fc_mode current_mode; /* FC mode in effect */ 382 enum ice_fc_mode req_mode; /* FC mode requested by caller */ 383 }; 384 385 /* Option ROM version information */ 386 struct ice_orom_info { 387 u8 major; /* Major version of OROM */ 388 u8 patch; /* Patch version of OROM */ 389 u16 build; /* Build version of OROM */ 390 }; 391 392 /* NVM version information */ 393 struct ice_nvm_info { 394 u32 eetrack; 395 u8 major; 396 u8 minor; 397 }; 398 399 /* netlist version information */ 400 struct ice_netlist_info { 401 u32 major; /* major high/low */ 402 u32 minor; /* minor high/low */ 403 u32 type; /* type high/low */ 404 u32 rev; /* revision high/low */ 405 u32 hash; /* SHA-1 hash word */ 406 u16 cust_ver; /* customer version */ 407 }; 408 409 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules 410 * of the flash image. 411 */ 412 enum ice_flash_bank { 413 ICE_INVALID_FLASH_BANK, 414 ICE_1ST_FLASH_BANK, 415 ICE_2ND_FLASH_BANK, 416 }; 417 418 /* Enumeration of which flash bank is desired to read from, either the active 419 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from 420 * code which just wants to read the active or inactive flash bank. 421 */ 422 enum ice_bank_select { 423 ICE_ACTIVE_FLASH_BANK, 424 ICE_INACTIVE_FLASH_BANK, 425 }; 426 427 /* information for accessing NVM, OROM, and Netlist flash banks */ 428 struct ice_bank_info { 429 u32 nvm_ptr; /* Pointer to 1st NVM bank */ 430 u32 nvm_size; /* Size of NVM bank */ 431 u32 orom_ptr; /* Pointer to 1st OROM bank */ 432 u32 orom_size; /* Size of OROM bank */ 433 u32 netlist_ptr; /* Pointer to 1st Netlist bank */ 434 u32 netlist_size; /* Size of Netlist bank */ 435 enum ice_flash_bank nvm_bank; /* Active NVM bank */ 436 enum ice_flash_bank orom_bank; /* Active OROM bank */ 437 enum ice_flash_bank netlist_bank; /* Active Netlist bank */ 438 }; 439 440 /* Flash Chip Information */ 441 struct ice_flash_info { 442 struct ice_orom_info orom; /* Option ROM version info */ 443 struct ice_nvm_info nvm; /* NVM version information */ 444 struct ice_netlist_info netlist;/* Netlist version info */ 445 struct ice_bank_info banks; /* Flash Bank information */ 446 u16 sr_words; /* Shadow RAM size in words */ 447 u32 flash_size; /* Size of available flash in bytes */ 448 u8 blank_nvm_mode; /* is NVM empty (no FW present) */ 449 }; 450 451 struct ice_link_default_override_tlv { 452 u8 options; 453 #define ICE_LINK_OVERRIDE_OPT_M 0x3F 454 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0) 455 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1) 456 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2) 457 #define ICE_LINK_OVERRIDE_EN BIT(3) 458 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4) 459 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5) 460 u8 phy_config; 461 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8 462 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S) 463 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3 464 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6) 465 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7) 466 u8 fec_options; 467 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF 468 u8 rsvd1; 469 u64 phy_type_low; 470 u64 phy_type_high; 471 }; 472 473 #define ICE_NVM_VER_LEN 32 474 475 /* Max number of port to queue branches w.r.t topology */ 476 #define ICE_MAX_TRAFFIC_CLASS 8 477 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS 478 479 #define ice_for_each_traffic_class(_i) \ 480 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++) 481 482 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects 483 * to driver defined policy for default aggregator 484 */ 485 #define ICE_INVAL_TEID 0xFFFFFFFF 486 #define ICE_DFLT_AGG_ID 0 487 488 struct ice_sched_node { 489 struct ice_sched_node *parent; 490 struct ice_sched_node *sibling; /* next sibling in the same layer */ 491 struct ice_sched_node **children; 492 struct ice_aqc_txsched_elem_data info; 493 u32 agg_id; /* aggregator group ID */ 494 u16 vsi_handle; 495 u8 in_use; /* suspended or in use */ 496 u8 tx_sched_layer; /* Logical Layer (1-9) */ 497 u8 num_children; 498 u8 tc_num; 499 u8 owner; 500 #define ICE_SCHED_NODE_OWNER_LAN 0 501 #define ICE_SCHED_NODE_OWNER_RDMA 2 502 }; 503 504 /* Access Macros for Tx Sched Elements data */ 505 #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid) 506 507 /* The aggregator type determines if identifier is for a VSI group, 508 * aggregator group, aggregator of queues, or queue group. 509 */ 510 enum ice_agg_type { 511 ICE_AGG_TYPE_UNKNOWN = 0, 512 ICE_AGG_TYPE_VSI, 513 ICE_AGG_TYPE_AGG, /* aggregator */ 514 ICE_AGG_TYPE_Q, 515 ICE_AGG_TYPE_QG 516 }; 517 518 /* Rate limit types */ 519 enum ice_rl_type { 520 ICE_UNKNOWN_BW = 0, 521 ICE_MIN_BW, /* for CIR profile */ 522 ICE_MAX_BW, /* for EIR profile */ 523 ICE_SHARED_BW /* for shared profile */ 524 }; 525 526 #define ICE_SCHED_MIN_BW 500 /* in Kbps */ 527 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */ 528 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */ 529 #define ICE_SCHED_DFLT_RL_PROF_ID 0 530 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF 531 #define ICE_SCHED_DFLT_BW_WT 4 532 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF 533 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */ 534 535 /* Data structure for saving BW information */ 536 enum ice_bw_type { 537 ICE_BW_TYPE_PRIO, 538 ICE_BW_TYPE_CIR, 539 ICE_BW_TYPE_CIR_WT, 540 ICE_BW_TYPE_EIR, 541 ICE_BW_TYPE_EIR_WT, 542 ICE_BW_TYPE_SHARED, 543 ICE_BW_TYPE_CNT /* This must be last */ 544 }; 545 546 struct ice_bw { 547 u32 bw; 548 u16 bw_alloc; 549 }; 550 551 struct ice_bw_type_info { 552 DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT); 553 u8 generic; 554 struct ice_bw cir_bw; 555 struct ice_bw eir_bw; 556 u32 shared_bw; 557 }; 558 559 /* VSI queue context structure for given TC */ 560 struct ice_q_ctx { 561 u16 q_handle; 562 u32 q_teid; 563 /* bw_t_info saves queue BW information */ 564 struct ice_bw_type_info bw_t_info; 565 }; 566 567 /* VSI type list entry to locate corresponding VSI/aggregator nodes */ 568 struct ice_sched_vsi_info { 569 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS]; 570 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS]; 571 struct list_head list_entry; 572 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS]; 573 u16 max_rdmaq[ICE_MAX_TRAFFIC_CLASS]; 574 /* bw_t_info saves VSI BW information */ 575 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS]; 576 }; 577 578 /* driver defines the policy */ 579 struct ice_sched_tx_policy { 580 u16 max_num_vsis; 581 u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS]; 582 u8 rdma_ena; 583 }; 584 585 /* CEE or IEEE 802.1Qaz ETS Configuration data */ 586 struct ice_dcb_ets_cfg { 587 u8 willing; 588 u8 cbs; 589 u8 maxtcs; 590 u8 prio_table[ICE_MAX_TRAFFIC_CLASS]; 591 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS]; 592 u8 tsatable[ICE_MAX_TRAFFIC_CLASS]; 593 }; 594 595 /* CEE or IEEE 802.1Qaz PFC Configuration data */ 596 struct ice_dcb_pfc_cfg { 597 u8 willing; 598 u8 mbc; 599 u8 pfccap; 600 u8 pfcena; 601 }; 602 603 /* CEE or IEEE 802.1Qaz Application Priority data */ 604 struct ice_dcb_app_priority_table { 605 u16 prot_id; 606 u8 priority; 607 u8 selector; 608 }; 609 610 #define ICE_MAX_USER_PRIORITY 8 611 #define ICE_DCBX_MAX_APPS 64 612 #define ICE_DSCP_NUM_VAL 64 613 #define ICE_LLDPDU_SIZE 1500 614 #define ICE_TLV_STATUS_OPER 0x1 615 #define ICE_TLV_STATUS_SYNC 0x2 616 #define ICE_TLV_STATUS_ERR 0x4 617 #define ICE_APP_PROT_ID_ISCSI_860 0x035c 618 #define ICE_APP_SEL_ETHTYPE 0x1 619 #define ICE_APP_SEL_TCPIP 0x2 620 #define ICE_CEE_APP_SEL_ETHTYPE 0x0 621 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134 622 #define ICE_CEE_APP_SEL_TCPIP 0x1 623 624 struct ice_dcbx_cfg { 625 u32 numapps; 626 u32 tlv_status; /* CEE mode TLV status */ 627 struct ice_dcb_ets_cfg etscfg; 628 struct ice_dcb_ets_cfg etsrec; 629 struct ice_dcb_pfc_cfg pfc; 630 #define ICE_QOS_MODE_VLAN 0x0 631 #define ICE_QOS_MODE_DSCP 0x1 632 u8 pfc_mode; 633 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS]; 634 /* when DSCP mapping defined by user set its bit to 1 */ 635 DECLARE_BITMAP(dscp_mapped, ICE_DSCP_NUM_VAL); 636 /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */ 637 u8 dscp_map[ICE_DSCP_NUM_VAL]; 638 u8 dcbx_mode; 639 #define ICE_DCBX_MODE_CEE 0x1 640 #define ICE_DCBX_MODE_IEEE 0x2 641 u8 app_mode; 642 #define ICE_DCBX_APPS_NON_WILLING 0x1 643 }; 644 645 struct ice_qos_cfg { 646 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */ 647 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */ 648 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */ 649 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */ 650 u8 is_sw_lldp : 1; 651 }; 652 653 struct ice_port_info { 654 struct ice_sched_node *root; /* Root Node per Port */ 655 struct ice_hw *hw; /* back pointer to HW instance */ 656 u32 last_node_teid; /* scheduler last node info */ 657 u16 sw_id; /* Initial switch ID belongs to port */ 658 u16 pf_vf_num; 659 u8 port_state; 660 #define ICE_SCHED_PORT_STATE_INIT 0x0 661 #define ICE_SCHED_PORT_STATE_READY 0x1 662 u8 lport; 663 #define ICE_LPORT_MASK 0xff 664 u16 dflt_tx_vsi_rule_id; 665 u16 dflt_tx_vsi_num; 666 u16 dflt_rx_vsi_rule_id; 667 u16 dflt_rx_vsi_num; 668 struct ice_fc_info fc; 669 struct ice_mac_info mac; 670 struct ice_phy_info phy; 671 struct mutex sched_lock; /* protect access to TXSched tree */ 672 struct ice_sched_node * 673 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM]; 674 /* List contain profile ID(s) and other params per layer */ 675 struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 676 struct ice_qos_cfg qos_cfg; 677 u8 is_vf:1; 678 }; 679 680 struct ice_switch_info { 681 struct list_head vsi_list_map_head; 682 struct ice_sw_recipe *recp_list; 683 u16 prof_res_bm_init; 684 u16 max_used_prof_index; 685 686 DECLARE_BITMAP(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS); 687 }; 688 689 /* FW logging configuration */ 690 struct ice_fw_log_evnt { 691 u8 cfg : 4; /* New event enables to configure */ 692 u8 cur : 4; /* Current/active event enables */ 693 }; 694 695 struct ice_fw_log_cfg { 696 u8 cq_en : 1; /* FW logging is enabled via the control queue */ 697 u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */ 698 u8 actv_evnts; /* Cumulation of currently enabled log events */ 699 700 #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S) 701 #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S) 702 #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S) 703 #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S) 704 struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX]; 705 }; 706 707 /* Enum defining the different states of the mailbox snapshot in the 708 * PF-VF mailbox overflow detection algorithm. The snapshot can be in 709 * states: 710 * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot 711 * within the mailbox buffer. 712 * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot 713 * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the 714 * mailbox and mark any VFs sending more messages than the threshold limit set. 715 * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF. 716 */ 717 enum ice_mbx_snapshot_state { 718 ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0, 719 ICE_MAL_VF_DETECT_STATE_TRAVERSE, 720 ICE_MAL_VF_DETECT_STATE_DETECT, 721 ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF, 722 }; 723 724 /* Structure to hold information of the static snapshot and the mailbox 725 * buffer data used to generate and track the snapshot. 726 * 1. state: the state of the mailbox snapshot in the malicious VF 727 * detection state handler ice_mbx_vf_state_handler() 728 * 2. head: head of the mailbox snapshot in a circular mailbox buffer 729 * 3. tail: tail of the mailbox snapshot in a circular mailbox buffer 730 * 4. num_iterations: number of messages traversed in circular mailbox buffer 731 * 5. num_msg_proc: number of messages processed in mailbox 732 * 6. num_pending_arq: number of pending asynchronous messages 733 * 7. max_num_msgs_mbx: maximum messages in mailbox for currently 734 * serviced work item or interrupt. 735 */ 736 struct ice_mbx_snap_buffer_data { 737 enum ice_mbx_snapshot_state state; 738 u32 head; 739 u32 tail; 740 u32 num_iterations; 741 u16 num_msg_proc; 742 u16 num_pending_arq; 743 u16 max_num_msgs_mbx; 744 }; 745 746 /* Structure to track messages sent by VFs on mailbox: 747 * 1. vf_cntr: a counter array of VFs to track the number of 748 * asynchronous messages sent by each VF 749 * 2. vfcntr_len: number of entries in VF counter array 750 */ 751 struct ice_mbx_vf_counter { 752 u32 *vf_cntr; 753 u32 vfcntr_len; 754 }; 755 756 /* Structure to hold data relevant to the captured static snapshot 757 * of the PF-VF mailbox. 758 */ 759 struct ice_mbx_snapshot { 760 struct ice_mbx_snap_buffer_data mbx_buf; 761 struct ice_mbx_vf_counter mbx_vf; 762 }; 763 764 /* Structure to hold data to be used for capturing or updating a 765 * static snapshot. 766 * 1. num_msg_proc: number of messages processed in mailbox 767 * 2. num_pending_arq: number of pending asynchronous messages 768 * 3. max_num_msgs_mbx: maximum messages in mailbox for currently 769 * serviced work item or interrupt. 770 * 4. async_watermark_val: An upper threshold set by caller to determine 771 * if the pending arq count is large enough to assume that there is 772 * the possibility of a mailicious VF. 773 */ 774 struct ice_mbx_data { 775 u16 num_msg_proc; 776 u16 num_pending_arq; 777 u16 max_num_msgs_mbx; 778 u16 async_watermark_val; 779 }; 780 781 /* Port hardware description */ 782 struct ice_hw { 783 u8 __iomem *hw_addr; 784 void *back; 785 struct ice_aqc_layer_props *layer_info; 786 struct ice_port_info *port_info; 787 /* PSM clock frequency for calculating RL profile params */ 788 u32 psm_clk_freq; 789 u64 debug_mask; /* bitmap for debug mask */ 790 enum ice_mac_type mac_type; 791 792 u16 fd_ctr_base; /* FD counter base index */ 793 794 /* pci info */ 795 u16 device_id; 796 u16 vendor_id; 797 u16 subsystem_device_id; 798 u16 subsystem_vendor_id; 799 u8 revision_id; 800 801 u8 pf_id; /* device profile info */ 802 803 u16 max_burst_size; /* driver sets this value */ 804 805 /* Tx Scheduler values */ 806 u8 num_tx_sched_layers; 807 u8 num_tx_sched_phys_layers; 808 u8 flattened_layers; 809 u8 max_cgds; 810 u8 sw_entry_point_layer; 811 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 812 struct list_head agg_list; /* lists all aggregator */ 813 814 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI]; 815 u8 evb_veb; /* true for VEB, false for VEPA */ 816 u8 reset_ongoing; /* true if HW is in reset, false otherwise */ 817 struct ice_bus_info bus; 818 struct ice_flash_info flash; 819 struct ice_hw_dev_caps dev_caps; /* device capabilities */ 820 struct ice_hw_func_caps func_caps; /* function capabilities */ 821 822 struct ice_switch_info *switch_info; /* switch filter lists */ 823 824 /* Control Queue info */ 825 struct ice_ctl_q_info adminq; 826 struct ice_ctl_q_info sbq; 827 struct ice_ctl_q_info mailboxq; 828 829 u8 api_branch; /* API branch version */ 830 u8 api_maj_ver; /* API major version */ 831 u8 api_min_ver; /* API minor version */ 832 u8 api_patch; /* API patch version */ 833 u8 fw_branch; /* firmware branch version */ 834 u8 fw_maj_ver; /* firmware major version */ 835 u8 fw_min_ver; /* firmware minor version */ 836 u8 fw_patch; /* firmware patch version */ 837 u32 fw_build; /* firmware build number */ 838 839 struct ice_fw_log_cfg fw_log; 840 841 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL 842 * register. Used for determining the ITR/INTRL granularity during 843 * initialization. 844 */ 845 #define ICE_MAX_AGG_BW_200G 0x0 846 #define ICE_MAX_AGG_BW_100G 0X1 847 #define ICE_MAX_AGG_BW_50G 0x2 848 #define ICE_MAX_AGG_BW_25G 0x3 849 /* ITR granularity for different speeds */ 850 #define ICE_ITR_GRAN_ABOVE_25 2 851 #define ICE_ITR_GRAN_MAX_25 4 852 /* ITR granularity in 1 us */ 853 u8 itr_gran; 854 /* INTRL granularity for different speeds */ 855 #define ICE_INTRL_GRAN_ABOVE_25 4 856 #define ICE_INTRL_GRAN_MAX_25 8 857 /* INTRL granularity in 1 us */ 858 u8 intrl_gran; 859 860 u8 ucast_shared; /* true if VSIs can share unicast addr */ 861 862 #define ICE_PHY_PER_NAC 1 863 #define ICE_MAX_QUAD 2 864 #define ICE_NUM_QUAD_TYPE 2 865 #define ICE_PORTS_PER_QUAD 4 866 #define ICE_PHY_0_LAST_QUAD 1 867 #define ICE_PORTS_PER_PHY 8 868 #define ICE_NUM_EXTERNAL_PORTS ICE_PORTS_PER_PHY 869 870 /* Active package version (currently active) */ 871 struct ice_pkg_ver active_pkg_ver; 872 u32 active_track_id; 873 u8 active_pkg_name[ICE_PKG_NAME_SIZE]; 874 u8 active_pkg_in_nvm; 875 876 enum ice_aq_err pkg_dwnld_status; 877 878 /* Driver's package ver - (from the Ice Metadata section) */ 879 struct ice_pkg_ver pkg_ver; 880 u8 pkg_name[ICE_PKG_NAME_SIZE]; 881 882 /* Driver's Ice segment format version and ID (from the Ice seg) */ 883 struct ice_pkg_ver ice_seg_fmt_ver; 884 u8 ice_seg_id[ICE_SEG_ID_SIZE]; 885 886 /* Pointer to the ice segment */ 887 struct ice_seg *seg; 888 889 /* Pointer to allocated copy of pkg memory */ 890 u8 *pkg_copy; 891 u32 pkg_size; 892 893 /* tunneling info */ 894 struct mutex tnl_lock; 895 struct ice_tunnel_table tnl; 896 897 struct udp_tunnel_nic_shared udp_tunnel_shared; 898 struct udp_tunnel_nic_info udp_tunnel_nic; 899 900 /* HW block tables */ 901 struct ice_blk_info blk[ICE_BLK_COUNT]; 902 struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */ 903 struct list_head fl_profs[ICE_BLK_COUNT]; 904 905 /* Flow Director filter info */ 906 int fdir_active_fltr; 907 908 struct mutex fdir_fltr_lock; /* protect Flow Director */ 909 struct list_head fdir_list_head; 910 911 /* Book-keeping of side-band filter count per flow-type. 912 * This is used to detect and handle input set changes for 913 * respective flow-type. 914 */ 915 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX]; 916 917 struct ice_fd_hw_prof **fdir_prof; 918 DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX); 919 struct mutex rss_locks; /* protect RSS configuration */ 920 struct list_head rss_list_head; 921 struct ice_mbx_snapshot mbx_snapshot; 922 u16 io_expander_handle; 923 }; 924 925 /* Statistics collected by each port, VSI, VEB, and S-channel */ 926 struct ice_eth_stats { 927 u64 rx_bytes; /* gorc */ 928 u64 rx_unicast; /* uprc */ 929 u64 rx_multicast; /* mprc */ 930 u64 rx_broadcast; /* bprc */ 931 u64 rx_discards; /* rdpc */ 932 u64 rx_unknown_protocol; /* rupp */ 933 u64 tx_bytes; /* gotc */ 934 u64 tx_unicast; /* uptc */ 935 u64 tx_multicast; /* mptc */ 936 u64 tx_broadcast; /* bptc */ 937 u64 tx_discards; /* tdpc */ 938 u64 tx_errors; /* tepc */ 939 }; 940 941 #define ICE_MAX_UP 8 942 943 /* Statistics collected by the MAC */ 944 struct ice_hw_port_stats { 945 /* eth stats collected by the port */ 946 struct ice_eth_stats eth; 947 /* additional port specific stats */ 948 u64 tx_dropped_link_down; /* tdold */ 949 u64 crc_errors; /* crcerrs */ 950 u64 illegal_bytes; /* illerrc */ 951 u64 error_bytes; /* errbc */ 952 u64 mac_local_faults; /* mlfc */ 953 u64 mac_remote_faults; /* mrfc */ 954 u64 rx_len_errors; /* rlec */ 955 u64 link_xon_rx; /* lxonrxc */ 956 u64 link_xoff_rx; /* lxoffrxc */ 957 u64 link_xon_tx; /* lxontxc */ 958 u64 link_xoff_tx; /* lxofftxc */ 959 u64 priority_xon_rx[8]; /* pxonrxc[8] */ 960 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 961 u64 priority_xon_tx[8]; /* pxontxc[8] */ 962 u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 963 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 964 u64 rx_size_64; /* prc64 */ 965 u64 rx_size_127; /* prc127 */ 966 u64 rx_size_255; /* prc255 */ 967 u64 rx_size_511; /* prc511 */ 968 u64 rx_size_1023; /* prc1023 */ 969 u64 rx_size_1522; /* prc1522 */ 970 u64 rx_size_big; /* prc9522 */ 971 u64 rx_undersize; /* ruc */ 972 u64 rx_fragments; /* rfc */ 973 u64 rx_oversize; /* roc */ 974 u64 rx_jabber; /* rjc */ 975 u64 tx_size_64; /* ptc64 */ 976 u64 tx_size_127; /* ptc127 */ 977 u64 tx_size_255; /* ptc255 */ 978 u64 tx_size_511; /* ptc511 */ 979 u64 tx_size_1023; /* ptc1023 */ 980 u64 tx_size_1522; /* ptc1522 */ 981 u64 tx_size_big; /* ptc9522 */ 982 /* flow director stats */ 983 u32 fd_sb_status; 984 u64 fd_sb_match; 985 }; 986 987 struct ice_aq_get_set_rss_lut_params { 988 u16 vsi_handle; /* software VSI handle */ 989 u16 lut_size; /* size of the LUT buffer */ 990 u8 lut_type; /* type of the LUT (i.e. VSI, PF, Global) */ 991 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */ 992 u8 global_lut_id; /* only valid when lut_type is global */ 993 }; 994 995 /* Checksum and Shadow RAM pointers */ 996 #define ICE_SR_NVM_CTRL_WORD 0x00 997 #define ICE_SR_BOOT_CFG_PTR 0x132 998 #define ICE_SR_NVM_WOL_CFG 0x19 999 #define ICE_NVM_OROM_VER_OFF 0x02 1000 #define ICE_SR_PBA_BLOCK_PTR 0x16 1001 #define ICE_SR_NVM_DEV_STARTER_VER 0x18 1002 #define ICE_SR_NVM_EETRACK_LO 0x2D 1003 #define ICE_SR_NVM_EETRACK_HI 0x2E 1004 #define ICE_NVM_VER_LO_SHIFT 0 1005 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT) 1006 #define ICE_NVM_VER_HI_SHIFT 12 1007 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT) 1008 #define ICE_OROM_VER_PATCH_SHIFT 0 1009 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT) 1010 #define ICE_OROM_VER_BUILD_SHIFT 8 1011 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT) 1012 #define ICE_OROM_VER_SHIFT 24 1013 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT) 1014 #define ICE_SR_PFA_PTR 0x40 1015 #define ICE_SR_1ST_NVM_BANK_PTR 0x42 1016 #define ICE_SR_NVM_BANK_SIZE 0x43 1017 #define ICE_SR_1ST_OROM_BANK_PTR 0x44 1018 #define ICE_SR_OROM_BANK_SIZE 0x45 1019 #define ICE_SR_NETLIST_BANK_PTR 0x46 1020 #define ICE_SR_NETLIST_BANK_SIZE 0x47 1021 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800 1022 1023 /* CSS Header words */ 1024 #define ICE_NVM_CSS_SREV_L 0x14 1025 #define ICE_NVM_CSS_SREV_H 0x15 1026 1027 /* Length of CSS header section in words */ 1028 #define ICE_CSS_HEADER_LENGTH 330 1029 1030 /* Offset of Shadow RAM copy in the NVM bank area. */ 1031 #define ICE_NVM_SR_COPY_WORD_OFFSET roundup(ICE_CSS_HEADER_LENGTH, 32) 1032 1033 /* Size in bytes of Option ROM trailer */ 1034 #define ICE_NVM_OROM_TRAILER_LENGTH (2 * ICE_CSS_HEADER_LENGTH) 1035 1036 /* The Link Topology Netlist section is stored as a series of words. It is 1037 * stored in the NVM as a TLV, with the first two words containing the type 1038 * and length. 1039 */ 1040 #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B 1041 #define ICE_NETLIST_TYPE_OFFSET 0x0000 1042 #define ICE_NETLIST_LEN_OFFSET 0x0001 1043 1044 /* The Link Topology section follows the TLV header. When reading the netlist 1045 * using ice_read_netlist_module, we need to account for the 2-word TLV 1046 * header. 1047 */ 1048 #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2) 1049 1050 #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000) 1051 #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001) 1052 1053 #define ICE_LINK_TOPO_NODE_COUNT_M ICE_M(0x3FF, 0) 1054 1055 /* The Netlist ID Block is located after all of the Link Topology nodes. */ 1056 #define ICE_NETLIST_ID_BLK_SIZE 0x30 1057 #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n)) 1058 1059 /* netlist ID block field offsets (word offsets) */ 1060 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02 1061 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03 1062 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04 1063 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05 1064 #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06 1065 #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07 1066 #define ICE_NETLIST_ID_BLK_REV_LOW 0x08 1067 #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09 1068 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n)) 1069 #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F 1070 1071 /* Auxiliary field, mask, and shift definition for Shadow RAM and NVM Flash */ 1072 #define ICE_SR_CTRL_WORD_1_S 0x06 1073 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S) 1074 #define ICE_SR_CTRL_WORD_VALID 0x1 1075 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3) 1076 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4) 1077 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5) 1078 1079 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15) 1080 1081 /* Link override related */ 1082 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10 1083 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4 1084 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2 1085 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1 1086 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2 1087 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1 1088 #define ICE_FW_API_LINK_OVERRIDE_MIN 5 1089 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2 1090 1091 #define ICE_SR_WORDS_IN_1KB 512 1092 1093 /* Hash redirection LUT for VSI - maximum array size */ 1094 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4) 1095 1096 /* AQ API version for LLDP_FILTER_CONTROL */ 1097 #define ICE_FW_API_LLDP_FLTR_MAJ 1 1098 #define ICE_FW_API_LLDP_FLTR_MIN 7 1099 #define ICE_FW_API_LLDP_FLTR_PATCH 1 1100 1101 /* AQ API version for report default configuration */ 1102 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1 1103 #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7 1104 #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3 1105 1106 #endif /* _ICE_TYPE_H_ */ 1107