1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_TYPE_H_ 5 #define _ICE_TYPE_H_ 6 7 #define ICE_BYTES_PER_WORD 2 8 #define ICE_BYTES_PER_DWORD 4 9 #define ICE_CHNL_MAX_TC 16 10 11 #include "ice_hw_autogen.h" 12 #include "ice_osdep.h" 13 #include "ice_controlq.h" 14 #include "ice_lan_tx_rx.h" 15 #include "ice_flex_type.h" 16 #include "ice_protocol_type.h" 17 #include "ice_sbq_cmd.h" 18 19 static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc) 20 { 21 return test_bit(tc, &bitmap); 22 } 23 24 static inline u64 round_up_64bit(u64 a, u32 b) 25 { 26 return div64_long(((a) + (b) / 2), (b)); 27 } 28 29 static inline u32 ice_round_to_num(u32 N, u32 R) 30 { 31 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) : 32 ((((N) + (R) - 1) / (R)) * (R))); 33 } 34 35 /* Driver always calls main vsi_handle first */ 36 #define ICE_MAIN_VSI_HANDLE 0 37 38 /* debug masks - set these bits in hw->debug_mask to control output */ 39 #define ICE_DBG_INIT BIT_ULL(1) 40 #define ICE_DBG_FW_LOG BIT_ULL(3) 41 #define ICE_DBG_LINK BIT_ULL(4) 42 #define ICE_DBG_PHY BIT_ULL(5) 43 #define ICE_DBG_QCTX BIT_ULL(6) 44 #define ICE_DBG_NVM BIT_ULL(7) 45 #define ICE_DBG_LAN BIT_ULL(8) 46 #define ICE_DBG_FLOW BIT_ULL(9) 47 #define ICE_DBG_SW BIT_ULL(13) 48 #define ICE_DBG_SCHED BIT_ULL(14) 49 #define ICE_DBG_RDMA BIT_ULL(15) 50 #define ICE_DBG_PKG BIT_ULL(16) 51 #define ICE_DBG_RES BIT_ULL(17) 52 #define ICE_DBG_PTP BIT_ULL(19) 53 #define ICE_DBG_AQ_MSG BIT_ULL(24) 54 #define ICE_DBG_AQ_DESC BIT_ULL(25) 55 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26) 56 #define ICE_DBG_AQ_CMD BIT_ULL(27) 57 #define ICE_DBG_USER BIT_ULL(31) 58 59 enum ice_aq_res_ids { 60 ICE_NVM_RES_ID = 1, 61 ICE_SPD_RES_ID, 62 ICE_CHANGE_LOCK_RES_ID, 63 ICE_GLOBAL_CFG_LOCK_RES_ID 64 }; 65 66 /* FW update timeout definitions are in milliseconds */ 67 #define ICE_NVM_TIMEOUT 180000 68 #define ICE_CHANGE_LOCK_TIMEOUT 1000 69 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 5000 70 71 enum ice_aq_res_access_type { 72 ICE_RES_READ = 1, 73 ICE_RES_WRITE 74 }; 75 76 struct ice_driver_ver { 77 u8 major_ver; 78 u8 minor_ver; 79 u8 build_ver; 80 u8 subbuild_ver; 81 u8 driver_string[32]; 82 }; 83 84 enum ice_fc_mode { 85 ICE_FC_NONE = 0, 86 ICE_FC_RX_PAUSE, 87 ICE_FC_TX_PAUSE, 88 ICE_FC_FULL, 89 ICE_FC_PFC, 90 ICE_FC_DFLT 91 }; 92 93 enum ice_phy_cache_mode { 94 ICE_FC_MODE = 0, 95 ICE_SPEED_MODE, 96 ICE_FEC_MODE 97 }; 98 99 enum ice_fec_mode { 100 ICE_FEC_NONE = 0, 101 ICE_FEC_RS, 102 ICE_FEC_BASER, 103 ICE_FEC_AUTO 104 }; 105 106 struct ice_phy_cache_mode_data { 107 union { 108 enum ice_fec_mode curr_user_fec_req; 109 enum ice_fc_mode curr_user_fc_req; 110 u16 curr_user_speed_req; 111 } data; 112 }; 113 114 enum ice_set_fc_aq_failures { 115 ICE_SET_FC_AQ_FAIL_NONE = 0, 116 ICE_SET_FC_AQ_FAIL_GET, 117 ICE_SET_FC_AQ_FAIL_SET, 118 ICE_SET_FC_AQ_FAIL_UPDATE 119 }; 120 121 /* Various MAC types */ 122 enum ice_mac_type { 123 ICE_MAC_UNKNOWN = 0, 124 ICE_MAC_E810, 125 ICE_MAC_GENERIC, 126 }; 127 128 /* Media Types */ 129 enum ice_media_type { 130 ICE_MEDIA_UNKNOWN = 0, 131 ICE_MEDIA_FIBER, 132 ICE_MEDIA_BASET, 133 ICE_MEDIA_BACKPLANE, 134 ICE_MEDIA_DA, 135 }; 136 137 enum ice_vsi_type { 138 ICE_VSI_PF = 0, 139 ICE_VSI_VF = 1, 140 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */ 141 ICE_VSI_CHNL = 4, 142 ICE_VSI_LB = 6, 143 ICE_VSI_SWITCHDEV_CTRL = 7, 144 }; 145 146 struct ice_link_status { 147 /* Refer to ice_aq_phy_type for bits definition */ 148 u64 phy_type_low; 149 u64 phy_type_high; 150 u8 topo_media_conflict; 151 u16 max_frame_size; 152 u16 link_speed; 153 u16 req_speeds; 154 u8 link_cfg_err; 155 u8 lse_ena; /* Link Status Event notification */ 156 u8 link_info; 157 u8 an_info; 158 u8 ext_info; 159 u8 fec_info; 160 u8 pacing; 161 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of 162 * ice_aqc_get_phy_caps structure 163 */ 164 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 165 }; 166 167 /* Different reset sources for which a disable queue AQ call has to be made in 168 * order to clean the Tx scheduler as a part of the reset 169 */ 170 enum ice_disq_rst_src { 171 ICE_NO_RESET = 0, 172 ICE_VM_RESET, 173 ICE_VF_RESET, 174 }; 175 176 /* PHY info such as phy_type, etc... */ 177 struct ice_phy_info { 178 struct ice_link_status link_info; 179 struct ice_link_status link_info_old; 180 u64 phy_type_low; 181 u64 phy_type_high; 182 enum ice_media_type media_type; 183 u8 get_link_info; 184 /* Please refer to struct ice_aqc_get_link_status_data to get 185 * detail of enable bit in curr_user_speed_req 186 */ 187 u16 curr_user_speed_req; 188 enum ice_fec_mode curr_user_fec_req; 189 enum ice_fc_mode curr_user_fc_req; 190 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg; 191 }; 192 193 /* protocol enumeration for filters */ 194 enum ice_fltr_ptype { 195 /* NONE - used for undef/error */ 196 ICE_FLTR_PTYPE_NONF_NONE = 0, 197 ICE_FLTR_PTYPE_NONF_IPV4_UDP, 198 ICE_FLTR_PTYPE_NONF_IPV4_TCP, 199 ICE_FLTR_PTYPE_NONF_IPV4_SCTP, 200 ICE_FLTR_PTYPE_NONF_IPV4_OTHER, 201 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP, 202 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP, 203 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP, 204 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER, 205 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER, 206 ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3, 207 ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3, 208 ICE_FLTR_PTYPE_NONF_IPV4_ESP, 209 ICE_FLTR_PTYPE_NONF_IPV6_ESP, 210 ICE_FLTR_PTYPE_NONF_IPV4_AH, 211 ICE_FLTR_PTYPE_NONF_IPV6_AH, 212 ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP, 213 ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP, 214 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE, 215 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION, 216 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE, 217 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION, 218 ICE_FLTR_PTYPE_NON_IP_L2, 219 ICE_FLTR_PTYPE_FRAG_IPV4, 220 ICE_FLTR_PTYPE_NONF_IPV6_UDP, 221 ICE_FLTR_PTYPE_NONF_IPV6_TCP, 222 ICE_FLTR_PTYPE_NONF_IPV6_SCTP, 223 ICE_FLTR_PTYPE_NONF_IPV6_OTHER, 224 ICE_FLTR_PTYPE_MAX, 225 }; 226 227 enum ice_fd_hw_seg { 228 ICE_FD_HW_SEG_NON_TUN = 0, 229 ICE_FD_HW_SEG_TUN, 230 ICE_FD_HW_SEG_MAX, 231 }; 232 233 /* 1 ICE_VSI_PF + 1 ICE_VSI_CTRL + ICE_CHNL_MAX_TC */ 234 #define ICE_MAX_FDIR_VSI_PER_FILTER (2 + ICE_CHNL_MAX_TC) 235 236 struct ice_fd_hw_prof { 237 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX]; 238 int cnt; 239 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX]; 240 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER]; 241 }; 242 243 /* Common HW capabilities for SW use */ 244 struct ice_hw_common_caps { 245 u32 valid_functions; 246 /* DCB capabilities */ 247 u32 active_tc_bitmap; 248 u32 maxtc; 249 250 /* Tx/Rx queues */ 251 u16 num_rxq; /* Number/Total Rx queues */ 252 u16 rxq_first_id; /* First queue ID for Rx queues */ 253 u16 num_txq; /* Number/Total Tx queues */ 254 u16 txq_first_id; /* First queue ID for Tx queues */ 255 256 /* MSI-X vectors */ 257 u16 num_msix_vectors; 258 u16 msix_vector_first_id; 259 260 /* Max MTU for function or device */ 261 u16 max_mtu; 262 263 /* Virtualization support */ 264 u8 sr_iov_1_1; /* SR-IOV enabled */ 265 266 /* RSS related capabilities */ 267 u16 rss_table_size; /* 512 for PFs and 64 for VFs */ 268 u8 rss_table_entry_width; /* RSS Entry width in bits */ 269 270 u8 dcb; 271 u8 ieee_1588; 272 u8 rdma; 273 274 bool nvm_update_pending_nvm; 275 bool nvm_update_pending_orom; 276 bool nvm_update_pending_netlist; 277 #define ICE_NVM_PENDING_NVM_IMAGE BIT(0) 278 #define ICE_NVM_PENDING_OROM BIT(1) 279 #define ICE_NVM_PENDING_NETLIST BIT(2) 280 bool nvm_unified_update; 281 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) 282 /* PCIe reset avoidance */ 283 bool pcie_reset_avoidance; 284 /* Post update reset restriction */ 285 bool reset_restrict_support; 286 }; 287 288 /* IEEE 1588 TIME_SYNC specific info */ 289 /* Function specific definitions */ 290 #define ICE_TS_FUNC_ENA_M BIT(0) 291 #define ICE_TS_SRC_TMR_OWND_M BIT(1) 292 #define ICE_TS_TMR_ENA_M BIT(2) 293 #define ICE_TS_TMR_IDX_OWND_S 4 294 #define ICE_TS_TMR_IDX_OWND_M BIT(4) 295 #define ICE_TS_CLK_FREQ_S 16 296 #define ICE_TS_CLK_FREQ_M ICE_M(0x7, ICE_TS_CLK_FREQ_S) 297 #define ICE_TS_CLK_SRC_S 20 298 #define ICE_TS_CLK_SRC_M BIT(20) 299 #define ICE_TS_TMR_IDX_ASSOC_S 24 300 #define ICE_TS_TMR_IDX_ASSOC_M BIT(24) 301 302 /* TIME_REF clock rate specification */ 303 enum ice_time_ref_freq { 304 ICE_TIME_REF_FREQ_25_000 = 0, 305 ICE_TIME_REF_FREQ_122_880 = 1, 306 ICE_TIME_REF_FREQ_125_000 = 2, 307 ICE_TIME_REF_FREQ_153_600 = 3, 308 ICE_TIME_REF_FREQ_156_250 = 4, 309 ICE_TIME_REF_FREQ_245_760 = 5, 310 311 NUM_ICE_TIME_REF_FREQ 312 }; 313 314 /* Clock source specification */ 315 enum ice_clk_src { 316 ICE_CLK_SRC_TCX0 = 0, /* Temperature compensated oscillator */ 317 ICE_CLK_SRC_TIME_REF = 1, /* Use TIME_REF reference clock */ 318 319 NUM_ICE_CLK_SRC 320 }; 321 322 struct ice_ts_func_info { 323 /* Function specific info */ 324 enum ice_time_ref_freq time_ref; 325 u8 clk_freq; 326 u8 clk_src; 327 u8 tmr_index_assoc; 328 u8 ena; 329 u8 tmr_index_owned; 330 u8 src_tmr_owned; 331 u8 tmr_ena; 332 }; 333 334 /* Device specific definitions */ 335 #define ICE_TS_TMR0_OWNR_M 0x7 336 #define ICE_TS_TMR0_OWND_M BIT(3) 337 #define ICE_TS_TMR1_OWNR_S 4 338 #define ICE_TS_TMR1_OWNR_M ICE_M(0x7, ICE_TS_TMR1_OWNR_S) 339 #define ICE_TS_TMR1_OWND_M BIT(7) 340 #define ICE_TS_DEV_ENA_M BIT(24) 341 #define ICE_TS_TMR0_ENA_M BIT(25) 342 #define ICE_TS_TMR1_ENA_M BIT(26) 343 344 struct ice_ts_dev_info { 345 /* Device specific info */ 346 u32 ena_ports; 347 u32 tmr_own_map; 348 u32 tmr0_owner; 349 u32 tmr1_owner; 350 u8 tmr0_owned; 351 u8 tmr1_owned; 352 u8 ena; 353 u8 tmr0_ena; 354 u8 tmr1_ena; 355 }; 356 357 /* Function specific capabilities */ 358 struct ice_hw_func_caps { 359 struct ice_hw_common_caps common_cap; 360 u32 num_allocd_vfs; /* Number of allocated VFs */ 361 u32 vf_base_id; /* Logical ID of the first VF */ 362 u32 guar_num_vsi; 363 u32 fd_fltr_guar; /* Number of filters guaranteed */ 364 u32 fd_fltr_best_effort; /* Number of best effort filters */ 365 struct ice_ts_func_info ts_func_info; 366 }; 367 368 /* Device wide capabilities */ 369 struct ice_hw_dev_caps { 370 struct ice_hw_common_caps common_cap; 371 u32 num_vfs_exposed; /* Total number of VFs exposed */ 372 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ 373 u32 num_flow_director_fltr; /* Number of FD filters available */ 374 struct ice_ts_dev_info ts_dev_info; 375 u32 num_funcs; 376 }; 377 378 /* MAC info */ 379 struct ice_mac_info { 380 u8 lan_addr[ETH_ALEN]; 381 u8 perm_addr[ETH_ALEN]; 382 }; 383 384 /* Reset types used to determine which kind of reset was requested. These 385 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register. 386 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register 387 * because its reset source is different than the other types listed. 388 */ 389 enum ice_reset_req { 390 ICE_RESET_POR = 0, 391 ICE_RESET_INVAL = 0, 392 ICE_RESET_CORER = 1, 393 ICE_RESET_GLOBR = 2, 394 ICE_RESET_EMPR = 3, 395 ICE_RESET_PFR = 4, 396 }; 397 398 /* Bus parameters */ 399 struct ice_bus_info { 400 u16 device; 401 u8 func; 402 }; 403 404 /* Flow control (FC) parameters */ 405 struct ice_fc_info { 406 enum ice_fc_mode current_mode; /* FC mode in effect */ 407 enum ice_fc_mode req_mode; /* FC mode requested by caller */ 408 }; 409 410 /* Option ROM version information */ 411 struct ice_orom_info { 412 u8 major; /* Major version of OROM */ 413 u8 patch; /* Patch version of OROM */ 414 u16 build; /* Build version of OROM */ 415 }; 416 417 /* NVM version information */ 418 struct ice_nvm_info { 419 u32 eetrack; 420 u8 major; 421 u8 minor; 422 }; 423 424 /* netlist version information */ 425 struct ice_netlist_info { 426 u32 major; /* major high/low */ 427 u32 minor; /* minor high/low */ 428 u32 type; /* type high/low */ 429 u32 rev; /* revision high/low */ 430 u32 hash; /* SHA-1 hash word */ 431 u16 cust_ver; /* customer version */ 432 }; 433 434 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules 435 * of the flash image. 436 */ 437 enum ice_flash_bank { 438 ICE_INVALID_FLASH_BANK, 439 ICE_1ST_FLASH_BANK, 440 ICE_2ND_FLASH_BANK, 441 }; 442 443 /* Enumeration of which flash bank is desired to read from, either the active 444 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from 445 * code which just wants to read the active or inactive flash bank. 446 */ 447 enum ice_bank_select { 448 ICE_ACTIVE_FLASH_BANK, 449 ICE_INACTIVE_FLASH_BANK, 450 }; 451 452 /* information for accessing NVM, OROM, and Netlist flash banks */ 453 struct ice_bank_info { 454 u32 nvm_ptr; /* Pointer to 1st NVM bank */ 455 u32 nvm_size; /* Size of NVM bank */ 456 u32 orom_ptr; /* Pointer to 1st OROM bank */ 457 u32 orom_size; /* Size of OROM bank */ 458 u32 netlist_ptr; /* Pointer to 1st Netlist bank */ 459 u32 netlist_size; /* Size of Netlist bank */ 460 enum ice_flash_bank nvm_bank; /* Active NVM bank */ 461 enum ice_flash_bank orom_bank; /* Active OROM bank */ 462 enum ice_flash_bank netlist_bank; /* Active Netlist bank */ 463 }; 464 465 /* Flash Chip Information */ 466 struct ice_flash_info { 467 struct ice_orom_info orom; /* Option ROM version info */ 468 struct ice_nvm_info nvm; /* NVM version information */ 469 struct ice_netlist_info netlist;/* Netlist version info */ 470 struct ice_bank_info banks; /* Flash Bank information */ 471 u16 sr_words; /* Shadow RAM size in words */ 472 u32 flash_size; /* Size of available flash in bytes */ 473 u8 blank_nvm_mode; /* is NVM empty (no FW present) */ 474 }; 475 476 struct ice_link_default_override_tlv { 477 u8 options; 478 #define ICE_LINK_OVERRIDE_OPT_M 0x3F 479 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0) 480 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1) 481 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2) 482 #define ICE_LINK_OVERRIDE_EN BIT(3) 483 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4) 484 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5) 485 u8 phy_config; 486 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8 487 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S) 488 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3 489 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6) 490 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7) 491 u8 fec_options; 492 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF 493 u8 rsvd1; 494 u64 phy_type_low; 495 u64 phy_type_high; 496 }; 497 498 #define ICE_NVM_VER_LEN 32 499 500 /* Max number of port to queue branches w.r.t topology */ 501 #define ICE_MAX_TRAFFIC_CLASS 8 502 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS 503 504 #define ice_for_each_traffic_class(_i) \ 505 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++) 506 507 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects 508 * to driver defined policy for default aggregator 509 */ 510 #define ICE_INVAL_TEID 0xFFFFFFFF 511 #define ICE_DFLT_AGG_ID 0 512 513 struct ice_sched_node { 514 struct ice_sched_node *parent; 515 struct ice_sched_node *sibling; /* next sibling in the same layer */ 516 struct ice_sched_node **children; 517 struct ice_aqc_txsched_elem_data info; 518 u32 agg_id; /* aggregator group ID */ 519 u16 vsi_handle; 520 u8 in_use; /* suspended or in use */ 521 u8 tx_sched_layer; /* Logical Layer (1-9) */ 522 u8 num_children; 523 u8 tc_num; 524 u8 owner; 525 #define ICE_SCHED_NODE_OWNER_LAN 0 526 #define ICE_SCHED_NODE_OWNER_RDMA 2 527 }; 528 529 /* Access Macros for Tx Sched Elements data */ 530 #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid) 531 532 /* The aggregator type determines if identifier is for a VSI group, 533 * aggregator group, aggregator of queues, or queue group. 534 */ 535 enum ice_agg_type { 536 ICE_AGG_TYPE_UNKNOWN = 0, 537 ICE_AGG_TYPE_VSI, 538 ICE_AGG_TYPE_AGG, /* aggregator */ 539 ICE_AGG_TYPE_Q, 540 ICE_AGG_TYPE_QG 541 }; 542 543 /* Rate limit types */ 544 enum ice_rl_type { 545 ICE_UNKNOWN_BW = 0, 546 ICE_MIN_BW, /* for CIR profile */ 547 ICE_MAX_BW, /* for EIR profile */ 548 ICE_SHARED_BW /* for shared profile */ 549 }; 550 551 #define ICE_SCHED_MIN_BW 500 /* in Kbps */ 552 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */ 553 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */ 554 #define ICE_SCHED_DFLT_RL_PROF_ID 0 555 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF 556 #define ICE_SCHED_DFLT_BW_WT 4 557 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF 558 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */ 559 560 /* Data structure for saving BW information */ 561 enum ice_bw_type { 562 ICE_BW_TYPE_PRIO, 563 ICE_BW_TYPE_CIR, 564 ICE_BW_TYPE_CIR_WT, 565 ICE_BW_TYPE_EIR, 566 ICE_BW_TYPE_EIR_WT, 567 ICE_BW_TYPE_SHARED, 568 ICE_BW_TYPE_CNT /* This must be last */ 569 }; 570 571 struct ice_bw { 572 u32 bw; 573 u16 bw_alloc; 574 }; 575 576 struct ice_bw_type_info { 577 DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT); 578 u8 generic; 579 struct ice_bw cir_bw; 580 struct ice_bw eir_bw; 581 u32 shared_bw; 582 }; 583 584 /* VSI queue context structure for given TC */ 585 struct ice_q_ctx { 586 u16 q_handle; 587 u32 q_teid; 588 /* bw_t_info saves queue BW information */ 589 struct ice_bw_type_info bw_t_info; 590 }; 591 592 /* VSI type list entry to locate corresponding VSI/aggregator nodes */ 593 struct ice_sched_vsi_info { 594 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS]; 595 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS]; 596 struct list_head list_entry; 597 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS]; 598 u16 max_rdmaq[ICE_MAX_TRAFFIC_CLASS]; 599 /* bw_t_info saves VSI BW information */ 600 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS]; 601 }; 602 603 /* driver defines the policy */ 604 struct ice_sched_tx_policy { 605 u16 max_num_vsis; 606 u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS]; 607 u8 rdma_ena; 608 }; 609 610 /* CEE or IEEE 802.1Qaz ETS Configuration data */ 611 struct ice_dcb_ets_cfg { 612 u8 willing; 613 u8 cbs; 614 u8 maxtcs; 615 u8 prio_table[ICE_MAX_TRAFFIC_CLASS]; 616 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS]; 617 u8 tsatable[ICE_MAX_TRAFFIC_CLASS]; 618 }; 619 620 /* CEE or IEEE 802.1Qaz PFC Configuration data */ 621 struct ice_dcb_pfc_cfg { 622 u8 willing; 623 u8 mbc; 624 u8 pfccap; 625 u8 pfcena; 626 }; 627 628 /* CEE or IEEE 802.1Qaz Application Priority data */ 629 struct ice_dcb_app_priority_table { 630 u16 prot_id; 631 u8 priority; 632 u8 selector; 633 }; 634 635 #define ICE_MAX_USER_PRIORITY 8 636 #define ICE_DCBX_MAX_APPS 64 637 #define ICE_DSCP_NUM_VAL 64 638 #define ICE_LLDPDU_SIZE 1500 639 #define ICE_TLV_STATUS_OPER 0x1 640 #define ICE_TLV_STATUS_SYNC 0x2 641 #define ICE_TLV_STATUS_ERR 0x4 642 #define ICE_APP_PROT_ID_ISCSI_860 0x035c 643 #define ICE_APP_SEL_ETHTYPE 0x1 644 #define ICE_APP_SEL_TCPIP 0x2 645 #define ICE_CEE_APP_SEL_ETHTYPE 0x0 646 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134 647 #define ICE_CEE_APP_SEL_TCPIP 0x1 648 649 struct ice_dcbx_cfg { 650 u32 numapps; 651 u32 tlv_status; /* CEE mode TLV status */ 652 struct ice_dcb_ets_cfg etscfg; 653 struct ice_dcb_ets_cfg etsrec; 654 struct ice_dcb_pfc_cfg pfc; 655 #define ICE_QOS_MODE_VLAN 0x0 656 #define ICE_QOS_MODE_DSCP 0x1 657 u8 pfc_mode; 658 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS]; 659 /* when DSCP mapping defined by user set its bit to 1 */ 660 DECLARE_BITMAP(dscp_mapped, ICE_DSCP_NUM_VAL); 661 /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */ 662 u8 dscp_map[ICE_DSCP_NUM_VAL]; 663 u8 dcbx_mode; 664 #define ICE_DCBX_MODE_CEE 0x1 665 #define ICE_DCBX_MODE_IEEE 0x2 666 u8 app_mode; 667 #define ICE_DCBX_APPS_NON_WILLING 0x1 668 }; 669 670 struct ice_qos_cfg { 671 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */ 672 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */ 673 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */ 674 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */ 675 u8 is_sw_lldp : 1; 676 }; 677 678 struct ice_port_info { 679 struct ice_sched_node *root; /* Root Node per Port */ 680 struct ice_hw *hw; /* back pointer to HW instance */ 681 u32 last_node_teid; /* scheduler last node info */ 682 u16 sw_id; /* Initial switch ID belongs to port */ 683 u16 pf_vf_num; 684 u8 port_state; 685 #define ICE_SCHED_PORT_STATE_INIT 0x0 686 #define ICE_SCHED_PORT_STATE_READY 0x1 687 u8 lport; 688 #define ICE_LPORT_MASK 0xff 689 u16 dflt_tx_vsi_rule_id; 690 u16 dflt_tx_vsi_num; 691 u16 dflt_rx_vsi_rule_id; 692 u16 dflt_rx_vsi_num; 693 struct ice_fc_info fc; 694 struct ice_mac_info mac; 695 struct ice_phy_info phy; 696 struct mutex sched_lock; /* protect access to TXSched tree */ 697 struct ice_sched_node * 698 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM]; 699 /* List contain profile ID(s) and other params per layer */ 700 struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 701 struct ice_qos_cfg qos_cfg; 702 u8 is_vf:1; 703 }; 704 705 struct ice_switch_info { 706 struct list_head vsi_list_map_head; 707 struct ice_sw_recipe *recp_list; 708 u16 prof_res_bm_init; 709 u16 max_used_prof_index; 710 711 DECLARE_BITMAP(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS); 712 }; 713 714 /* FW logging configuration */ 715 struct ice_fw_log_evnt { 716 u8 cfg : 4; /* New event enables to configure */ 717 u8 cur : 4; /* Current/active event enables */ 718 }; 719 720 struct ice_fw_log_cfg { 721 u8 cq_en : 1; /* FW logging is enabled via the control queue */ 722 u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */ 723 u8 actv_evnts; /* Cumulation of currently enabled log events */ 724 725 #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S) 726 #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S) 727 #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S) 728 #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S) 729 struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX]; 730 }; 731 732 /* Enum defining the different states of the mailbox snapshot in the 733 * PF-VF mailbox overflow detection algorithm. The snapshot can be in 734 * states: 735 * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot 736 * within the mailbox buffer. 737 * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot 738 * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the 739 * mailbox and mark any VFs sending more messages than the threshold limit set. 740 * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF. 741 */ 742 enum ice_mbx_snapshot_state { 743 ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0, 744 ICE_MAL_VF_DETECT_STATE_TRAVERSE, 745 ICE_MAL_VF_DETECT_STATE_DETECT, 746 ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF, 747 }; 748 749 /* Structure to hold information of the static snapshot and the mailbox 750 * buffer data used to generate and track the snapshot. 751 * 1. state: the state of the mailbox snapshot in the malicious VF 752 * detection state handler ice_mbx_vf_state_handler() 753 * 2. head: head of the mailbox snapshot in a circular mailbox buffer 754 * 3. tail: tail of the mailbox snapshot in a circular mailbox buffer 755 * 4. num_iterations: number of messages traversed in circular mailbox buffer 756 * 5. num_msg_proc: number of messages processed in mailbox 757 * 6. num_pending_arq: number of pending asynchronous messages 758 * 7. max_num_msgs_mbx: maximum messages in mailbox for currently 759 * serviced work item or interrupt. 760 */ 761 struct ice_mbx_snap_buffer_data { 762 enum ice_mbx_snapshot_state state; 763 u32 head; 764 u32 tail; 765 u32 num_iterations; 766 u16 num_msg_proc; 767 u16 num_pending_arq; 768 u16 max_num_msgs_mbx; 769 }; 770 771 /* Structure to track messages sent by VFs on mailbox: 772 * 1. vf_cntr: a counter array of VFs to track the number of 773 * asynchronous messages sent by each VF 774 * 2. vfcntr_len: number of entries in VF counter array 775 */ 776 struct ice_mbx_vf_counter { 777 u32 *vf_cntr; 778 u32 vfcntr_len; 779 }; 780 781 /* Structure to hold data relevant to the captured static snapshot 782 * of the PF-VF mailbox. 783 */ 784 struct ice_mbx_snapshot { 785 struct ice_mbx_snap_buffer_data mbx_buf; 786 struct ice_mbx_vf_counter mbx_vf; 787 }; 788 789 /* Structure to hold data to be used for capturing or updating a 790 * static snapshot. 791 * 1. num_msg_proc: number of messages processed in mailbox 792 * 2. num_pending_arq: number of pending asynchronous messages 793 * 3. max_num_msgs_mbx: maximum messages in mailbox for currently 794 * serviced work item or interrupt. 795 * 4. async_watermark_val: An upper threshold set by caller to determine 796 * if the pending arq count is large enough to assume that there is 797 * the possibility of a mailicious VF. 798 */ 799 struct ice_mbx_data { 800 u16 num_msg_proc; 801 u16 num_pending_arq; 802 u16 max_num_msgs_mbx; 803 u16 async_watermark_val; 804 }; 805 806 /* Port hardware description */ 807 struct ice_hw { 808 u8 __iomem *hw_addr; 809 void *back; 810 struct ice_aqc_layer_props *layer_info; 811 struct ice_port_info *port_info; 812 /* PSM clock frequency for calculating RL profile params */ 813 u32 psm_clk_freq; 814 u64 debug_mask; /* bitmap for debug mask */ 815 enum ice_mac_type mac_type; 816 817 u16 fd_ctr_base; /* FD counter base index */ 818 819 /* pci info */ 820 u16 device_id; 821 u16 vendor_id; 822 u16 subsystem_device_id; 823 u16 subsystem_vendor_id; 824 u8 revision_id; 825 826 u8 pf_id; /* device profile info */ 827 828 u16 max_burst_size; /* driver sets this value */ 829 830 /* Tx Scheduler values */ 831 u8 num_tx_sched_layers; 832 u8 num_tx_sched_phys_layers; 833 u8 flattened_layers; 834 u8 max_cgds; 835 u8 sw_entry_point_layer; 836 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 837 struct list_head agg_list; /* lists all aggregator */ 838 839 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI]; 840 u8 evb_veb; /* true for VEB, false for VEPA */ 841 u8 reset_ongoing; /* true if HW is in reset, false otherwise */ 842 struct ice_bus_info bus; 843 struct ice_flash_info flash; 844 struct ice_hw_dev_caps dev_caps; /* device capabilities */ 845 struct ice_hw_func_caps func_caps; /* function capabilities */ 846 847 struct ice_switch_info *switch_info; /* switch filter lists */ 848 849 /* Control Queue info */ 850 struct ice_ctl_q_info adminq; 851 struct ice_ctl_q_info sbq; 852 struct ice_ctl_q_info mailboxq; 853 854 u8 api_branch; /* API branch version */ 855 u8 api_maj_ver; /* API major version */ 856 u8 api_min_ver; /* API minor version */ 857 u8 api_patch; /* API patch version */ 858 u8 fw_branch; /* firmware branch version */ 859 u8 fw_maj_ver; /* firmware major version */ 860 u8 fw_min_ver; /* firmware minor version */ 861 u8 fw_patch; /* firmware patch version */ 862 u32 fw_build; /* firmware build number */ 863 864 struct ice_fw_log_cfg fw_log; 865 866 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL 867 * register. Used for determining the ITR/INTRL granularity during 868 * initialization. 869 */ 870 #define ICE_MAX_AGG_BW_200G 0x0 871 #define ICE_MAX_AGG_BW_100G 0X1 872 #define ICE_MAX_AGG_BW_50G 0x2 873 #define ICE_MAX_AGG_BW_25G 0x3 874 /* ITR granularity for different speeds */ 875 #define ICE_ITR_GRAN_ABOVE_25 2 876 #define ICE_ITR_GRAN_MAX_25 4 877 /* ITR granularity in 1 us */ 878 u8 itr_gran; 879 /* INTRL granularity for different speeds */ 880 #define ICE_INTRL_GRAN_ABOVE_25 4 881 #define ICE_INTRL_GRAN_MAX_25 8 882 /* INTRL granularity in 1 us */ 883 u8 intrl_gran; 884 885 u8 ucast_shared; /* true if VSIs can share unicast addr */ 886 887 #define ICE_PHY_PER_NAC 1 888 #define ICE_MAX_QUAD 2 889 #define ICE_NUM_QUAD_TYPE 2 890 #define ICE_PORTS_PER_QUAD 4 891 #define ICE_PHY_0_LAST_QUAD 1 892 #define ICE_PORTS_PER_PHY 8 893 #define ICE_NUM_EXTERNAL_PORTS ICE_PORTS_PER_PHY 894 895 /* Active package version (currently active) */ 896 struct ice_pkg_ver active_pkg_ver; 897 u32 active_track_id; 898 u8 active_pkg_name[ICE_PKG_NAME_SIZE]; 899 u8 active_pkg_in_nvm; 900 901 /* Driver's package ver - (from the Ice Metadata section) */ 902 struct ice_pkg_ver pkg_ver; 903 u8 pkg_name[ICE_PKG_NAME_SIZE]; 904 905 /* Driver's Ice segment format version and ID (from the Ice seg) */ 906 struct ice_pkg_ver ice_seg_fmt_ver; 907 u8 ice_seg_id[ICE_SEG_ID_SIZE]; 908 909 /* Pointer to the ice segment */ 910 struct ice_seg *seg; 911 912 /* Pointer to allocated copy of pkg memory */ 913 u8 *pkg_copy; 914 u32 pkg_size; 915 916 /* tunneling info */ 917 struct mutex tnl_lock; 918 struct ice_tunnel_table tnl; 919 920 struct udp_tunnel_nic_shared udp_tunnel_shared; 921 struct udp_tunnel_nic_info udp_tunnel_nic; 922 923 /* HW block tables */ 924 struct ice_blk_info blk[ICE_BLK_COUNT]; 925 struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */ 926 struct list_head fl_profs[ICE_BLK_COUNT]; 927 928 /* Flow Director filter info */ 929 int fdir_active_fltr; 930 931 struct mutex fdir_fltr_lock; /* protect Flow Director */ 932 struct list_head fdir_list_head; 933 934 /* Book-keeping of side-band filter count per flow-type. 935 * This is used to detect and handle input set changes for 936 * respective flow-type. 937 */ 938 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX]; 939 940 struct ice_fd_hw_prof **fdir_prof; 941 DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX); 942 struct mutex rss_locks; /* protect RSS configuration */ 943 struct list_head rss_list_head; 944 struct ice_mbx_snapshot mbx_snapshot; 945 DECLARE_BITMAP(hw_ptype, ICE_FLOW_PTYPE_MAX); 946 u16 io_expander_handle; 947 }; 948 949 /* Statistics collected by each port, VSI, VEB, and S-channel */ 950 struct ice_eth_stats { 951 u64 rx_bytes; /* gorc */ 952 u64 rx_unicast; /* uprc */ 953 u64 rx_multicast; /* mprc */ 954 u64 rx_broadcast; /* bprc */ 955 u64 rx_discards; /* rdpc */ 956 u64 rx_unknown_protocol; /* rupp */ 957 u64 tx_bytes; /* gotc */ 958 u64 tx_unicast; /* uptc */ 959 u64 tx_multicast; /* mptc */ 960 u64 tx_broadcast; /* bptc */ 961 u64 tx_discards; /* tdpc */ 962 u64 tx_errors; /* tepc */ 963 }; 964 965 #define ICE_MAX_UP 8 966 967 /* Statistics collected by the MAC */ 968 struct ice_hw_port_stats { 969 /* eth stats collected by the port */ 970 struct ice_eth_stats eth; 971 /* additional port specific stats */ 972 u64 tx_dropped_link_down; /* tdold */ 973 u64 crc_errors; /* crcerrs */ 974 u64 illegal_bytes; /* illerrc */ 975 u64 error_bytes; /* errbc */ 976 u64 mac_local_faults; /* mlfc */ 977 u64 mac_remote_faults; /* mrfc */ 978 u64 rx_len_errors; /* rlec */ 979 u64 link_xon_rx; /* lxonrxc */ 980 u64 link_xoff_rx; /* lxoffrxc */ 981 u64 link_xon_tx; /* lxontxc */ 982 u64 link_xoff_tx; /* lxofftxc */ 983 u64 priority_xon_rx[8]; /* pxonrxc[8] */ 984 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 985 u64 priority_xon_tx[8]; /* pxontxc[8] */ 986 u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 987 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 988 u64 rx_size_64; /* prc64 */ 989 u64 rx_size_127; /* prc127 */ 990 u64 rx_size_255; /* prc255 */ 991 u64 rx_size_511; /* prc511 */ 992 u64 rx_size_1023; /* prc1023 */ 993 u64 rx_size_1522; /* prc1522 */ 994 u64 rx_size_big; /* prc9522 */ 995 u64 rx_undersize; /* ruc */ 996 u64 rx_fragments; /* rfc */ 997 u64 rx_oversize; /* roc */ 998 u64 rx_jabber; /* rjc */ 999 u64 tx_size_64; /* ptc64 */ 1000 u64 tx_size_127; /* ptc127 */ 1001 u64 tx_size_255; /* ptc255 */ 1002 u64 tx_size_511; /* ptc511 */ 1003 u64 tx_size_1023; /* ptc1023 */ 1004 u64 tx_size_1522; /* ptc1522 */ 1005 u64 tx_size_big; /* ptc9522 */ 1006 /* flow director stats */ 1007 u32 fd_sb_status; 1008 u64 fd_sb_match; 1009 }; 1010 1011 struct ice_aq_get_set_rss_lut_params { 1012 u16 vsi_handle; /* software VSI handle */ 1013 u16 lut_size; /* size of the LUT buffer */ 1014 u8 lut_type; /* type of the LUT (i.e. VSI, PF, Global) */ 1015 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */ 1016 u8 global_lut_id; /* only valid when lut_type is global */ 1017 }; 1018 1019 /* Checksum and Shadow RAM pointers */ 1020 #define ICE_SR_NVM_CTRL_WORD 0x00 1021 #define ICE_SR_BOOT_CFG_PTR 0x132 1022 #define ICE_SR_NVM_WOL_CFG 0x19 1023 #define ICE_NVM_OROM_VER_OFF 0x02 1024 #define ICE_SR_PBA_BLOCK_PTR 0x16 1025 #define ICE_SR_NVM_DEV_STARTER_VER 0x18 1026 #define ICE_SR_NVM_EETRACK_LO 0x2D 1027 #define ICE_SR_NVM_EETRACK_HI 0x2E 1028 #define ICE_NVM_VER_LO_SHIFT 0 1029 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT) 1030 #define ICE_NVM_VER_HI_SHIFT 12 1031 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT) 1032 #define ICE_OROM_VER_PATCH_SHIFT 0 1033 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT) 1034 #define ICE_OROM_VER_BUILD_SHIFT 8 1035 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT) 1036 #define ICE_OROM_VER_SHIFT 24 1037 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT) 1038 #define ICE_SR_PFA_PTR 0x40 1039 #define ICE_SR_1ST_NVM_BANK_PTR 0x42 1040 #define ICE_SR_NVM_BANK_SIZE 0x43 1041 #define ICE_SR_1ST_OROM_BANK_PTR 0x44 1042 #define ICE_SR_OROM_BANK_SIZE 0x45 1043 #define ICE_SR_NETLIST_BANK_PTR 0x46 1044 #define ICE_SR_NETLIST_BANK_SIZE 0x47 1045 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800 1046 1047 /* CSS Header words */ 1048 #define ICE_NVM_CSS_SREV_L 0x14 1049 #define ICE_NVM_CSS_SREV_H 0x15 1050 1051 /* Length of CSS header section in words */ 1052 #define ICE_CSS_HEADER_LENGTH 330 1053 1054 /* Offset of Shadow RAM copy in the NVM bank area. */ 1055 #define ICE_NVM_SR_COPY_WORD_OFFSET roundup(ICE_CSS_HEADER_LENGTH, 32) 1056 1057 /* Size in bytes of Option ROM trailer */ 1058 #define ICE_NVM_OROM_TRAILER_LENGTH (2 * ICE_CSS_HEADER_LENGTH) 1059 1060 /* The Link Topology Netlist section is stored as a series of words. It is 1061 * stored in the NVM as a TLV, with the first two words containing the type 1062 * and length. 1063 */ 1064 #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B 1065 #define ICE_NETLIST_TYPE_OFFSET 0x0000 1066 #define ICE_NETLIST_LEN_OFFSET 0x0001 1067 1068 /* The Link Topology section follows the TLV header. When reading the netlist 1069 * using ice_read_netlist_module, we need to account for the 2-word TLV 1070 * header. 1071 */ 1072 #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2) 1073 1074 #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000) 1075 #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001) 1076 1077 #define ICE_LINK_TOPO_NODE_COUNT_M ICE_M(0x3FF, 0) 1078 1079 /* The Netlist ID Block is located after all of the Link Topology nodes. */ 1080 #define ICE_NETLIST_ID_BLK_SIZE 0x30 1081 #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n)) 1082 1083 /* netlist ID block field offsets (word offsets) */ 1084 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02 1085 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03 1086 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04 1087 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05 1088 #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06 1089 #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07 1090 #define ICE_NETLIST_ID_BLK_REV_LOW 0x08 1091 #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09 1092 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n)) 1093 #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F 1094 1095 /* Auxiliary field, mask, and shift definition for Shadow RAM and NVM Flash */ 1096 #define ICE_SR_CTRL_WORD_1_S 0x06 1097 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S) 1098 #define ICE_SR_CTRL_WORD_VALID 0x1 1099 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3) 1100 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4) 1101 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5) 1102 1103 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15) 1104 1105 /* Link override related */ 1106 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10 1107 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4 1108 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2 1109 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1 1110 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2 1111 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1 1112 #define ICE_FW_API_LINK_OVERRIDE_MIN 5 1113 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2 1114 1115 #define ICE_SR_WORDS_IN_1KB 512 1116 1117 /* Hash redirection LUT for VSI - maximum array size */ 1118 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4) 1119 1120 /* AQ API version for LLDP_FILTER_CONTROL */ 1121 #define ICE_FW_API_LLDP_FLTR_MAJ 1 1122 #define ICE_FW_API_LLDP_FLTR_MIN 7 1123 #define ICE_FW_API_LLDP_FLTR_PATCH 1 1124 1125 /* AQ API version for report default configuration */ 1126 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1 1127 #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7 1128 #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3 1129 1130 #endif /* _ICE_TYPE_H_ */ 1131