1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_TYPE_H_ 5 #define _ICE_TYPE_H_ 6 7 #define ICE_BYTES_PER_WORD 2 8 #define ICE_BYTES_PER_DWORD 4 9 10 #include "ice_status.h" 11 #include "ice_hw_autogen.h" 12 #include "ice_osdep.h" 13 #include "ice_controlq.h" 14 #include "ice_lan_tx_rx.h" 15 #include "ice_flex_type.h" 16 #include "ice_protocol_type.h" 17 18 static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc) 19 { 20 return test_bit(tc, &bitmap); 21 } 22 23 static inline u64 round_up_64bit(u64 a, u32 b) 24 { 25 return div64_long(((a) + (b) / 2), (b)); 26 } 27 28 static inline u32 ice_round_to_num(u32 N, u32 R) 29 { 30 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) : 31 ((((N) + (R) - 1) / (R)) * (R))); 32 } 33 34 /* Driver always calls main vsi_handle first */ 35 #define ICE_MAIN_VSI_HANDLE 0 36 37 /* debug masks - set these bits in hw->debug_mask to control output */ 38 #define ICE_DBG_INIT BIT_ULL(1) 39 #define ICE_DBG_FW_LOG BIT_ULL(3) 40 #define ICE_DBG_LINK BIT_ULL(4) 41 #define ICE_DBG_PHY BIT_ULL(5) 42 #define ICE_DBG_QCTX BIT_ULL(6) 43 #define ICE_DBG_NVM BIT_ULL(7) 44 #define ICE_DBG_LAN BIT_ULL(8) 45 #define ICE_DBG_FLOW BIT_ULL(9) 46 #define ICE_DBG_SW BIT_ULL(13) 47 #define ICE_DBG_SCHED BIT_ULL(14) 48 #define ICE_DBG_PKG BIT_ULL(16) 49 #define ICE_DBG_RES BIT_ULL(17) 50 #define ICE_DBG_AQ_MSG BIT_ULL(24) 51 #define ICE_DBG_AQ_DESC BIT_ULL(25) 52 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26) 53 #define ICE_DBG_AQ_CMD BIT_ULL(27) 54 #define ICE_DBG_USER BIT_ULL(31) 55 56 enum ice_aq_res_ids { 57 ICE_NVM_RES_ID = 1, 58 ICE_SPD_RES_ID, 59 ICE_CHANGE_LOCK_RES_ID, 60 ICE_GLOBAL_CFG_LOCK_RES_ID 61 }; 62 63 /* FW update timeout definitions are in milliseconds */ 64 #define ICE_NVM_TIMEOUT 180000 65 #define ICE_CHANGE_LOCK_TIMEOUT 1000 66 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000 67 68 enum ice_aq_res_access_type { 69 ICE_RES_READ = 1, 70 ICE_RES_WRITE 71 }; 72 73 struct ice_driver_ver { 74 u8 major_ver; 75 u8 minor_ver; 76 u8 build_ver; 77 u8 subbuild_ver; 78 u8 driver_string[32]; 79 }; 80 81 enum ice_fc_mode { 82 ICE_FC_NONE = 0, 83 ICE_FC_RX_PAUSE, 84 ICE_FC_TX_PAUSE, 85 ICE_FC_FULL, 86 ICE_FC_PFC, 87 ICE_FC_DFLT 88 }; 89 90 enum ice_phy_cache_mode { 91 ICE_FC_MODE = 0, 92 ICE_SPEED_MODE, 93 ICE_FEC_MODE 94 }; 95 96 enum ice_fec_mode { 97 ICE_FEC_NONE = 0, 98 ICE_FEC_RS, 99 ICE_FEC_BASER, 100 ICE_FEC_AUTO 101 }; 102 103 struct ice_phy_cache_mode_data { 104 union { 105 enum ice_fec_mode curr_user_fec_req; 106 enum ice_fc_mode curr_user_fc_req; 107 u16 curr_user_speed_req; 108 } data; 109 }; 110 111 enum ice_set_fc_aq_failures { 112 ICE_SET_FC_AQ_FAIL_NONE = 0, 113 ICE_SET_FC_AQ_FAIL_GET, 114 ICE_SET_FC_AQ_FAIL_SET, 115 ICE_SET_FC_AQ_FAIL_UPDATE 116 }; 117 118 /* Various MAC types */ 119 enum ice_mac_type { 120 ICE_MAC_UNKNOWN = 0, 121 ICE_MAC_E810, 122 ICE_MAC_GENERIC, 123 }; 124 125 /* Media Types */ 126 enum ice_media_type { 127 ICE_MEDIA_UNKNOWN = 0, 128 ICE_MEDIA_FIBER, 129 ICE_MEDIA_BASET, 130 ICE_MEDIA_BACKPLANE, 131 ICE_MEDIA_DA, 132 }; 133 134 enum ice_vsi_type { 135 ICE_VSI_PF = 0, 136 ICE_VSI_VF = 1, 137 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */ 138 ICE_VSI_LB = 6, 139 }; 140 141 struct ice_link_status { 142 /* Refer to ice_aq_phy_type for bits definition */ 143 u64 phy_type_low; 144 u64 phy_type_high; 145 u8 topo_media_conflict; 146 u16 max_frame_size; 147 u16 link_speed; 148 u16 req_speeds; 149 u8 lse_ena; /* Link Status Event notification */ 150 u8 link_info; 151 u8 an_info; 152 u8 ext_info; 153 u8 fec_info; 154 u8 pacing; 155 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of 156 * ice_aqc_get_phy_caps structure 157 */ 158 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 159 }; 160 161 /* Different reset sources for which a disable queue AQ call has to be made in 162 * order to clean the Tx scheduler as a part of the reset 163 */ 164 enum ice_disq_rst_src { 165 ICE_NO_RESET = 0, 166 ICE_VM_RESET, 167 ICE_VF_RESET, 168 }; 169 170 /* PHY info such as phy_type, etc... */ 171 struct ice_phy_info { 172 struct ice_link_status link_info; 173 struct ice_link_status link_info_old; 174 u64 phy_type_low; 175 u64 phy_type_high; 176 enum ice_media_type media_type; 177 u8 get_link_info; 178 /* Please refer to struct ice_aqc_get_link_status_data to get 179 * detail of enable bit in curr_user_speed_req 180 */ 181 u16 curr_user_speed_req; 182 enum ice_fec_mode curr_user_fec_req; 183 enum ice_fc_mode curr_user_fc_req; 184 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg; 185 }; 186 187 /* protocol enumeration for filters */ 188 enum ice_fltr_ptype { 189 /* NONE - used for undef/error */ 190 ICE_FLTR_PTYPE_NONF_NONE = 0, 191 ICE_FLTR_PTYPE_NONF_IPV4_UDP, 192 ICE_FLTR_PTYPE_NONF_IPV4_TCP, 193 ICE_FLTR_PTYPE_NONF_IPV4_SCTP, 194 ICE_FLTR_PTYPE_NONF_IPV4_OTHER, 195 ICE_FLTR_PTYPE_FRAG_IPV4, 196 ICE_FLTR_PTYPE_NONF_IPV6_UDP, 197 ICE_FLTR_PTYPE_NONF_IPV6_TCP, 198 ICE_FLTR_PTYPE_NONF_IPV6_SCTP, 199 ICE_FLTR_PTYPE_NONF_IPV6_OTHER, 200 ICE_FLTR_PTYPE_MAX, 201 }; 202 203 enum ice_fd_hw_seg { 204 ICE_FD_HW_SEG_NON_TUN = 0, 205 ICE_FD_HW_SEG_TUN, 206 ICE_FD_HW_SEG_MAX, 207 }; 208 209 /* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */ 210 #define ICE_MAX_FDIR_VSI_PER_FILTER 2 211 212 struct ice_fd_hw_prof { 213 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX]; 214 int cnt; 215 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX]; 216 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER]; 217 }; 218 219 /* Common HW capabilities for SW use */ 220 struct ice_hw_common_caps { 221 u32 valid_functions; 222 /* DCB capabilities */ 223 u32 active_tc_bitmap; 224 u32 maxtc; 225 226 /* Tx/Rx queues */ 227 u16 num_rxq; /* Number/Total Rx queues */ 228 u16 rxq_first_id; /* First queue ID for Rx queues */ 229 u16 num_txq; /* Number/Total Tx queues */ 230 u16 txq_first_id; /* First queue ID for Tx queues */ 231 232 /* MSI-X vectors */ 233 u16 num_msix_vectors; 234 u16 msix_vector_first_id; 235 236 /* Max MTU for function or device */ 237 u16 max_mtu; 238 239 /* Virtualization support */ 240 u8 sr_iov_1_1; /* SR-IOV enabled */ 241 242 /* RSS related capabilities */ 243 u16 rss_table_size; /* 512 for PFs and 64 for VFs */ 244 u8 rss_table_entry_width; /* RSS Entry width in bits */ 245 246 u8 dcb; 247 248 bool nvm_update_pending_nvm; 249 bool nvm_update_pending_orom; 250 bool nvm_update_pending_netlist; 251 #define ICE_NVM_PENDING_NVM_IMAGE BIT(0) 252 #define ICE_NVM_PENDING_OROM BIT(1) 253 #define ICE_NVM_PENDING_NETLIST BIT(2) 254 bool nvm_unified_update; 255 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) 256 }; 257 258 /* Function specific capabilities */ 259 struct ice_hw_func_caps { 260 struct ice_hw_common_caps common_cap; 261 u32 num_allocd_vfs; /* Number of allocated VFs */ 262 u32 vf_base_id; /* Logical ID of the first VF */ 263 u32 guar_num_vsi; 264 u32 fd_fltr_guar; /* Number of filters guaranteed */ 265 u32 fd_fltr_best_effort; /* Number of best effort filters */ 266 }; 267 268 /* Device wide capabilities */ 269 struct ice_hw_dev_caps { 270 struct ice_hw_common_caps common_cap; 271 u32 num_vfs_exposed; /* Total number of VFs exposed */ 272 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ 273 u32 num_flow_director_fltr; /* Number of FD filters available */ 274 u32 num_funcs; 275 }; 276 277 /* MAC info */ 278 struct ice_mac_info { 279 u8 lan_addr[ETH_ALEN]; 280 u8 perm_addr[ETH_ALEN]; 281 }; 282 283 /* Reset types used to determine which kind of reset was requested. These 284 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register. 285 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register 286 * because its reset source is different than the other types listed. 287 */ 288 enum ice_reset_req { 289 ICE_RESET_POR = 0, 290 ICE_RESET_INVAL = 0, 291 ICE_RESET_CORER = 1, 292 ICE_RESET_GLOBR = 2, 293 ICE_RESET_EMPR = 3, 294 ICE_RESET_PFR = 4, 295 }; 296 297 /* Bus parameters */ 298 struct ice_bus_info { 299 u16 device; 300 u8 func; 301 }; 302 303 /* Flow control (FC) parameters */ 304 struct ice_fc_info { 305 enum ice_fc_mode current_mode; /* FC mode in effect */ 306 enum ice_fc_mode req_mode; /* FC mode requested by caller */ 307 }; 308 309 /* Option ROM version information */ 310 struct ice_orom_info { 311 u8 major; /* Major version of OROM */ 312 u8 patch; /* Patch version of OROM */ 313 u16 build; /* Build version of OROM */ 314 }; 315 316 /* NVM version information */ 317 struct ice_nvm_info { 318 u32 eetrack; 319 u8 major; 320 u8 minor; 321 }; 322 323 /* netlist version information */ 324 struct ice_netlist_info { 325 u32 major; /* major high/low */ 326 u32 minor; /* minor high/low */ 327 u32 type; /* type high/low */ 328 u32 rev; /* revision high/low */ 329 u32 hash; /* SHA-1 hash word */ 330 u16 cust_ver; /* customer version */ 331 }; 332 333 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules 334 * of the flash image. 335 */ 336 enum ice_flash_bank { 337 ICE_INVALID_FLASH_BANK, 338 ICE_1ST_FLASH_BANK, 339 ICE_2ND_FLASH_BANK, 340 }; 341 342 /* Enumeration of which flash bank is desired to read from, either the active 343 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from 344 * code which just wants to read the active or inactive flash bank. 345 */ 346 enum ice_bank_select { 347 ICE_ACTIVE_FLASH_BANK, 348 ICE_INACTIVE_FLASH_BANK, 349 }; 350 351 /* information for accessing NVM, OROM, and Netlist flash banks */ 352 struct ice_bank_info { 353 u32 nvm_ptr; /* Pointer to 1st NVM bank */ 354 u32 nvm_size; /* Size of NVM bank */ 355 u32 orom_ptr; /* Pointer to 1st OROM bank */ 356 u32 orom_size; /* Size of OROM bank */ 357 u32 netlist_ptr; /* Pointer to 1st Netlist bank */ 358 u32 netlist_size; /* Size of Netlist bank */ 359 enum ice_flash_bank nvm_bank; /* Active NVM bank */ 360 enum ice_flash_bank orom_bank; /* Active OROM bank */ 361 enum ice_flash_bank netlist_bank; /* Active Netlist bank */ 362 }; 363 364 /* Flash Chip Information */ 365 struct ice_flash_info { 366 struct ice_orom_info orom; /* Option ROM version info */ 367 struct ice_nvm_info nvm; /* NVM version information */ 368 struct ice_netlist_info netlist;/* Netlist version info */ 369 struct ice_bank_info banks; /* Flash Bank information */ 370 u16 sr_words; /* Shadow RAM size in words */ 371 u32 flash_size; /* Size of available flash in bytes */ 372 u8 blank_nvm_mode; /* is NVM empty (no FW present) */ 373 }; 374 375 struct ice_link_default_override_tlv { 376 u8 options; 377 #define ICE_LINK_OVERRIDE_OPT_M 0x3F 378 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0) 379 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1) 380 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2) 381 #define ICE_LINK_OVERRIDE_EN BIT(3) 382 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4) 383 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5) 384 u8 phy_config; 385 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8 386 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S) 387 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3 388 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6) 389 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7) 390 u8 fec_options; 391 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF 392 u8 rsvd1; 393 u64 phy_type_low; 394 u64 phy_type_high; 395 }; 396 397 #define ICE_NVM_VER_LEN 32 398 399 /* Max number of port to queue branches w.r.t topology */ 400 #define ICE_MAX_TRAFFIC_CLASS 8 401 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS 402 403 #define ice_for_each_traffic_class(_i) \ 404 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++) 405 406 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects 407 * to driver defined policy for default aggregator 408 */ 409 #define ICE_INVAL_TEID 0xFFFFFFFF 410 #define ICE_DFLT_AGG_ID 0 411 412 struct ice_sched_node { 413 struct ice_sched_node *parent; 414 struct ice_sched_node *sibling; /* next sibling in the same layer */ 415 struct ice_sched_node **children; 416 struct ice_aqc_txsched_elem_data info; 417 u32 agg_id; /* aggregator group ID */ 418 u16 vsi_handle; 419 u8 in_use; /* suspended or in use */ 420 u8 tx_sched_layer; /* Logical Layer (1-9) */ 421 u8 num_children; 422 u8 tc_num; 423 u8 owner; 424 #define ICE_SCHED_NODE_OWNER_LAN 0 425 }; 426 427 /* Access Macros for Tx Sched Elements data */ 428 #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid) 429 430 /* The aggregator type determines if identifier is for a VSI group, 431 * aggregator group, aggregator of queues, or queue group. 432 */ 433 enum ice_agg_type { 434 ICE_AGG_TYPE_UNKNOWN = 0, 435 ICE_AGG_TYPE_VSI, 436 ICE_AGG_TYPE_AGG, /* aggregator */ 437 ICE_AGG_TYPE_Q, 438 ICE_AGG_TYPE_QG 439 }; 440 441 /* Rate limit types */ 442 enum ice_rl_type { 443 ICE_UNKNOWN_BW = 0, 444 ICE_MIN_BW, /* for CIR profile */ 445 ICE_MAX_BW, /* for EIR profile */ 446 ICE_SHARED_BW /* for shared profile */ 447 }; 448 449 #define ICE_SCHED_MIN_BW 500 /* in Kbps */ 450 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */ 451 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */ 452 #define ICE_SCHED_DFLT_RL_PROF_ID 0 453 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF 454 #define ICE_SCHED_DFLT_BW_WT 4 455 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF 456 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */ 457 458 /* Data structure for saving BW information */ 459 enum ice_bw_type { 460 ICE_BW_TYPE_PRIO, 461 ICE_BW_TYPE_CIR, 462 ICE_BW_TYPE_CIR_WT, 463 ICE_BW_TYPE_EIR, 464 ICE_BW_TYPE_EIR_WT, 465 ICE_BW_TYPE_SHARED, 466 ICE_BW_TYPE_CNT /* This must be last */ 467 }; 468 469 struct ice_bw { 470 u32 bw; 471 u16 bw_alloc; 472 }; 473 474 struct ice_bw_type_info { 475 DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT); 476 u8 generic; 477 struct ice_bw cir_bw; 478 struct ice_bw eir_bw; 479 u32 shared_bw; 480 }; 481 482 /* VSI queue context structure for given TC */ 483 struct ice_q_ctx { 484 u16 q_handle; 485 u32 q_teid; 486 /* bw_t_info saves queue BW information */ 487 struct ice_bw_type_info bw_t_info; 488 }; 489 490 /* VSI type list entry to locate corresponding VSI/aggregator nodes */ 491 struct ice_sched_vsi_info { 492 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS]; 493 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS]; 494 struct list_head list_entry; 495 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS]; 496 }; 497 498 /* driver defines the policy */ 499 struct ice_sched_tx_policy { 500 u16 max_num_vsis; 501 u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS]; 502 u8 rdma_ena; 503 }; 504 505 /* CEE or IEEE 802.1Qaz ETS Configuration data */ 506 struct ice_dcb_ets_cfg { 507 u8 willing; 508 u8 cbs; 509 u8 maxtcs; 510 u8 prio_table[ICE_MAX_TRAFFIC_CLASS]; 511 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS]; 512 u8 tsatable[ICE_MAX_TRAFFIC_CLASS]; 513 }; 514 515 /* CEE or IEEE 802.1Qaz PFC Configuration data */ 516 struct ice_dcb_pfc_cfg { 517 u8 willing; 518 u8 mbc; 519 u8 pfccap; 520 u8 pfcena; 521 }; 522 523 /* CEE or IEEE 802.1Qaz Application Priority data */ 524 struct ice_dcb_app_priority_table { 525 u16 prot_id; 526 u8 priority; 527 u8 selector; 528 }; 529 530 #define ICE_MAX_USER_PRIORITY 8 531 #define ICE_DCBX_MAX_APPS 32 532 #define ICE_LLDPDU_SIZE 1500 533 #define ICE_TLV_STATUS_OPER 0x1 534 #define ICE_TLV_STATUS_SYNC 0x2 535 #define ICE_TLV_STATUS_ERR 0x4 536 #define ICE_APP_PROT_ID_FCOE 0x8906 537 #define ICE_APP_PROT_ID_ISCSI 0x0cbc 538 #define ICE_APP_PROT_ID_ISCSI_860 0x035c 539 #define ICE_APP_PROT_ID_FIP 0x8914 540 #define ICE_APP_SEL_ETHTYPE 0x1 541 #define ICE_APP_SEL_TCPIP 0x2 542 #define ICE_CEE_APP_SEL_ETHTYPE 0x0 543 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134 544 #define ICE_CEE_APP_SEL_TCPIP 0x1 545 546 struct ice_dcbx_cfg { 547 u32 numapps; 548 u32 tlv_status; /* CEE mode TLV status */ 549 struct ice_dcb_ets_cfg etscfg; 550 struct ice_dcb_ets_cfg etsrec; 551 struct ice_dcb_pfc_cfg pfc; 552 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS]; 553 u8 dcbx_mode; 554 #define ICE_DCBX_MODE_CEE 0x1 555 #define ICE_DCBX_MODE_IEEE 0x2 556 u8 app_mode; 557 #define ICE_DCBX_APPS_NON_WILLING 0x1 558 }; 559 560 struct ice_qos_cfg { 561 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */ 562 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */ 563 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */ 564 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */ 565 u8 is_sw_lldp : 1; 566 }; 567 568 struct ice_port_info { 569 struct ice_sched_node *root; /* Root Node per Port */ 570 struct ice_hw *hw; /* back pointer to HW instance */ 571 u32 last_node_teid; /* scheduler last node info */ 572 u16 sw_id; /* Initial switch ID belongs to port */ 573 u16 pf_vf_num; 574 u8 port_state; 575 #define ICE_SCHED_PORT_STATE_INIT 0x0 576 #define ICE_SCHED_PORT_STATE_READY 0x1 577 u8 lport; 578 #define ICE_LPORT_MASK 0xff 579 u16 dflt_tx_vsi_rule_id; 580 u16 dflt_tx_vsi_num; 581 u16 dflt_rx_vsi_rule_id; 582 u16 dflt_rx_vsi_num; 583 struct ice_fc_info fc; 584 struct ice_mac_info mac; 585 struct ice_phy_info phy; 586 struct mutex sched_lock; /* protect access to TXSched tree */ 587 struct ice_sched_node * 588 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM]; 589 /* List contain profile ID(s) and other params per layer */ 590 struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 591 struct ice_qos_cfg qos_cfg; 592 u8 is_vf:1; 593 }; 594 595 struct ice_switch_info { 596 struct list_head vsi_list_map_head; 597 struct ice_sw_recipe *recp_list; 598 }; 599 600 /* FW logging configuration */ 601 struct ice_fw_log_evnt { 602 u8 cfg : 4; /* New event enables to configure */ 603 u8 cur : 4; /* Current/active event enables */ 604 }; 605 606 struct ice_fw_log_cfg { 607 u8 cq_en : 1; /* FW logging is enabled via the control queue */ 608 u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */ 609 u8 actv_evnts; /* Cumulation of currently enabled log events */ 610 611 #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S) 612 #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S) 613 #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S) 614 #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S) 615 struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX]; 616 }; 617 618 /* Port hardware description */ 619 struct ice_hw { 620 u8 __iomem *hw_addr; 621 void *back; 622 struct ice_aqc_layer_props *layer_info; 623 struct ice_port_info *port_info; 624 /* PSM clock frequency for calculating RL profile params */ 625 u32 psm_clk_freq; 626 u64 debug_mask; /* bitmap for debug mask */ 627 enum ice_mac_type mac_type; 628 629 u16 fd_ctr_base; /* FD counter base index */ 630 631 /* pci info */ 632 u16 device_id; 633 u16 vendor_id; 634 u16 subsystem_device_id; 635 u16 subsystem_vendor_id; 636 u8 revision_id; 637 638 u8 pf_id; /* device profile info */ 639 640 u16 max_burst_size; /* driver sets this value */ 641 642 /* Tx Scheduler values */ 643 u8 num_tx_sched_layers; 644 u8 num_tx_sched_phys_layers; 645 u8 flattened_layers; 646 u8 max_cgds; 647 u8 sw_entry_point_layer; 648 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 649 struct list_head agg_list; /* lists all aggregator */ 650 651 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI]; 652 u8 evb_veb; /* true for VEB, false for VEPA */ 653 u8 reset_ongoing; /* true if HW is in reset, false otherwise */ 654 struct ice_bus_info bus; 655 struct ice_flash_info flash; 656 struct ice_hw_dev_caps dev_caps; /* device capabilities */ 657 struct ice_hw_func_caps func_caps; /* function capabilities */ 658 659 struct ice_switch_info *switch_info; /* switch filter lists */ 660 661 /* Control Queue info */ 662 struct ice_ctl_q_info adminq; 663 struct ice_ctl_q_info mailboxq; 664 665 u8 api_branch; /* API branch version */ 666 u8 api_maj_ver; /* API major version */ 667 u8 api_min_ver; /* API minor version */ 668 u8 api_patch; /* API patch version */ 669 u8 fw_branch; /* firmware branch version */ 670 u8 fw_maj_ver; /* firmware major version */ 671 u8 fw_min_ver; /* firmware minor version */ 672 u8 fw_patch; /* firmware patch version */ 673 u32 fw_build; /* firmware build number */ 674 675 struct ice_fw_log_cfg fw_log; 676 677 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL 678 * register. Used for determining the ITR/INTRL granularity during 679 * initialization. 680 */ 681 #define ICE_MAX_AGG_BW_200G 0x0 682 #define ICE_MAX_AGG_BW_100G 0X1 683 #define ICE_MAX_AGG_BW_50G 0x2 684 #define ICE_MAX_AGG_BW_25G 0x3 685 /* ITR granularity for different speeds */ 686 #define ICE_ITR_GRAN_ABOVE_25 2 687 #define ICE_ITR_GRAN_MAX_25 4 688 /* ITR granularity in 1 us */ 689 u8 itr_gran; 690 /* INTRL granularity for different speeds */ 691 #define ICE_INTRL_GRAN_ABOVE_25 4 692 #define ICE_INTRL_GRAN_MAX_25 8 693 /* INTRL granularity in 1 us */ 694 u8 intrl_gran; 695 696 u8 ucast_shared; /* true if VSIs can share unicast addr */ 697 698 /* Active package version (currently active) */ 699 struct ice_pkg_ver active_pkg_ver; 700 u32 active_track_id; 701 u8 active_pkg_name[ICE_PKG_NAME_SIZE]; 702 u8 active_pkg_in_nvm; 703 704 enum ice_aq_err pkg_dwnld_status; 705 706 /* Driver's package ver - (from the Metadata seg) */ 707 struct ice_pkg_ver pkg_ver; 708 u8 pkg_name[ICE_PKG_NAME_SIZE]; 709 710 /* Driver's Ice package version (from the Ice seg) */ 711 struct ice_pkg_ver ice_pkg_ver; 712 u8 ice_pkg_name[ICE_PKG_NAME_SIZE]; 713 714 /* Pointer to the ice segment */ 715 struct ice_seg *seg; 716 717 /* Pointer to allocated copy of pkg memory */ 718 u8 *pkg_copy; 719 u32 pkg_size; 720 721 /* tunneling info */ 722 struct mutex tnl_lock; 723 struct ice_tunnel_table tnl; 724 725 struct udp_tunnel_nic_shared udp_tunnel_shared; 726 struct udp_tunnel_nic_info udp_tunnel_nic; 727 728 /* HW block tables */ 729 struct ice_blk_info blk[ICE_BLK_COUNT]; 730 struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */ 731 struct list_head fl_profs[ICE_BLK_COUNT]; 732 733 /* Flow Director filter info */ 734 int fdir_active_fltr; 735 736 struct mutex fdir_fltr_lock; /* protect Flow Director */ 737 struct list_head fdir_list_head; 738 739 /* Book-keeping of side-band filter count per flow-type. 740 * This is used to detect and handle input set changes for 741 * respective flow-type. 742 */ 743 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX]; 744 745 struct ice_fd_hw_prof **fdir_prof; 746 DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX); 747 struct mutex rss_locks; /* protect RSS configuration */ 748 struct list_head rss_list_head; 749 }; 750 751 /* Statistics collected by each port, VSI, VEB, and S-channel */ 752 struct ice_eth_stats { 753 u64 rx_bytes; /* gorc */ 754 u64 rx_unicast; /* uprc */ 755 u64 rx_multicast; /* mprc */ 756 u64 rx_broadcast; /* bprc */ 757 u64 rx_discards; /* rdpc */ 758 u64 rx_unknown_protocol; /* rupp */ 759 u64 tx_bytes; /* gotc */ 760 u64 tx_unicast; /* uptc */ 761 u64 tx_multicast; /* mptc */ 762 u64 tx_broadcast; /* bptc */ 763 u64 tx_discards; /* tdpc */ 764 u64 tx_errors; /* tepc */ 765 }; 766 767 #define ICE_MAX_UP 8 768 769 /* Statistics collected by the MAC */ 770 struct ice_hw_port_stats { 771 /* eth stats collected by the port */ 772 struct ice_eth_stats eth; 773 /* additional port specific stats */ 774 u64 tx_dropped_link_down; /* tdold */ 775 u64 crc_errors; /* crcerrs */ 776 u64 illegal_bytes; /* illerrc */ 777 u64 error_bytes; /* errbc */ 778 u64 mac_local_faults; /* mlfc */ 779 u64 mac_remote_faults; /* mrfc */ 780 u64 rx_len_errors; /* rlec */ 781 u64 link_xon_rx; /* lxonrxc */ 782 u64 link_xoff_rx; /* lxoffrxc */ 783 u64 link_xon_tx; /* lxontxc */ 784 u64 link_xoff_tx; /* lxofftxc */ 785 u64 priority_xon_rx[8]; /* pxonrxc[8] */ 786 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 787 u64 priority_xon_tx[8]; /* pxontxc[8] */ 788 u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 789 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 790 u64 rx_size_64; /* prc64 */ 791 u64 rx_size_127; /* prc127 */ 792 u64 rx_size_255; /* prc255 */ 793 u64 rx_size_511; /* prc511 */ 794 u64 rx_size_1023; /* prc1023 */ 795 u64 rx_size_1522; /* prc1522 */ 796 u64 rx_size_big; /* prc9522 */ 797 u64 rx_undersize; /* ruc */ 798 u64 rx_fragments; /* rfc */ 799 u64 rx_oversize; /* roc */ 800 u64 rx_jabber; /* rjc */ 801 u64 tx_size_64; /* ptc64 */ 802 u64 tx_size_127; /* ptc127 */ 803 u64 tx_size_255; /* ptc255 */ 804 u64 tx_size_511; /* ptc511 */ 805 u64 tx_size_1023; /* ptc1023 */ 806 u64 tx_size_1522; /* ptc1522 */ 807 u64 tx_size_big; /* ptc9522 */ 808 /* flow director stats */ 809 u32 fd_sb_status; 810 u64 fd_sb_match; 811 }; 812 813 /* Checksum and Shadow RAM pointers */ 814 #define ICE_SR_NVM_CTRL_WORD 0x00 815 #define ICE_SR_BOOT_CFG_PTR 0x132 816 #define ICE_SR_NVM_WOL_CFG 0x19 817 #define ICE_NVM_OROM_VER_OFF 0x02 818 #define ICE_SR_PBA_BLOCK_PTR 0x16 819 #define ICE_SR_NVM_DEV_STARTER_VER 0x18 820 #define ICE_SR_NVM_EETRACK_LO 0x2D 821 #define ICE_SR_NVM_EETRACK_HI 0x2E 822 #define ICE_NVM_VER_LO_SHIFT 0 823 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT) 824 #define ICE_NVM_VER_HI_SHIFT 12 825 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT) 826 #define ICE_OROM_VER_PATCH_SHIFT 0 827 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT) 828 #define ICE_OROM_VER_BUILD_SHIFT 8 829 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT) 830 #define ICE_OROM_VER_SHIFT 24 831 #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT) 832 #define ICE_SR_PFA_PTR 0x40 833 #define ICE_SR_1ST_NVM_BANK_PTR 0x42 834 #define ICE_SR_NVM_BANK_SIZE 0x43 835 #define ICE_SR_1ST_OROM_BANK_PTR 0x44 836 #define ICE_SR_OROM_BANK_SIZE 0x45 837 #define ICE_SR_NETLIST_BANK_PTR 0x46 838 #define ICE_SR_NETLIST_BANK_SIZE 0x47 839 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800 840 841 /* CSS Header words */ 842 #define ICE_NVM_CSS_SREV_L 0x14 843 #define ICE_NVM_CSS_SREV_H 0x15 844 845 /* Length of CSS header section in words */ 846 #define ICE_CSS_HEADER_LENGTH 330 847 848 /* Offset of Shadow RAM copy in the NVM bank area. */ 849 #define ICE_NVM_SR_COPY_WORD_OFFSET roundup(ICE_CSS_HEADER_LENGTH, 32) 850 851 /* Size in bytes of Option ROM trailer */ 852 #define ICE_NVM_OROM_TRAILER_LENGTH (2 * ICE_CSS_HEADER_LENGTH) 853 854 /* The Link Topology Netlist section is stored as a series of words. It is 855 * stored in the NVM as a TLV, with the first two words containing the type 856 * and length. 857 */ 858 #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B 859 #define ICE_NETLIST_TYPE_OFFSET 0x0000 860 #define ICE_NETLIST_LEN_OFFSET 0x0001 861 862 /* The Link Topology section follows the TLV header. When reading the netlist 863 * using ice_read_netlist_module, we need to account for the 2-word TLV 864 * header. 865 */ 866 #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2) 867 868 #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000) 869 #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001) 870 871 #define ICE_LINK_TOPO_NODE_COUNT_M ICE_M(0x3FF, 0) 872 873 /* The Netlist ID Block is located after all of the Link Topology nodes. */ 874 #define ICE_NETLIST_ID_BLK_SIZE 0x30 875 #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n)) 876 877 /* netlist ID block field offsets (word offsets) */ 878 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02 879 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03 880 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04 881 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05 882 #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06 883 #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07 884 #define ICE_NETLIST_ID_BLK_REV_LOW 0x08 885 #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09 886 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n)) 887 #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F 888 889 /* Auxiliary field, mask, and shift definition for Shadow RAM and NVM Flash */ 890 #define ICE_SR_CTRL_WORD_1_S 0x06 891 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S) 892 #define ICE_SR_CTRL_WORD_VALID 0x1 893 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3) 894 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4) 895 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5) 896 897 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15) 898 899 /* Link override related */ 900 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10 901 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4 902 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2 903 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1 904 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2 905 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1 906 #define ICE_FW_API_LINK_OVERRIDE_MIN 5 907 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2 908 909 #define ICE_SR_WORDS_IN_1KB 512 910 911 /* Hash redirection LUT for VSI - maximum array size */ 912 #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4) 913 914 /* AQ API version for LLDP_FILTER_CONTROL */ 915 #define ICE_FW_API_LLDP_FLTR_MAJ 1 916 #define ICE_FW_API_LLDP_FLTR_MIN 7 917 #define ICE_FW_API_LLDP_FLTR_PATCH 1 918 919 #endif /* _ICE_TYPE_H_ */ 920