1837f08fdSAnirudh Venkataramanan /* SPDX-License-Identifier: GPL-2.0 */ 2837f08fdSAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */ 3837f08fdSAnirudh Venkataramanan 4837f08fdSAnirudh Venkataramanan #ifndef _ICE_TYPE_H_ 5837f08fdSAnirudh Venkataramanan #define _ICE_TYPE_H_ 6837f08fdSAnirudh Venkataramanan 76a025730STony Nguyen #define ICE_BYTES_PER_WORD 2 86a025730STony Nguyen #define ICE_BYTES_PER_DWORD 4 96a025730STony Nguyen 107ec59eeaSAnirudh Venkataramanan #include "ice_status.h" 117ec59eeaSAnirudh Venkataramanan #include "ice_hw_autogen.h" 127ec59eeaSAnirudh Venkataramanan #include "ice_osdep.h" 137ec59eeaSAnirudh Venkataramanan #include "ice_controlq.h" 14cdedef59SAnirudh Venkataramanan #include "ice_lan_tx_rx.h" 15c7648810STony Nguyen #include "ice_flex_type.h" 1631ad4e4eSTony Nguyen #include "ice_protocol_type.h" 177ec59eeaSAnirudh Venkataramanan 1835b4f437SJacob Keller static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc) 195513b920SAnirudh Venkataramanan { 2035b4f437SJacob Keller return test_bit(tc, &bitmap); 215513b920SAnirudh Venkataramanan } 225513b920SAnirudh Venkataramanan 231ddef455SUsha Ketineni static inline u64 round_up_64bit(u64 a, u32 b) 241ddef455SUsha Ketineni { 251ddef455SUsha Ketineni return div64_long(((a) + (b) / 2), (b)); 261ddef455SUsha Ketineni } 271ddef455SUsha Ketineni 281ddef455SUsha Ketineni static inline u32 ice_round_to_num(u32 N, u32 R) 291ddef455SUsha Ketineni { 301ddef455SUsha Ketineni return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) : 311ddef455SUsha Ketineni ((((N) + (R) - 1) / (R)) * (R))); 321ddef455SUsha Ketineni } 331ddef455SUsha Ketineni 34334cb062SAnirudh Venkataramanan /* Driver always calls main vsi_handle first */ 35334cb062SAnirudh Venkataramanan #define ICE_MAIN_VSI_HANDLE 0 36334cb062SAnirudh Venkataramanan 377ec59eeaSAnirudh Venkataramanan /* debug masks - set these bits in hw->debug_mask to control output */ 38f31e4b6fSAnirudh Venkataramanan #define ICE_DBG_INIT BIT_ULL(1) 394f70daa0SJacob Keller #define ICE_DBG_FW_LOG BIT_ULL(3) 400b28b702SAnirudh Venkataramanan #define ICE_DBG_LINK BIT_ULL(4) 41d8df260aSChinh T Cao #define ICE_DBG_PHY BIT_ULL(5) 42cdedef59SAnirudh Venkataramanan #define ICE_DBG_QCTX BIT_ULL(6) 43f31e4b6fSAnirudh Venkataramanan #define ICE_DBG_NVM BIT_ULL(7) 44dc49c772SAnirudh Venkataramanan #define ICE_DBG_LAN BIT_ULL(8) 4531ad4e4eSTony Nguyen #define ICE_DBG_FLOW BIT_ULL(9) 469c20346bSAnirudh Venkataramanan #define ICE_DBG_SW BIT_ULL(13) 479c20346bSAnirudh Venkataramanan #define ICE_DBG_SCHED BIT_ULL(14) 48c7648810STony Nguyen #define ICE_DBG_PKG BIT_ULL(16) 49f31e4b6fSAnirudh Venkataramanan #define ICE_DBG_RES BIT_ULL(17) 507ec59eeaSAnirudh Venkataramanan #define ICE_DBG_AQ_MSG BIT_ULL(24) 51faa01721SJacob Keller #define ICE_DBG_AQ_DESC BIT_ULL(25) 52faa01721SJacob Keller #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26) 537ec59eeaSAnirudh Venkataramanan #define ICE_DBG_AQ_CMD BIT_ULL(27) 54fcea6f3dSAnirudh Venkataramanan #define ICE_DBG_USER BIT_ULL(31) 557ec59eeaSAnirudh Venkataramanan 56f31e4b6fSAnirudh Venkataramanan enum ice_aq_res_ids { 57f31e4b6fSAnirudh Venkataramanan ICE_NVM_RES_ID = 1, 58f31e4b6fSAnirudh Venkataramanan ICE_SPD_RES_ID, 59ff2b1321SDan Nowlin ICE_CHANGE_LOCK_RES_ID, 60ff2b1321SDan Nowlin ICE_GLOBAL_CFG_LOCK_RES_ID 61f31e4b6fSAnirudh Venkataramanan }; 62f31e4b6fSAnirudh Venkataramanan 63ff2b1321SDan Nowlin /* FW update timeout definitions are in milliseconds */ 64ff2b1321SDan Nowlin #define ICE_NVM_TIMEOUT 180000 65ff2b1321SDan Nowlin #define ICE_CHANGE_LOCK_TIMEOUT 1000 66ff2b1321SDan Nowlin #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000 67ff2b1321SDan Nowlin 68f31e4b6fSAnirudh Venkataramanan enum ice_aq_res_access_type { 69f31e4b6fSAnirudh Venkataramanan ICE_RES_READ = 1, 70f31e4b6fSAnirudh Venkataramanan ICE_RES_WRITE 71f31e4b6fSAnirudh Venkataramanan }; 72f31e4b6fSAnirudh Venkataramanan 73e3710a01SPaul M Stillwell Jr struct ice_driver_ver { 74e3710a01SPaul M Stillwell Jr u8 major_ver; 75e3710a01SPaul M Stillwell Jr u8 minor_ver; 76e3710a01SPaul M Stillwell Jr u8 build_ver; 77e3710a01SPaul M Stillwell Jr u8 subbuild_ver; 78e3710a01SPaul M Stillwell Jr u8 driver_string[32]; 79e3710a01SPaul M Stillwell Jr }; 80e3710a01SPaul M Stillwell Jr 81dc49c772SAnirudh Venkataramanan enum ice_fc_mode { 82dc49c772SAnirudh Venkataramanan ICE_FC_NONE = 0, 83dc49c772SAnirudh Venkataramanan ICE_FC_RX_PAUSE, 84dc49c772SAnirudh Venkataramanan ICE_FC_TX_PAUSE, 85dc49c772SAnirudh Venkataramanan ICE_FC_FULL, 86dc49c772SAnirudh Venkataramanan ICE_FC_PFC, 87dc49c772SAnirudh Venkataramanan ICE_FC_DFLT 88dc49c772SAnirudh Venkataramanan }; 89dc49c772SAnirudh Venkataramanan 901a3571b5SPaul Greenwalt enum ice_phy_cache_mode { 911a3571b5SPaul Greenwalt ICE_FC_MODE = 0, 921a3571b5SPaul Greenwalt ICE_SPEED_MODE, 931a3571b5SPaul Greenwalt ICE_FEC_MODE 941a3571b5SPaul Greenwalt }; 951a3571b5SPaul Greenwalt 96f776b3acSPaul Greenwalt enum ice_fec_mode { 97f776b3acSPaul Greenwalt ICE_FEC_NONE = 0, 98f776b3acSPaul Greenwalt ICE_FEC_RS, 99f776b3acSPaul Greenwalt ICE_FEC_BASER, 100f776b3acSPaul Greenwalt ICE_FEC_AUTO 101f776b3acSPaul Greenwalt }; 102f776b3acSPaul Greenwalt 1031a3571b5SPaul Greenwalt struct ice_phy_cache_mode_data { 1041a3571b5SPaul Greenwalt union { 1051a3571b5SPaul Greenwalt enum ice_fec_mode curr_user_fec_req; 1061a3571b5SPaul Greenwalt enum ice_fc_mode curr_user_fc_req; 1071a3571b5SPaul Greenwalt u16 curr_user_speed_req; 1081a3571b5SPaul Greenwalt } data; 1091a3571b5SPaul Greenwalt }; 1101a3571b5SPaul Greenwalt 111fcea6f3dSAnirudh Venkataramanan enum ice_set_fc_aq_failures { 112fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_NONE = 0, 113fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_GET, 114fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_SET, 115fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_UPDATE 116fcea6f3dSAnirudh Venkataramanan }; 117fcea6f3dSAnirudh Venkataramanan 118f31e4b6fSAnirudh Venkataramanan /* Various MAC types */ 119f31e4b6fSAnirudh Venkataramanan enum ice_mac_type { 120f31e4b6fSAnirudh Venkataramanan ICE_MAC_UNKNOWN = 0, 121ea78ce4dSPaul Greenwalt ICE_MAC_E810, 122f31e4b6fSAnirudh Venkataramanan ICE_MAC_GENERIC, 123f31e4b6fSAnirudh Venkataramanan }; 124f31e4b6fSAnirudh Venkataramanan 125dc49c772SAnirudh Venkataramanan /* Media Types */ 126dc49c772SAnirudh Venkataramanan enum ice_media_type { 127dc49c772SAnirudh Venkataramanan ICE_MEDIA_UNKNOWN = 0, 128dc49c772SAnirudh Venkataramanan ICE_MEDIA_FIBER, 129dc49c772SAnirudh Venkataramanan ICE_MEDIA_BASET, 130dc49c772SAnirudh Venkataramanan ICE_MEDIA_BACKPLANE, 131dc49c772SAnirudh Venkataramanan ICE_MEDIA_DA, 132dc49c772SAnirudh Venkataramanan }; 133dc49c772SAnirudh Venkataramanan 1343a858ba3SAnirudh Venkataramanan enum ice_vsi_type { 1353a858ba3SAnirudh Venkataramanan ICE_VSI_PF = 0, 136148beb61SHenry Tieman ICE_VSI_VF = 1, 137148beb61SHenry Tieman ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */ 1380e674aebSAnirudh Venkataramanan ICE_VSI_LB = 6, 1393a858ba3SAnirudh Venkataramanan }; 1403a858ba3SAnirudh Venkataramanan 141dc49c772SAnirudh Venkataramanan struct ice_link_status { 142dc49c772SAnirudh Venkataramanan /* Refer to ice_aq_phy_type for bits definition */ 143dc49c772SAnirudh Venkataramanan u64 phy_type_low; 144aef74145SAnirudh Venkataramanan u64 phy_type_high; 145f776b3acSPaul Greenwalt u8 topo_media_conflict; 146dc49c772SAnirudh Venkataramanan u16 max_frame_size; 147dc49c772SAnirudh Venkataramanan u16 link_speed; 148ffe49823SChinh T Cao u16 req_speeds; 14943f8b224SBruce Allan u8 lse_ena; /* Link Status Event notification */ 150dc49c772SAnirudh Venkataramanan u8 link_info; 151dc49c772SAnirudh Venkataramanan u8 an_info; 152dc49c772SAnirudh Venkataramanan u8 ext_info; 153f776b3acSPaul Greenwalt u8 fec_info; 154dc49c772SAnirudh Venkataramanan u8 pacing; 155dc49c772SAnirudh Venkataramanan /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of 156dc49c772SAnirudh Venkataramanan * ice_aqc_get_phy_caps structure 157dc49c772SAnirudh Venkataramanan */ 158dc49c772SAnirudh Venkataramanan u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 159dc49c772SAnirudh Venkataramanan }; 160dc49c772SAnirudh Venkataramanan 161ddf30f7fSAnirudh Venkataramanan /* Different reset sources for which a disable queue AQ call has to be made in 162f9867df6SAnirudh Venkataramanan * order to clean the Tx scheduler as a part of the reset 163ddf30f7fSAnirudh Venkataramanan */ 164ddf30f7fSAnirudh Venkataramanan enum ice_disq_rst_src { 165ddf30f7fSAnirudh Venkataramanan ICE_NO_RESET = 0, 166ddf30f7fSAnirudh Venkataramanan ICE_VM_RESET, 167ddf30f7fSAnirudh Venkataramanan ICE_VF_RESET, 168ddf30f7fSAnirudh Venkataramanan }; 169ddf30f7fSAnirudh Venkataramanan 170dc49c772SAnirudh Venkataramanan /* PHY info such as phy_type, etc... */ 171dc49c772SAnirudh Venkataramanan struct ice_phy_info { 172dc49c772SAnirudh Venkataramanan struct ice_link_status link_info; 173dc49c772SAnirudh Venkataramanan struct ice_link_status link_info_old; 174dc49c772SAnirudh Venkataramanan u64 phy_type_low; 175aef74145SAnirudh Venkataramanan u64 phy_type_high; 176dc49c772SAnirudh Venkataramanan enum ice_media_type media_type; 17743f8b224SBruce Allan u8 get_link_info; 1781a3571b5SPaul Greenwalt /* Please refer to struct ice_aqc_get_link_status_data to get 1791a3571b5SPaul Greenwalt * detail of enable bit in curr_user_speed_req 1801a3571b5SPaul Greenwalt */ 1811a3571b5SPaul Greenwalt u16 curr_user_speed_req; 1821a3571b5SPaul Greenwalt enum ice_fec_mode curr_user_fec_req; 1831a3571b5SPaul Greenwalt enum ice_fc_mode curr_user_fc_req; 1841a3571b5SPaul Greenwalt struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg; 185dc49c772SAnirudh Venkataramanan }; 186dc49c772SAnirudh Venkataramanan 187148beb61SHenry Tieman /* protocol enumeration for filters */ 188148beb61SHenry Tieman enum ice_fltr_ptype { 189148beb61SHenry Tieman /* NONE - used for undef/error */ 190148beb61SHenry Tieman ICE_FLTR_PTYPE_NONF_NONE = 0, 191148beb61SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV4_UDP, 192148beb61SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV4_TCP, 193148beb61SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV4_SCTP, 194148beb61SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV4_OTHER, 195148beb61SHenry Tieman ICE_FLTR_PTYPE_FRAG_IPV4, 196165d80d6SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV6_UDP, 197165d80d6SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV6_TCP, 198165d80d6SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV6_SCTP, 199165d80d6SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV6_OTHER, 200148beb61SHenry Tieman ICE_FLTR_PTYPE_MAX, 201148beb61SHenry Tieman }; 202148beb61SHenry Tieman 203148beb61SHenry Tieman enum ice_fd_hw_seg { 204148beb61SHenry Tieman ICE_FD_HW_SEG_NON_TUN = 0, 205148beb61SHenry Tieman ICE_FD_HW_SEG_TUN, 206148beb61SHenry Tieman ICE_FD_HW_SEG_MAX, 207148beb61SHenry Tieman }; 208148beb61SHenry Tieman 209148beb61SHenry Tieman /* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */ 210148beb61SHenry Tieman #define ICE_MAX_FDIR_VSI_PER_FILTER 2 211148beb61SHenry Tieman 212148beb61SHenry Tieman struct ice_fd_hw_prof { 213148beb61SHenry Tieman struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX]; 214148beb61SHenry Tieman int cnt; 215148beb61SHenry Tieman u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX]; 216148beb61SHenry Tieman u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER]; 217148beb61SHenry Tieman }; 218148beb61SHenry Tieman 2199c20346bSAnirudh Venkataramanan /* Common HW capabilities for SW use */ 2209c20346bSAnirudh Venkataramanan struct ice_hw_common_caps { 221995c90f2SAnirudh Venkataramanan u32 valid_functions; 222a257f188SUsha Ketineni /* DCB capabilities */ 223a257f188SUsha Ketineni u32 active_tc_bitmap; 224a257f188SUsha Ketineni u32 maxtc; 225995c90f2SAnirudh Venkataramanan 226f9867df6SAnirudh Venkataramanan /* Tx/Rx queues */ 227f9867df6SAnirudh Venkataramanan u16 num_rxq; /* Number/Total Rx queues */ 228f9867df6SAnirudh Venkataramanan u16 rxq_first_id; /* First queue ID for Rx queues */ 229f9867df6SAnirudh Venkataramanan u16 num_txq; /* Number/Total Tx queues */ 230f9867df6SAnirudh Venkataramanan u16 txq_first_id; /* First queue ID for Tx queues */ 2319c20346bSAnirudh Venkataramanan 2329c20346bSAnirudh Venkataramanan /* MSI-X vectors */ 2339c20346bSAnirudh Venkataramanan u16 num_msix_vectors; 2349c20346bSAnirudh Venkataramanan u16 msix_vector_first_id; 2359c20346bSAnirudh Venkataramanan 2369c20346bSAnirudh Venkataramanan /* Max MTU for function or device */ 2379c20346bSAnirudh Venkataramanan u16 max_mtu; 2389c20346bSAnirudh Venkataramanan 23975d2b253SAnirudh Venkataramanan /* Virtualization support */ 24075d2b253SAnirudh Venkataramanan u8 sr_iov_1_1; /* SR-IOV enabled */ 241ddf30f7fSAnirudh Venkataramanan 2429c20346bSAnirudh Venkataramanan /* RSS related capabilities */ 2439c20346bSAnirudh Venkataramanan u16 rss_table_size; /* 512 for PFs and 64 for VFs */ 2449c20346bSAnirudh Venkataramanan u8 rss_table_entry_width; /* RSS Entry width in bits */ 24537b6f646SAnirudh Venkataramanan 24637b6f646SAnirudh Venkataramanan u8 dcb; 247de9b277eSJacek Naczyk 2482ab560a7SJacob Keller bool nvm_update_pending_nvm; 2492ab560a7SJacob Keller bool nvm_update_pending_orom; 2502ab560a7SJacob Keller bool nvm_update_pending_netlist; 2512ab560a7SJacob Keller #define ICE_NVM_PENDING_NVM_IMAGE BIT(0) 2522ab560a7SJacob Keller #define ICE_NVM_PENDING_OROM BIT(1) 2532ab560a7SJacob Keller #define ICE_NVM_PENDING_NETLIST BIT(2) 254de9b277eSJacek Naczyk bool nvm_unified_update; 255de9b277eSJacek Naczyk #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) 2569c20346bSAnirudh Venkataramanan }; 2579c20346bSAnirudh Venkataramanan 2589c20346bSAnirudh Venkataramanan /* Function specific capabilities */ 2599c20346bSAnirudh Venkataramanan struct ice_hw_func_caps { 2609c20346bSAnirudh Venkataramanan struct ice_hw_common_caps common_cap; 26175d2b253SAnirudh Venkataramanan u32 num_allocd_vfs; /* Number of allocated VFs */ 26275d2b253SAnirudh Venkataramanan u32 vf_base_id; /* Logical ID of the first VF */ 263995c90f2SAnirudh Venkataramanan u32 guar_num_vsi; 264148beb61SHenry Tieman u32 fd_fltr_guar; /* Number of filters guaranteed */ 265148beb61SHenry Tieman u32 fd_fltr_best_effort; /* Number of best effort filters */ 2669c20346bSAnirudh Venkataramanan }; 2679c20346bSAnirudh Venkataramanan 2689c20346bSAnirudh Venkataramanan /* Device wide capabilities */ 2699c20346bSAnirudh Venkataramanan struct ice_hw_dev_caps { 2709c20346bSAnirudh Venkataramanan struct ice_hw_common_caps common_cap; 27175d2b253SAnirudh Venkataramanan u32 num_vfs_exposed; /* Total number of VFs exposed */ 2729c20346bSAnirudh Venkataramanan u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ 273148beb61SHenry Tieman u32 num_flow_director_fltr; /* Number of FD filters available */ 274eae1bbb2SBruce Allan u32 num_funcs; 2759c20346bSAnirudh Venkataramanan }; 2769c20346bSAnirudh Venkataramanan 277dc49c772SAnirudh Venkataramanan /* MAC info */ 278dc49c772SAnirudh Venkataramanan struct ice_mac_info { 279dc49c772SAnirudh Venkataramanan u8 lan_addr[ETH_ALEN]; 280dc49c772SAnirudh Venkataramanan u8 perm_addr[ETH_ALEN]; 281dc49c772SAnirudh Venkataramanan }; 282dc49c772SAnirudh Venkataramanan 283ca4929b6SBrett Creeley /* Reset types used to determine which kind of reset was requested. These 284ca4929b6SBrett Creeley * defines match what the RESET_TYPE field of the GLGEN_RSTAT register. 285ca4929b6SBrett Creeley * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register 286ca4929b6SBrett Creeley * because its reset source is different than the other types listed. 287ca4929b6SBrett Creeley */ 288f31e4b6fSAnirudh Venkataramanan enum ice_reset_req { 289ca4929b6SBrett Creeley ICE_RESET_POR = 0, 2900f9d5027SAnirudh Venkataramanan ICE_RESET_INVAL = 0, 291ca4929b6SBrett Creeley ICE_RESET_CORER = 1, 292ca4929b6SBrett Creeley ICE_RESET_GLOBR = 2, 293ca4929b6SBrett Creeley ICE_RESET_EMPR = 3, 294ca4929b6SBrett Creeley ICE_RESET_PFR = 4, 295f31e4b6fSAnirudh Venkataramanan }; 296f31e4b6fSAnirudh Venkataramanan 297837f08fdSAnirudh Venkataramanan /* Bus parameters */ 298837f08fdSAnirudh Venkataramanan struct ice_bus_info { 299837f08fdSAnirudh Venkataramanan u16 device; 300837f08fdSAnirudh Venkataramanan u8 func; 301837f08fdSAnirudh Venkataramanan }; 302837f08fdSAnirudh Venkataramanan 303dc49c772SAnirudh Venkataramanan /* Flow control (FC) parameters */ 304dc49c772SAnirudh Venkataramanan struct ice_fc_info { 305dc49c772SAnirudh Venkataramanan enum ice_fc_mode current_mode; /* FC mode in effect */ 306dc49c772SAnirudh Venkataramanan enum ice_fc_mode req_mode; /* FC mode requested by caller */ 307dc49c772SAnirudh Venkataramanan }; 308dc49c772SAnirudh Venkataramanan 309d4e87444SJacob Keller /* Option ROM version information */ 310d4e87444SJacob Keller struct ice_orom_info { 311d4e87444SJacob Keller u8 major; /* Major version of OROM */ 312d4e87444SJacob Keller u8 patch; /* Patch version of OROM */ 313d4e87444SJacob Keller u16 build; /* Build version of OROM */ 314d4e87444SJacob Keller }; 315d4e87444SJacob Keller 3169af368faSJacob Keller /* NVM version information */ 317f31e4b6fSAnirudh Venkataramanan struct ice_nvm_info { 3189af368faSJacob Keller u32 eetrack; 3199af368faSJacob Keller u8 major; 3209af368faSJacob Keller u8 minor; 3219af368faSJacob Keller }; 3229af368faSJacob Keller 3239af368faSJacob Keller /* netlist version information */ 3249af368faSJacob Keller struct ice_netlist_info { 3259af368faSJacob Keller u32 major; /* major high/low */ 3269af368faSJacob Keller u32 minor; /* minor high/low */ 3279af368faSJacob Keller u32 type; /* type high/low */ 3289af368faSJacob Keller u32 rev; /* revision high/low */ 3299af368faSJacob Keller u32 hash; /* SHA-1 hash word */ 3309af368faSJacob Keller u16 cust_ver; /* customer version */ 3319af368faSJacob Keller }; 3329af368faSJacob Keller 3331fa95e01SJacob Keller /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules 3341fa95e01SJacob Keller * of the flash image. 3351fa95e01SJacob Keller */ 3361fa95e01SJacob Keller enum ice_flash_bank { 3371fa95e01SJacob Keller ICE_INVALID_FLASH_BANK, 3381fa95e01SJacob Keller ICE_1ST_FLASH_BANK, 3391fa95e01SJacob Keller ICE_2ND_FLASH_BANK, 3401fa95e01SJacob Keller }; 3411fa95e01SJacob Keller 3420ce50c70SJacob Keller /* Enumeration of which flash bank is desired to read from, either the active 3430ce50c70SJacob Keller * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from 3440ce50c70SJacob Keller * code which just wants to read the active or inactive flash bank. 3450ce50c70SJacob Keller */ 3460ce50c70SJacob Keller enum ice_bank_select { 3470ce50c70SJacob Keller ICE_ACTIVE_FLASH_BANK, 3480ce50c70SJacob Keller ICE_INACTIVE_FLASH_BANK, 3490ce50c70SJacob Keller }; 3500ce50c70SJacob Keller 3511fa95e01SJacob Keller /* information for accessing NVM, OROM, and Netlist flash banks */ 3521fa95e01SJacob Keller struct ice_bank_info { 3531fa95e01SJacob Keller u32 nvm_ptr; /* Pointer to 1st NVM bank */ 3541fa95e01SJacob Keller u32 nvm_size; /* Size of NVM bank */ 3551fa95e01SJacob Keller u32 orom_ptr; /* Pointer to 1st OROM bank */ 3561fa95e01SJacob Keller u32 orom_size; /* Size of OROM bank */ 3571fa95e01SJacob Keller u32 netlist_ptr; /* Pointer to 1st Netlist bank */ 3581fa95e01SJacob Keller u32 netlist_size; /* Size of Netlist bank */ 3591fa95e01SJacob Keller enum ice_flash_bank nvm_bank; /* Active NVM bank */ 3601fa95e01SJacob Keller enum ice_flash_bank orom_bank; /* Active OROM bank */ 3611fa95e01SJacob Keller enum ice_flash_bank netlist_bank; /* Active Netlist bank */ 3621fa95e01SJacob Keller }; 3631fa95e01SJacob Keller 3649af368faSJacob Keller /* Flash Chip Information */ 3659af368faSJacob Keller struct ice_flash_info { 366d4e87444SJacob Keller struct ice_orom_info orom; /* Option ROM version info */ 3679af368faSJacob Keller struct ice_nvm_info nvm; /* NVM version information */ 3689af368faSJacob Keller struct ice_netlist_info netlist;/* Netlist version info */ 3691fa95e01SJacob Keller struct ice_bank_info banks; /* Flash Bank information */ 370f31e4b6fSAnirudh Venkataramanan u16 sr_words; /* Shadow RAM size in words */ 37181f07491SJacob Keller u32 flash_size; /* Size of available flash in bytes */ 37243f8b224SBruce Allan u8 blank_nvm_mode; /* is NVM empty (no FW present) */ 373f31e4b6fSAnirudh Venkataramanan }; 374f31e4b6fSAnirudh Venkataramanan 375ea78ce4dSPaul Greenwalt struct ice_link_default_override_tlv { 376ea78ce4dSPaul Greenwalt u8 options; 377ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_OPT_M 0x3F 378ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0) 379ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1) 380ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2) 381ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_EN BIT(3) 382ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4) 383ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_EEE_EN BIT(5) 384ea78ce4dSPaul Greenwalt u8 phy_config; 385ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_PHY_CFG_S 8 386ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S) 387ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_PAUSE_M 0x3 388ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_LESM_EN BIT(6) 389ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7) 390ea78ce4dSPaul Greenwalt u8 fec_options; 391ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF 392ea78ce4dSPaul Greenwalt u8 rsvd1; 393ea78ce4dSPaul Greenwalt u64 phy_type_low; 394ea78ce4dSPaul Greenwalt u64 phy_type_high; 395ea78ce4dSPaul Greenwalt }; 396ea78ce4dSPaul Greenwalt 397870f805eSLukasz Czapnik #define ICE_NVM_VER_LEN 32 398870f805eSLukasz Czapnik 3999c20346bSAnirudh Venkataramanan /* Max number of port to queue branches w.r.t topology */ 4009c20346bSAnirudh Venkataramanan #define ICE_MAX_TRAFFIC_CLASS 8 401dc49c772SAnirudh Venkataramanan #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS 4029c20346bSAnirudh Venkataramanan 4032bdc97beSBruce Allan #define ice_for_each_traffic_class(_i) \ 4042bdc97beSBruce Allan for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++) 4052bdc97beSBruce Allan 4067b9ffc76SAnirudh Venkataramanan #define ICE_INVAL_TEID 0xFFFFFFFF 4077b9ffc76SAnirudh Venkataramanan 4089c20346bSAnirudh Venkataramanan struct ice_sched_node { 4099c20346bSAnirudh Venkataramanan struct ice_sched_node *parent; 4109c20346bSAnirudh Venkataramanan struct ice_sched_node *sibling; /* next sibling in the same layer */ 4119c20346bSAnirudh Venkataramanan struct ice_sched_node **children; 4129c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_elem_data info; 413f9867df6SAnirudh Venkataramanan u32 agg_id; /* aggregator group ID */ 4144fb33f31SAnirudh Venkataramanan u16 vsi_handle; 41543f8b224SBruce Allan u8 in_use; /* suspended or in use */ 4169c20346bSAnirudh Venkataramanan u8 tx_sched_layer; /* Logical Layer (1-9) */ 4179c20346bSAnirudh Venkataramanan u8 num_children; 4189c20346bSAnirudh Venkataramanan u8 tc_num; 4199c20346bSAnirudh Venkataramanan u8 owner; 4209c20346bSAnirudh Venkataramanan #define ICE_SCHED_NODE_OWNER_LAN 0 4219c20346bSAnirudh Venkataramanan }; 4229c20346bSAnirudh Venkataramanan 423dc49c772SAnirudh Venkataramanan /* Access Macros for Tx Sched Elements data */ 424dc49c772SAnirudh Venkataramanan #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid) 425dc49c772SAnirudh Venkataramanan 4269c20346bSAnirudh Venkataramanan /* The aggregator type determines if identifier is for a VSI group, 4279c20346bSAnirudh Venkataramanan * aggregator group, aggregator of queues, or queue group. 4289c20346bSAnirudh Venkataramanan */ 4299c20346bSAnirudh Venkataramanan enum ice_agg_type { 4309c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_UNKNOWN = 0, 4319c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_VSI, 4329c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_AGG, /* aggregator */ 4339c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_Q, 4349c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_QG 4359c20346bSAnirudh Venkataramanan }; 4369c20346bSAnirudh Venkataramanan 4371ddef455SUsha Ketineni /* Rate limit types */ 4381ddef455SUsha Ketineni enum ice_rl_type { 4391ddef455SUsha Ketineni ICE_UNKNOWN_BW = 0, 4401ddef455SUsha Ketineni ICE_MIN_BW, /* for CIR profile */ 4411ddef455SUsha Ketineni ICE_MAX_BW, /* for EIR profile */ 4421ddef455SUsha Ketineni ICE_SHARED_BW /* for shared profile */ 4431ddef455SUsha Ketineni }; 4445513b920SAnirudh Venkataramanan 4451ddef455SUsha Ketineni #define ICE_SCHED_MIN_BW 500 /* in Kbps */ 4461ddef455SUsha Ketineni #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */ 4471ddef455SUsha Ketineni #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */ 4481ddef455SUsha Ketineni #define ICE_SCHED_DFLT_RL_PROF_ID 0 4491ddef455SUsha Ketineni #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF 450984824a2STarun Singh #define ICE_SCHED_DFLT_BW_WT 4 4511ddef455SUsha Ketineni #define ICE_SCHED_INVAL_PROF_ID 0xFFFF 4521ddef455SUsha Ketineni #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */ 4531ddef455SUsha Ketineni 4541ddef455SUsha Ketineni /* Data structure for saving BW information */ 4551ddef455SUsha Ketineni enum ice_bw_type { 4561ddef455SUsha Ketineni ICE_BW_TYPE_PRIO, 4571ddef455SUsha Ketineni ICE_BW_TYPE_CIR, 4581ddef455SUsha Ketineni ICE_BW_TYPE_CIR_WT, 4591ddef455SUsha Ketineni ICE_BW_TYPE_EIR, 4601ddef455SUsha Ketineni ICE_BW_TYPE_EIR_WT, 4611ddef455SUsha Ketineni ICE_BW_TYPE_SHARED, 4621ddef455SUsha Ketineni ICE_BW_TYPE_CNT /* This must be last */ 4631ddef455SUsha Ketineni }; 4641ddef455SUsha Ketineni 4651ddef455SUsha Ketineni struct ice_bw { 4661ddef455SUsha Ketineni u32 bw; 4671ddef455SUsha Ketineni u16 bw_alloc; 4681ddef455SUsha Ketineni }; 4691ddef455SUsha Ketineni 4701ddef455SUsha Ketineni struct ice_bw_type_info { 4711ddef455SUsha Ketineni DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT); 4721ddef455SUsha Ketineni u8 generic; 4731ddef455SUsha Ketineni struct ice_bw cir_bw; 4741ddef455SUsha Ketineni struct ice_bw eir_bw; 4751ddef455SUsha Ketineni u32 shared_bw; 4761ddef455SUsha Ketineni }; 4771ddef455SUsha Ketineni 4781ddef455SUsha Ketineni /* VSI queue context structure for given TC */ 4791ddef455SUsha Ketineni struct ice_q_ctx { 4801ddef455SUsha Ketineni u16 q_handle; 4811ddef455SUsha Ketineni u32 q_teid; 4821ddef455SUsha Ketineni /* bw_t_info saves queue BW information */ 4831ddef455SUsha Ketineni struct ice_bw_type_info bw_t_info; 4841ddef455SUsha Ketineni }; 4851ddef455SUsha Ketineni 4861ddef455SUsha Ketineni /* VSI type list entry to locate corresponding VSI/aggregator nodes */ 4879c20346bSAnirudh Venkataramanan struct ice_sched_vsi_info { 4889c20346bSAnirudh Venkataramanan struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS]; 4899c20346bSAnirudh Venkataramanan struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS]; 4909c20346bSAnirudh Venkataramanan struct list_head list_entry; 4919c20346bSAnirudh Venkataramanan u16 max_lanq[ICE_MAX_TRAFFIC_CLASS]; 4929c20346bSAnirudh Venkataramanan }; 4939c20346bSAnirudh Venkataramanan 4949c20346bSAnirudh Venkataramanan /* driver defines the policy */ 4959c20346bSAnirudh Venkataramanan struct ice_sched_tx_policy { 4969c20346bSAnirudh Venkataramanan u16 max_num_vsis; 4979c20346bSAnirudh Venkataramanan u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS]; 49843f8b224SBruce Allan u8 rdma_ena; 4999c20346bSAnirudh Venkataramanan }; 5009c20346bSAnirudh Venkataramanan 5010ebd3ff1SAnirudh Venkataramanan /* CEE or IEEE 802.1Qaz ETS Configuration data */ 5020ebd3ff1SAnirudh Venkataramanan struct ice_dcb_ets_cfg { 5030ebd3ff1SAnirudh Venkataramanan u8 willing; 5040ebd3ff1SAnirudh Venkataramanan u8 cbs; 5050ebd3ff1SAnirudh Venkataramanan u8 maxtcs; 5060ebd3ff1SAnirudh Venkataramanan u8 prio_table[ICE_MAX_TRAFFIC_CLASS]; 5070ebd3ff1SAnirudh Venkataramanan u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS]; 5080ebd3ff1SAnirudh Venkataramanan u8 tsatable[ICE_MAX_TRAFFIC_CLASS]; 5090ebd3ff1SAnirudh Venkataramanan }; 5100ebd3ff1SAnirudh Venkataramanan 5110ebd3ff1SAnirudh Venkataramanan /* CEE or IEEE 802.1Qaz PFC Configuration data */ 5120ebd3ff1SAnirudh Venkataramanan struct ice_dcb_pfc_cfg { 5130ebd3ff1SAnirudh Venkataramanan u8 willing; 5140ebd3ff1SAnirudh Venkataramanan u8 mbc; 5150ebd3ff1SAnirudh Venkataramanan u8 pfccap; 5160ebd3ff1SAnirudh Venkataramanan u8 pfcena; 5170ebd3ff1SAnirudh Venkataramanan }; 5180ebd3ff1SAnirudh Venkataramanan 5190ebd3ff1SAnirudh Venkataramanan /* CEE or IEEE 802.1Qaz Application Priority data */ 5200ebd3ff1SAnirudh Venkataramanan struct ice_dcb_app_priority_table { 5210ebd3ff1SAnirudh Venkataramanan u16 prot_id; 5220ebd3ff1SAnirudh Venkataramanan u8 priority; 5230ebd3ff1SAnirudh Venkataramanan u8 selector; 5240ebd3ff1SAnirudh Venkataramanan }; 5250ebd3ff1SAnirudh Venkataramanan 5260ebd3ff1SAnirudh Venkataramanan #define ICE_MAX_USER_PRIORITY 8 5270ebd3ff1SAnirudh Venkataramanan #define ICE_DCBX_MAX_APPS 32 5280ebd3ff1SAnirudh Venkataramanan #define ICE_LLDPDU_SIZE 1500 5290ebd3ff1SAnirudh Venkataramanan #define ICE_TLV_STATUS_OPER 0x1 5300ebd3ff1SAnirudh Venkataramanan #define ICE_TLV_STATUS_SYNC 0x2 5310ebd3ff1SAnirudh Venkataramanan #define ICE_TLV_STATUS_ERR 0x4 5320ebd3ff1SAnirudh Venkataramanan #define ICE_APP_PROT_ID_FCOE 0x8906 5330ebd3ff1SAnirudh Venkataramanan #define ICE_APP_PROT_ID_ISCSI 0x0cbc 5340ebd3ff1SAnirudh Venkataramanan #define ICE_APP_PROT_ID_FIP 0x8914 5350ebd3ff1SAnirudh Venkataramanan #define ICE_APP_SEL_ETHTYPE 0x1 5360ebd3ff1SAnirudh Venkataramanan #define ICE_APP_SEL_TCPIP 0x2 5370ebd3ff1SAnirudh Venkataramanan #define ICE_CEE_APP_SEL_ETHTYPE 0x0 538ea78ce4dSPaul Greenwalt #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134 5390ebd3ff1SAnirudh Venkataramanan #define ICE_CEE_APP_SEL_TCPIP 0x1 5400ebd3ff1SAnirudh Venkataramanan 5410ebd3ff1SAnirudh Venkataramanan struct ice_dcbx_cfg { 5420ebd3ff1SAnirudh Venkataramanan u32 numapps; 5430ebd3ff1SAnirudh Venkataramanan u32 tlv_status; /* CEE mode TLV status */ 5440ebd3ff1SAnirudh Venkataramanan struct ice_dcb_ets_cfg etscfg; 5450ebd3ff1SAnirudh Venkataramanan struct ice_dcb_ets_cfg etsrec; 5460ebd3ff1SAnirudh Venkataramanan struct ice_dcb_pfc_cfg pfc; 5470ebd3ff1SAnirudh Venkataramanan struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS]; 5480ebd3ff1SAnirudh Venkataramanan u8 dcbx_mode; 5490ebd3ff1SAnirudh Venkataramanan #define ICE_DCBX_MODE_CEE 0x1 5500ebd3ff1SAnirudh Venkataramanan #define ICE_DCBX_MODE_IEEE 0x2 5510ebd3ff1SAnirudh Venkataramanan u8 app_mode; 5520ebd3ff1SAnirudh Venkataramanan #define ICE_DCBX_APPS_NON_WILLING 0x1 5530ebd3ff1SAnirudh Venkataramanan }; 5540ebd3ff1SAnirudh Venkataramanan 5559c20346bSAnirudh Venkataramanan struct ice_port_info { 5569c20346bSAnirudh Venkataramanan struct ice_sched_node *root; /* Root Node per Port */ 557f9867df6SAnirudh Venkataramanan struct ice_hw *hw; /* back pointer to HW instance */ 558dc49c772SAnirudh Venkataramanan u32 last_node_teid; /* scheduler last node info */ 5599c20346bSAnirudh Venkataramanan u16 sw_id; /* Initial switch ID belongs to port */ 5609c20346bSAnirudh Venkataramanan u16 pf_vf_num; 5619c20346bSAnirudh Venkataramanan u8 port_state; 5629c20346bSAnirudh Venkataramanan #define ICE_SCHED_PORT_STATE_INIT 0x0 5639c20346bSAnirudh Venkataramanan #define ICE_SCHED_PORT_STATE_READY 0x1 5640437f1a9SJesse Brandeburg u8 lport; 5650437f1a9SJesse Brandeburg #define ICE_LPORT_MASK 0xff 566e94d4478SAnirudh Venkataramanan u16 dflt_tx_vsi_rule_id; 5679c20346bSAnirudh Venkataramanan u16 dflt_tx_vsi_num; 568e94d4478SAnirudh Venkataramanan u16 dflt_rx_vsi_rule_id; 5699c20346bSAnirudh Venkataramanan u16 dflt_rx_vsi_num; 570dc49c772SAnirudh Venkataramanan struct ice_fc_info fc; 571dc49c772SAnirudh Venkataramanan struct ice_mac_info mac; 572dc49c772SAnirudh Venkataramanan struct ice_phy_info phy; 5739c20346bSAnirudh Venkataramanan struct mutex sched_lock; /* protect access to TXSched tree */ 57429358248SVictor Raj struct ice_sched_node * 57529358248SVictor Raj sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM]; 5761ddef455SUsha Ketineni /* List contain profile ID(s) and other params per layer */ 5771ddef455SUsha Ketineni struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 5780ebd3ff1SAnirudh Venkataramanan struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */ 5790ebd3ff1SAnirudh Venkataramanan /* DCBX info */ 5800ebd3ff1SAnirudh Venkataramanan struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */ 5810ebd3ff1SAnirudh Venkataramanan struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */ 58237b6f646SAnirudh Venkataramanan /* LLDP/DCBX Status */ 5830437f1a9SJesse Brandeburg u8 dcbx_status:3; /* see ICE_DCBX_STATUS_DIS */ 5840437f1a9SJesse Brandeburg u8 is_sw_lldp:1; 5850437f1a9SJesse Brandeburg u8 is_vf:1; 5869c20346bSAnirudh Venkataramanan }; 5879c20346bSAnirudh Venkataramanan 5889daf8208SAnirudh Venkataramanan struct ice_switch_info { 5899daf8208SAnirudh Venkataramanan struct list_head vsi_list_map_head; 59080d144c9SAnirudh Venkataramanan struct ice_sw_recipe *recp_list; 5919daf8208SAnirudh Venkataramanan }; 5929daf8208SAnirudh Venkataramanan 5938b97ceb1SHieu Tran /* FW logging configuration */ 5948b97ceb1SHieu Tran struct ice_fw_log_evnt { 5958b97ceb1SHieu Tran u8 cfg : 4; /* New event enables to configure */ 5968b97ceb1SHieu Tran u8 cur : 4; /* Current/active event enables */ 5978b97ceb1SHieu Tran }; 5988b97ceb1SHieu Tran 5998b97ceb1SHieu Tran struct ice_fw_log_cfg { 6008b97ceb1SHieu Tran u8 cq_en : 1; /* FW logging is enabled via the control queue */ 6018b97ceb1SHieu Tran u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */ 6028b97ceb1SHieu Tran u8 actv_evnts; /* Cumulation of currently enabled log events */ 6038b97ceb1SHieu Tran 6048b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S) 6058b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S) 6068b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S) 6078b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S) 6088b97ceb1SHieu Tran struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX]; 6098b97ceb1SHieu Tran }; 6108b97ceb1SHieu Tran 611837f08fdSAnirudh Venkataramanan /* Port hardware description */ 612837f08fdSAnirudh Venkataramanan struct ice_hw { 613837f08fdSAnirudh Venkataramanan u8 __iomem *hw_addr; 614837f08fdSAnirudh Venkataramanan void *back; 6159c20346bSAnirudh Venkataramanan struct ice_aqc_layer_props *layer_info; 6169c20346bSAnirudh Venkataramanan struct ice_port_info *port_info; 6177ec59eeaSAnirudh Venkataramanan u64 debug_mask; /* bitmap for debug mask */ 618f31e4b6fSAnirudh Venkataramanan enum ice_mac_type mac_type; 619837f08fdSAnirudh Venkataramanan 620148beb61SHenry Tieman u16 fd_ctr_base; /* FD counter base index */ 621148beb61SHenry Tieman 622837f08fdSAnirudh Venkataramanan /* pci info */ 623837f08fdSAnirudh Venkataramanan u16 device_id; 624837f08fdSAnirudh Venkataramanan u16 vendor_id; 625837f08fdSAnirudh Venkataramanan u16 subsystem_device_id; 626837f08fdSAnirudh Venkataramanan u16 subsystem_vendor_id; 627837f08fdSAnirudh Venkataramanan u8 revision_id; 628837f08fdSAnirudh Venkataramanan 629f31e4b6fSAnirudh Venkataramanan u8 pf_id; /* device profile info */ 630f31e4b6fSAnirudh Venkataramanan 6311ddef455SUsha Ketineni u16 max_burst_size; /* driver sets this value */ 6321ddef455SUsha Ketineni 633f9867df6SAnirudh Venkataramanan /* Tx Scheduler values */ 63488865fc4SKarol Kolacinski u8 num_tx_sched_layers; 63588865fc4SKarol Kolacinski u8 num_tx_sched_phys_layers; 6369c20346bSAnirudh Venkataramanan u8 flattened_layers; 6379c20346bSAnirudh Venkataramanan u8 max_cgds; 6389c20346bSAnirudh Venkataramanan u8 sw_entry_point_layer; 639b36c598cSAnirudh Venkataramanan u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 6409be1d6f8SAnirudh Venkataramanan struct list_head agg_list; /* lists all aggregator */ 6419c20346bSAnirudh Venkataramanan 6420f9d5027SAnirudh Venkataramanan struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI]; 64343f8b224SBruce Allan u8 evb_veb; /* true for VEB, false for VEPA */ 644f9867df6SAnirudh Venkataramanan u8 reset_ongoing; /* true if HW is in reset, false otherwise */ 645837f08fdSAnirudh Venkataramanan struct ice_bus_info bus; 6469af368faSJacob Keller struct ice_flash_info flash; 6479c20346bSAnirudh Venkataramanan struct ice_hw_dev_caps dev_caps; /* device capabilities */ 6489c20346bSAnirudh Venkataramanan struct ice_hw_func_caps func_caps; /* function capabilities */ 649f31e4b6fSAnirudh Venkataramanan 6509daf8208SAnirudh Venkataramanan struct ice_switch_info *switch_info; /* switch filter lists */ 6519daf8208SAnirudh Venkataramanan 6527ec59eeaSAnirudh Venkataramanan /* Control Queue info */ 6537ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_info adminq; 65475d2b253SAnirudh Venkataramanan struct ice_ctl_q_info mailboxq; 6557ec59eeaSAnirudh Venkataramanan 6567ec59eeaSAnirudh Venkataramanan u8 api_branch; /* API branch version */ 6577ec59eeaSAnirudh Venkataramanan u8 api_maj_ver; /* API major version */ 6587ec59eeaSAnirudh Venkataramanan u8 api_min_ver; /* API minor version */ 6597ec59eeaSAnirudh Venkataramanan u8 api_patch; /* API patch version */ 6607ec59eeaSAnirudh Venkataramanan u8 fw_branch; /* firmware branch version */ 6617ec59eeaSAnirudh Venkataramanan u8 fw_maj_ver; /* firmware major version */ 6627ec59eeaSAnirudh Venkataramanan u8 fw_min_ver; /* firmware minor version */ 6637ec59eeaSAnirudh Venkataramanan u8 fw_patch; /* firmware patch version */ 6647ec59eeaSAnirudh Venkataramanan u32 fw_build; /* firmware build number */ 665940b61afSAnirudh Venkataramanan 6668b97ceb1SHieu Tran struct ice_fw_log_cfg fw_log; 6679e4ab4c2SBrett Creeley 6689e4ab4c2SBrett Creeley /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL 6694ee656bbSTony Nguyen * register. Used for determining the ITR/INTRL granularity during 6709e4ab4c2SBrett Creeley * initialization. 6719e4ab4c2SBrett Creeley */ 6729e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_200G 0x0 6739e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_100G 0X1 6749e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_50G 0x2 6759e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_25G 0x3 6769e4ab4c2SBrett Creeley /* ITR granularity for different speeds */ 6779e4ab4c2SBrett Creeley #define ICE_ITR_GRAN_ABOVE_25 2 6789e4ab4c2SBrett Creeley #define ICE_ITR_GRAN_MAX_25 4 679940b61afSAnirudh Venkataramanan /* ITR granularity in 1 us */ 6809e4ab4c2SBrett Creeley u8 itr_gran; 6819e4ab4c2SBrett Creeley /* INTRL granularity for different speeds */ 6829e4ab4c2SBrett Creeley #define ICE_INTRL_GRAN_ABOVE_25 4 6839e4ab4c2SBrett Creeley #define ICE_INTRL_GRAN_MAX_25 8 6849e4ab4c2SBrett Creeley /* INTRL granularity in 1 us */ 6859e4ab4c2SBrett Creeley u8 intrl_gran; 6869e4ab4c2SBrett Creeley 68743f8b224SBruce Allan u8 ucast_shared; /* true if VSIs can share unicast addr */ 6889daf8208SAnirudh Venkataramanan 689c7648810STony Nguyen /* Active package version (currently active) */ 690c7648810STony Nguyen struct ice_pkg_ver active_pkg_ver; 691b8272919SVictor Raj u32 active_track_id; 692c7648810STony Nguyen u8 active_pkg_name[ICE_PKG_NAME_SIZE]; 693c7648810STony Nguyen u8 active_pkg_in_nvm; 694c7648810STony Nguyen 695c7648810STony Nguyen enum ice_aq_err pkg_dwnld_status; 696c7648810STony Nguyen 697c7648810STony Nguyen /* Driver's package ver - (from the Metadata seg) */ 698c7648810STony Nguyen struct ice_pkg_ver pkg_ver; 699c7648810STony Nguyen u8 pkg_name[ICE_PKG_NAME_SIZE]; 700c7648810STony Nguyen 701c7648810STony Nguyen /* Driver's Ice package version (from the Ice seg) */ 702c7648810STony Nguyen struct ice_pkg_ver ice_pkg_ver; 703c7648810STony Nguyen u8 ice_pkg_name[ICE_PKG_NAME_SIZE]; 704c7648810STony Nguyen 705c7648810STony Nguyen /* Pointer to the ice segment */ 706c7648810STony Nguyen struct ice_seg *seg; 707c7648810STony Nguyen 708c7648810STony Nguyen /* Pointer to allocated copy of pkg memory */ 709c7648810STony Nguyen u8 *pkg_copy; 710c7648810STony Nguyen u32 pkg_size; 711c7648810STony Nguyen 712a4e82a81STony Nguyen /* tunneling info */ 713a4e82a81STony Nguyen struct mutex tnl_lock; 714a4e82a81STony Nguyen struct ice_tunnel_table tnl; 715a4e82a81STony Nguyen 716b20e6c17SJakub Kicinski struct udp_tunnel_nic_shared udp_tunnel_shared; 717b20e6c17SJakub Kicinski struct udp_tunnel_nic_info udp_tunnel_nic; 718b20e6c17SJakub Kicinski 719c7648810STony Nguyen /* HW block tables */ 720c7648810STony Nguyen struct ice_blk_info blk[ICE_BLK_COUNT]; 721c90ed40cSTony Nguyen struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */ 722c90ed40cSTony Nguyen struct list_head fl_profs[ICE_BLK_COUNT]; 723148beb61SHenry Tieman 724148beb61SHenry Tieman /* Flow Director filter info */ 725148beb61SHenry Tieman int fdir_active_fltr; 726148beb61SHenry Tieman 727148beb61SHenry Tieman struct mutex fdir_fltr_lock; /* protect Flow Director */ 728148beb61SHenry Tieman struct list_head fdir_list_head; 729148beb61SHenry Tieman 730cac2a27cSHenry Tieman /* Book-keeping of side-band filter count per flow-type. 731cac2a27cSHenry Tieman * This is used to detect and handle input set changes for 732cac2a27cSHenry Tieman * respective flow-type. 733cac2a27cSHenry Tieman */ 734cac2a27cSHenry Tieman u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX]; 735cac2a27cSHenry Tieman 736148beb61SHenry Tieman struct ice_fd_hw_prof **fdir_prof; 737148beb61SHenry Tieman DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX); 738c90ed40cSTony Nguyen struct mutex rss_locks; /* protect RSS configuration */ 739c90ed40cSTony Nguyen struct list_head rss_list_head; 740837f08fdSAnirudh Venkataramanan }; 741837f08fdSAnirudh Venkataramanan 742fcea6f3dSAnirudh Venkataramanan /* Statistics collected by each port, VSI, VEB, and S-channel */ 743fcea6f3dSAnirudh Venkataramanan struct ice_eth_stats { 744fcea6f3dSAnirudh Venkataramanan u64 rx_bytes; /* gorc */ 745fcea6f3dSAnirudh Venkataramanan u64 rx_unicast; /* uprc */ 746fcea6f3dSAnirudh Venkataramanan u64 rx_multicast; /* mprc */ 747fcea6f3dSAnirudh Venkataramanan u64 rx_broadcast; /* bprc */ 748fcea6f3dSAnirudh Venkataramanan u64 rx_discards; /* rdpc */ 749fcea6f3dSAnirudh Venkataramanan u64 rx_unknown_protocol; /* rupp */ 750fcea6f3dSAnirudh Venkataramanan u64 tx_bytes; /* gotc */ 751fcea6f3dSAnirudh Venkataramanan u64 tx_unicast; /* uptc */ 752fcea6f3dSAnirudh Venkataramanan u64 tx_multicast; /* mptc */ 753fcea6f3dSAnirudh Venkataramanan u64 tx_broadcast; /* bptc */ 754fcea6f3dSAnirudh Venkataramanan u64 tx_discards; /* tdpc */ 755fcea6f3dSAnirudh Venkataramanan u64 tx_errors; /* tepc */ 756fcea6f3dSAnirudh Venkataramanan }; 757fcea6f3dSAnirudh Venkataramanan 758610ed0e9SAvinash JD #define ICE_MAX_UP 8 759610ed0e9SAvinash JD 760fcea6f3dSAnirudh Venkataramanan /* Statistics collected by the MAC */ 761fcea6f3dSAnirudh Venkataramanan struct ice_hw_port_stats { 762fcea6f3dSAnirudh Venkataramanan /* eth stats collected by the port */ 763fcea6f3dSAnirudh Venkataramanan struct ice_eth_stats eth; 764fcea6f3dSAnirudh Venkataramanan /* additional port specific stats */ 765fcea6f3dSAnirudh Venkataramanan u64 tx_dropped_link_down; /* tdold */ 766fcea6f3dSAnirudh Venkataramanan u64 crc_errors; /* crcerrs */ 767fcea6f3dSAnirudh Venkataramanan u64 illegal_bytes; /* illerrc */ 768fcea6f3dSAnirudh Venkataramanan u64 error_bytes; /* errbc */ 769fcea6f3dSAnirudh Venkataramanan u64 mac_local_faults; /* mlfc */ 770fcea6f3dSAnirudh Venkataramanan u64 mac_remote_faults; /* mrfc */ 771fcea6f3dSAnirudh Venkataramanan u64 rx_len_errors; /* rlec */ 772fcea6f3dSAnirudh Venkataramanan u64 link_xon_rx; /* lxonrxc */ 773fcea6f3dSAnirudh Venkataramanan u64 link_xoff_rx; /* lxoffrxc */ 774fcea6f3dSAnirudh Venkataramanan u64 link_xon_tx; /* lxontxc */ 775fcea6f3dSAnirudh Venkataramanan u64 link_xoff_tx; /* lxofftxc */ 7764b0fdcebSAnirudh Venkataramanan u64 priority_xon_rx[8]; /* pxonrxc[8] */ 7774b0fdcebSAnirudh Venkataramanan u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 7784b0fdcebSAnirudh Venkataramanan u64 priority_xon_tx[8]; /* pxontxc[8] */ 7794b0fdcebSAnirudh Venkataramanan u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 7804b0fdcebSAnirudh Venkataramanan u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 781fcea6f3dSAnirudh Venkataramanan u64 rx_size_64; /* prc64 */ 782fcea6f3dSAnirudh Venkataramanan u64 rx_size_127; /* prc127 */ 783fcea6f3dSAnirudh Venkataramanan u64 rx_size_255; /* prc255 */ 784fcea6f3dSAnirudh Venkataramanan u64 rx_size_511; /* prc511 */ 785fcea6f3dSAnirudh Venkataramanan u64 rx_size_1023; /* prc1023 */ 786fcea6f3dSAnirudh Venkataramanan u64 rx_size_1522; /* prc1522 */ 787fcea6f3dSAnirudh Venkataramanan u64 rx_size_big; /* prc9522 */ 788fcea6f3dSAnirudh Venkataramanan u64 rx_undersize; /* ruc */ 789fcea6f3dSAnirudh Venkataramanan u64 rx_fragments; /* rfc */ 790fcea6f3dSAnirudh Venkataramanan u64 rx_oversize; /* roc */ 791fcea6f3dSAnirudh Venkataramanan u64 rx_jabber; /* rjc */ 792fcea6f3dSAnirudh Venkataramanan u64 tx_size_64; /* ptc64 */ 793fcea6f3dSAnirudh Venkataramanan u64 tx_size_127; /* ptc127 */ 794fcea6f3dSAnirudh Venkataramanan u64 tx_size_255; /* ptc255 */ 795fcea6f3dSAnirudh Venkataramanan u64 tx_size_511; /* ptc511 */ 796fcea6f3dSAnirudh Venkataramanan u64 tx_size_1023; /* ptc1023 */ 797fcea6f3dSAnirudh Venkataramanan u64 tx_size_1522; /* ptc1522 */ 798fcea6f3dSAnirudh Venkataramanan u64 tx_size_big; /* ptc9522 */ 7994ab95646SHenry Tieman /* flow director stats */ 8004ab95646SHenry Tieman u32 fd_sb_status; 8014ab95646SHenry Tieman u64 fd_sb_match; 802fcea6f3dSAnirudh Venkataramanan }; 803fcea6f3dSAnirudh Venkataramanan 804f31e4b6fSAnirudh Venkataramanan /* Checksum and Shadow RAM pointers */ 8051fa95e01SJacob Keller #define ICE_SR_NVM_CTRL_WORD 0x00 806031f2147SMd Fahad Iqbal Polash #define ICE_SR_BOOT_CFG_PTR 0x132 807769c500dSAkeem G Abodunrin #define ICE_SR_NVM_WOL_CFG 0x19 808d4e87444SJacob Keller #define ICE_NVM_OROM_VER_OFF 0x02 809e961b679SJacob Keller #define ICE_SR_PBA_BLOCK_PTR 0x16 810f31e4b6fSAnirudh Venkataramanan #define ICE_SR_NVM_DEV_STARTER_VER 0x18 811f31e4b6fSAnirudh Venkataramanan #define ICE_SR_NVM_EETRACK_LO 0x2D 812f31e4b6fSAnirudh Venkataramanan #define ICE_SR_NVM_EETRACK_HI 0x2E 813fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_LO_SHIFT 0 814fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT) 815fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_HI_SHIFT 12 816fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT) 817d4e87444SJacob Keller #define ICE_OROM_VER_PATCH_SHIFT 0 818d4e87444SJacob Keller #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT) 819d4e87444SJacob Keller #define ICE_OROM_VER_BUILD_SHIFT 8 820d4e87444SJacob Keller #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT) 821d4e87444SJacob Keller #define ICE_OROM_VER_SHIFT 24 822d4e87444SJacob Keller #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT) 823031f2147SMd Fahad Iqbal Polash #define ICE_SR_PFA_PTR 0x40 824544cd2acSCudzilo, Szymon T #define ICE_SR_1ST_NVM_BANK_PTR 0x42 8251fa95e01SJacob Keller #define ICE_SR_NVM_BANK_SIZE 0x43 826544cd2acSCudzilo, Szymon T #define ICE_SR_1ST_OROM_BANK_PTR 0x44 8271fa95e01SJacob Keller #define ICE_SR_OROM_BANK_SIZE 0x45 828544cd2acSCudzilo, Szymon T #define ICE_SR_NETLIST_BANK_PTR 0x46 8291fa95e01SJacob Keller #define ICE_SR_NETLIST_BANK_SIZE 0x47 830f31e4b6fSAnirudh Venkataramanan #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800 831ea78ce4dSPaul Greenwalt 8320ce50c70SJacob Keller /* CSS Header words */ 8330ce50c70SJacob Keller #define ICE_NVM_CSS_SREV_L 0x14 8340ce50c70SJacob Keller #define ICE_NVM_CSS_SREV_H 0x15 8350ce50c70SJacob Keller 8360ce50c70SJacob Keller /* Length of CSS header section in words */ 8370ce50c70SJacob Keller #define ICE_CSS_HEADER_LENGTH 330 8380ce50c70SJacob Keller 8390ce50c70SJacob Keller /* Offset of Shadow RAM copy in the NVM bank area. */ 8400ce50c70SJacob Keller #define ICE_NVM_SR_COPY_WORD_OFFSET roundup(ICE_CSS_HEADER_LENGTH, 32) 8410ce50c70SJacob Keller 8420ce50c70SJacob Keller /* Size in bytes of Option ROM trailer */ 8430ce50c70SJacob Keller #define ICE_NVM_OROM_TRAILER_LENGTH (2 * ICE_CSS_HEADER_LENGTH) 8440ce50c70SJacob Keller 845*e120a9abSJacob Keller /* The Link Topology Netlist section is stored as a series of words. It is 846*e120a9abSJacob Keller * stored in the NVM as a TLV, with the first two words containing the type 847*e120a9abSJacob Keller * and length. 848*e120a9abSJacob Keller */ 849*e120a9abSJacob Keller #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B 850*e120a9abSJacob Keller #define ICE_NETLIST_TYPE_OFFSET 0x0000 851*e120a9abSJacob Keller #define ICE_NETLIST_LEN_OFFSET 0x0001 852*e120a9abSJacob Keller 853*e120a9abSJacob Keller /* The Link Topology section follows the TLV header. When reading the netlist 854*e120a9abSJacob Keller * using ice_read_netlist_module, we need to account for the 2-word TLV 855*e120a9abSJacob Keller * header. 856*e120a9abSJacob Keller */ 857*e120a9abSJacob Keller #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2) 858*e120a9abSJacob Keller 859*e120a9abSJacob Keller #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000) 860*e120a9abSJacob Keller #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001) 861*e120a9abSJacob Keller 862*e120a9abSJacob Keller #define ICE_LINK_TOPO_NODE_COUNT_M ICE_M(0x3FF, 0) 863*e120a9abSJacob Keller 864*e120a9abSJacob Keller /* The Netlist ID Block is located after all of the Link Topology nodes. */ 865*e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_SIZE 0x30 866*e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n)) 867*e120a9abSJacob Keller 868*e120a9abSJacob Keller /* netlist ID block field offsets (word offsets) */ 869*e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02 870*e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03 871*e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04 872*e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05 873*e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06 874*e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07 875*e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_REV_LOW 0x08 876*e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09 877*e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n)) 878*e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F 879*e120a9abSJacob Keller 8801fa95e01SJacob Keller /* Auxiliary field, mask, and shift definition for Shadow RAM and NVM Flash */ 8811fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_1_S 0x06 8821fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S) 8831fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_VALID 0x1 8841fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3) 8851fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4) 8861fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5) 8871fa95e01SJacob Keller 8881fa95e01SJacob Keller #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15) 8891fa95e01SJacob Keller 890ea78ce4dSPaul Greenwalt /* Link override related */ 891ea78ce4dSPaul Greenwalt #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10 892ea78ce4dSPaul Greenwalt #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4 893ea78ce4dSPaul Greenwalt #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2 894ea78ce4dSPaul Greenwalt #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1 895ea78ce4dSPaul Greenwalt #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2 896ea78ce4dSPaul Greenwalt #define ICE_FW_API_LINK_OVERRIDE_MAJ 1 897ea78ce4dSPaul Greenwalt #define ICE_FW_API_LINK_OVERRIDE_MIN 5 898ea78ce4dSPaul Greenwalt #define ICE_FW_API_LINK_OVERRIDE_PATCH 2 899ea78ce4dSPaul Greenwalt 900f31e4b6fSAnirudh Venkataramanan #define ICE_SR_WORDS_IN_1KB 512 901f31e4b6fSAnirudh Venkataramanan 9028ede0178SAnirudh Venkataramanan /* Hash redirection LUT for VSI - maximum array size */ 9038ede0178SAnirudh Venkataramanan #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4) 9048ede0178SAnirudh Venkataramanan 905837f08fdSAnirudh Venkataramanan #endif /* _ICE_TYPE_H_ */ 906