1837f08fdSAnirudh Venkataramanan /* SPDX-License-Identifier: GPL-2.0 */ 2837f08fdSAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */ 3837f08fdSAnirudh Venkataramanan 4837f08fdSAnirudh Venkataramanan #ifndef _ICE_TYPE_H_ 5837f08fdSAnirudh Venkataramanan #define _ICE_TYPE_H_ 6837f08fdSAnirudh Venkataramanan 76a025730STony Nguyen #define ICE_BYTES_PER_WORD 2 86a025730STony Nguyen #define ICE_BYTES_PER_DWORD 4 96a025730STony Nguyen 107ec59eeaSAnirudh Venkataramanan #include "ice_status.h" 117ec59eeaSAnirudh Venkataramanan #include "ice_hw_autogen.h" 127ec59eeaSAnirudh Venkataramanan #include "ice_osdep.h" 137ec59eeaSAnirudh Venkataramanan #include "ice_controlq.h" 14cdedef59SAnirudh Venkataramanan #include "ice_lan_tx_rx.h" 15c7648810STony Nguyen #include "ice_flex_type.h" 1631ad4e4eSTony Nguyen #include "ice_protocol_type.h" 177ec59eeaSAnirudh Venkataramanan 1835b4f437SJacob Keller static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc) 195513b920SAnirudh Venkataramanan { 2035b4f437SJacob Keller return test_bit(tc, &bitmap); 215513b920SAnirudh Venkataramanan } 225513b920SAnirudh Venkataramanan 231ddef455SUsha Ketineni static inline u64 round_up_64bit(u64 a, u32 b) 241ddef455SUsha Ketineni { 251ddef455SUsha Ketineni return div64_long(((a) + (b) / 2), (b)); 261ddef455SUsha Ketineni } 271ddef455SUsha Ketineni 281ddef455SUsha Ketineni static inline u32 ice_round_to_num(u32 N, u32 R) 291ddef455SUsha Ketineni { 301ddef455SUsha Ketineni return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) : 311ddef455SUsha Ketineni ((((N) + (R) - 1) / (R)) * (R))); 321ddef455SUsha Ketineni } 331ddef455SUsha Ketineni 34334cb062SAnirudh Venkataramanan /* Driver always calls main vsi_handle first */ 35334cb062SAnirudh Venkataramanan #define ICE_MAIN_VSI_HANDLE 0 36334cb062SAnirudh Venkataramanan 377ec59eeaSAnirudh Venkataramanan /* debug masks - set these bits in hw->debug_mask to control output */ 38f31e4b6fSAnirudh Venkataramanan #define ICE_DBG_INIT BIT_ULL(1) 394f70daa0SJacob Keller #define ICE_DBG_FW_LOG BIT_ULL(3) 400b28b702SAnirudh Venkataramanan #define ICE_DBG_LINK BIT_ULL(4) 41d8df260aSChinh T Cao #define ICE_DBG_PHY BIT_ULL(5) 42cdedef59SAnirudh Venkataramanan #define ICE_DBG_QCTX BIT_ULL(6) 43f31e4b6fSAnirudh Venkataramanan #define ICE_DBG_NVM BIT_ULL(7) 44dc49c772SAnirudh Venkataramanan #define ICE_DBG_LAN BIT_ULL(8) 4531ad4e4eSTony Nguyen #define ICE_DBG_FLOW BIT_ULL(9) 469c20346bSAnirudh Venkataramanan #define ICE_DBG_SW BIT_ULL(13) 479c20346bSAnirudh Venkataramanan #define ICE_DBG_SCHED BIT_ULL(14) 48c7648810STony Nguyen #define ICE_DBG_PKG BIT_ULL(16) 49f31e4b6fSAnirudh Venkataramanan #define ICE_DBG_RES BIT_ULL(17) 507ec59eeaSAnirudh Venkataramanan #define ICE_DBG_AQ_MSG BIT_ULL(24) 51faa01721SJacob Keller #define ICE_DBG_AQ_DESC BIT_ULL(25) 52faa01721SJacob Keller #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26) 537ec59eeaSAnirudh Venkataramanan #define ICE_DBG_AQ_CMD BIT_ULL(27) 54fcea6f3dSAnirudh Venkataramanan #define ICE_DBG_USER BIT_ULL(31) 557ec59eeaSAnirudh Venkataramanan 56f31e4b6fSAnirudh Venkataramanan enum ice_aq_res_ids { 57f31e4b6fSAnirudh Venkataramanan ICE_NVM_RES_ID = 1, 58f31e4b6fSAnirudh Venkataramanan ICE_SPD_RES_ID, 59ff2b1321SDan Nowlin ICE_CHANGE_LOCK_RES_ID, 60ff2b1321SDan Nowlin ICE_GLOBAL_CFG_LOCK_RES_ID 61f31e4b6fSAnirudh Venkataramanan }; 62f31e4b6fSAnirudh Venkataramanan 63ff2b1321SDan Nowlin /* FW update timeout definitions are in milliseconds */ 64ff2b1321SDan Nowlin #define ICE_NVM_TIMEOUT 180000 65ff2b1321SDan Nowlin #define ICE_CHANGE_LOCK_TIMEOUT 1000 66ff2b1321SDan Nowlin #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000 67ff2b1321SDan Nowlin 68f31e4b6fSAnirudh Venkataramanan enum ice_aq_res_access_type { 69f31e4b6fSAnirudh Venkataramanan ICE_RES_READ = 1, 70f31e4b6fSAnirudh Venkataramanan ICE_RES_WRITE 71f31e4b6fSAnirudh Venkataramanan }; 72f31e4b6fSAnirudh Venkataramanan 73e3710a01SPaul M Stillwell Jr struct ice_driver_ver { 74e3710a01SPaul M Stillwell Jr u8 major_ver; 75e3710a01SPaul M Stillwell Jr u8 minor_ver; 76e3710a01SPaul M Stillwell Jr u8 build_ver; 77e3710a01SPaul M Stillwell Jr u8 subbuild_ver; 78e3710a01SPaul M Stillwell Jr u8 driver_string[32]; 79e3710a01SPaul M Stillwell Jr }; 80e3710a01SPaul M Stillwell Jr 81dc49c772SAnirudh Venkataramanan enum ice_fc_mode { 82dc49c772SAnirudh Venkataramanan ICE_FC_NONE = 0, 83dc49c772SAnirudh Venkataramanan ICE_FC_RX_PAUSE, 84dc49c772SAnirudh Venkataramanan ICE_FC_TX_PAUSE, 85dc49c772SAnirudh Venkataramanan ICE_FC_FULL, 86dc49c772SAnirudh Venkataramanan ICE_FC_PFC, 87dc49c772SAnirudh Venkataramanan ICE_FC_DFLT 88dc49c772SAnirudh Venkataramanan }; 89dc49c772SAnirudh Venkataramanan 901a3571b5SPaul Greenwalt enum ice_phy_cache_mode { 911a3571b5SPaul Greenwalt ICE_FC_MODE = 0, 921a3571b5SPaul Greenwalt ICE_SPEED_MODE, 931a3571b5SPaul Greenwalt ICE_FEC_MODE 941a3571b5SPaul Greenwalt }; 951a3571b5SPaul Greenwalt 96f776b3acSPaul Greenwalt enum ice_fec_mode { 97f776b3acSPaul Greenwalt ICE_FEC_NONE = 0, 98f776b3acSPaul Greenwalt ICE_FEC_RS, 99f776b3acSPaul Greenwalt ICE_FEC_BASER, 100f776b3acSPaul Greenwalt ICE_FEC_AUTO 101f776b3acSPaul Greenwalt }; 102f776b3acSPaul Greenwalt 1031a3571b5SPaul Greenwalt struct ice_phy_cache_mode_data { 1041a3571b5SPaul Greenwalt union { 1051a3571b5SPaul Greenwalt enum ice_fec_mode curr_user_fec_req; 1061a3571b5SPaul Greenwalt enum ice_fc_mode curr_user_fc_req; 1071a3571b5SPaul Greenwalt u16 curr_user_speed_req; 1081a3571b5SPaul Greenwalt } data; 1091a3571b5SPaul Greenwalt }; 1101a3571b5SPaul Greenwalt 111fcea6f3dSAnirudh Venkataramanan enum ice_set_fc_aq_failures { 112fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_NONE = 0, 113fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_GET, 114fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_SET, 115fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_UPDATE 116fcea6f3dSAnirudh Venkataramanan }; 117fcea6f3dSAnirudh Venkataramanan 118f31e4b6fSAnirudh Venkataramanan /* Various MAC types */ 119f31e4b6fSAnirudh Venkataramanan enum ice_mac_type { 120f31e4b6fSAnirudh Venkataramanan ICE_MAC_UNKNOWN = 0, 121ea78ce4dSPaul Greenwalt ICE_MAC_E810, 122f31e4b6fSAnirudh Venkataramanan ICE_MAC_GENERIC, 123f31e4b6fSAnirudh Venkataramanan }; 124f31e4b6fSAnirudh Venkataramanan 125dc49c772SAnirudh Venkataramanan /* Media Types */ 126dc49c772SAnirudh Venkataramanan enum ice_media_type { 127dc49c772SAnirudh Venkataramanan ICE_MEDIA_UNKNOWN = 0, 128dc49c772SAnirudh Venkataramanan ICE_MEDIA_FIBER, 129dc49c772SAnirudh Venkataramanan ICE_MEDIA_BASET, 130dc49c772SAnirudh Venkataramanan ICE_MEDIA_BACKPLANE, 131dc49c772SAnirudh Venkataramanan ICE_MEDIA_DA, 132dc49c772SAnirudh Venkataramanan }; 133dc49c772SAnirudh Venkataramanan 1343a858ba3SAnirudh Venkataramanan enum ice_vsi_type { 1353a858ba3SAnirudh Venkataramanan ICE_VSI_PF = 0, 136148beb61SHenry Tieman ICE_VSI_VF = 1, 137148beb61SHenry Tieman ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */ 1380e674aebSAnirudh Venkataramanan ICE_VSI_LB = 6, 1393a858ba3SAnirudh Venkataramanan }; 1403a858ba3SAnirudh Venkataramanan 141dc49c772SAnirudh Venkataramanan struct ice_link_status { 142dc49c772SAnirudh Venkataramanan /* Refer to ice_aq_phy_type for bits definition */ 143dc49c772SAnirudh Venkataramanan u64 phy_type_low; 144aef74145SAnirudh Venkataramanan u64 phy_type_high; 145f776b3acSPaul Greenwalt u8 topo_media_conflict; 146dc49c772SAnirudh Venkataramanan u16 max_frame_size; 147dc49c772SAnirudh Venkataramanan u16 link_speed; 148ffe49823SChinh T Cao u16 req_speeds; 14943f8b224SBruce Allan u8 lse_ena; /* Link Status Event notification */ 150dc49c772SAnirudh Venkataramanan u8 link_info; 151dc49c772SAnirudh Venkataramanan u8 an_info; 152dc49c772SAnirudh Venkataramanan u8 ext_info; 153f776b3acSPaul Greenwalt u8 fec_info; 154dc49c772SAnirudh Venkataramanan u8 pacing; 155dc49c772SAnirudh Venkataramanan /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of 156dc49c772SAnirudh Venkataramanan * ice_aqc_get_phy_caps structure 157dc49c772SAnirudh Venkataramanan */ 158dc49c772SAnirudh Venkataramanan u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 159dc49c772SAnirudh Venkataramanan }; 160dc49c772SAnirudh Venkataramanan 161ddf30f7fSAnirudh Venkataramanan /* Different reset sources for which a disable queue AQ call has to be made in 162f9867df6SAnirudh Venkataramanan * order to clean the Tx scheduler as a part of the reset 163ddf30f7fSAnirudh Venkataramanan */ 164ddf30f7fSAnirudh Venkataramanan enum ice_disq_rst_src { 165ddf30f7fSAnirudh Venkataramanan ICE_NO_RESET = 0, 166ddf30f7fSAnirudh Venkataramanan ICE_VM_RESET, 167ddf30f7fSAnirudh Venkataramanan ICE_VF_RESET, 168ddf30f7fSAnirudh Venkataramanan }; 169ddf30f7fSAnirudh Venkataramanan 170dc49c772SAnirudh Venkataramanan /* PHY info such as phy_type, etc... */ 171dc49c772SAnirudh Venkataramanan struct ice_phy_info { 172dc49c772SAnirudh Venkataramanan struct ice_link_status link_info; 173dc49c772SAnirudh Venkataramanan struct ice_link_status link_info_old; 174dc49c772SAnirudh Venkataramanan u64 phy_type_low; 175aef74145SAnirudh Venkataramanan u64 phy_type_high; 176dc49c772SAnirudh Venkataramanan enum ice_media_type media_type; 17743f8b224SBruce Allan u8 get_link_info; 1781a3571b5SPaul Greenwalt /* Please refer to struct ice_aqc_get_link_status_data to get 1791a3571b5SPaul Greenwalt * detail of enable bit in curr_user_speed_req 1801a3571b5SPaul Greenwalt */ 1811a3571b5SPaul Greenwalt u16 curr_user_speed_req; 1821a3571b5SPaul Greenwalt enum ice_fec_mode curr_user_fec_req; 1831a3571b5SPaul Greenwalt enum ice_fc_mode curr_user_fc_req; 1841a3571b5SPaul Greenwalt struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg; 185dc49c772SAnirudh Venkataramanan }; 186dc49c772SAnirudh Venkataramanan 187148beb61SHenry Tieman /* protocol enumeration for filters */ 188148beb61SHenry Tieman enum ice_fltr_ptype { 189148beb61SHenry Tieman /* NONE - used for undef/error */ 190148beb61SHenry Tieman ICE_FLTR_PTYPE_NONF_NONE = 0, 191148beb61SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV4_UDP, 192148beb61SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV4_TCP, 193148beb61SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV4_SCTP, 194148beb61SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV4_OTHER, 195ef9e4cc5SQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP, 196ef9e4cc5SQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP, 197ef9e4cc5SQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP, 198ef9e4cc5SQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER, 199213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER, 200213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3, 201213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3, 202213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_ESP, 203213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV6_ESP, 204213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_AH, 205213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV6_AH, 206213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP, 207213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP, 208213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE, 209213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION, 210213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE, 211213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION, 21221606584SQi Zhang ICE_FLTR_PTYPE_NON_IP_L2, 213148beb61SHenry Tieman ICE_FLTR_PTYPE_FRAG_IPV4, 214165d80d6SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV6_UDP, 215165d80d6SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV6_TCP, 216165d80d6SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV6_SCTP, 217165d80d6SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV6_OTHER, 218148beb61SHenry Tieman ICE_FLTR_PTYPE_MAX, 219148beb61SHenry Tieman }; 220148beb61SHenry Tieman 221148beb61SHenry Tieman enum ice_fd_hw_seg { 222148beb61SHenry Tieman ICE_FD_HW_SEG_NON_TUN = 0, 223148beb61SHenry Tieman ICE_FD_HW_SEG_TUN, 224148beb61SHenry Tieman ICE_FD_HW_SEG_MAX, 225148beb61SHenry Tieman }; 226148beb61SHenry Tieman 227148beb61SHenry Tieman /* 2 VSI = 1 ICE_VSI_PF + 1 ICE_VSI_CTRL */ 228148beb61SHenry Tieman #define ICE_MAX_FDIR_VSI_PER_FILTER 2 229148beb61SHenry Tieman 230148beb61SHenry Tieman struct ice_fd_hw_prof { 231148beb61SHenry Tieman struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX]; 232148beb61SHenry Tieman int cnt; 233148beb61SHenry Tieman u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX]; 234148beb61SHenry Tieman u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER]; 235148beb61SHenry Tieman }; 236148beb61SHenry Tieman 2379c20346bSAnirudh Venkataramanan /* Common HW capabilities for SW use */ 2389c20346bSAnirudh Venkataramanan struct ice_hw_common_caps { 239995c90f2SAnirudh Venkataramanan u32 valid_functions; 240a257f188SUsha Ketineni /* DCB capabilities */ 241a257f188SUsha Ketineni u32 active_tc_bitmap; 242a257f188SUsha Ketineni u32 maxtc; 243995c90f2SAnirudh Venkataramanan 244f9867df6SAnirudh Venkataramanan /* Tx/Rx queues */ 245f9867df6SAnirudh Venkataramanan u16 num_rxq; /* Number/Total Rx queues */ 246f9867df6SAnirudh Venkataramanan u16 rxq_first_id; /* First queue ID for Rx queues */ 247f9867df6SAnirudh Venkataramanan u16 num_txq; /* Number/Total Tx queues */ 248f9867df6SAnirudh Venkataramanan u16 txq_first_id; /* First queue ID for Tx queues */ 2499c20346bSAnirudh Venkataramanan 2509c20346bSAnirudh Venkataramanan /* MSI-X vectors */ 2519c20346bSAnirudh Venkataramanan u16 num_msix_vectors; 2529c20346bSAnirudh Venkataramanan u16 msix_vector_first_id; 2539c20346bSAnirudh Venkataramanan 2549c20346bSAnirudh Venkataramanan /* Max MTU for function or device */ 2559c20346bSAnirudh Venkataramanan u16 max_mtu; 2569c20346bSAnirudh Venkataramanan 25775d2b253SAnirudh Venkataramanan /* Virtualization support */ 25875d2b253SAnirudh Venkataramanan u8 sr_iov_1_1; /* SR-IOV enabled */ 259ddf30f7fSAnirudh Venkataramanan 2609c20346bSAnirudh Venkataramanan /* RSS related capabilities */ 2619c20346bSAnirudh Venkataramanan u16 rss_table_size; /* 512 for PFs and 64 for VFs */ 2629c20346bSAnirudh Venkataramanan u8 rss_table_entry_width; /* RSS Entry width in bits */ 26337b6f646SAnirudh Venkataramanan 26437b6f646SAnirudh Venkataramanan u8 dcb; 265*d25a0fc4SDave Ertman u8 rdma; 266de9b277eSJacek Naczyk 2672ab560a7SJacob Keller bool nvm_update_pending_nvm; 2682ab560a7SJacob Keller bool nvm_update_pending_orom; 2692ab560a7SJacob Keller bool nvm_update_pending_netlist; 2702ab560a7SJacob Keller #define ICE_NVM_PENDING_NVM_IMAGE BIT(0) 2712ab560a7SJacob Keller #define ICE_NVM_PENDING_OROM BIT(1) 2722ab560a7SJacob Keller #define ICE_NVM_PENDING_NETLIST BIT(2) 273de9b277eSJacek Naczyk bool nvm_unified_update; 274de9b277eSJacek Naczyk #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) 2759c20346bSAnirudh Venkataramanan }; 2769c20346bSAnirudh Venkataramanan 2779c20346bSAnirudh Venkataramanan /* Function specific capabilities */ 2789c20346bSAnirudh Venkataramanan struct ice_hw_func_caps { 2799c20346bSAnirudh Venkataramanan struct ice_hw_common_caps common_cap; 28075d2b253SAnirudh Venkataramanan u32 num_allocd_vfs; /* Number of allocated VFs */ 28175d2b253SAnirudh Venkataramanan u32 vf_base_id; /* Logical ID of the first VF */ 282995c90f2SAnirudh Venkataramanan u32 guar_num_vsi; 283148beb61SHenry Tieman u32 fd_fltr_guar; /* Number of filters guaranteed */ 284148beb61SHenry Tieman u32 fd_fltr_best_effort; /* Number of best effort filters */ 2859c20346bSAnirudh Venkataramanan }; 2869c20346bSAnirudh Venkataramanan 2879c20346bSAnirudh Venkataramanan /* Device wide capabilities */ 2889c20346bSAnirudh Venkataramanan struct ice_hw_dev_caps { 2899c20346bSAnirudh Venkataramanan struct ice_hw_common_caps common_cap; 29075d2b253SAnirudh Venkataramanan u32 num_vfs_exposed; /* Total number of VFs exposed */ 2919c20346bSAnirudh Venkataramanan u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ 292148beb61SHenry Tieman u32 num_flow_director_fltr; /* Number of FD filters available */ 293eae1bbb2SBruce Allan u32 num_funcs; 2949c20346bSAnirudh Venkataramanan }; 2959c20346bSAnirudh Venkataramanan 296dc49c772SAnirudh Venkataramanan /* MAC info */ 297dc49c772SAnirudh Venkataramanan struct ice_mac_info { 298dc49c772SAnirudh Venkataramanan u8 lan_addr[ETH_ALEN]; 299dc49c772SAnirudh Venkataramanan u8 perm_addr[ETH_ALEN]; 300dc49c772SAnirudh Venkataramanan }; 301dc49c772SAnirudh Venkataramanan 302ca4929b6SBrett Creeley /* Reset types used to determine which kind of reset was requested. These 303ca4929b6SBrett Creeley * defines match what the RESET_TYPE field of the GLGEN_RSTAT register. 304ca4929b6SBrett Creeley * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register 305ca4929b6SBrett Creeley * because its reset source is different than the other types listed. 306ca4929b6SBrett Creeley */ 307f31e4b6fSAnirudh Venkataramanan enum ice_reset_req { 308ca4929b6SBrett Creeley ICE_RESET_POR = 0, 3090f9d5027SAnirudh Venkataramanan ICE_RESET_INVAL = 0, 310ca4929b6SBrett Creeley ICE_RESET_CORER = 1, 311ca4929b6SBrett Creeley ICE_RESET_GLOBR = 2, 312ca4929b6SBrett Creeley ICE_RESET_EMPR = 3, 313ca4929b6SBrett Creeley ICE_RESET_PFR = 4, 314f31e4b6fSAnirudh Venkataramanan }; 315f31e4b6fSAnirudh Venkataramanan 316837f08fdSAnirudh Venkataramanan /* Bus parameters */ 317837f08fdSAnirudh Venkataramanan struct ice_bus_info { 318837f08fdSAnirudh Venkataramanan u16 device; 319837f08fdSAnirudh Venkataramanan u8 func; 320837f08fdSAnirudh Venkataramanan }; 321837f08fdSAnirudh Venkataramanan 322dc49c772SAnirudh Venkataramanan /* Flow control (FC) parameters */ 323dc49c772SAnirudh Venkataramanan struct ice_fc_info { 324dc49c772SAnirudh Venkataramanan enum ice_fc_mode current_mode; /* FC mode in effect */ 325dc49c772SAnirudh Venkataramanan enum ice_fc_mode req_mode; /* FC mode requested by caller */ 326dc49c772SAnirudh Venkataramanan }; 327dc49c772SAnirudh Venkataramanan 328d4e87444SJacob Keller /* Option ROM version information */ 329d4e87444SJacob Keller struct ice_orom_info { 330d4e87444SJacob Keller u8 major; /* Major version of OROM */ 331d4e87444SJacob Keller u8 patch; /* Patch version of OROM */ 332d4e87444SJacob Keller u16 build; /* Build version of OROM */ 333d4e87444SJacob Keller }; 334d4e87444SJacob Keller 3359af368faSJacob Keller /* NVM version information */ 336f31e4b6fSAnirudh Venkataramanan struct ice_nvm_info { 3379af368faSJacob Keller u32 eetrack; 3389af368faSJacob Keller u8 major; 3399af368faSJacob Keller u8 minor; 3409af368faSJacob Keller }; 3419af368faSJacob Keller 3429af368faSJacob Keller /* netlist version information */ 3439af368faSJacob Keller struct ice_netlist_info { 3449af368faSJacob Keller u32 major; /* major high/low */ 3459af368faSJacob Keller u32 minor; /* minor high/low */ 3469af368faSJacob Keller u32 type; /* type high/low */ 3479af368faSJacob Keller u32 rev; /* revision high/low */ 3489af368faSJacob Keller u32 hash; /* SHA-1 hash word */ 3499af368faSJacob Keller u16 cust_ver; /* customer version */ 3509af368faSJacob Keller }; 3519af368faSJacob Keller 3521fa95e01SJacob Keller /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules 3531fa95e01SJacob Keller * of the flash image. 3541fa95e01SJacob Keller */ 3551fa95e01SJacob Keller enum ice_flash_bank { 3561fa95e01SJacob Keller ICE_INVALID_FLASH_BANK, 3571fa95e01SJacob Keller ICE_1ST_FLASH_BANK, 3581fa95e01SJacob Keller ICE_2ND_FLASH_BANK, 3591fa95e01SJacob Keller }; 3601fa95e01SJacob Keller 3610ce50c70SJacob Keller /* Enumeration of which flash bank is desired to read from, either the active 3620ce50c70SJacob Keller * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from 3630ce50c70SJacob Keller * code which just wants to read the active or inactive flash bank. 3640ce50c70SJacob Keller */ 3650ce50c70SJacob Keller enum ice_bank_select { 3660ce50c70SJacob Keller ICE_ACTIVE_FLASH_BANK, 3670ce50c70SJacob Keller ICE_INACTIVE_FLASH_BANK, 3680ce50c70SJacob Keller }; 3690ce50c70SJacob Keller 3701fa95e01SJacob Keller /* information for accessing NVM, OROM, and Netlist flash banks */ 3711fa95e01SJacob Keller struct ice_bank_info { 3721fa95e01SJacob Keller u32 nvm_ptr; /* Pointer to 1st NVM bank */ 3731fa95e01SJacob Keller u32 nvm_size; /* Size of NVM bank */ 3741fa95e01SJacob Keller u32 orom_ptr; /* Pointer to 1st OROM bank */ 3751fa95e01SJacob Keller u32 orom_size; /* Size of OROM bank */ 3761fa95e01SJacob Keller u32 netlist_ptr; /* Pointer to 1st Netlist bank */ 3771fa95e01SJacob Keller u32 netlist_size; /* Size of Netlist bank */ 3781fa95e01SJacob Keller enum ice_flash_bank nvm_bank; /* Active NVM bank */ 3791fa95e01SJacob Keller enum ice_flash_bank orom_bank; /* Active OROM bank */ 3801fa95e01SJacob Keller enum ice_flash_bank netlist_bank; /* Active Netlist bank */ 3811fa95e01SJacob Keller }; 3821fa95e01SJacob Keller 3839af368faSJacob Keller /* Flash Chip Information */ 3849af368faSJacob Keller struct ice_flash_info { 385d4e87444SJacob Keller struct ice_orom_info orom; /* Option ROM version info */ 3869af368faSJacob Keller struct ice_nvm_info nvm; /* NVM version information */ 3879af368faSJacob Keller struct ice_netlist_info netlist;/* Netlist version info */ 3881fa95e01SJacob Keller struct ice_bank_info banks; /* Flash Bank information */ 389f31e4b6fSAnirudh Venkataramanan u16 sr_words; /* Shadow RAM size in words */ 39081f07491SJacob Keller u32 flash_size; /* Size of available flash in bytes */ 39143f8b224SBruce Allan u8 blank_nvm_mode; /* is NVM empty (no FW present) */ 392f31e4b6fSAnirudh Venkataramanan }; 393f31e4b6fSAnirudh Venkataramanan 394ea78ce4dSPaul Greenwalt struct ice_link_default_override_tlv { 395ea78ce4dSPaul Greenwalt u8 options; 396ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_OPT_M 0x3F 397ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0) 398ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1) 399ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2) 400ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_EN BIT(3) 401ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4) 402ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_EEE_EN BIT(5) 403ea78ce4dSPaul Greenwalt u8 phy_config; 404ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_PHY_CFG_S 8 405ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S) 406ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_PAUSE_M 0x3 407ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_LESM_EN BIT(6) 408ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7) 409ea78ce4dSPaul Greenwalt u8 fec_options; 410ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF 411ea78ce4dSPaul Greenwalt u8 rsvd1; 412ea78ce4dSPaul Greenwalt u64 phy_type_low; 413ea78ce4dSPaul Greenwalt u64 phy_type_high; 414ea78ce4dSPaul Greenwalt }; 415ea78ce4dSPaul Greenwalt 416870f805eSLukasz Czapnik #define ICE_NVM_VER_LEN 32 417870f805eSLukasz Czapnik 4189c20346bSAnirudh Venkataramanan /* Max number of port to queue branches w.r.t topology */ 4199c20346bSAnirudh Venkataramanan #define ICE_MAX_TRAFFIC_CLASS 8 420dc49c772SAnirudh Venkataramanan #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS 4219c20346bSAnirudh Venkataramanan 4222bdc97beSBruce Allan #define ice_for_each_traffic_class(_i) \ 4232bdc97beSBruce Allan for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++) 4242bdc97beSBruce Allan 425b126bd6bSKiran Patil /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects 426b126bd6bSKiran Patil * to driver defined policy for default aggregator 427b126bd6bSKiran Patil */ 4287b9ffc76SAnirudh Venkataramanan #define ICE_INVAL_TEID 0xFFFFFFFF 429b126bd6bSKiran Patil #define ICE_DFLT_AGG_ID 0 4307b9ffc76SAnirudh Venkataramanan 4319c20346bSAnirudh Venkataramanan struct ice_sched_node { 4329c20346bSAnirudh Venkataramanan struct ice_sched_node *parent; 4339c20346bSAnirudh Venkataramanan struct ice_sched_node *sibling; /* next sibling in the same layer */ 4349c20346bSAnirudh Venkataramanan struct ice_sched_node **children; 4359c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_elem_data info; 436f9867df6SAnirudh Venkataramanan u32 agg_id; /* aggregator group ID */ 4374fb33f31SAnirudh Venkataramanan u16 vsi_handle; 43843f8b224SBruce Allan u8 in_use; /* suspended or in use */ 4399c20346bSAnirudh Venkataramanan u8 tx_sched_layer; /* Logical Layer (1-9) */ 4409c20346bSAnirudh Venkataramanan u8 num_children; 4419c20346bSAnirudh Venkataramanan u8 tc_num; 4429c20346bSAnirudh Venkataramanan u8 owner; 4439c20346bSAnirudh Venkataramanan #define ICE_SCHED_NODE_OWNER_LAN 0 4449c20346bSAnirudh Venkataramanan }; 4459c20346bSAnirudh Venkataramanan 446dc49c772SAnirudh Venkataramanan /* Access Macros for Tx Sched Elements data */ 447dc49c772SAnirudh Venkataramanan #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid) 448dc49c772SAnirudh Venkataramanan 4499c20346bSAnirudh Venkataramanan /* The aggregator type determines if identifier is for a VSI group, 4509c20346bSAnirudh Venkataramanan * aggregator group, aggregator of queues, or queue group. 4519c20346bSAnirudh Venkataramanan */ 4529c20346bSAnirudh Venkataramanan enum ice_agg_type { 4539c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_UNKNOWN = 0, 4549c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_VSI, 4559c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_AGG, /* aggregator */ 4569c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_Q, 4579c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_QG 4589c20346bSAnirudh Venkataramanan }; 4599c20346bSAnirudh Venkataramanan 4601ddef455SUsha Ketineni /* Rate limit types */ 4611ddef455SUsha Ketineni enum ice_rl_type { 4621ddef455SUsha Ketineni ICE_UNKNOWN_BW = 0, 4631ddef455SUsha Ketineni ICE_MIN_BW, /* for CIR profile */ 4641ddef455SUsha Ketineni ICE_MAX_BW, /* for EIR profile */ 4651ddef455SUsha Ketineni ICE_SHARED_BW /* for shared profile */ 4661ddef455SUsha Ketineni }; 4675513b920SAnirudh Venkataramanan 4681ddef455SUsha Ketineni #define ICE_SCHED_MIN_BW 500 /* in Kbps */ 4691ddef455SUsha Ketineni #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */ 4701ddef455SUsha Ketineni #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */ 4711ddef455SUsha Ketineni #define ICE_SCHED_DFLT_RL_PROF_ID 0 4721ddef455SUsha Ketineni #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF 473984824a2STarun Singh #define ICE_SCHED_DFLT_BW_WT 4 4741ddef455SUsha Ketineni #define ICE_SCHED_INVAL_PROF_ID 0xFFFF 4751ddef455SUsha Ketineni #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */ 4761ddef455SUsha Ketineni 4771ddef455SUsha Ketineni /* Data structure for saving BW information */ 4781ddef455SUsha Ketineni enum ice_bw_type { 4791ddef455SUsha Ketineni ICE_BW_TYPE_PRIO, 4801ddef455SUsha Ketineni ICE_BW_TYPE_CIR, 4811ddef455SUsha Ketineni ICE_BW_TYPE_CIR_WT, 4821ddef455SUsha Ketineni ICE_BW_TYPE_EIR, 4831ddef455SUsha Ketineni ICE_BW_TYPE_EIR_WT, 4841ddef455SUsha Ketineni ICE_BW_TYPE_SHARED, 4851ddef455SUsha Ketineni ICE_BW_TYPE_CNT /* This must be last */ 4861ddef455SUsha Ketineni }; 4871ddef455SUsha Ketineni 4881ddef455SUsha Ketineni struct ice_bw { 4891ddef455SUsha Ketineni u32 bw; 4901ddef455SUsha Ketineni u16 bw_alloc; 4911ddef455SUsha Ketineni }; 4921ddef455SUsha Ketineni 4931ddef455SUsha Ketineni struct ice_bw_type_info { 4941ddef455SUsha Ketineni DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT); 4951ddef455SUsha Ketineni u8 generic; 4961ddef455SUsha Ketineni struct ice_bw cir_bw; 4971ddef455SUsha Ketineni struct ice_bw eir_bw; 4981ddef455SUsha Ketineni u32 shared_bw; 4991ddef455SUsha Ketineni }; 5001ddef455SUsha Ketineni 5011ddef455SUsha Ketineni /* VSI queue context structure for given TC */ 5021ddef455SUsha Ketineni struct ice_q_ctx { 5031ddef455SUsha Ketineni u16 q_handle; 5041ddef455SUsha Ketineni u32 q_teid; 5051ddef455SUsha Ketineni /* bw_t_info saves queue BW information */ 5061ddef455SUsha Ketineni struct ice_bw_type_info bw_t_info; 5071ddef455SUsha Ketineni }; 5081ddef455SUsha Ketineni 5091ddef455SUsha Ketineni /* VSI type list entry to locate corresponding VSI/aggregator nodes */ 5109c20346bSAnirudh Venkataramanan struct ice_sched_vsi_info { 5119c20346bSAnirudh Venkataramanan struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS]; 5129c20346bSAnirudh Venkataramanan struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS]; 5139c20346bSAnirudh Venkataramanan struct list_head list_entry; 5149c20346bSAnirudh Venkataramanan u16 max_lanq[ICE_MAX_TRAFFIC_CLASS]; 5159c20346bSAnirudh Venkataramanan }; 5169c20346bSAnirudh Venkataramanan 5179c20346bSAnirudh Venkataramanan /* driver defines the policy */ 5189c20346bSAnirudh Venkataramanan struct ice_sched_tx_policy { 5199c20346bSAnirudh Venkataramanan u16 max_num_vsis; 5209c20346bSAnirudh Venkataramanan u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS]; 52143f8b224SBruce Allan u8 rdma_ena; 5229c20346bSAnirudh Venkataramanan }; 5239c20346bSAnirudh Venkataramanan 5240ebd3ff1SAnirudh Venkataramanan /* CEE or IEEE 802.1Qaz ETS Configuration data */ 5250ebd3ff1SAnirudh Venkataramanan struct ice_dcb_ets_cfg { 5260ebd3ff1SAnirudh Venkataramanan u8 willing; 5270ebd3ff1SAnirudh Venkataramanan u8 cbs; 5280ebd3ff1SAnirudh Venkataramanan u8 maxtcs; 5290ebd3ff1SAnirudh Venkataramanan u8 prio_table[ICE_MAX_TRAFFIC_CLASS]; 5300ebd3ff1SAnirudh Venkataramanan u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS]; 5310ebd3ff1SAnirudh Venkataramanan u8 tsatable[ICE_MAX_TRAFFIC_CLASS]; 5320ebd3ff1SAnirudh Venkataramanan }; 5330ebd3ff1SAnirudh Venkataramanan 5340ebd3ff1SAnirudh Venkataramanan /* CEE or IEEE 802.1Qaz PFC Configuration data */ 5350ebd3ff1SAnirudh Venkataramanan struct ice_dcb_pfc_cfg { 5360ebd3ff1SAnirudh Venkataramanan u8 willing; 5370ebd3ff1SAnirudh Venkataramanan u8 mbc; 5380ebd3ff1SAnirudh Venkataramanan u8 pfccap; 5390ebd3ff1SAnirudh Venkataramanan u8 pfcena; 5400ebd3ff1SAnirudh Venkataramanan }; 5410ebd3ff1SAnirudh Venkataramanan 5420ebd3ff1SAnirudh Venkataramanan /* CEE or IEEE 802.1Qaz Application Priority data */ 5430ebd3ff1SAnirudh Venkataramanan struct ice_dcb_app_priority_table { 5440ebd3ff1SAnirudh Venkataramanan u16 prot_id; 5450ebd3ff1SAnirudh Venkataramanan u8 priority; 5460ebd3ff1SAnirudh Venkataramanan u8 selector; 5470ebd3ff1SAnirudh Venkataramanan }; 5480ebd3ff1SAnirudh Venkataramanan 5490ebd3ff1SAnirudh Venkataramanan #define ICE_MAX_USER_PRIORITY 8 5500ebd3ff1SAnirudh Venkataramanan #define ICE_DCBX_MAX_APPS 32 5510ebd3ff1SAnirudh Venkataramanan #define ICE_LLDPDU_SIZE 1500 5520ebd3ff1SAnirudh Venkataramanan #define ICE_TLV_STATUS_OPER 0x1 5530ebd3ff1SAnirudh Venkataramanan #define ICE_TLV_STATUS_SYNC 0x2 5540ebd3ff1SAnirudh Venkataramanan #define ICE_TLV_STATUS_ERR 0x4 555aeac8ce8SChinh T Cao #define ICE_APP_PROT_ID_ISCSI_860 0x035c 5560ebd3ff1SAnirudh Venkataramanan #define ICE_APP_SEL_ETHTYPE 0x1 5570ebd3ff1SAnirudh Venkataramanan #define ICE_APP_SEL_TCPIP 0x2 5580ebd3ff1SAnirudh Venkataramanan #define ICE_CEE_APP_SEL_ETHTYPE 0x0 559ea78ce4dSPaul Greenwalt #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134 5600ebd3ff1SAnirudh Venkataramanan #define ICE_CEE_APP_SEL_TCPIP 0x1 5610ebd3ff1SAnirudh Venkataramanan 5620ebd3ff1SAnirudh Venkataramanan struct ice_dcbx_cfg { 5630ebd3ff1SAnirudh Venkataramanan u32 numapps; 5640ebd3ff1SAnirudh Venkataramanan u32 tlv_status; /* CEE mode TLV status */ 5650ebd3ff1SAnirudh Venkataramanan struct ice_dcb_ets_cfg etscfg; 5660ebd3ff1SAnirudh Venkataramanan struct ice_dcb_ets_cfg etsrec; 5670ebd3ff1SAnirudh Venkataramanan struct ice_dcb_pfc_cfg pfc; 5680ebd3ff1SAnirudh Venkataramanan struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS]; 5690ebd3ff1SAnirudh Venkataramanan u8 dcbx_mode; 5700ebd3ff1SAnirudh Venkataramanan #define ICE_DCBX_MODE_CEE 0x1 5710ebd3ff1SAnirudh Venkataramanan #define ICE_DCBX_MODE_IEEE 0x2 5720ebd3ff1SAnirudh Venkataramanan u8 app_mode; 5730ebd3ff1SAnirudh Venkataramanan #define ICE_DCBX_APPS_NON_WILLING 0x1 5740ebd3ff1SAnirudh Venkataramanan }; 5750ebd3ff1SAnirudh Venkataramanan 576fc2d1165SChinh T Cao struct ice_qos_cfg { 577fc2d1165SChinh T Cao struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */ 578fc2d1165SChinh T Cao struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */ 579fc2d1165SChinh T Cao struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */ 580fc2d1165SChinh T Cao u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */ 581fc2d1165SChinh T Cao u8 is_sw_lldp : 1; 582fc2d1165SChinh T Cao }; 583fc2d1165SChinh T Cao 5849c20346bSAnirudh Venkataramanan struct ice_port_info { 5859c20346bSAnirudh Venkataramanan struct ice_sched_node *root; /* Root Node per Port */ 586f9867df6SAnirudh Venkataramanan struct ice_hw *hw; /* back pointer to HW instance */ 587dc49c772SAnirudh Venkataramanan u32 last_node_teid; /* scheduler last node info */ 5889c20346bSAnirudh Venkataramanan u16 sw_id; /* Initial switch ID belongs to port */ 5899c20346bSAnirudh Venkataramanan u16 pf_vf_num; 5909c20346bSAnirudh Venkataramanan u8 port_state; 5919c20346bSAnirudh Venkataramanan #define ICE_SCHED_PORT_STATE_INIT 0x0 5929c20346bSAnirudh Venkataramanan #define ICE_SCHED_PORT_STATE_READY 0x1 5930437f1a9SJesse Brandeburg u8 lport; 5940437f1a9SJesse Brandeburg #define ICE_LPORT_MASK 0xff 595e94d4478SAnirudh Venkataramanan u16 dflt_tx_vsi_rule_id; 5969c20346bSAnirudh Venkataramanan u16 dflt_tx_vsi_num; 597e94d4478SAnirudh Venkataramanan u16 dflt_rx_vsi_rule_id; 5989c20346bSAnirudh Venkataramanan u16 dflt_rx_vsi_num; 599dc49c772SAnirudh Venkataramanan struct ice_fc_info fc; 600dc49c772SAnirudh Venkataramanan struct ice_mac_info mac; 601dc49c772SAnirudh Venkataramanan struct ice_phy_info phy; 6029c20346bSAnirudh Venkataramanan struct mutex sched_lock; /* protect access to TXSched tree */ 60329358248SVictor Raj struct ice_sched_node * 60429358248SVictor Raj sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM]; 6051ddef455SUsha Ketineni /* List contain profile ID(s) and other params per layer */ 6061ddef455SUsha Ketineni struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 607fc2d1165SChinh T Cao struct ice_qos_cfg qos_cfg; 6080437f1a9SJesse Brandeburg u8 is_vf:1; 6099c20346bSAnirudh Venkataramanan }; 6109c20346bSAnirudh Venkataramanan 6119daf8208SAnirudh Venkataramanan struct ice_switch_info { 6129daf8208SAnirudh Venkataramanan struct list_head vsi_list_map_head; 61380d144c9SAnirudh Venkataramanan struct ice_sw_recipe *recp_list; 6149daf8208SAnirudh Venkataramanan }; 6159daf8208SAnirudh Venkataramanan 6168b97ceb1SHieu Tran /* FW logging configuration */ 6178b97ceb1SHieu Tran struct ice_fw_log_evnt { 6188b97ceb1SHieu Tran u8 cfg : 4; /* New event enables to configure */ 6198b97ceb1SHieu Tran u8 cur : 4; /* Current/active event enables */ 6208b97ceb1SHieu Tran }; 6218b97ceb1SHieu Tran 6228b97ceb1SHieu Tran struct ice_fw_log_cfg { 6238b97ceb1SHieu Tran u8 cq_en : 1; /* FW logging is enabled via the control queue */ 6248b97ceb1SHieu Tran u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */ 6258b97ceb1SHieu Tran u8 actv_evnts; /* Cumulation of currently enabled log events */ 6268b97ceb1SHieu Tran 6278b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S) 6288b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S) 6298b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S) 6308b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S) 6318b97ceb1SHieu Tran struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX]; 6328b97ceb1SHieu Tran }; 6338b97ceb1SHieu Tran 6340891c896SVignesh Sridhar /* Enum defining the different states of the mailbox snapshot in the 6350891c896SVignesh Sridhar * PF-VF mailbox overflow detection algorithm. The snapshot can be in 6360891c896SVignesh Sridhar * states: 6370891c896SVignesh Sridhar * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot 6380891c896SVignesh Sridhar * within the mailbox buffer. 6390891c896SVignesh Sridhar * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot 6400891c896SVignesh Sridhar * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the 6410891c896SVignesh Sridhar * mailbox and mark any VFs sending more messages than the threshold limit set. 6420891c896SVignesh Sridhar * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF. 6430891c896SVignesh Sridhar */ 6440891c896SVignesh Sridhar enum ice_mbx_snapshot_state { 6450891c896SVignesh Sridhar ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0, 6460891c896SVignesh Sridhar ICE_MAL_VF_DETECT_STATE_TRAVERSE, 6470891c896SVignesh Sridhar ICE_MAL_VF_DETECT_STATE_DETECT, 6480891c896SVignesh Sridhar ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF, 6490891c896SVignesh Sridhar }; 6500891c896SVignesh Sridhar 6510891c896SVignesh Sridhar /* Structure to hold information of the static snapshot and the mailbox 6520891c896SVignesh Sridhar * buffer data used to generate and track the snapshot. 6530891c896SVignesh Sridhar * 1. state: the state of the mailbox snapshot in the malicious VF 6540891c896SVignesh Sridhar * detection state handler ice_mbx_vf_state_handler() 6550891c896SVignesh Sridhar * 2. head: head of the mailbox snapshot in a circular mailbox buffer 6560891c896SVignesh Sridhar * 3. tail: tail of the mailbox snapshot in a circular mailbox buffer 6570891c896SVignesh Sridhar * 4. num_iterations: number of messages traversed in circular mailbox buffer 6580891c896SVignesh Sridhar * 5. num_msg_proc: number of messages processed in mailbox 6590891c896SVignesh Sridhar * 6. num_pending_arq: number of pending asynchronous messages 6600891c896SVignesh Sridhar * 7. max_num_msgs_mbx: maximum messages in mailbox for currently 6610891c896SVignesh Sridhar * serviced work item or interrupt. 6620891c896SVignesh Sridhar */ 6630891c896SVignesh Sridhar struct ice_mbx_snap_buffer_data { 6640891c896SVignesh Sridhar enum ice_mbx_snapshot_state state; 6650891c896SVignesh Sridhar u32 head; 6660891c896SVignesh Sridhar u32 tail; 6670891c896SVignesh Sridhar u32 num_iterations; 6680891c896SVignesh Sridhar u16 num_msg_proc; 6690891c896SVignesh Sridhar u16 num_pending_arq; 6700891c896SVignesh Sridhar u16 max_num_msgs_mbx; 6710891c896SVignesh Sridhar }; 6720891c896SVignesh Sridhar 6730891c896SVignesh Sridhar /* Structure to track messages sent by VFs on mailbox: 6740891c896SVignesh Sridhar * 1. vf_cntr: a counter array of VFs to track the number of 6750891c896SVignesh Sridhar * asynchronous messages sent by each VF 6760891c896SVignesh Sridhar * 2. vfcntr_len: number of entries in VF counter array 6770891c896SVignesh Sridhar */ 6780891c896SVignesh Sridhar struct ice_mbx_vf_counter { 6790891c896SVignesh Sridhar u32 *vf_cntr; 6800891c896SVignesh Sridhar u32 vfcntr_len; 6810891c896SVignesh Sridhar }; 6820891c896SVignesh Sridhar 6830891c896SVignesh Sridhar /* Structure to hold data relevant to the captured static snapshot 6840891c896SVignesh Sridhar * of the PF-VF mailbox. 6850891c896SVignesh Sridhar */ 6860891c896SVignesh Sridhar struct ice_mbx_snapshot { 6870891c896SVignesh Sridhar struct ice_mbx_snap_buffer_data mbx_buf; 6880891c896SVignesh Sridhar struct ice_mbx_vf_counter mbx_vf; 6890891c896SVignesh Sridhar }; 6900891c896SVignesh Sridhar 6910891c896SVignesh Sridhar /* Structure to hold data to be used for capturing or updating a 6920891c896SVignesh Sridhar * static snapshot. 6930891c896SVignesh Sridhar * 1. num_msg_proc: number of messages processed in mailbox 6940891c896SVignesh Sridhar * 2. num_pending_arq: number of pending asynchronous messages 6950891c896SVignesh Sridhar * 3. max_num_msgs_mbx: maximum messages in mailbox for currently 6960891c896SVignesh Sridhar * serviced work item or interrupt. 6970891c896SVignesh Sridhar * 4. async_watermark_val: An upper threshold set by caller to determine 6980891c896SVignesh Sridhar * if the pending arq count is large enough to assume that there is 6990891c896SVignesh Sridhar * the possibility of a mailicious VF. 7000891c896SVignesh Sridhar */ 7010891c896SVignesh Sridhar struct ice_mbx_data { 7020891c896SVignesh Sridhar u16 num_msg_proc; 7030891c896SVignesh Sridhar u16 num_pending_arq; 7040891c896SVignesh Sridhar u16 max_num_msgs_mbx; 7050891c896SVignesh Sridhar u16 async_watermark_val; 7060891c896SVignesh Sridhar }; 7070891c896SVignesh Sridhar 708837f08fdSAnirudh Venkataramanan /* Port hardware description */ 709837f08fdSAnirudh Venkataramanan struct ice_hw { 710837f08fdSAnirudh Venkataramanan u8 __iomem *hw_addr; 711837f08fdSAnirudh Venkataramanan void *back; 7129c20346bSAnirudh Venkataramanan struct ice_aqc_layer_props *layer_info; 7139c20346bSAnirudh Venkataramanan struct ice_port_info *port_info; 7144f8a1497SBen Shelton /* PSM clock frequency for calculating RL profile params */ 7154f8a1497SBen Shelton u32 psm_clk_freq; 7167ec59eeaSAnirudh Venkataramanan u64 debug_mask; /* bitmap for debug mask */ 717f31e4b6fSAnirudh Venkataramanan enum ice_mac_type mac_type; 718837f08fdSAnirudh Venkataramanan 719148beb61SHenry Tieman u16 fd_ctr_base; /* FD counter base index */ 720148beb61SHenry Tieman 721837f08fdSAnirudh Venkataramanan /* pci info */ 722837f08fdSAnirudh Venkataramanan u16 device_id; 723837f08fdSAnirudh Venkataramanan u16 vendor_id; 724837f08fdSAnirudh Venkataramanan u16 subsystem_device_id; 725837f08fdSAnirudh Venkataramanan u16 subsystem_vendor_id; 726837f08fdSAnirudh Venkataramanan u8 revision_id; 727837f08fdSAnirudh Venkataramanan 728f31e4b6fSAnirudh Venkataramanan u8 pf_id; /* device profile info */ 729f31e4b6fSAnirudh Venkataramanan 7301ddef455SUsha Ketineni u16 max_burst_size; /* driver sets this value */ 7311ddef455SUsha Ketineni 732f9867df6SAnirudh Venkataramanan /* Tx Scheduler values */ 73388865fc4SKarol Kolacinski u8 num_tx_sched_layers; 73488865fc4SKarol Kolacinski u8 num_tx_sched_phys_layers; 7359c20346bSAnirudh Venkataramanan u8 flattened_layers; 7369c20346bSAnirudh Venkataramanan u8 max_cgds; 7379c20346bSAnirudh Venkataramanan u8 sw_entry_point_layer; 738b36c598cSAnirudh Venkataramanan u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 7399be1d6f8SAnirudh Venkataramanan struct list_head agg_list; /* lists all aggregator */ 7409c20346bSAnirudh Venkataramanan 7410f9d5027SAnirudh Venkataramanan struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI]; 74243f8b224SBruce Allan u8 evb_veb; /* true for VEB, false for VEPA */ 743f9867df6SAnirudh Venkataramanan u8 reset_ongoing; /* true if HW is in reset, false otherwise */ 744837f08fdSAnirudh Venkataramanan struct ice_bus_info bus; 7459af368faSJacob Keller struct ice_flash_info flash; 7469c20346bSAnirudh Venkataramanan struct ice_hw_dev_caps dev_caps; /* device capabilities */ 7479c20346bSAnirudh Venkataramanan struct ice_hw_func_caps func_caps; /* function capabilities */ 748f31e4b6fSAnirudh Venkataramanan 7499daf8208SAnirudh Venkataramanan struct ice_switch_info *switch_info; /* switch filter lists */ 7509daf8208SAnirudh Venkataramanan 7517ec59eeaSAnirudh Venkataramanan /* Control Queue info */ 7527ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_info adminq; 75375d2b253SAnirudh Venkataramanan struct ice_ctl_q_info mailboxq; 7547ec59eeaSAnirudh Venkataramanan 7557ec59eeaSAnirudh Venkataramanan u8 api_branch; /* API branch version */ 7567ec59eeaSAnirudh Venkataramanan u8 api_maj_ver; /* API major version */ 7577ec59eeaSAnirudh Venkataramanan u8 api_min_ver; /* API minor version */ 7587ec59eeaSAnirudh Venkataramanan u8 api_patch; /* API patch version */ 7597ec59eeaSAnirudh Venkataramanan u8 fw_branch; /* firmware branch version */ 7607ec59eeaSAnirudh Venkataramanan u8 fw_maj_ver; /* firmware major version */ 7617ec59eeaSAnirudh Venkataramanan u8 fw_min_ver; /* firmware minor version */ 7627ec59eeaSAnirudh Venkataramanan u8 fw_patch; /* firmware patch version */ 7637ec59eeaSAnirudh Venkataramanan u32 fw_build; /* firmware build number */ 764940b61afSAnirudh Venkataramanan 7658b97ceb1SHieu Tran struct ice_fw_log_cfg fw_log; 7669e4ab4c2SBrett Creeley 7679e4ab4c2SBrett Creeley /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL 7684ee656bbSTony Nguyen * register. Used for determining the ITR/INTRL granularity during 7699e4ab4c2SBrett Creeley * initialization. 7709e4ab4c2SBrett Creeley */ 7719e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_200G 0x0 7729e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_100G 0X1 7739e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_50G 0x2 7749e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_25G 0x3 7759e4ab4c2SBrett Creeley /* ITR granularity for different speeds */ 7769e4ab4c2SBrett Creeley #define ICE_ITR_GRAN_ABOVE_25 2 7779e4ab4c2SBrett Creeley #define ICE_ITR_GRAN_MAX_25 4 778940b61afSAnirudh Venkataramanan /* ITR granularity in 1 us */ 7799e4ab4c2SBrett Creeley u8 itr_gran; 7809e4ab4c2SBrett Creeley /* INTRL granularity for different speeds */ 7819e4ab4c2SBrett Creeley #define ICE_INTRL_GRAN_ABOVE_25 4 7829e4ab4c2SBrett Creeley #define ICE_INTRL_GRAN_MAX_25 8 7839e4ab4c2SBrett Creeley /* INTRL granularity in 1 us */ 7849e4ab4c2SBrett Creeley u8 intrl_gran; 7859e4ab4c2SBrett Creeley 78643f8b224SBruce Allan u8 ucast_shared; /* true if VSIs can share unicast addr */ 7879daf8208SAnirudh Venkataramanan 788c7648810STony Nguyen /* Active package version (currently active) */ 789c7648810STony Nguyen struct ice_pkg_ver active_pkg_ver; 790b8272919SVictor Raj u32 active_track_id; 791c7648810STony Nguyen u8 active_pkg_name[ICE_PKG_NAME_SIZE]; 792c7648810STony Nguyen u8 active_pkg_in_nvm; 793c7648810STony Nguyen 794c7648810STony Nguyen enum ice_aq_err pkg_dwnld_status; 795c7648810STony Nguyen 796a05983c3SDan Nowlin /* Driver's package ver - (from the Ice Metadata section) */ 797c7648810STony Nguyen struct ice_pkg_ver pkg_ver; 798c7648810STony Nguyen u8 pkg_name[ICE_PKG_NAME_SIZE]; 799c7648810STony Nguyen 800a05983c3SDan Nowlin /* Driver's Ice segment format version and ID (from the Ice seg) */ 801a05983c3SDan Nowlin struct ice_pkg_ver ice_seg_fmt_ver; 802a05983c3SDan Nowlin u8 ice_seg_id[ICE_SEG_ID_SIZE]; 803c7648810STony Nguyen 804c7648810STony Nguyen /* Pointer to the ice segment */ 805c7648810STony Nguyen struct ice_seg *seg; 806c7648810STony Nguyen 807c7648810STony Nguyen /* Pointer to allocated copy of pkg memory */ 808c7648810STony Nguyen u8 *pkg_copy; 809c7648810STony Nguyen u32 pkg_size; 810c7648810STony Nguyen 811a4e82a81STony Nguyen /* tunneling info */ 812a4e82a81STony Nguyen struct mutex tnl_lock; 813a4e82a81STony Nguyen struct ice_tunnel_table tnl; 814a4e82a81STony Nguyen 815b20e6c17SJakub Kicinski struct udp_tunnel_nic_shared udp_tunnel_shared; 816b20e6c17SJakub Kicinski struct udp_tunnel_nic_info udp_tunnel_nic; 817b20e6c17SJakub Kicinski 818c7648810STony Nguyen /* HW block tables */ 819c7648810STony Nguyen struct ice_blk_info blk[ICE_BLK_COUNT]; 820c90ed40cSTony Nguyen struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */ 821c90ed40cSTony Nguyen struct list_head fl_profs[ICE_BLK_COUNT]; 822148beb61SHenry Tieman 823148beb61SHenry Tieman /* Flow Director filter info */ 824148beb61SHenry Tieman int fdir_active_fltr; 825148beb61SHenry Tieman 826148beb61SHenry Tieman struct mutex fdir_fltr_lock; /* protect Flow Director */ 827148beb61SHenry Tieman struct list_head fdir_list_head; 828148beb61SHenry Tieman 829cac2a27cSHenry Tieman /* Book-keeping of side-band filter count per flow-type. 830cac2a27cSHenry Tieman * This is used to detect and handle input set changes for 831cac2a27cSHenry Tieman * respective flow-type. 832cac2a27cSHenry Tieman */ 833cac2a27cSHenry Tieman u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX]; 834cac2a27cSHenry Tieman 835148beb61SHenry Tieman struct ice_fd_hw_prof **fdir_prof; 836148beb61SHenry Tieman DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX); 837c90ed40cSTony Nguyen struct mutex rss_locks; /* protect RSS configuration */ 838c90ed40cSTony Nguyen struct list_head rss_list_head; 8390891c896SVignesh Sridhar struct ice_mbx_snapshot mbx_snapshot; 840837f08fdSAnirudh Venkataramanan }; 841837f08fdSAnirudh Venkataramanan 842fcea6f3dSAnirudh Venkataramanan /* Statistics collected by each port, VSI, VEB, and S-channel */ 843fcea6f3dSAnirudh Venkataramanan struct ice_eth_stats { 844fcea6f3dSAnirudh Venkataramanan u64 rx_bytes; /* gorc */ 845fcea6f3dSAnirudh Venkataramanan u64 rx_unicast; /* uprc */ 846fcea6f3dSAnirudh Venkataramanan u64 rx_multicast; /* mprc */ 847fcea6f3dSAnirudh Venkataramanan u64 rx_broadcast; /* bprc */ 848fcea6f3dSAnirudh Venkataramanan u64 rx_discards; /* rdpc */ 849fcea6f3dSAnirudh Venkataramanan u64 rx_unknown_protocol; /* rupp */ 850fcea6f3dSAnirudh Venkataramanan u64 tx_bytes; /* gotc */ 851fcea6f3dSAnirudh Venkataramanan u64 tx_unicast; /* uptc */ 852fcea6f3dSAnirudh Venkataramanan u64 tx_multicast; /* mptc */ 853fcea6f3dSAnirudh Venkataramanan u64 tx_broadcast; /* bptc */ 854fcea6f3dSAnirudh Venkataramanan u64 tx_discards; /* tdpc */ 855fcea6f3dSAnirudh Venkataramanan u64 tx_errors; /* tepc */ 856fcea6f3dSAnirudh Venkataramanan }; 857fcea6f3dSAnirudh Venkataramanan 858610ed0e9SAvinash JD #define ICE_MAX_UP 8 859610ed0e9SAvinash JD 860fcea6f3dSAnirudh Venkataramanan /* Statistics collected by the MAC */ 861fcea6f3dSAnirudh Venkataramanan struct ice_hw_port_stats { 862fcea6f3dSAnirudh Venkataramanan /* eth stats collected by the port */ 863fcea6f3dSAnirudh Venkataramanan struct ice_eth_stats eth; 864fcea6f3dSAnirudh Venkataramanan /* additional port specific stats */ 865fcea6f3dSAnirudh Venkataramanan u64 tx_dropped_link_down; /* tdold */ 866fcea6f3dSAnirudh Venkataramanan u64 crc_errors; /* crcerrs */ 867fcea6f3dSAnirudh Venkataramanan u64 illegal_bytes; /* illerrc */ 868fcea6f3dSAnirudh Venkataramanan u64 error_bytes; /* errbc */ 869fcea6f3dSAnirudh Venkataramanan u64 mac_local_faults; /* mlfc */ 870fcea6f3dSAnirudh Venkataramanan u64 mac_remote_faults; /* mrfc */ 871fcea6f3dSAnirudh Venkataramanan u64 rx_len_errors; /* rlec */ 872fcea6f3dSAnirudh Venkataramanan u64 link_xon_rx; /* lxonrxc */ 873fcea6f3dSAnirudh Venkataramanan u64 link_xoff_rx; /* lxoffrxc */ 874fcea6f3dSAnirudh Venkataramanan u64 link_xon_tx; /* lxontxc */ 875fcea6f3dSAnirudh Venkataramanan u64 link_xoff_tx; /* lxofftxc */ 8764b0fdcebSAnirudh Venkataramanan u64 priority_xon_rx[8]; /* pxonrxc[8] */ 8774b0fdcebSAnirudh Venkataramanan u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 8784b0fdcebSAnirudh Venkataramanan u64 priority_xon_tx[8]; /* pxontxc[8] */ 8794b0fdcebSAnirudh Venkataramanan u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 8804b0fdcebSAnirudh Venkataramanan u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 881fcea6f3dSAnirudh Venkataramanan u64 rx_size_64; /* prc64 */ 882fcea6f3dSAnirudh Venkataramanan u64 rx_size_127; /* prc127 */ 883fcea6f3dSAnirudh Venkataramanan u64 rx_size_255; /* prc255 */ 884fcea6f3dSAnirudh Venkataramanan u64 rx_size_511; /* prc511 */ 885fcea6f3dSAnirudh Venkataramanan u64 rx_size_1023; /* prc1023 */ 886fcea6f3dSAnirudh Venkataramanan u64 rx_size_1522; /* prc1522 */ 887fcea6f3dSAnirudh Venkataramanan u64 rx_size_big; /* prc9522 */ 888fcea6f3dSAnirudh Venkataramanan u64 rx_undersize; /* ruc */ 889fcea6f3dSAnirudh Venkataramanan u64 rx_fragments; /* rfc */ 890fcea6f3dSAnirudh Venkataramanan u64 rx_oversize; /* roc */ 891fcea6f3dSAnirudh Venkataramanan u64 rx_jabber; /* rjc */ 892fcea6f3dSAnirudh Venkataramanan u64 tx_size_64; /* ptc64 */ 893fcea6f3dSAnirudh Venkataramanan u64 tx_size_127; /* ptc127 */ 894fcea6f3dSAnirudh Venkataramanan u64 tx_size_255; /* ptc255 */ 895fcea6f3dSAnirudh Venkataramanan u64 tx_size_511; /* ptc511 */ 896fcea6f3dSAnirudh Venkataramanan u64 tx_size_1023; /* ptc1023 */ 897fcea6f3dSAnirudh Venkataramanan u64 tx_size_1522; /* ptc1522 */ 898fcea6f3dSAnirudh Venkataramanan u64 tx_size_big; /* ptc9522 */ 8994ab95646SHenry Tieman /* flow director stats */ 9004ab95646SHenry Tieman u32 fd_sb_status; 9014ab95646SHenry Tieman u64 fd_sb_match; 902fcea6f3dSAnirudh Venkataramanan }; 903fcea6f3dSAnirudh Venkataramanan 904e3c53928SBrett Creeley struct ice_aq_get_set_rss_lut_params { 905e3c53928SBrett Creeley u16 vsi_handle; /* software VSI handle */ 906e3c53928SBrett Creeley u16 lut_size; /* size of the LUT buffer */ 907e3c53928SBrett Creeley u8 lut_type; /* type of the LUT (i.e. VSI, PF, Global) */ 908e3c53928SBrett Creeley u8 *lut; /* input RSS LUT for set and output RSS LUT for get */ 909e3c53928SBrett Creeley u8 global_lut_id; /* only valid when lut_type is global */ 910e3c53928SBrett Creeley }; 911e3c53928SBrett Creeley 912f31e4b6fSAnirudh Venkataramanan /* Checksum and Shadow RAM pointers */ 9131fa95e01SJacob Keller #define ICE_SR_NVM_CTRL_WORD 0x00 914031f2147SMd Fahad Iqbal Polash #define ICE_SR_BOOT_CFG_PTR 0x132 915769c500dSAkeem G Abodunrin #define ICE_SR_NVM_WOL_CFG 0x19 916d4e87444SJacob Keller #define ICE_NVM_OROM_VER_OFF 0x02 917e961b679SJacob Keller #define ICE_SR_PBA_BLOCK_PTR 0x16 918f31e4b6fSAnirudh Venkataramanan #define ICE_SR_NVM_DEV_STARTER_VER 0x18 919f31e4b6fSAnirudh Venkataramanan #define ICE_SR_NVM_EETRACK_LO 0x2D 920f31e4b6fSAnirudh Venkataramanan #define ICE_SR_NVM_EETRACK_HI 0x2E 921fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_LO_SHIFT 0 922fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT) 923fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_HI_SHIFT 12 924fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT) 925d4e87444SJacob Keller #define ICE_OROM_VER_PATCH_SHIFT 0 926d4e87444SJacob Keller #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT) 927d4e87444SJacob Keller #define ICE_OROM_VER_BUILD_SHIFT 8 928d4e87444SJacob Keller #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT) 929d4e87444SJacob Keller #define ICE_OROM_VER_SHIFT 24 930d4e87444SJacob Keller #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT) 931031f2147SMd Fahad Iqbal Polash #define ICE_SR_PFA_PTR 0x40 932544cd2acSCudzilo, Szymon T #define ICE_SR_1ST_NVM_BANK_PTR 0x42 9331fa95e01SJacob Keller #define ICE_SR_NVM_BANK_SIZE 0x43 934544cd2acSCudzilo, Szymon T #define ICE_SR_1ST_OROM_BANK_PTR 0x44 9351fa95e01SJacob Keller #define ICE_SR_OROM_BANK_SIZE 0x45 936544cd2acSCudzilo, Szymon T #define ICE_SR_NETLIST_BANK_PTR 0x46 9371fa95e01SJacob Keller #define ICE_SR_NETLIST_BANK_SIZE 0x47 938f31e4b6fSAnirudh Venkataramanan #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800 939ea78ce4dSPaul Greenwalt 9400ce50c70SJacob Keller /* CSS Header words */ 9410ce50c70SJacob Keller #define ICE_NVM_CSS_SREV_L 0x14 9420ce50c70SJacob Keller #define ICE_NVM_CSS_SREV_H 0x15 9430ce50c70SJacob Keller 9440ce50c70SJacob Keller /* Length of CSS header section in words */ 9450ce50c70SJacob Keller #define ICE_CSS_HEADER_LENGTH 330 9460ce50c70SJacob Keller 9470ce50c70SJacob Keller /* Offset of Shadow RAM copy in the NVM bank area. */ 9480ce50c70SJacob Keller #define ICE_NVM_SR_COPY_WORD_OFFSET roundup(ICE_CSS_HEADER_LENGTH, 32) 9490ce50c70SJacob Keller 9500ce50c70SJacob Keller /* Size in bytes of Option ROM trailer */ 9510ce50c70SJacob Keller #define ICE_NVM_OROM_TRAILER_LENGTH (2 * ICE_CSS_HEADER_LENGTH) 9520ce50c70SJacob Keller 953e120a9abSJacob Keller /* The Link Topology Netlist section is stored as a series of words. It is 954e120a9abSJacob Keller * stored in the NVM as a TLV, with the first two words containing the type 955e120a9abSJacob Keller * and length. 956e120a9abSJacob Keller */ 957e120a9abSJacob Keller #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B 958e120a9abSJacob Keller #define ICE_NETLIST_TYPE_OFFSET 0x0000 959e120a9abSJacob Keller #define ICE_NETLIST_LEN_OFFSET 0x0001 960e120a9abSJacob Keller 961e120a9abSJacob Keller /* The Link Topology section follows the TLV header. When reading the netlist 962e120a9abSJacob Keller * using ice_read_netlist_module, we need to account for the 2-word TLV 963e120a9abSJacob Keller * header. 964e120a9abSJacob Keller */ 965e120a9abSJacob Keller #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2) 966e120a9abSJacob Keller 967e120a9abSJacob Keller #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000) 968e120a9abSJacob Keller #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001) 969e120a9abSJacob Keller 970e120a9abSJacob Keller #define ICE_LINK_TOPO_NODE_COUNT_M ICE_M(0x3FF, 0) 971e120a9abSJacob Keller 972e120a9abSJacob Keller /* The Netlist ID Block is located after all of the Link Topology nodes. */ 973e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_SIZE 0x30 974e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n)) 975e120a9abSJacob Keller 976e120a9abSJacob Keller /* netlist ID block field offsets (word offsets) */ 977e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02 978e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03 979e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04 980e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05 981e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06 982e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07 983e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_REV_LOW 0x08 984e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09 985e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n)) 986e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F 987e120a9abSJacob Keller 9881fa95e01SJacob Keller /* Auxiliary field, mask, and shift definition for Shadow RAM and NVM Flash */ 9891fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_1_S 0x06 9901fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S) 9911fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_VALID 0x1 9921fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3) 9931fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4) 9941fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5) 9951fa95e01SJacob Keller 9961fa95e01SJacob Keller #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15) 9971fa95e01SJacob Keller 998ea78ce4dSPaul Greenwalt /* Link override related */ 999ea78ce4dSPaul Greenwalt #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10 1000ea78ce4dSPaul Greenwalt #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4 1001ea78ce4dSPaul Greenwalt #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2 1002ea78ce4dSPaul Greenwalt #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1 1003ea78ce4dSPaul Greenwalt #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2 1004ea78ce4dSPaul Greenwalt #define ICE_FW_API_LINK_OVERRIDE_MAJ 1 1005ea78ce4dSPaul Greenwalt #define ICE_FW_API_LINK_OVERRIDE_MIN 5 1006ea78ce4dSPaul Greenwalt #define ICE_FW_API_LINK_OVERRIDE_PATCH 2 1007ea78ce4dSPaul Greenwalt 1008f31e4b6fSAnirudh Venkataramanan #define ICE_SR_WORDS_IN_1KB 512 1009f31e4b6fSAnirudh Venkataramanan 10108ede0178SAnirudh Venkataramanan /* Hash redirection LUT for VSI - maximum array size */ 10118ede0178SAnirudh Venkataramanan #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4) 10128ede0178SAnirudh Venkataramanan 101334295a36SDave Ertman /* AQ API version for LLDP_FILTER_CONTROL */ 101434295a36SDave Ertman #define ICE_FW_API_LLDP_FLTR_MAJ 1 101534295a36SDave Ertman #define ICE_FW_API_LLDP_FLTR_MIN 7 101634295a36SDave Ertman #define ICE_FW_API_LLDP_FLTR_PATCH 1 101734295a36SDave Ertman 10180a02944fSAnirudh Venkataramanan /* AQ API version for report default configuration */ 10190a02944fSAnirudh Venkataramanan #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1 10200a02944fSAnirudh Venkataramanan #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7 10210a02944fSAnirudh Venkataramanan #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3 10220a02944fSAnirudh Venkataramanan 1023837f08fdSAnirudh Venkataramanan #endif /* _ICE_TYPE_H_ */ 1024