1837f08fdSAnirudh Venkataramanan /* SPDX-License-Identifier: GPL-2.0 */ 2837f08fdSAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */ 3837f08fdSAnirudh Venkataramanan 4837f08fdSAnirudh Venkataramanan #ifndef _ICE_TYPE_H_ 5837f08fdSAnirudh Venkataramanan #define _ICE_TYPE_H_ 6837f08fdSAnirudh Venkataramanan 76a025730STony Nguyen #define ICE_BYTES_PER_WORD 2 86a025730STony Nguyen #define ICE_BYTES_PER_DWORD 4 96a025730STony Nguyen 107ec59eeaSAnirudh Venkataramanan #include "ice_status.h" 117ec59eeaSAnirudh Venkataramanan #include "ice_hw_autogen.h" 127ec59eeaSAnirudh Venkataramanan #include "ice_osdep.h" 137ec59eeaSAnirudh Venkataramanan #include "ice_controlq.h" 14cdedef59SAnirudh Venkataramanan #include "ice_lan_tx_rx.h" 157ec59eeaSAnirudh Venkataramanan 1635b4f437SJacob Keller static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc) 175513b920SAnirudh Venkataramanan { 1835b4f437SJacob Keller return test_bit(tc, &bitmap); 195513b920SAnirudh Venkataramanan } 205513b920SAnirudh Venkataramanan 21334cb062SAnirudh Venkataramanan /* Driver always calls main vsi_handle first */ 22334cb062SAnirudh Venkataramanan #define ICE_MAIN_VSI_HANDLE 0 23334cb062SAnirudh Venkataramanan 247ec59eeaSAnirudh Venkataramanan /* debug masks - set these bits in hw->debug_mask to control output */ 25f31e4b6fSAnirudh Venkataramanan #define ICE_DBG_INIT BIT_ULL(1) 264f70daa0SJacob Keller #define ICE_DBG_FW_LOG BIT_ULL(3) 270b28b702SAnirudh Venkataramanan #define ICE_DBG_LINK BIT_ULL(4) 28d8df260aSChinh T Cao #define ICE_DBG_PHY BIT_ULL(5) 29cdedef59SAnirudh Venkataramanan #define ICE_DBG_QCTX BIT_ULL(6) 30f31e4b6fSAnirudh Venkataramanan #define ICE_DBG_NVM BIT_ULL(7) 31dc49c772SAnirudh Venkataramanan #define ICE_DBG_LAN BIT_ULL(8) 329c20346bSAnirudh Venkataramanan #define ICE_DBG_SW BIT_ULL(13) 339c20346bSAnirudh Venkataramanan #define ICE_DBG_SCHED BIT_ULL(14) 34f31e4b6fSAnirudh Venkataramanan #define ICE_DBG_RES BIT_ULL(17) 357ec59eeaSAnirudh Venkataramanan #define ICE_DBG_AQ_MSG BIT_ULL(24) 367ec59eeaSAnirudh Venkataramanan #define ICE_DBG_AQ_CMD BIT_ULL(27) 37fcea6f3dSAnirudh Venkataramanan #define ICE_DBG_USER BIT_ULL(31) 387ec59eeaSAnirudh Venkataramanan 39f31e4b6fSAnirudh Venkataramanan enum ice_aq_res_ids { 40f31e4b6fSAnirudh Venkataramanan ICE_NVM_RES_ID = 1, 41f31e4b6fSAnirudh Venkataramanan ICE_SPD_RES_ID, 42ff2b1321SDan Nowlin ICE_CHANGE_LOCK_RES_ID, 43ff2b1321SDan Nowlin ICE_GLOBAL_CFG_LOCK_RES_ID 44f31e4b6fSAnirudh Venkataramanan }; 45f31e4b6fSAnirudh Venkataramanan 46ff2b1321SDan Nowlin /* FW update timeout definitions are in milliseconds */ 47ff2b1321SDan Nowlin #define ICE_NVM_TIMEOUT 180000 48ff2b1321SDan Nowlin #define ICE_CHANGE_LOCK_TIMEOUT 1000 49ff2b1321SDan Nowlin #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000 50ff2b1321SDan Nowlin 51f31e4b6fSAnirudh Venkataramanan enum ice_aq_res_access_type { 52f31e4b6fSAnirudh Venkataramanan ICE_RES_READ = 1, 53f31e4b6fSAnirudh Venkataramanan ICE_RES_WRITE 54f31e4b6fSAnirudh Venkataramanan }; 55f31e4b6fSAnirudh Venkataramanan 56dc49c772SAnirudh Venkataramanan enum ice_fc_mode { 57dc49c772SAnirudh Venkataramanan ICE_FC_NONE = 0, 58dc49c772SAnirudh Venkataramanan ICE_FC_RX_PAUSE, 59dc49c772SAnirudh Venkataramanan ICE_FC_TX_PAUSE, 60dc49c772SAnirudh Venkataramanan ICE_FC_FULL, 61dc49c772SAnirudh Venkataramanan ICE_FC_PFC, 62dc49c772SAnirudh Venkataramanan ICE_FC_DFLT 63dc49c772SAnirudh Venkataramanan }; 64dc49c772SAnirudh Venkataramanan 65f776b3acSPaul Greenwalt enum ice_fec_mode { 66f776b3acSPaul Greenwalt ICE_FEC_NONE = 0, 67f776b3acSPaul Greenwalt ICE_FEC_RS, 68f776b3acSPaul Greenwalt ICE_FEC_BASER, 69f776b3acSPaul Greenwalt ICE_FEC_AUTO 70f776b3acSPaul Greenwalt }; 71f776b3acSPaul Greenwalt 72fcea6f3dSAnirudh Venkataramanan enum ice_set_fc_aq_failures { 73fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_NONE = 0, 74fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_GET, 75fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_SET, 76fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_UPDATE 77fcea6f3dSAnirudh Venkataramanan }; 78fcea6f3dSAnirudh Venkataramanan 79f31e4b6fSAnirudh Venkataramanan /* Various MAC types */ 80f31e4b6fSAnirudh Venkataramanan enum ice_mac_type { 81f31e4b6fSAnirudh Venkataramanan ICE_MAC_UNKNOWN = 0, 82f31e4b6fSAnirudh Venkataramanan ICE_MAC_GENERIC, 83f31e4b6fSAnirudh Venkataramanan }; 84f31e4b6fSAnirudh Venkataramanan 85dc49c772SAnirudh Venkataramanan /* Media Types */ 86dc49c772SAnirudh Venkataramanan enum ice_media_type { 87dc49c772SAnirudh Venkataramanan ICE_MEDIA_UNKNOWN = 0, 88dc49c772SAnirudh Venkataramanan ICE_MEDIA_FIBER, 89dc49c772SAnirudh Venkataramanan ICE_MEDIA_BASET, 90dc49c772SAnirudh Venkataramanan ICE_MEDIA_BACKPLANE, 91dc49c772SAnirudh Venkataramanan ICE_MEDIA_DA, 92dc49c772SAnirudh Venkataramanan }; 93dc49c772SAnirudh Venkataramanan 943a858ba3SAnirudh Venkataramanan enum ice_vsi_type { 953a858ba3SAnirudh Venkataramanan ICE_VSI_PF = 0, 9675d2b253SAnirudh Venkataramanan ICE_VSI_VF, 970e674aebSAnirudh Venkataramanan ICE_VSI_LB = 6, 983a858ba3SAnirudh Venkataramanan }; 993a858ba3SAnirudh Venkataramanan 100dc49c772SAnirudh Venkataramanan struct ice_link_status { 101dc49c772SAnirudh Venkataramanan /* Refer to ice_aq_phy_type for bits definition */ 102dc49c772SAnirudh Venkataramanan u64 phy_type_low; 103aef74145SAnirudh Venkataramanan u64 phy_type_high; 104f776b3acSPaul Greenwalt u8 topo_media_conflict; 105dc49c772SAnirudh Venkataramanan u16 max_frame_size; 106dc49c772SAnirudh Venkataramanan u16 link_speed; 107ffe49823SChinh T Cao u16 req_speeds; 10843f8b224SBruce Allan u8 lse_ena; /* Link Status Event notification */ 109dc49c772SAnirudh Venkataramanan u8 link_info; 110dc49c772SAnirudh Venkataramanan u8 an_info; 111dc49c772SAnirudh Venkataramanan u8 ext_info; 112f776b3acSPaul Greenwalt u8 fec_info; 113dc49c772SAnirudh Venkataramanan u8 pacing; 114dc49c772SAnirudh Venkataramanan /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of 115dc49c772SAnirudh Venkataramanan * ice_aqc_get_phy_caps structure 116dc49c772SAnirudh Venkataramanan */ 117dc49c772SAnirudh Venkataramanan u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 118dc49c772SAnirudh Venkataramanan }; 119dc49c772SAnirudh Venkataramanan 120ddf30f7fSAnirudh Venkataramanan /* Different reset sources for which a disable queue AQ call has to be made in 121f9867df6SAnirudh Venkataramanan * order to clean the Tx scheduler as a part of the reset 122ddf30f7fSAnirudh Venkataramanan */ 123ddf30f7fSAnirudh Venkataramanan enum ice_disq_rst_src { 124ddf30f7fSAnirudh Venkataramanan ICE_NO_RESET = 0, 125ddf30f7fSAnirudh Venkataramanan ICE_VM_RESET, 126ddf30f7fSAnirudh Venkataramanan ICE_VF_RESET, 127ddf30f7fSAnirudh Venkataramanan }; 128ddf30f7fSAnirudh Venkataramanan 129dc49c772SAnirudh Venkataramanan /* PHY info such as phy_type, etc... */ 130dc49c772SAnirudh Venkataramanan struct ice_phy_info { 131dc49c772SAnirudh Venkataramanan struct ice_link_status link_info; 132dc49c772SAnirudh Venkataramanan struct ice_link_status link_info_old; 133dc49c772SAnirudh Venkataramanan u64 phy_type_low; 134aef74145SAnirudh Venkataramanan u64 phy_type_high; 135dc49c772SAnirudh Venkataramanan enum ice_media_type media_type; 13643f8b224SBruce Allan u8 get_link_info; 137dc49c772SAnirudh Venkataramanan }; 138dc49c772SAnirudh Venkataramanan 1399c20346bSAnirudh Venkataramanan /* Common HW capabilities for SW use */ 1409c20346bSAnirudh Venkataramanan struct ice_hw_common_caps { 141995c90f2SAnirudh Venkataramanan u32 valid_functions; 142a257f188SUsha Ketineni /* DCB capabilities */ 143a257f188SUsha Ketineni u32 active_tc_bitmap; 144a257f188SUsha Ketineni u32 maxtc; 145995c90f2SAnirudh Venkataramanan 146f9867df6SAnirudh Venkataramanan /* Tx/Rx queues */ 147f9867df6SAnirudh Venkataramanan u16 num_rxq; /* Number/Total Rx queues */ 148f9867df6SAnirudh Venkataramanan u16 rxq_first_id; /* First queue ID for Rx queues */ 149f9867df6SAnirudh Venkataramanan u16 num_txq; /* Number/Total Tx queues */ 150f9867df6SAnirudh Venkataramanan u16 txq_first_id; /* First queue ID for Tx queues */ 1519c20346bSAnirudh Venkataramanan 1529c20346bSAnirudh Venkataramanan /* MSI-X vectors */ 1539c20346bSAnirudh Venkataramanan u16 num_msix_vectors; 1549c20346bSAnirudh Venkataramanan u16 msix_vector_first_id; 1559c20346bSAnirudh Venkataramanan 1569c20346bSAnirudh Venkataramanan /* Max MTU for function or device */ 1579c20346bSAnirudh Venkataramanan u16 max_mtu; 1589c20346bSAnirudh Venkataramanan 15975d2b253SAnirudh Venkataramanan /* Virtualization support */ 16075d2b253SAnirudh Venkataramanan u8 sr_iov_1_1; /* SR-IOV enabled */ 161ddf30f7fSAnirudh Venkataramanan 1629c20346bSAnirudh Venkataramanan /* RSS related capabilities */ 1639c20346bSAnirudh Venkataramanan u16 rss_table_size; /* 512 for PFs and 64 for VFs */ 1649c20346bSAnirudh Venkataramanan u8 rss_table_entry_width; /* RSS Entry width in bits */ 16537b6f646SAnirudh Venkataramanan 16637b6f646SAnirudh Venkataramanan u8 dcb; 1679c20346bSAnirudh Venkataramanan }; 1689c20346bSAnirudh Venkataramanan 1699c20346bSAnirudh Venkataramanan /* Function specific capabilities */ 1709c20346bSAnirudh Venkataramanan struct ice_hw_func_caps { 1719c20346bSAnirudh Venkataramanan struct ice_hw_common_caps common_cap; 17275d2b253SAnirudh Venkataramanan u32 num_allocd_vfs; /* Number of allocated VFs */ 17375d2b253SAnirudh Venkataramanan u32 vf_base_id; /* Logical ID of the first VF */ 174995c90f2SAnirudh Venkataramanan u32 guar_num_vsi; 1759c20346bSAnirudh Venkataramanan }; 1769c20346bSAnirudh Venkataramanan 1779c20346bSAnirudh Venkataramanan /* Device wide capabilities */ 1789c20346bSAnirudh Venkataramanan struct ice_hw_dev_caps { 1799c20346bSAnirudh Venkataramanan struct ice_hw_common_caps common_cap; 18075d2b253SAnirudh Venkataramanan u32 num_vfs_exposed; /* Total number of VFs exposed */ 1819c20346bSAnirudh Venkataramanan u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ 1829c20346bSAnirudh Venkataramanan }; 1839c20346bSAnirudh Venkataramanan 184dc49c772SAnirudh Venkataramanan /* MAC info */ 185dc49c772SAnirudh Venkataramanan struct ice_mac_info { 186dc49c772SAnirudh Venkataramanan u8 lan_addr[ETH_ALEN]; 187dc49c772SAnirudh Venkataramanan u8 perm_addr[ETH_ALEN]; 188dc49c772SAnirudh Venkataramanan }; 189dc49c772SAnirudh Venkataramanan 190ca4929b6SBrett Creeley /* Reset types used to determine which kind of reset was requested. These 191ca4929b6SBrett Creeley * defines match what the RESET_TYPE field of the GLGEN_RSTAT register. 192ca4929b6SBrett Creeley * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register 193ca4929b6SBrett Creeley * because its reset source is different than the other types listed. 194ca4929b6SBrett Creeley */ 195f31e4b6fSAnirudh Venkataramanan enum ice_reset_req { 196ca4929b6SBrett Creeley ICE_RESET_POR = 0, 1970f9d5027SAnirudh Venkataramanan ICE_RESET_INVAL = 0, 198ca4929b6SBrett Creeley ICE_RESET_CORER = 1, 199ca4929b6SBrett Creeley ICE_RESET_GLOBR = 2, 200ca4929b6SBrett Creeley ICE_RESET_EMPR = 3, 201ca4929b6SBrett Creeley ICE_RESET_PFR = 4, 202f31e4b6fSAnirudh Venkataramanan }; 203f31e4b6fSAnirudh Venkataramanan 204837f08fdSAnirudh Venkataramanan /* Bus parameters */ 205837f08fdSAnirudh Venkataramanan struct ice_bus_info { 206837f08fdSAnirudh Venkataramanan u16 device; 207837f08fdSAnirudh Venkataramanan u8 func; 208837f08fdSAnirudh Venkataramanan }; 209837f08fdSAnirudh Venkataramanan 210dc49c772SAnirudh Venkataramanan /* Flow control (FC) parameters */ 211dc49c772SAnirudh Venkataramanan struct ice_fc_info { 212dc49c772SAnirudh Venkataramanan enum ice_fc_mode current_mode; /* FC mode in effect */ 213dc49c772SAnirudh Venkataramanan enum ice_fc_mode req_mode; /* FC mode requested by caller */ 214dc49c772SAnirudh Venkataramanan }; 215dc49c772SAnirudh Venkataramanan 216f31e4b6fSAnirudh Venkataramanan /* NVM Information */ 217f31e4b6fSAnirudh Venkataramanan struct ice_nvm_info { 218f31e4b6fSAnirudh Venkataramanan u32 eetrack; /* NVM data version */ 219f31e4b6fSAnirudh Venkataramanan u32 oem_ver; /* OEM version info */ 220f31e4b6fSAnirudh Venkataramanan u16 sr_words; /* Shadow RAM size in words */ 221f31e4b6fSAnirudh Venkataramanan u16 ver; /* NVM package version */ 22243f8b224SBruce Allan u8 blank_nvm_mode; /* is NVM empty (no FW present) */ 223f31e4b6fSAnirudh Venkataramanan }; 224f31e4b6fSAnirudh Venkataramanan 2259c20346bSAnirudh Venkataramanan /* Max number of port to queue branches w.r.t topology */ 2269c20346bSAnirudh Venkataramanan #define ICE_MAX_TRAFFIC_CLASS 8 227dc49c772SAnirudh Venkataramanan #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS 2289c20346bSAnirudh Venkataramanan 2292bdc97beSBruce Allan #define ice_for_each_traffic_class(_i) \ 2302bdc97beSBruce Allan for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++) 2312bdc97beSBruce Allan 2327b9ffc76SAnirudh Venkataramanan #define ICE_INVAL_TEID 0xFFFFFFFF 2337b9ffc76SAnirudh Venkataramanan 2349c20346bSAnirudh Venkataramanan struct ice_sched_node { 2359c20346bSAnirudh Venkataramanan struct ice_sched_node *parent; 2369c20346bSAnirudh Venkataramanan struct ice_sched_node *sibling; /* next sibling in the same layer */ 2379c20346bSAnirudh Venkataramanan struct ice_sched_node **children; 2389c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_elem_data info; 239f9867df6SAnirudh Venkataramanan u32 agg_id; /* aggregator group ID */ 2404fb33f31SAnirudh Venkataramanan u16 vsi_handle; 24143f8b224SBruce Allan u8 in_use; /* suspended or in use */ 2429c20346bSAnirudh Venkataramanan u8 tx_sched_layer; /* Logical Layer (1-9) */ 2439c20346bSAnirudh Venkataramanan u8 num_children; 2449c20346bSAnirudh Venkataramanan u8 tc_num; 2459c20346bSAnirudh Venkataramanan u8 owner; 2469c20346bSAnirudh Venkataramanan #define ICE_SCHED_NODE_OWNER_LAN 0 2479c20346bSAnirudh Venkataramanan }; 2489c20346bSAnirudh Venkataramanan 249dc49c772SAnirudh Venkataramanan /* Access Macros for Tx Sched Elements data */ 250dc49c772SAnirudh Venkataramanan #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid) 251dc49c772SAnirudh Venkataramanan 2529c20346bSAnirudh Venkataramanan /* The aggregator type determines if identifier is for a VSI group, 2539c20346bSAnirudh Venkataramanan * aggregator group, aggregator of queues, or queue group. 2549c20346bSAnirudh Venkataramanan */ 2559c20346bSAnirudh Venkataramanan enum ice_agg_type { 2569c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_UNKNOWN = 0, 2579c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_VSI, 2589c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_AGG, /* aggregator */ 2599c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_Q, 2609c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_QG 2619c20346bSAnirudh Venkataramanan }; 2629c20346bSAnirudh Venkataramanan 2635513b920SAnirudh Venkataramanan #define ICE_SCHED_DFLT_RL_PROF_ID 0 264b36c598cSAnirudh Venkataramanan #define ICE_SCHED_DFLT_BW_WT 1 2655513b920SAnirudh Venkataramanan 266f9867df6SAnirudh Venkataramanan /* VSI type list entry to locate corresponding VSI/ag nodes */ 2679c20346bSAnirudh Venkataramanan struct ice_sched_vsi_info { 2689c20346bSAnirudh Venkataramanan struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS]; 2699c20346bSAnirudh Venkataramanan struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS]; 2709c20346bSAnirudh Venkataramanan struct list_head list_entry; 2719c20346bSAnirudh Venkataramanan u16 max_lanq[ICE_MAX_TRAFFIC_CLASS]; 2729c20346bSAnirudh Venkataramanan }; 2739c20346bSAnirudh Venkataramanan 2749c20346bSAnirudh Venkataramanan /* driver defines the policy */ 2759c20346bSAnirudh Venkataramanan struct ice_sched_tx_policy { 2769c20346bSAnirudh Venkataramanan u16 max_num_vsis; 2779c20346bSAnirudh Venkataramanan u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS]; 27843f8b224SBruce Allan u8 rdma_ena; 2799c20346bSAnirudh Venkataramanan }; 2809c20346bSAnirudh Venkataramanan 2810ebd3ff1SAnirudh Venkataramanan /* CEE or IEEE 802.1Qaz ETS Configuration data */ 2820ebd3ff1SAnirudh Venkataramanan struct ice_dcb_ets_cfg { 2830ebd3ff1SAnirudh Venkataramanan u8 willing; 2840ebd3ff1SAnirudh Venkataramanan u8 cbs; 2850ebd3ff1SAnirudh Venkataramanan u8 maxtcs; 2860ebd3ff1SAnirudh Venkataramanan u8 prio_table[ICE_MAX_TRAFFIC_CLASS]; 2870ebd3ff1SAnirudh Venkataramanan u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS]; 2880ebd3ff1SAnirudh Venkataramanan u8 tsatable[ICE_MAX_TRAFFIC_CLASS]; 2890ebd3ff1SAnirudh Venkataramanan }; 2900ebd3ff1SAnirudh Venkataramanan 2910ebd3ff1SAnirudh Venkataramanan /* CEE or IEEE 802.1Qaz PFC Configuration data */ 2920ebd3ff1SAnirudh Venkataramanan struct ice_dcb_pfc_cfg { 2930ebd3ff1SAnirudh Venkataramanan u8 willing; 2940ebd3ff1SAnirudh Venkataramanan u8 mbc; 2950ebd3ff1SAnirudh Venkataramanan u8 pfccap; 2960ebd3ff1SAnirudh Venkataramanan u8 pfcena; 2970ebd3ff1SAnirudh Venkataramanan }; 2980ebd3ff1SAnirudh Venkataramanan 2990ebd3ff1SAnirudh Venkataramanan /* CEE or IEEE 802.1Qaz Application Priority data */ 3000ebd3ff1SAnirudh Venkataramanan struct ice_dcb_app_priority_table { 3010ebd3ff1SAnirudh Venkataramanan u16 prot_id; 3020ebd3ff1SAnirudh Venkataramanan u8 priority; 3030ebd3ff1SAnirudh Venkataramanan u8 selector; 3040ebd3ff1SAnirudh Venkataramanan }; 3050ebd3ff1SAnirudh Venkataramanan 3060ebd3ff1SAnirudh Venkataramanan #define ICE_MAX_USER_PRIORITY 8 3070ebd3ff1SAnirudh Venkataramanan #define ICE_DCBX_MAX_APPS 32 3080ebd3ff1SAnirudh Venkataramanan #define ICE_LLDPDU_SIZE 1500 3090ebd3ff1SAnirudh Venkataramanan #define ICE_TLV_STATUS_OPER 0x1 3100ebd3ff1SAnirudh Venkataramanan #define ICE_TLV_STATUS_SYNC 0x2 3110ebd3ff1SAnirudh Venkataramanan #define ICE_TLV_STATUS_ERR 0x4 3120ebd3ff1SAnirudh Venkataramanan #define ICE_APP_PROT_ID_FCOE 0x8906 3130ebd3ff1SAnirudh Venkataramanan #define ICE_APP_PROT_ID_ISCSI 0x0cbc 3140ebd3ff1SAnirudh Venkataramanan #define ICE_APP_PROT_ID_FIP 0x8914 3150ebd3ff1SAnirudh Venkataramanan #define ICE_APP_SEL_ETHTYPE 0x1 3160ebd3ff1SAnirudh Venkataramanan #define ICE_APP_SEL_TCPIP 0x2 3170ebd3ff1SAnirudh Venkataramanan #define ICE_CEE_APP_SEL_ETHTYPE 0x0 3180ebd3ff1SAnirudh Venkataramanan #define ICE_CEE_APP_SEL_TCPIP 0x1 3190ebd3ff1SAnirudh Venkataramanan 3200ebd3ff1SAnirudh Venkataramanan struct ice_dcbx_cfg { 3210ebd3ff1SAnirudh Venkataramanan u32 numapps; 3220ebd3ff1SAnirudh Venkataramanan u32 tlv_status; /* CEE mode TLV status */ 3230ebd3ff1SAnirudh Venkataramanan struct ice_dcb_ets_cfg etscfg; 3240ebd3ff1SAnirudh Venkataramanan struct ice_dcb_ets_cfg etsrec; 3250ebd3ff1SAnirudh Venkataramanan struct ice_dcb_pfc_cfg pfc; 3260ebd3ff1SAnirudh Venkataramanan struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS]; 3270ebd3ff1SAnirudh Venkataramanan u8 dcbx_mode; 3280ebd3ff1SAnirudh Venkataramanan #define ICE_DCBX_MODE_CEE 0x1 3290ebd3ff1SAnirudh Venkataramanan #define ICE_DCBX_MODE_IEEE 0x2 3300ebd3ff1SAnirudh Venkataramanan u8 app_mode; 3310ebd3ff1SAnirudh Venkataramanan #define ICE_DCBX_APPS_NON_WILLING 0x1 3320ebd3ff1SAnirudh Venkataramanan }; 3330ebd3ff1SAnirudh Venkataramanan 3349c20346bSAnirudh Venkataramanan struct ice_port_info { 3359c20346bSAnirudh Venkataramanan struct ice_sched_node *root; /* Root Node per Port */ 336f9867df6SAnirudh Venkataramanan struct ice_hw *hw; /* back pointer to HW instance */ 337dc49c772SAnirudh Venkataramanan u32 last_node_teid; /* scheduler last node info */ 3389c20346bSAnirudh Venkataramanan u16 sw_id; /* Initial switch ID belongs to port */ 3399c20346bSAnirudh Venkataramanan u16 pf_vf_num; 3409c20346bSAnirudh Venkataramanan u8 port_state; 3419c20346bSAnirudh Venkataramanan #define ICE_SCHED_PORT_STATE_INIT 0x0 3429c20346bSAnirudh Venkataramanan #define ICE_SCHED_PORT_STATE_READY 0x1 3430437f1a9SJesse Brandeburg u8 lport; 3440437f1a9SJesse Brandeburg #define ICE_LPORT_MASK 0xff 345e94d4478SAnirudh Venkataramanan u16 dflt_tx_vsi_rule_id; 3469c20346bSAnirudh Venkataramanan u16 dflt_tx_vsi_num; 347e94d4478SAnirudh Venkataramanan u16 dflt_rx_vsi_rule_id; 3489c20346bSAnirudh Venkataramanan u16 dflt_rx_vsi_num; 349dc49c772SAnirudh Venkataramanan struct ice_fc_info fc; 350dc49c772SAnirudh Venkataramanan struct ice_mac_info mac; 351dc49c772SAnirudh Venkataramanan struct ice_phy_info phy; 3529c20346bSAnirudh Venkataramanan struct mutex sched_lock; /* protect access to TXSched tree */ 35329358248SVictor Raj struct ice_sched_node * 35429358248SVictor Raj sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM]; 3550ebd3ff1SAnirudh Venkataramanan struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */ 3560ebd3ff1SAnirudh Venkataramanan /* DCBX info */ 3570ebd3ff1SAnirudh Venkataramanan struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */ 3580ebd3ff1SAnirudh Venkataramanan struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */ 35937b6f646SAnirudh Venkataramanan /* LLDP/DCBX Status */ 3600437f1a9SJesse Brandeburg u8 dcbx_status:3; /* see ICE_DCBX_STATUS_DIS */ 3610437f1a9SJesse Brandeburg u8 is_sw_lldp:1; 3620437f1a9SJesse Brandeburg u8 is_vf:1; 3639c20346bSAnirudh Venkataramanan }; 3649c20346bSAnirudh Venkataramanan 3659daf8208SAnirudh Venkataramanan struct ice_switch_info { 3669daf8208SAnirudh Venkataramanan struct list_head vsi_list_map_head; 36780d144c9SAnirudh Venkataramanan struct ice_sw_recipe *recp_list; 3689daf8208SAnirudh Venkataramanan }; 3699daf8208SAnirudh Venkataramanan 3708b97ceb1SHieu Tran /* FW logging configuration */ 3718b97ceb1SHieu Tran struct ice_fw_log_evnt { 3728b97ceb1SHieu Tran u8 cfg : 4; /* New event enables to configure */ 3738b97ceb1SHieu Tran u8 cur : 4; /* Current/active event enables */ 3748b97ceb1SHieu Tran }; 3758b97ceb1SHieu Tran 3768b97ceb1SHieu Tran struct ice_fw_log_cfg { 3778b97ceb1SHieu Tran u8 cq_en : 1; /* FW logging is enabled via the control queue */ 3788b97ceb1SHieu Tran u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */ 3798b97ceb1SHieu Tran u8 actv_evnts; /* Cumulation of currently enabled log events */ 3808b97ceb1SHieu Tran 3818b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S) 3828b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S) 3838b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S) 3848b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S) 3858b97ceb1SHieu Tran struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX]; 3868b97ceb1SHieu Tran }; 3878b97ceb1SHieu Tran 388837f08fdSAnirudh Venkataramanan /* Port hardware description */ 389837f08fdSAnirudh Venkataramanan struct ice_hw { 390837f08fdSAnirudh Venkataramanan u8 __iomem *hw_addr; 391837f08fdSAnirudh Venkataramanan void *back; 3929c20346bSAnirudh Venkataramanan struct ice_aqc_layer_props *layer_info; 3939c20346bSAnirudh Venkataramanan struct ice_port_info *port_info; 3947ec59eeaSAnirudh Venkataramanan u64 debug_mask; /* bitmap for debug mask */ 395f31e4b6fSAnirudh Venkataramanan enum ice_mac_type mac_type; 396837f08fdSAnirudh Venkataramanan 397837f08fdSAnirudh Venkataramanan /* pci info */ 398837f08fdSAnirudh Venkataramanan u16 device_id; 399837f08fdSAnirudh Venkataramanan u16 vendor_id; 400837f08fdSAnirudh Venkataramanan u16 subsystem_device_id; 401837f08fdSAnirudh Venkataramanan u16 subsystem_vendor_id; 402837f08fdSAnirudh Venkataramanan u8 revision_id; 403837f08fdSAnirudh Venkataramanan 404f31e4b6fSAnirudh Venkataramanan u8 pf_id; /* device profile info */ 405f31e4b6fSAnirudh Venkataramanan 406f9867df6SAnirudh Venkataramanan /* Tx Scheduler values */ 4079c20346bSAnirudh Venkataramanan u16 num_tx_sched_layers; 4089c20346bSAnirudh Venkataramanan u16 num_tx_sched_phys_layers; 4099c20346bSAnirudh Venkataramanan u8 flattened_layers; 4109c20346bSAnirudh Venkataramanan u8 max_cgds; 4119c20346bSAnirudh Venkataramanan u8 sw_entry_point_layer; 412b36c598cSAnirudh Venkataramanan u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 4139be1d6f8SAnirudh Venkataramanan struct list_head agg_list; /* lists all aggregator */ 4149c20346bSAnirudh Venkataramanan 4150f9d5027SAnirudh Venkataramanan struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI]; 41643f8b224SBruce Allan u8 evb_veb; /* true for VEB, false for VEPA */ 417f9867df6SAnirudh Venkataramanan u8 reset_ongoing; /* true if HW is in reset, false otherwise */ 418837f08fdSAnirudh Venkataramanan struct ice_bus_info bus; 419f31e4b6fSAnirudh Venkataramanan struct ice_nvm_info nvm; 4209c20346bSAnirudh Venkataramanan struct ice_hw_dev_caps dev_caps; /* device capabilities */ 4219c20346bSAnirudh Venkataramanan struct ice_hw_func_caps func_caps; /* function capabilities */ 422f31e4b6fSAnirudh Venkataramanan 4239daf8208SAnirudh Venkataramanan struct ice_switch_info *switch_info; /* switch filter lists */ 4249daf8208SAnirudh Venkataramanan 4257ec59eeaSAnirudh Venkataramanan /* Control Queue info */ 4267ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_info adminq; 42775d2b253SAnirudh Venkataramanan struct ice_ctl_q_info mailboxq; 4287ec59eeaSAnirudh Venkataramanan 4297ec59eeaSAnirudh Venkataramanan u8 api_branch; /* API branch version */ 4307ec59eeaSAnirudh Venkataramanan u8 api_maj_ver; /* API major version */ 4317ec59eeaSAnirudh Venkataramanan u8 api_min_ver; /* API minor version */ 4327ec59eeaSAnirudh Venkataramanan u8 api_patch; /* API patch version */ 4337ec59eeaSAnirudh Venkataramanan u8 fw_branch; /* firmware branch version */ 4347ec59eeaSAnirudh Venkataramanan u8 fw_maj_ver; /* firmware major version */ 4357ec59eeaSAnirudh Venkataramanan u8 fw_min_ver; /* firmware minor version */ 4367ec59eeaSAnirudh Venkataramanan u8 fw_patch; /* firmware patch version */ 4377ec59eeaSAnirudh Venkataramanan u32 fw_build; /* firmware build number */ 438940b61afSAnirudh Venkataramanan 4398b97ceb1SHieu Tran struct ice_fw_log_cfg fw_log; 4409e4ab4c2SBrett Creeley 4419e4ab4c2SBrett Creeley /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL 4422f2da36eSAnirudh Venkataramanan * register. Used for determining the ITR/intrl granularity during 4439e4ab4c2SBrett Creeley * initialization. 4449e4ab4c2SBrett Creeley */ 4459e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_200G 0x0 4469e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_100G 0X1 4479e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_50G 0x2 4489e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_25G 0x3 4499e4ab4c2SBrett Creeley /* ITR granularity for different speeds */ 4509e4ab4c2SBrett Creeley #define ICE_ITR_GRAN_ABOVE_25 2 4519e4ab4c2SBrett Creeley #define ICE_ITR_GRAN_MAX_25 4 452940b61afSAnirudh Venkataramanan /* ITR granularity in 1 us */ 4539e4ab4c2SBrett Creeley u8 itr_gran; 4549e4ab4c2SBrett Creeley /* INTRL granularity for different speeds */ 4559e4ab4c2SBrett Creeley #define ICE_INTRL_GRAN_ABOVE_25 4 4569e4ab4c2SBrett Creeley #define ICE_INTRL_GRAN_MAX_25 8 4579e4ab4c2SBrett Creeley /* INTRL granularity in 1 us */ 4589e4ab4c2SBrett Creeley u8 intrl_gran; 4599e4ab4c2SBrett Creeley 46043f8b224SBruce Allan u8 ucast_shared; /* true if VSIs can share unicast addr */ 4619daf8208SAnirudh Venkataramanan 462837f08fdSAnirudh Venkataramanan }; 463837f08fdSAnirudh Venkataramanan 464fcea6f3dSAnirudh Venkataramanan /* Statistics collected by each port, VSI, VEB, and S-channel */ 465fcea6f3dSAnirudh Venkataramanan struct ice_eth_stats { 466fcea6f3dSAnirudh Venkataramanan u64 rx_bytes; /* gorc */ 467fcea6f3dSAnirudh Venkataramanan u64 rx_unicast; /* uprc */ 468fcea6f3dSAnirudh Venkataramanan u64 rx_multicast; /* mprc */ 469fcea6f3dSAnirudh Venkataramanan u64 rx_broadcast; /* bprc */ 470fcea6f3dSAnirudh Venkataramanan u64 rx_discards; /* rdpc */ 471fcea6f3dSAnirudh Venkataramanan u64 rx_unknown_protocol; /* rupp */ 472fcea6f3dSAnirudh Venkataramanan u64 tx_bytes; /* gotc */ 473fcea6f3dSAnirudh Venkataramanan u64 tx_unicast; /* uptc */ 474fcea6f3dSAnirudh Venkataramanan u64 tx_multicast; /* mptc */ 475fcea6f3dSAnirudh Venkataramanan u64 tx_broadcast; /* bptc */ 476fcea6f3dSAnirudh Venkataramanan u64 tx_discards; /* tdpc */ 477fcea6f3dSAnirudh Venkataramanan u64 tx_errors; /* tepc */ 478fcea6f3dSAnirudh Venkataramanan }; 479fcea6f3dSAnirudh Venkataramanan 480fcea6f3dSAnirudh Venkataramanan /* Statistics collected by the MAC */ 481fcea6f3dSAnirudh Venkataramanan struct ice_hw_port_stats { 482fcea6f3dSAnirudh Venkataramanan /* eth stats collected by the port */ 483fcea6f3dSAnirudh Venkataramanan struct ice_eth_stats eth; 484fcea6f3dSAnirudh Venkataramanan /* additional port specific stats */ 485fcea6f3dSAnirudh Venkataramanan u64 tx_dropped_link_down; /* tdold */ 486fcea6f3dSAnirudh Venkataramanan u64 crc_errors; /* crcerrs */ 487fcea6f3dSAnirudh Venkataramanan u64 illegal_bytes; /* illerrc */ 488fcea6f3dSAnirudh Venkataramanan u64 error_bytes; /* errbc */ 489fcea6f3dSAnirudh Venkataramanan u64 mac_local_faults; /* mlfc */ 490fcea6f3dSAnirudh Venkataramanan u64 mac_remote_faults; /* mrfc */ 491fcea6f3dSAnirudh Venkataramanan u64 rx_len_errors; /* rlec */ 492fcea6f3dSAnirudh Venkataramanan u64 link_xon_rx; /* lxonrxc */ 493fcea6f3dSAnirudh Venkataramanan u64 link_xoff_rx; /* lxoffrxc */ 494fcea6f3dSAnirudh Venkataramanan u64 link_xon_tx; /* lxontxc */ 495fcea6f3dSAnirudh Venkataramanan u64 link_xoff_tx; /* lxofftxc */ 4964b0fdcebSAnirudh Venkataramanan u64 priority_xon_rx[8]; /* pxonrxc[8] */ 4974b0fdcebSAnirudh Venkataramanan u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 4984b0fdcebSAnirudh Venkataramanan u64 priority_xon_tx[8]; /* pxontxc[8] */ 4994b0fdcebSAnirudh Venkataramanan u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 5004b0fdcebSAnirudh Venkataramanan u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 501fcea6f3dSAnirudh Venkataramanan u64 rx_size_64; /* prc64 */ 502fcea6f3dSAnirudh Venkataramanan u64 rx_size_127; /* prc127 */ 503fcea6f3dSAnirudh Venkataramanan u64 rx_size_255; /* prc255 */ 504fcea6f3dSAnirudh Venkataramanan u64 rx_size_511; /* prc511 */ 505fcea6f3dSAnirudh Venkataramanan u64 rx_size_1023; /* prc1023 */ 506fcea6f3dSAnirudh Venkataramanan u64 rx_size_1522; /* prc1522 */ 507fcea6f3dSAnirudh Venkataramanan u64 rx_size_big; /* prc9522 */ 508fcea6f3dSAnirudh Venkataramanan u64 rx_undersize; /* ruc */ 509fcea6f3dSAnirudh Venkataramanan u64 rx_fragments; /* rfc */ 510fcea6f3dSAnirudh Venkataramanan u64 rx_oversize; /* roc */ 511fcea6f3dSAnirudh Venkataramanan u64 rx_jabber; /* rjc */ 512fcea6f3dSAnirudh Venkataramanan u64 tx_size_64; /* ptc64 */ 513fcea6f3dSAnirudh Venkataramanan u64 tx_size_127; /* ptc127 */ 514fcea6f3dSAnirudh Venkataramanan u64 tx_size_255; /* ptc255 */ 515fcea6f3dSAnirudh Venkataramanan u64 tx_size_511; /* ptc511 */ 516fcea6f3dSAnirudh Venkataramanan u64 tx_size_1023; /* ptc1023 */ 517fcea6f3dSAnirudh Venkataramanan u64 tx_size_1522; /* ptc1522 */ 518fcea6f3dSAnirudh Venkataramanan u64 tx_size_big; /* ptc9522 */ 519fcea6f3dSAnirudh Venkataramanan }; 520fcea6f3dSAnirudh Venkataramanan 521f31e4b6fSAnirudh Venkataramanan /* Checksum and Shadow RAM pointers */ 522f31e4b6fSAnirudh Venkataramanan #define ICE_SR_NVM_DEV_STARTER_VER 0x18 523f31e4b6fSAnirudh Venkataramanan #define ICE_SR_NVM_EETRACK_LO 0x2D 524f31e4b6fSAnirudh Venkataramanan #define ICE_SR_NVM_EETRACK_HI 0x2E 525fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_LO_SHIFT 0 526fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT) 527fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_HI_SHIFT 12 528fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT) 529fcea6f3dSAnirudh Venkataramanan #define ICE_OEM_VER_PATCH_SHIFT 0 530fcea6f3dSAnirudh Venkataramanan #define ICE_OEM_VER_PATCH_MASK (0xff << ICE_OEM_VER_PATCH_SHIFT) 531fcea6f3dSAnirudh Venkataramanan #define ICE_OEM_VER_BUILD_SHIFT 8 532fcea6f3dSAnirudh Venkataramanan #define ICE_OEM_VER_BUILD_MASK (0xffff << ICE_OEM_VER_BUILD_SHIFT) 533fcea6f3dSAnirudh Venkataramanan #define ICE_OEM_VER_SHIFT 24 534fcea6f3dSAnirudh Venkataramanan #define ICE_OEM_VER_MASK (0xff << ICE_OEM_VER_SHIFT) 535f31e4b6fSAnirudh Venkataramanan #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800 536f31e4b6fSAnirudh Venkataramanan #define ICE_SR_WORDS_IN_1KB 512 537f31e4b6fSAnirudh Venkataramanan 5388ede0178SAnirudh Venkataramanan /* Hash redirection LUT for VSI - maximum array size */ 5398ede0178SAnirudh Venkataramanan #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4) 5408ede0178SAnirudh Venkataramanan 541837f08fdSAnirudh Venkataramanan #endif /* _ICE_TYPE_H_ */ 542