1837f08fdSAnirudh Venkataramanan /* SPDX-License-Identifier: GPL-2.0 */ 2837f08fdSAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */ 3837f08fdSAnirudh Venkataramanan 4837f08fdSAnirudh Venkataramanan #ifndef _ICE_TYPE_H_ 5837f08fdSAnirudh Venkataramanan #define _ICE_TYPE_H_ 6837f08fdSAnirudh Venkataramanan 76a025730STony Nguyen #define ICE_BYTES_PER_WORD 2 86a025730STony Nguyen #define ICE_BYTES_PER_DWORD 4 940319796SKiran Patil #define ICE_CHNL_MAX_TC 16 106a025730STony Nguyen 117ec59eeaSAnirudh Venkataramanan #include "ice_hw_autogen.h" 127ec59eeaSAnirudh Venkataramanan #include "ice_osdep.h" 137ec59eeaSAnirudh Venkataramanan #include "ice_controlq.h" 14cdedef59SAnirudh Venkataramanan #include "ice_lan_tx_rx.h" 15c7648810STony Nguyen #include "ice_flex_type.h" 1631ad4e4eSTony Nguyen #include "ice_protocol_type.h" 178f5ee3c4SJacob Keller #include "ice_sbq_cmd.h" 18*a1ffafb0SBrett Creeley #include "ice_vlan_mode.h" 197ec59eeaSAnirudh Venkataramanan 2035b4f437SJacob Keller static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc) 215513b920SAnirudh Venkataramanan { 2235b4f437SJacob Keller return test_bit(tc, &bitmap); 235513b920SAnirudh Venkataramanan } 245513b920SAnirudh Venkataramanan 251ddef455SUsha Ketineni static inline u64 round_up_64bit(u64 a, u32 b) 261ddef455SUsha Ketineni { 271ddef455SUsha Ketineni return div64_long(((a) + (b) / 2), (b)); 281ddef455SUsha Ketineni } 291ddef455SUsha Ketineni 301ddef455SUsha Ketineni static inline u32 ice_round_to_num(u32 N, u32 R) 311ddef455SUsha Ketineni { 321ddef455SUsha Ketineni return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) : 331ddef455SUsha Ketineni ((((N) + (R) - 1) / (R)) * (R))); 341ddef455SUsha Ketineni } 351ddef455SUsha Ketineni 36334cb062SAnirudh Venkataramanan /* Driver always calls main vsi_handle first */ 37334cb062SAnirudh Venkataramanan #define ICE_MAIN_VSI_HANDLE 0 38334cb062SAnirudh Venkataramanan 397ec59eeaSAnirudh Venkataramanan /* debug masks - set these bits in hw->debug_mask to control output */ 40f31e4b6fSAnirudh Venkataramanan #define ICE_DBG_INIT BIT_ULL(1) 414f70daa0SJacob Keller #define ICE_DBG_FW_LOG BIT_ULL(3) 420b28b702SAnirudh Venkataramanan #define ICE_DBG_LINK BIT_ULL(4) 43d8df260aSChinh T Cao #define ICE_DBG_PHY BIT_ULL(5) 44cdedef59SAnirudh Venkataramanan #define ICE_DBG_QCTX BIT_ULL(6) 45f31e4b6fSAnirudh Venkataramanan #define ICE_DBG_NVM BIT_ULL(7) 46dc49c772SAnirudh Venkataramanan #define ICE_DBG_LAN BIT_ULL(8) 4731ad4e4eSTony Nguyen #define ICE_DBG_FLOW BIT_ULL(9) 489c20346bSAnirudh Venkataramanan #define ICE_DBG_SW BIT_ULL(13) 499c20346bSAnirudh Venkataramanan #define ICE_DBG_SCHED BIT_ULL(14) 50348048e7SDave Ertman #define ICE_DBG_RDMA BIT_ULL(15) 51c7648810STony Nguyen #define ICE_DBG_PKG BIT_ULL(16) 52f31e4b6fSAnirudh Venkataramanan #define ICE_DBG_RES BIT_ULL(17) 5303cb4473SJacob Keller #define ICE_DBG_PTP BIT_ULL(19) 547ec59eeaSAnirudh Venkataramanan #define ICE_DBG_AQ_MSG BIT_ULL(24) 55faa01721SJacob Keller #define ICE_DBG_AQ_DESC BIT_ULL(25) 56faa01721SJacob Keller #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26) 577ec59eeaSAnirudh Venkataramanan #define ICE_DBG_AQ_CMD BIT_ULL(27) 58*a1ffafb0SBrett Creeley #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \ 59*a1ffafb0SBrett Creeley ICE_DBG_AQ_DESC | \ 60*a1ffafb0SBrett Creeley ICE_DBG_AQ_DESC_BUF | \ 61*a1ffafb0SBrett Creeley ICE_DBG_AQ_CMD) 62*a1ffafb0SBrett Creeley 63fcea6f3dSAnirudh Venkataramanan #define ICE_DBG_USER BIT_ULL(31) 647ec59eeaSAnirudh Venkataramanan 65f31e4b6fSAnirudh Venkataramanan enum ice_aq_res_ids { 66f31e4b6fSAnirudh Venkataramanan ICE_NVM_RES_ID = 1, 67f31e4b6fSAnirudh Venkataramanan ICE_SPD_RES_ID, 68ff2b1321SDan Nowlin ICE_CHANGE_LOCK_RES_ID, 69ff2b1321SDan Nowlin ICE_GLOBAL_CFG_LOCK_RES_ID 70f31e4b6fSAnirudh Venkataramanan }; 71f31e4b6fSAnirudh Venkataramanan 72ff2b1321SDan Nowlin /* FW update timeout definitions are in milliseconds */ 73ff2b1321SDan Nowlin #define ICE_NVM_TIMEOUT 180000 74ff2b1321SDan Nowlin #define ICE_CHANGE_LOCK_TIMEOUT 1000 75fb361284SLiwei Song #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 5000 76ff2b1321SDan Nowlin 77f31e4b6fSAnirudh Venkataramanan enum ice_aq_res_access_type { 78f31e4b6fSAnirudh Venkataramanan ICE_RES_READ = 1, 79f31e4b6fSAnirudh Venkataramanan ICE_RES_WRITE 80f31e4b6fSAnirudh Venkataramanan }; 81f31e4b6fSAnirudh Venkataramanan 82e3710a01SPaul M Stillwell Jr struct ice_driver_ver { 83e3710a01SPaul M Stillwell Jr u8 major_ver; 84e3710a01SPaul M Stillwell Jr u8 minor_ver; 85e3710a01SPaul M Stillwell Jr u8 build_ver; 86e3710a01SPaul M Stillwell Jr u8 subbuild_ver; 87e3710a01SPaul M Stillwell Jr u8 driver_string[32]; 88e3710a01SPaul M Stillwell Jr }; 89e3710a01SPaul M Stillwell Jr 90dc49c772SAnirudh Venkataramanan enum ice_fc_mode { 91dc49c772SAnirudh Venkataramanan ICE_FC_NONE = 0, 92dc49c772SAnirudh Venkataramanan ICE_FC_RX_PAUSE, 93dc49c772SAnirudh Venkataramanan ICE_FC_TX_PAUSE, 94dc49c772SAnirudh Venkataramanan ICE_FC_FULL, 95dc49c772SAnirudh Venkataramanan ICE_FC_PFC, 96dc49c772SAnirudh Venkataramanan ICE_FC_DFLT 97dc49c772SAnirudh Venkataramanan }; 98dc49c772SAnirudh Venkataramanan 991a3571b5SPaul Greenwalt enum ice_phy_cache_mode { 1001a3571b5SPaul Greenwalt ICE_FC_MODE = 0, 1011a3571b5SPaul Greenwalt ICE_SPEED_MODE, 1021a3571b5SPaul Greenwalt ICE_FEC_MODE 1031a3571b5SPaul Greenwalt }; 1041a3571b5SPaul Greenwalt 105f776b3acSPaul Greenwalt enum ice_fec_mode { 106f776b3acSPaul Greenwalt ICE_FEC_NONE = 0, 107f776b3acSPaul Greenwalt ICE_FEC_RS, 108f776b3acSPaul Greenwalt ICE_FEC_BASER, 109f776b3acSPaul Greenwalt ICE_FEC_AUTO 110f776b3acSPaul Greenwalt }; 111f776b3acSPaul Greenwalt 1121a3571b5SPaul Greenwalt struct ice_phy_cache_mode_data { 1131a3571b5SPaul Greenwalt union { 1141a3571b5SPaul Greenwalt enum ice_fec_mode curr_user_fec_req; 1151a3571b5SPaul Greenwalt enum ice_fc_mode curr_user_fc_req; 1161a3571b5SPaul Greenwalt u16 curr_user_speed_req; 1171a3571b5SPaul Greenwalt } data; 1181a3571b5SPaul Greenwalt }; 1191a3571b5SPaul Greenwalt 120fcea6f3dSAnirudh Venkataramanan enum ice_set_fc_aq_failures { 121fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_NONE = 0, 122fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_GET, 123fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_SET, 124fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_UPDATE 125fcea6f3dSAnirudh Venkataramanan }; 126fcea6f3dSAnirudh Venkataramanan 127f31e4b6fSAnirudh Venkataramanan /* Various MAC types */ 128f31e4b6fSAnirudh Venkataramanan enum ice_mac_type { 129f31e4b6fSAnirudh Venkataramanan ICE_MAC_UNKNOWN = 0, 130ea78ce4dSPaul Greenwalt ICE_MAC_E810, 131f31e4b6fSAnirudh Venkataramanan ICE_MAC_GENERIC, 132f31e4b6fSAnirudh Venkataramanan }; 133f31e4b6fSAnirudh Venkataramanan 134dc49c772SAnirudh Venkataramanan /* Media Types */ 135dc49c772SAnirudh Venkataramanan enum ice_media_type { 136dc49c772SAnirudh Venkataramanan ICE_MEDIA_UNKNOWN = 0, 137dc49c772SAnirudh Venkataramanan ICE_MEDIA_FIBER, 138dc49c772SAnirudh Venkataramanan ICE_MEDIA_BASET, 139dc49c772SAnirudh Venkataramanan ICE_MEDIA_BACKPLANE, 140dc49c772SAnirudh Venkataramanan ICE_MEDIA_DA, 141dc49c772SAnirudh Venkataramanan }; 142dc49c772SAnirudh Venkataramanan 1433a858ba3SAnirudh Venkataramanan enum ice_vsi_type { 1443a858ba3SAnirudh Venkataramanan ICE_VSI_PF = 0, 145148beb61SHenry Tieman ICE_VSI_VF = 1, 146148beb61SHenry Tieman ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */ 1470754d65bSKiran Patil ICE_VSI_CHNL = 4, 1480e674aebSAnirudh Venkataramanan ICE_VSI_LB = 6, 149f66756e0SGrzegorz Nitka ICE_VSI_SWITCHDEV_CTRL = 7, 1503a858ba3SAnirudh Venkataramanan }; 1513a858ba3SAnirudh Venkataramanan 152dc49c772SAnirudh Venkataramanan struct ice_link_status { 153dc49c772SAnirudh Venkataramanan /* Refer to ice_aq_phy_type for bits definition */ 154dc49c772SAnirudh Venkataramanan u64 phy_type_low; 155aef74145SAnirudh Venkataramanan u64 phy_type_high; 156f776b3acSPaul Greenwalt u8 topo_media_conflict; 157dc49c772SAnirudh Venkataramanan u16 max_frame_size; 158dc49c772SAnirudh Venkataramanan u16 link_speed; 159ffe49823SChinh T Cao u16 req_speeds; 160c77849f5SAnirudh Venkataramanan u8 link_cfg_err; 16143f8b224SBruce Allan u8 lse_ena; /* Link Status Event notification */ 162dc49c772SAnirudh Venkataramanan u8 link_info; 163dc49c772SAnirudh Venkataramanan u8 an_info; 164dc49c772SAnirudh Venkataramanan u8 ext_info; 165f776b3acSPaul Greenwalt u8 fec_info; 166dc49c772SAnirudh Venkataramanan u8 pacing; 167dc49c772SAnirudh Venkataramanan /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of 168dc49c772SAnirudh Venkataramanan * ice_aqc_get_phy_caps structure 169dc49c772SAnirudh Venkataramanan */ 170dc49c772SAnirudh Venkataramanan u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 171dc49c772SAnirudh Venkataramanan }; 172dc49c772SAnirudh Venkataramanan 173ddf30f7fSAnirudh Venkataramanan /* Different reset sources for which a disable queue AQ call has to be made in 174f9867df6SAnirudh Venkataramanan * order to clean the Tx scheduler as a part of the reset 175ddf30f7fSAnirudh Venkataramanan */ 176ddf30f7fSAnirudh Venkataramanan enum ice_disq_rst_src { 177ddf30f7fSAnirudh Venkataramanan ICE_NO_RESET = 0, 178ddf30f7fSAnirudh Venkataramanan ICE_VM_RESET, 179ddf30f7fSAnirudh Venkataramanan ICE_VF_RESET, 180ddf30f7fSAnirudh Venkataramanan }; 181ddf30f7fSAnirudh Venkataramanan 182dc49c772SAnirudh Venkataramanan /* PHY info such as phy_type, etc... */ 183dc49c772SAnirudh Venkataramanan struct ice_phy_info { 184dc49c772SAnirudh Venkataramanan struct ice_link_status link_info; 185dc49c772SAnirudh Venkataramanan struct ice_link_status link_info_old; 186dc49c772SAnirudh Venkataramanan u64 phy_type_low; 187aef74145SAnirudh Venkataramanan u64 phy_type_high; 188dc49c772SAnirudh Venkataramanan enum ice_media_type media_type; 18943f8b224SBruce Allan u8 get_link_info; 1901a3571b5SPaul Greenwalt /* Please refer to struct ice_aqc_get_link_status_data to get 1911a3571b5SPaul Greenwalt * detail of enable bit in curr_user_speed_req 1921a3571b5SPaul Greenwalt */ 1931a3571b5SPaul Greenwalt u16 curr_user_speed_req; 1941a3571b5SPaul Greenwalt enum ice_fec_mode curr_user_fec_req; 1951a3571b5SPaul Greenwalt enum ice_fc_mode curr_user_fc_req; 1961a3571b5SPaul Greenwalt struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg; 197dc49c772SAnirudh Venkataramanan }; 198dc49c772SAnirudh Venkataramanan 199148beb61SHenry Tieman /* protocol enumeration for filters */ 200148beb61SHenry Tieman enum ice_fltr_ptype { 201148beb61SHenry Tieman /* NONE - used for undef/error */ 202148beb61SHenry Tieman ICE_FLTR_PTYPE_NONF_NONE = 0, 203148beb61SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV4_UDP, 204148beb61SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV4_TCP, 205148beb61SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV4_SCTP, 206148beb61SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV4_OTHER, 207ef9e4cc5SQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP, 208ef9e4cc5SQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP, 209ef9e4cc5SQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP, 210ef9e4cc5SQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER, 211213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER, 212213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3, 213213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3, 214213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_ESP, 215213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV6_ESP, 216213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_AH, 217213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV6_AH, 218213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP, 219213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP, 220213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE, 221213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION, 222213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE, 223213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION, 22421606584SQi Zhang ICE_FLTR_PTYPE_NON_IP_L2, 225148beb61SHenry Tieman ICE_FLTR_PTYPE_FRAG_IPV4, 226165d80d6SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV6_UDP, 227165d80d6SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV6_TCP, 228165d80d6SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV6_SCTP, 229165d80d6SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV6_OTHER, 230148beb61SHenry Tieman ICE_FLTR_PTYPE_MAX, 231148beb61SHenry Tieman }; 232148beb61SHenry Tieman 233148beb61SHenry Tieman enum ice_fd_hw_seg { 234148beb61SHenry Tieman ICE_FD_HW_SEG_NON_TUN = 0, 235148beb61SHenry Tieman ICE_FD_HW_SEG_TUN, 236148beb61SHenry Tieman ICE_FD_HW_SEG_MAX, 237148beb61SHenry Tieman }; 238148beb61SHenry Tieman 23940319796SKiran Patil /* 1 ICE_VSI_PF + 1 ICE_VSI_CTRL + ICE_CHNL_MAX_TC */ 24040319796SKiran Patil #define ICE_MAX_FDIR_VSI_PER_FILTER (2 + ICE_CHNL_MAX_TC) 241148beb61SHenry Tieman 242148beb61SHenry Tieman struct ice_fd_hw_prof { 243148beb61SHenry Tieman struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX]; 244148beb61SHenry Tieman int cnt; 245148beb61SHenry Tieman u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX]; 246148beb61SHenry Tieman u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER]; 247148beb61SHenry Tieman }; 248148beb61SHenry Tieman 2499c20346bSAnirudh Venkataramanan /* Common HW capabilities for SW use */ 2509c20346bSAnirudh Venkataramanan struct ice_hw_common_caps { 251995c90f2SAnirudh Venkataramanan u32 valid_functions; 252a257f188SUsha Ketineni /* DCB capabilities */ 253a257f188SUsha Ketineni u32 active_tc_bitmap; 254a257f188SUsha Ketineni u32 maxtc; 255995c90f2SAnirudh Venkataramanan 256f9867df6SAnirudh Venkataramanan /* Tx/Rx queues */ 257f9867df6SAnirudh Venkataramanan u16 num_rxq; /* Number/Total Rx queues */ 258f9867df6SAnirudh Venkataramanan u16 rxq_first_id; /* First queue ID for Rx queues */ 259f9867df6SAnirudh Venkataramanan u16 num_txq; /* Number/Total Tx queues */ 260f9867df6SAnirudh Venkataramanan u16 txq_first_id; /* First queue ID for Tx queues */ 2619c20346bSAnirudh Venkataramanan 2629c20346bSAnirudh Venkataramanan /* MSI-X vectors */ 2639c20346bSAnirudh Venkataramanan u16 num_msix_vectors; 2649c20346bSAnirudh Venkataramanan u16 msix_vector_first_id; 2659c20346bSAnirudh Venkataramanan 2669c20346bSAnirudh Venkataramanan /* Max MTU for function or device */ 2679c20346bSAnirudh Venkataramanan u16 max_mtu; 2689c20346bSAnirudh Venkataramanan 26975d2b253SAnirudh Venkataramanan /* Virtualization support */ 27075d2b253SAnirudh Venkataramanan u8 sr_iov_1_1; /* SR-IOV enabled */ 271ddf30f7fSAnirudh Venkataramanan 2729c20346bSAnirudh Venkataramanan /* RSS related capabilities */ 2739c20346bSAnirudh Venkataramanan u16 rss_table_size; /* 512 for PFs and 64 for VFs */ 2749c20346bSAnirudh Venkataramanan u8 rss_table_entry_width; /* RSS Entry width in bits */ 27537b6f646SAnirudh Venkataramanan 27637b6f646SAnirudh Venkataramanan u8 dcb; 2779733cc94SJacob Keller u8 ieee_1588; 278d25a0fc4SDave Ertman u8 rdma; 279de9b277eSJacek Naczyk 2802ab560a7SJacob Keller bool nvm_update_pending_nvm; 2812ab560a7SJacob Keller bool nvm_update_pending_orom; 2822ab560a7SJacob Keller bool nvm_update_pending_netlist; 2832ab560a7SJacob Keller #define ICE_NVM_PENDING_NVM_IMAGE BIT(0) 2842ab560a7SJacob Keller #define ICE_NVM_PENDING_OROM BIT(1) 2852ab560a7SJacob Keller #define ICE_NVM_PENDING_NETLIST BIT(2) 286de9b277eSJacek Naczyk bool nvm_unified_update; 287de9b277eSJacek Naczyk #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3) 288399e27dbSJacob Keller /* PCIe reset avoidance */ 289399e27dbSJacob Keller bool pcie_reset_avoidance; 290399e27dbSJacob Keller /* Post update reset restriction */ 291399e27dbSJacob Keller bool reset_restrict_support; 2929c20346bSAnirudh Venkataramanan }; 2939c20346bSAnirudh Venkataramanan 2949733cc94SJacob Keller /* IEEE 1588 TIME_SYNC specific info */ 2959733cc94SJacob Keller /* Function specific definitions */ 2969733cc94SJacob Keller #define ICE_TS_FUNC_ENA_M BIT(0) 2979733cc94SJacob Keller #define ICE_TS_SRC_TMR_OWND_M BIT(1) 2989733cc94SJacob Keller #define ICE_TS_TMR_ENA_M BIT(2) 2999733cc94SJacob Keller #define ICE_TS_TMR_IDX_OWND_S 4 3009733cc94SJacob Keller #define ICE_TS_TMR_IDX_OWND_M BIT(4) 3019733cc94SJacob Keller #define ICE_TS_CLK_FREQ_S 16 3029733cc94SJacob Keller #define ICE_TS_CLK_FREQ_M ICE_M(0x7, ICE_TS_CLK_FREQ_S) 3039733cc94SJacob Keller #define ICE_TS_CLK_SRC_S 20 3049733cc94SJacob Keller #define ICE_TS_CLK_SRC_M BIT(20) 3059733cc94SJacob Keller #define ICE_TS_TMR_IDX_ASSOC_S 24 3069733cc94SJacob Keller #define ICE_TS_TMR_IDX_ASSOC_M BIT(24) 3079733cc94SJacob Keller 308405efa49SJacob Keller /* TIME_REF clock rate specification */ 309405efa49SJacob Keller enum ice_time_ref_freq { 310405efa49SJacob Keller ICE_TIME_REF_FREQ_25_000 = 0, 311405efa49SJacob Keller ICE_TIME_REF_FREQ_122_880 = 1, 312405efa49SJacob Keller ICE_TIME_REF_FREQ_125_000 = 2, 313405efa49SJacob Keller ICE_TIME_REF_FREQ_153_600 = 3, 314405efa49SJacob Keller ICE_TIME_REF_FREQ_156_250 = 4, 315405efa49SJacob Keller ICE_TIME_REF_FREQ_245_760 = 5, 316405efa49SJacob Keller 317405efa49SJacob Keller NUM_ICE_TIME_REF_FREQ 318405efa49SJacob Keller }; 319405efa49SJacob Keller 320405efa49SJacob Keller /* Clock source specification */ 321405efa49SJacob Keller enum ice_clk_src { 322405efa49SJacob Keller ICE_CLK_SRC_TCX0 = 0, /* Temperature compensated oscillator */ 323405efa49SJacob Keller ICE_CLK_SRC_TIME_REF = 1, /* Use TIME_REF reference clock */ 324405efa49SJacob Keller 325405efa49SJacob Keller NUM_ICE_CLK_SRC 326405efa49SJacob Keller }; 327405efa49SJacob Keller 3289733cc94SJacob Keller struct ice_ts_func_info { 3299733cc94SJacob Keller /* Function specific info */ 330405efa49SJacob Keller enum ice_time_ref_freq time_ref; 331405efa49SJacob Keller u8 clk_freq; 3329733cc94SJacob Keller u8 clk_src; 3339733cc94SJacob Keller u8 tmr_index_assoc; 3349733cc94SJacob Keller u8 ena; 3359733cc94SJacob Keller u8 tmr_index_owned; 3369733cc94SJacob Keller u8 src_tmr_owned; 3379733cc94SJacob Keller u8 tmr_ena; 3389733cc94SJacob Keller }; 3399733cc94SJacob Keller 3409733cc94SJacob Keller /* Device specific definitions */ 3419733cc94SJacob Keller #define ICE_TS_TMR0_OWNR_M 0x7 3429733cc94SJacob Keller #define ICE_TS_TMR0_OWND_M BIT(3) 3439733cc94SJacob Keller #define ICE_TS_TMR1_OWNR_S 4 3449733cc94SJacob Keller #define ICE_TS_TMR1_OWNR_M ICE_M(0x7, ICE_TS_TMR1_OWNR_S) 3459733cc94SJacob Keller #define ICE_TS_TMR1_OWND_M BIT(7) 3469733cc94SJacob Keller #define ICE_TS_DEV_ENA_M BIT(24) 3479733cc94SJacob Keller #define ICE_TS_TMR0_ENA_M BIT(25) 3489733cc94SJacob Keller #define ICE_TS_TMR1_ENA_M BIT(26) 3499733cc94SJacob Keller 3509733cc94SJacob Keller struct ice_ts_dev_info { 3519733cc94SJacob Keller /* Device specific info */ 3529733cc94SJacob Keller u32 ena_ports; 3539733cc94SJacob Keller u32 tmr_own_map; 3549733cc94SJacob Keller u32 tmr0_owner; 3559733cc94SJacob Keller u32 tmr1_owner; 3569733cc94SJacob Keller u8 tmr0_owned; 3579733cc94SJacob Keller u8 tmr1_owned; 3589733cc94SJacob Keller u8 ena; 3599733cc94SJacob Keller u8 tmr0_ena; 3609733cc94SJacob Keller u8 tmr1_ena; 3619733cc94SJacob Keller }; 3629733cc94SJacob Keller 3639c20346bSAnirudh Venkataramanan /* Function specific capabilities */ 3649c20346bSAnirudh Venkataramanan struct ice_hw_func_caps { 3659c20346bSAnirudh Venkataramanan struct ice_hw_common_caps common_cap; 36675d2b253SAnirudh Venkataramanan u32 num_allocd_vfs; /* Number of allocated VFs */ 36775d2b253SAnirudh Venkataramanan u32 vf_base_id; /* Logical ID of the first VF */ 368995c90f2SAnirudh Venkataramanan u32 guar_num_vsi; 369148beb61SHenry Tieman u32 fd_fltr_guar; /* Number of filters guaranteed */ 370148beb61SHenry Tieman u32 fd_fltr_best_effort; /* Number of best effort filters */ 3719733cc94SJacob Keller struct ice_ts_func_info ts_func_info; 3729c20346bSAnirudh Venkataramanan }; 3739c20346bSAnirudh Venkataramanan 3749c20346bSAnirudh Venkataramanan /* Device wide capabilities */ 3759c20346bSAnirudh Venkataramanan struct ice_hw_dev_caps { 3769c20346bSAnirudh Venkataramanan struct ice_hw_common_caps common_cap; 37775d2b253SAnirudh Venkataramanan u32 num_vfs_exposed; /* Total number of VFs exposed */ 3789c20346bSAnirudh Venkataramanan u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ 379148beb61SHenry Tieman u32 num_flow_director_fltr; /* Number of FD filters available */ 3809733cc94SJacob Keller struct ice_ts_dev_info ts_dev_info; 381eae1bbb2SBruce Allan u32 num_funcs; 3829c20346bSAnirudh Venkataramanan }; 3839c20346bSAnirudh Venkataramanan 384dc49c772SAnirudh Venkataramanan /* MAC info */ 385dc49c772SAnirudh Venkataramanan struct ice_mac_info { 386dc49c772SAnirudh Venkataramanan u8 lan_addr[ETH_ALEN]; 387dc49c772SAnirudh Venkataramanan u8 perm_addr[ETH_ALEN]; 388dc49c772SAnirudh Venkataramanan }; 389dc49c772SAnirudh Venkataramanan 390ca4929b6SBrett Creeley /* Reset types used to determine which kind of reset was requested. These 391ca4929b6SBrett Creeley * defines match what the RESET_TYPE field of the GLGEN_RSTAT register. 392ca4929b6SBrett Creeley * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register 393ca4929b6SBrett Creeley * because its reset source is different than the other types listed. 394ca4929b6SBrett Creeley */ 395f31e4b6fSAnirudh Venkataramanan enum ice_reset_req { 396ca4929b6SBrett Creeley ICE_RESET_POR = 0, 3970f9d5027SAnirudh Venkataramanan ICE_RESET_INVAL = 0, 398ca4929b6SBrett Creeley ICE_RESET_CORER = 1, 399ca4929b6SBrett Creeley ICE_RESET_GLOBR = 2, 400ca4929b6SBrett Creeley ICE_RESET_EMPR = 3, 401ca4929b6SBrett Creeley ICE_RESET_PFR = 4, 402f31e4b6fSAnirudh Venkataramanan }; 403f31e4b6fSAnirudh Venkataramanan 404837f08fdSAnirudh Venkataramanan /* Bus parameters */ 405837f08fdSAnirudh Venkataramanan struct ice_bus_info { 406837f08fdSAnirudh Venkataramanan u16 device; 407837f08fdSAnirudh Venkataramanan u8 func; 408837f08fdSAnirudh Venkataramanan }; 409837f08fdSAnirudh Venkataramanan 410dc49c772SAnirudh Venkataramanan /* Flow control (FC) parameters */ 411dc49c772SAnirudh Venkataramanan struct ice_fc_info { 412dc49c772SAnirudh Venkataramanan enum ice_fc_mode current_mode; /* FC mode in effect */ 413dc49c772SAnirudh Venkataramanan enum ice_fc_mode req_mode; /* FC mode requested by caller */ 414dc49c772SAnirudh Venkataramanan }; 415dc49c772SAnirudh Venkataramanan 416d4e87444SJacob Keller /* Option ROM version information */ 417d4e87444SJacob Keller struct ice_orom_info { 418d4e87444SJacob Keller u8 major; /* Major version of OROM */ 419d4e87444SJacob Keller u8 patch; /* Patch version of OROM */ 420d4e87444SJacob Keller u16 build; /* Build version of OROM */ 421d4e87444SJacob Keller }; 422d4e87444SJacob Keller 4239af368faSJacob Keller /* NVM version information */ 424f31e4b6fSAnirudh Venkataramanan struct ice_nvm_info { 4259af368faSJacob Keller u32 eetrack; 4269af368faSJacob Keller u8 major; 4279af368faSJacob Keller u8 minor; 4289af368faSJacob Keller }; 4299af368faSJacob Keller 4309af368faSJacob Keller /* netlist version information */ 4319af368faSJacob Keller struct ice_netlist_info { 4329af368faSJacob Keller u32 major; /* major high/low */ 4339af368faSJacob Keller u32 minor; /* minor high/low */ 4349af368faSJacob Keller u32 type; /* type high/low */ 4359af368faSJacob Keller u32 rev; /* revision high/low */ 4369af368faSJacob Keller u32 hash; /* SHA-1 hash word */ 4379af368faSJacob Keller u16 cust_ver; /* customer version */ 4389af368faSJacob Keller }; 4399af368faSJacob Keller 4401fa95e01SJacob Keller /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules 4411fa95e01SJacob Keller * of the flash image. 4421fa95e01SJacob Keller */ 4431fa95e01SJacob Keller enum ice_flash_bank { 4441fa95e01SJacob Keller ICE_INVALID_FLASH_BANK, 4451fa95e01SJacob Keller ICE_1ST_FLASH_BANK, 4461fa95e01SJacob Keller ICE_2ND_FLASH_BANK, 4471fa95e01SJacob Keller }; 4481fa95e01SJacob Keller 4490ce50c70SJacob Keller /* Enumeration of which flash bank is desired to read from, either the active 4500ce50c70SJacob Keller * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from 4510ce50c70SJacob Keller * code which just wants to read the active or inactive flash bank. 4520ce50c70SJacob Keller */ 4530ce50c70SJacob Keller enum ice_bank_select { 4540ce50c70SJacob Keller ICE_ACTIVE_FLASH_BANK, 4550ce50c70SJacob Keller ICE_INACTIVE_FLASH_BANK, 4560ce50c70SJacob Keller }; 4570ce50c70SJacob Keller 4581fa95e01SJacob Keller /* information for accessing NVM, OROM, and Netlist flash banks */ 4591fa95e01SJacob Keller struct ice_bank_info { 4601fa95e01SJacob Keller u32 nvm_ptr; /* Pointer to 1st NVM bank */ 4611fa95e01SJacob Keller u32 nvm_size; /* Size of NVM bank */ 4621fa95e01SJacob Keller u32 orom_ptr; /* Pointer to 1st OROM bank */ 4631fa95e01SJacob Keller u32 orom_size; /* Size of OROM bank */ 4641fa95e01SJacob Keller u32 netlist_ptr; /* Pointer to 1st Netlist bank */ 4651fa95e01SJacob Keller u32 netlist_size; /* Size of Netlist bank */ 4661fa95e01SJacob Keller enum ice_flash_bank nvm_bank; /* Active NVM bank */ 4671fa95e01SJacob Keller enum ice_flash_bank orom_bank; /* Active OROM bank */ 4681fa95e01SJacob Keller enum ice_flash_bank netlist_bank; /* Active Netlist bank */ 4691fa95e01SJacob Keller }; 4701fa95e01SJacob Keller 4719af368faSJacob Keller /* Flash Chip Information */ 4729af368faSJacob Keller struct ice_flash_info { 473d4e87444SJacob Keller struct ice_orom_info orom; /* Option ROM version info */ 4749af368faSJacob Keller struct ice_nvm_info nvm; /* NVM version information */ 4759af368faSJacob Keller struct ice_netlist_info netlist;/* Netlist version info */ 4761fa95e01SJacob Keller struct ice_bank_info banks; /* Flash Bank information */ 477f31e4b6fSAnirudh Venkataramanan u16 sr_words; /* Shadow RAM size in words */ 47881f07491SJacob Keller u32 flash_size; /* Size of available flash in bytes */ 47943f8b224SBruce Allan u8 blank_nvm_mode; /* is NVM empty (no FW present) */ 480f31e4b6fSAnirudh Venkataramanan }; 481f31e4b6fSAnirudh Venkataramanan 482ea78ce4dSPaul Greenwalt struct ice_link_default_override_tlv { 483ea78ce4dSPaul Greenwalt u8 options; 484ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_OPT_M 0x3F 485ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0) 486ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1) 487ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2) 488ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_EN BIT(3) 489ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4) 490ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_EEE_EN BIT(5) 491ea78ce4dSPaul Greenwalt u8 phy_config; 492ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_PHY_CFG_S 8 493ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S) 494ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_PAUSE_M 0x3 495ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_LESM_EN BIT(6) 496ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7) 497ea78ce4dSPaul Greenwalt u8 fec_options; 498ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF 499ea78ce4dSPaul Greenwalt u8 rsvd1; 500ea78ce4dSPaul Greenwalt u64 phy_type_low; 501ea78ce4dSPaul Greenwalt u64 phy_type_high; 502ea78ce4dSPaul Greenwalt }; 503ea78ce4dSPaul Greenwalt 504870f805eSLukasz Czapnik #define ICE_NVM_VER_LEN 32 505870f805eSLukasz Czapnik 5069c20346bSAnirudh Venkataramanan /* Max number of port to queue branches w.r.t topology */ 5079c20346bSAnirudh Venkataramanan #define ICE_MAX_TRAFFIC_CLASS 8 508dc49c772SAnirudh Venkataramanan #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS 5099c20346bSAnirudh Venkataramanan 5102bdc97beSBruce Allan #define ice_for_each_traffic_class(_i) \ 5112bdc97beSBruce Allan for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++) 5122bdc97beSBruce Allan 513b126bd6bSKiran Patil /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects 514b126bd6bSKiran Patil * to driver defined policy for default aggregator 515b126bd6bSKiran Patil */ 5167b9ffc76SAnirudh Venkataramanan #define ICE_INVAL_TEID 0xFFFFFFFF 517b126bd6bSKiran Patil #define ICE_DFLT_AGG_ID 0 5187b9ffc76SAnirudh Venkataramanan 5199c20346bSAnirudh Venkataramanan struct ice_sched_node { 5209c20346bSAnirudh Venkataramanan struct ice_sched_node *parent; 5219c20346bSAnirudh Venkataramanan struct ice_sched_node *sibling; /* next sibling in the same layer */ 5229c20346bSAnirudh Venkataramanan struct ice_sched_node **children; 5239c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_elem_data info; 524f9867df6SAnirudh Venkataramanan u32 agg_id; /* aggregator group ID */ 5254fb33f31SAnirudh Venkataramanan u16 vsi_handle; 52643f8b224SBruce Allan u8 in_use; /* suspended or in use */ 5279c20346bSAnirudh Venkataramanan u8 tx_sched_layer; /* Logical Layer (1-9) */ 5289c20346bSAnirudh Venkataramanan u8 num_children; 5299c20346bSAnirudh Venkataramanan u8 tc_num; 5309c20346bSAnirudh Venkataramanan u8 owner; 5319c20346bSAnirudh Venkataramanan #define ICE_SCHED_NODE_OWNER_LAN 0 532348048e7SDave Ertman #define ICE_SCHED_NODE_OWNER_RDMA 2 5339c20346bSAnirudh Venkataramanan }; 5349c20346bSAnirudh Venkataramanan 535dc49c772SAnirudh Venkataramanan /* Access Macros for Tx Sched Elements data */ 536dc49c772SAnirudh Venkataramanan #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid) 537dc49c772SAnirudh Venkataramanan 5389c20346bSAnirudh Venkataramanan /* The aggregator type determines if identifier is for a VSI group, 5399c20346bSAnirudh Venkataramanan * aggregator group, aggregator of queues, or queue group. 5409c20346bSAnirudh Venkataramanan */ 5419c20346bSAnirudh Venkataramanan enum ice_agg_type { 5429c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_UNKNOWN = 0, 5439c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_VSI, 5449c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_AGG, /* aggregator */ 5459c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_Q, 5469c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_QG 5479c20346bSAnirudh Venkataramanan }; 5489c20346bSAnirudh Venkataramanan 5491ddef455SUsha Ketineni /* Rate limit types */ 5501ddef455SUsha Ketineni enum ice_rl_type { 5511ddef455SUsha Ketineni ICE_UNKNOWN_BW = 0, 5521ddef455SUsha Ketineni ICE_MIN_BW, /* for CIR profile */ 5531ddef455SUsha Ketineni ICE_MAX_BW, /* for EIR profile */ 5541ddef455SUsha Ketineni ICE_SHARED_BW /* for shared profile */ 5551ddef455SUsha Ketineni }; 5565513b920SAnirudh Venkataramanan 5571ddef455SUsha Ketineni #define ICE_SCHED_MIN_BW 500 /* in Kbps */ 5581ddef455SUsha Ketineni #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */ 5591ddef455SUsha Ketineni #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */ 5601ddef455SUsha Ketineni #define ICE_SCHED_DFLT_RL_PROF_ID 0 5611ddef455SUsha Ketineni #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF 562984824a2STarun Singh #define ICE_SCHED_DFLT_BW_WT 4 5631ddef455SUsha Ketineni #define ICE_SCHED_INVAL_PROF_ID 0xFFFF 5641ddef455SUsha Ketineni #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */ 5651ddef455SUsha Ketineni 5661ddef455SUsha Ketineni /* Data structure for saving BW information */ 5671ddef455SUsha Ketineni enum ice_bw_type { 5681ddef455SUsha Ketineni ICE_BW_TYPE_PRIO, 5691ddef455SUsha Ketineni ICE_BW_TYPE_CIR, 5701ddef455SUsha Ketineni ICE_BW_TYPE_CIR_WT, 5711ddef455SUsha Ketineni ICE_BW_TYPE_EIR, 5721ddef455SUsha Ketineni ICE_BW_TYPE_EIR_WT, 5731ddef455SUsha Ketineni ICE_BW_TYPE_SHARED, 5741ddef455SUsha Ketineni ICE_BW_TYPE_CNT /* This must be last */ 5751ddef455SUsha Ketineni }; 5761ddef455SUsha Ketineni 5771ddef455SUsha Ketineni struct ice_bw { 5781ddef455SUsha Ketineni u32 bw; 5791ddef455SUsha Ketineni u16 bw_alloc; 5801ddef455SUsha Ketineni }; 5811ddef455SUsha Ketineni 5821ddef455SUsha Ketineni struct ice_bw_type_info { 5831ddef455SUsha Ketineni DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT); 5841ddef455SUsha Ketineni u8 generic; 5851ddef455SUsha Ketineni struct ice_bw cir_bw; 5861ddef455SUsha Ketineni struct ice_bw eir_bw; 5871ddef455SUsha Ketineni u32 shared_bw; 5881ddef455SUsha Ketineni }; 5891ddef455SUsha Ketineni 5901ddef455SUsha Ketineni /* VSI queue context structure for given TC */ 5911ddef455SUsha Ketineni struct ice_q_ctx { 5921ddef455SUsha Ketineni u16 q_handle; 5931ddef455SUsha Ketineni u32 q_teid; 5941ddef455SUsha Ketineni /* bw_t_info saves queue BW information */ 5951ddef455SUsha Ketineni struct ice_bw_type_info bw_t_info; 5961ddef455SUsha Ketineni }; 5971ddef455SUsha Ketineni 5981ddef455SUsha Ketineni /* VSI type list entry to locate corresponding VSI/aggregator nodes */ 5999c20346bSAnirudh Venkataramanan struct ice_sched_vsi_info { 6009c20346bSAnirudh Venkataramanan struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS]; 6019c20346bSAnirudh Venkataramanan struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS]; 6029c20346bSAnirudh Venkataramanan struct list_head list_entry; 6039c20346bSAnirudh Venkataramanan u16 max_lanq[ICE_MAX_TRAFFIC_CLASS]; 604348048e7SDave Ertman u16 max_rdmaq[ICE_MAX_TRAFFIC_CLASS]; 6050754d65bSKiran Patil /* bw_t_info saves VSI BW information */ 6060754d65bSKiran Patil struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS]; 6079c20346bSAnirudh Venkataramanan }; 6089c20346bSAnirudh Venkataramanan 6099c20346bSAnirudh Venkataramanan /* driver defines the policy */ 6109c20346bSAnirudh Venkataramanan struct ice_sched_tx_policy { 6119c20346bSAnirudh Venkataramanan u16 max_num_vsis; 6129c20346bSAnirudh Venkataramanan u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS]; 61343f8b224SBruce Allan u8 rdma_ena; 6149c20346bSAnirudh Venkataramanan }; 6159c20346bSAnirudh Venkataramanan 6160ebd3ff1SAnirudh Venkataramanan /* CEE or IEEE 802.1Qaz ETS Configuration data */ 6170ebd3ff1SAnirudh Venkataramanan struct ice_dcb_ets_cfg { 6180ebd3ff1SAnirudh Venkataramanan u8 willing; 6190ebd3ff1SAnirudh Venkataramanan u8 cbs; 6200ebd3ff1SAnirudh Venkataramanan u8 maxtcs; 6210ebd3ff1SAnirudh Venkataramanan u8 prio_table[ICE_MAX_TRAFFIC_CLASS]; 6220ebd3ff1SAnirudh Venkataramanan u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS]; 6230ebd3ff1SAnirudh Venkataramanan u8 tsatable[ICE_MAX_TRAFFIC_CLASS]; 6240ebd3ff1SAnirudh Venkataramanan }; 6250ebd3ff1SAnirudh Venkataramanan 6260ebd3ff1SAnirudh Venkataramanan /* CEE or IEEE 802.1Qaz PFC Configuration data */ 6270ebd3ff1SAnirudh Venkataramanan struct ice_dcb_pfc_cfg { 6280ebd3ff1SAnirudh Venkataramanan u8 willing; 6290ebd3ff1SAnirudh Venkataramanan u8 mbc; 6300ebd3ff1SAnirudh Venkataramanan u8 pfccap; 6310ebd3ff1SAnirudh Venkataramanan u8 pfcena; 6320ebd3ff1SAnirudh Venkataramanan }; 6330ebd3ff1SAnirudh Venkataramanan 6340ebd3ff1SAnirudh Venkataramanan /* CEE or IEEE 802.1Qaz Application Priority data */ 6350ebd3ff1SAnirudh Venkataramanan struct ice_dcb_app_priority_table { 6360ebd3ff1SAnirudh Venkataramanan u16 prot_id; 6370ebd3ff1SAnirudh Venkataramanan u8 priority; 6380ebd3ff1SAnirudh Venkataramanan u8 selector; 6390ebd3ff1SAnirudh Venkataramanan }; 6400ebd3ff1SAnirudh Venkataramanan 6410ebd3ff1SAnirudh Venkataramanan #define ICE_MAX_USER_PRIORITY 8 6422a87bd73SDave Ertman #define ICE_DCBX_MAX_APPS 64 6432a87bd73SDave Ertman #define ICE_DSCP_NUM_VAL 64 6440ebd3ff1SAnirudh Venkataramanan #define ICE_LLDPDU_SIZE 1500 6450ebd3ff1SAnirudh Venkataramanan #define ICE_TLV_STATUS_OPER 0x1 6460ebd3ff1SAnirudh Venkataramanan #define ICE_TLV_STATUS_SYNC 0x2 6470ebd3ff1SAnirudh Venkataramanan #define ICE_TLV_STATUS_ERR 0x4 648aeac8ce8SChinh T Cao #define ICE_APP_PROT_ID_ISCSI_860 0x035c 6490ebd3ff1SAnirudh Venkataramanan #define ICE_APP_SEL_ETHTYPE 0x1 6500ebd3ff1SAnirudh Venkataramanan #define ICE_APP_SEL_TCPIP 0x2 6510ebd3ff1SAnirudh Venkataramanan #define ICE_CEE_APP_SEL_ETHTYPE 0x0 652ea78ce4dSPaul Greenwalt #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134 6530ebd3ff1SAnirudh Venkataramanan #define ICE_CEE_APP_SEL_TCPIP 0x1 6540ebd3ff1SAnirudh Venkataramanan 6550ebd3ff1SAnirudh Venkataramanan struct ice_dcbx_cfg { 6560ebd3ff1SAnirudh Venkataramanan u32 numapps; 6570ebd3ff1SAnirudh Venkataramanan u32 tlv_status; /* CEE mode TLV status */ 6580ebd3ff1SAnirudh Venkataramanan struct ice_dcb_ets_cfg etscfg; 6590ebd3ff1SAnirudh Venkataramanan struct ice_dcb_ets_cfg etsrec; 6600ebd3ff1SAnirudh Venkataramanan struct ice_dcb_pfc_cfg pfc; 6612a87bd73SDave Ertman #define ICE_QOS_MODE_VLAN 0x0 6622a87bd73SDave Ertman #define ICE_QOS_MODE_DSCP 0x1 6632a87bd73SDave Ertman u8 pfc_mode; 6640ebd3ff1SAnirudh Venkataramanan struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS]; 6652a87bd73SDave Ertman /* when DSCP mapping defined by user set its bit to 1 */ 6662a87bd73SDave Ertman DECLARE_BITMAP(dscp_mapped, ICE_DSCP_NUM_VAL); 6672a87bd73SDave Ertman /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */ 6682a87bd73SDave Ertman u8 dscp_map[ICE_DSCP_NUM_VAL]; 6690ebd3ff1SAnirudh Venkataramanan u8 dcbx_mode; 6700ebd3ff1SAnirudh Venkataramanan #define ICE_DCBX_MODE_CEE 0x1 6710ebd3ff1SAnirudh Venkataramanan #define ICE_DCBX_MODE_IEEE 0x2 6720ebd3ff1SAnirudh Venkataramanan u8 app_mode; 6730ebd3ff1SAnirudh Venkataramanan #define ICE_DCBX_APPS_NON_WILLING 0x1 6740ebd3ff1SAnirudh Venkataramanan }; 6750ebd3ff1SAnirudh Venkataramanan 676fc2d1165SChinh T Cao struct ice_qos_cfg { 677fc2d1165SChinh T Cao struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */ 678fc2d1165SChinh T Cao struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */ 679fc2d1165SChinh T Cao struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */ 680fc2d1165SChinh T Cao u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */ 681fc2d1165SChinh T Cao u8 is_sw_lldp : 1; 682fc2d1165SChinh T Cao }; 683fc2d1165SChinh T Cao 6849c20346bSAnirudh Venkataramanan struct ice_port_info { 6859c20346bSAnirudh Venkataramanan struct ice_sched_node *root; /* Root Node per Port */ 686f9867df6SAnirudh Venkataramanan struct ice_hw *hw; /* back pointer to HW instance */ 687dc49c772SAnirudh Venkataramanan u32 last_node_teid; /* scheduler last node info */ 6889c20346bSAnirudh Venkataramanan u16 sw_id; /* Initial switch ID belongs to port */ 6899c20346bSAnirudh Venkataramanan u16 pf_vf_num; 6909c20346bSAnirudh Venkataramanan u8 port_state; 6919c20346bSAnirudh Venkataramanan #define ICE_SCHED_PORT_STATE_INIT 0x0 6929c20346bSAnirudh Venkataramanan #define ICE_SCHED_PORT_STATE_READY 0x1 6930437f1a9SJesse Brandeburg u8 lport; 6940437f1a9SJesse Brandeburg #define ICE_LPORT_MASK 0xff 695e94d4478SAnirudh Venkataramanan u16 dflt_tx_vsi_rule_id; 6969c20346bSAnirudh Venkataramanan u16 dflt_tx_vsi_num; 697e94d4478SAnirudh Venkataramanan u16 dflt_rx_vsi_rule_id; 6989c20346bSAnirudh Venkataramanan u16 dflt_rx_vsi_num; 699dc49c772SAnirudh Venkataramanan struct ice_fc_info fc; 700dc49c772SAnirudh Venkataramanan struct ice_mac_info mac; 701dc49c772SAnirudh Venkataramanan struct ice_phy_info phy; 7029c20346bSAnirudh Venkataramanan struct mutex sched_lock; /* protect access to TXSched tree */ 70329358248SVictor Raj struct ice_sched_node * 70429358248SVictor Raj sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM]; 7051ddef455SUsha Ketineni /* List contain profile ID(s) and other params per layer */ 7061ddef455SUsha Ketineni struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 707fc2d1165SChinh T Cao struct ice_qos_cfg qos_cfg; 7080437f1a9SJesse Brandeburg u8 is_vf:1; 7099c20346bSAnirudh Venkataramanan }; 7109c20346bSAnirudh Venkataramanan 7119daf8208SAnirudh Venkataramanan struct ice_switch_info { 7129daf8208SAnirudh Venkataramanan struct list_head vsi_list_map_head; 71380d144c9SAnirudh Venkataramanan struct ice_sw_recipe *recp_list; 7140f94570dSGrishma Kotecha u16 prof_res_bm_init; 715450052a4SDan Nowlin u16 max_used_prof_index; 716450052a4SDan Nowlin 717450052a4SDan Nowlin DECLARE_BITMAP(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS); 7189daf8208SAnirudh Venkataramanan }; 7199daf8208SAnirudh Venkataramanan 7208b97ceb1SHieu Tran /* FW logging configuration */ 7218b97ceb1SHieu Tran struct ice_fw_log_evnt { 7228b97ceb1SHieu Tran u8 cfg : 4; /* New event enables to configure */ 7238b97ceb1SHieu Tran u8 cur : 4; /* Current/active event enables */ 7248b97ceb1SHieu Tran }; 7258b97ceb1SHieu Tran 7268b97ceb1SHieu Tran struct ice_fw_log_cfg { 7278b97ceb1SHieu Tran u8 cq_en : 1; /* FW logging is enabled via the control queue */ 7288b97ceb1SHieu Tran u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */ 7298b97ceb1SHieu Tran u8 actv_evnts; /* Cumulation of currently enabled log events */ 7308b97ceb1SHieu Tran 7318b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S) 7328b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S) 7338b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S) 7348b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S) 7358b97ceb1SHieu Tran struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX]; 7368b97ceb1SHieu Tran }; 7378b97ceb1SHieu Tran 7380891c896SVignesh Sridhar /* Enum defining the different states of the mailbox snapshot in the 7390891c896SVignesh Sridhar * PF-VF mailbox overflow detection algorithm. The snapshot can be in 7400891c896SVignesh Sridhar * states: 7410891c896SVignesh Sridhar * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot 7420891c896SVignesh Sridhar * within the mailbox buffer. 7430891c896SVignesh Sridhar * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot 7440891c896SVignesh Sridhar * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the 7450891c896SVignesh Sridhar * mailbox and mark any VFs sending more messages than the threshold limit set. 7460891c896SVignesh Sridhar * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF. 7470891c896SVignesh Sridhar */ 7480891c896SVignesh Sridhar enum ice_mbx_snapshot_state { 7490891c896SVignesh Sridhar ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0, 7500891c896SVignesh Sridhar ICE_MAL_VF_DETECT_STATE_TRAVERSE, 7510891c896SVignesh Sridhar ICE_MAL_VF_DETECT_STATE_DETECT, 7520891c896SVignesh Sridhar ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF, 7530891c896SVignesh Sridhar }; 7540891c896SVignesh Sridhar 7550891c896SVignesh Sridhar /* Structure to hold information of the static snapshot and the mailbox 7560891c896SVignesh Sridhar * buffer data used to generate and track the snapshot. 7570891c896SVignesh Sridhar * 1. state: the state of the mailbox snapshot in the malicious VF 7580891c896SVignesh Sridhar * detection state handler ice_mbx_vf_state_handler() 7590891c896SVignesh Sridhar * 2. head: head of the mailbox snapshot in a circular mailbox buffer 7600891c896SVignesh Sridhar * 3. tail: tail of the mailbox snapshot in a circular mailbox buffer 7610891c896SVignesh Sridhar * 4. num_iterations: number of messages traversed in circular mailbox buffer 7620891c896SVignesh Sridhar * 5. num_msg_proc: number of messages processed in mailbox 7630891c896SVignesh Sridhar * 6. num_pending_arq: number of pending asynchronous messages 7640891c896SVignesh Sridhar * 7. max_num_msgs_mbx: maximum messages in mailbox for currently 7650891c896SVignesh Sridhar * serviced work item or interrupt. 7660891c896SVignesh Sridhar */ 7670891c896SVignesh Sridhar struct ice_mbx_snap_buffer_data { 7680891c896SVignesh Sridhar enum ice_mbx_snapshot_state state; 7690891c896SVignesh Sridhar u32 head; 7700891c896SVignesh Sridhar u32 tail; 7710891c896SVignesh Sridhar u32 num_iterations; 7720891c896SVignesh Sridhar u16 num_msg_proc; 7730891c896SVignesh Sridhar u16 num_pending_arq; 7740891c896SVignesh Sridhar u16 max_num_msgs_mbx; 7750891c896SVignesh Sridhar }; 7760891c896SVignesh Sridhar 7770891c896SVignesh Sridhar /* Structure to track messages sent by VFs on mailbox: 7780891c896SVignesh Sridhar * 1. vf_cntr: a counter array of VFs to track the number of 7790891c896SVignesh Sridhar * asynchronous messages sent by each VF 7800891c896SVignesh Sridhar * 2. vfcntr_len: number of entries in VF counter array 7810891c896SVignesh Sridhar */ 7820891c896SVignesh Sridhar struct ice_mbx_vf_counter { 7830891c896SVignesh Sridhar u32 *vf_cntr; 7840891c896SVignesh Sridhar u32 vfcntr_len; 7850891c896SVignesh Sridhar }; 7860891c896SVignesh Sridhar 7870891c896SVignesh Sridhar /* Structure to hold data relevant to the captured static snapshot 7880891c896SVignesh Sridhar * of the PF-VF mailbox. 7890891c896SVignesh Sridhar */ 7900891c896SVignesh Sridhar struct ice_mbx_snapshot { 7910891c896SVignesh Sridhar struct ice_mbx_snap_buffer_data mbx_buf; 7920891c896SVignesh Sridhar struct ice_mbx_vf_counter mbx_vf; 7930891c896SVignesh Sridhar }; 7940891c896SVignesh Sridhar 7950891c896SVignesh Sridhar /* Structure to hold data to be used for capturing or updating a 7960891c896SVignesh Sridhar * static snapshot. 7970891c896SVignesh Sridhar * 1. num_msg_proc: number of messages processed in mailbox 7980891c896SVignesh Sridhar * 2. num_pending_arq: number of pending asynchronous messages 7990891c896SVignesh Sridhar * 3. max_num_msgs_mbx: maximum messages in mailbox for currently 8000891c896SVignesh Sridhar * serviced work item or interrupt. 8010891c896SVignesh Sridhar * 4. async_watermark_val: An upper threshold set by caller to determine 8020891c896SVignesh Sridhar * if the pending arq count is large enough to assume that there is 8030891c896SVignesh Sridhar * the possibility of a mailicious VF. 8040891c896SVignesh Sridhar */ 8050891c896SVignesh Sridhar struct ice_mbx_data { 8060891c896SVignesh Sridhar u16 num_msg_proc; 8070891c896SVignesh Sridhar u16 num_pending_arq; 8080891c896SVignesh Sridhar u16 max_num_msgs_mbx; 8090891c896SVignesh Sridhar u16 async_watermark_val; 8100891c896SVignesh Sridhar }; 8110891c896SVignesh Sridhar 812837f08fdSAnirudh Venkataramanan /* Port hardware description */ 813837f08fdSAnirudh Venkataramanan struct ice_hw { 814837f08fdSAnirudh Venkataramanan u8 __iomem *hw_addr; 815837f08fdSAnirudh Venkataramanan void *back; 8169c20346bSAnirudh Venkataramanan struct ice_aqc_layer_props *layer_info; 8179c20346bSAnirudh Venkataramanan struct ice_port_info *port_info; 8184f8a1497SBen Shelton /* PSM clock frequency for calculating RL profile params */ 8194f8a1497SBen Shelton u32 psm_clk_freq; 8207ec59eeaSAnirudh Venkataramanan u64 debug_mask; /* bitmap for debug mask */ 821f31e4b6fSAnirudh Venkataramanan enum ice_mac_type mac_type; 822837f08fdSAnirudh Venkataramanan 823148beb61SHenry Tieman u16 fd_ctr_base; /* FD counter base index */ 824148beb61SHenry Tieman 825837f08fdSAnirudh Venkataramanan /* pci info */ 826837f08fdSAnirudh Venkataramanan u16 device_id; 827837f08fdSAnirudh Venkataramanan u16 vendor_id; 828837f08fdSAnirudh Venkataramanan u16 subsystem_device_id; 829837f08fdSAnirudh Venkataramanan u16 subsystem_vendor_id; 830837f08fdSAnirudh Venkataramanan u8 revision_id; 831837f08fdSAnirudh Venkataramanan 832f31e4b6fSAnirudh Venkataramanan u8 pf_id; /* device profile info */ 833f31e4b6fSAnirudh Venkataramanan 8341ddef455SUsha Ketineni u16 max_burst_size; /* driver sets this value */ 8351ddef455SUsha Ketineni 836f9867df6SAnirudh Venkataramanan /* Tx Scheduler values */ 83788865fc4SKarol Kolacinski u8 num_tx_sched_layers; 83888865fc4SKarol Kolacinski u8 num_tx_sched_phys_layers; 8399c20346bSAnirudh Venkataramanan u8 flattened_layers; 8409c20346bSAnirudh Venkataramanan u8 max_cgds; 8419c20346bSAnirudh Venkataramanan u8 sw_entry_point_layer; 842b36c598cSAnirudh Venkataramanan u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 8439be1d6f8SAnirudh Venkataramanan struct list_head agg_list; /* lists all aggregator */ 8449c20346bSAnirudh Venkataramanan 8450f9d5027SAnirudh Venkataramanan struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI]; 84643f8b224SBruce Allan u8 evb_veb; /* true for VEB, false for VEPA */ 847f9867df6SAnirudh Venkataramanan u8 reset_ongoing; /* true if HW is in reset, false otherwise */ 848837f08fdSAnirudh Venkataramanan struct ice_bus_info bus; 8499af368faSJacob Keller struct ice_flash_info flash; 8509c20346bSAnirudh Venkataramanan struct ice_hw_dev_caps dev_caps; /* device capabilities */ 8519c20346bSAnirudh Venkataramanan struct ice_hw_func_caps func_caps; /* function capabilities */ 852f31e4b6fSAnirudh Venkataramanan 8539daf8208SAnirudh Venkataramanan struct ice_switch_info *switch_info; /* switch filter lists */ 8549daf8208SAnirudh Venkataramanan 8557ec59eeaSAnirudh Venkataramanan /* Control Queue info */ 8567ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_info adminq; 8578f5ee3c4SJacob Keller struct ice_ctl_q_info sbq; 85875d2b253SAnirudh Venkataramanan struct ice_ctl_q_info mailboxq; 8597ec59eeaSAnirudh Venkataramanan 8607ec59eeaSAnirudh Venkataramanan u8 api_branch; /* API branch version */ 8617ec59eeaSAnirudh Venkataramanan u8 api_maj_ver; /* API major version */ 8627ec59eeaSAnirudh Venkataramanan u8 api_min_ver; /* API minor version */ 8637ec59eeaSAnirudh Venkataramanan u8 api_patch; /* API patch version */ 8647ec59eeaSAnirudh Venkataramanan u8 fw_branch; /* firmware branch version */ 8657ec59eeaSAnirudh Venkataramanan u8 fw_maj_ver; /* firmware major version */ 8667ec59eeaSAnirudh Venkataramanan u8 fw_min_ver; /* firmware minor version */ 8677ec59eeaSAnirudh Venkataramanan u8 fw_patch; /* firmware patch version */ 8687ec59eeaSAnirudh Venkataramanan u32 fw_build; /* firmware build number */ 869940b61afSAnirudh Venkataramanan 8708b97ceb1SHieu Tran struct ice_fw_log_cfg fw_log; 8719e4ab4c2SBrett Creeley 8729e4ab4c2SBrett Creeley /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL 8734ee656bbSTony Nguyen * register. Used for determining the ITR/INTRL granularity during 8749e4ab4c2SBrett Creeley * initialization. 8759e4ab4c2SBrett Creeley */ 8769e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_200G 0x0 8779e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_100G 0X1 8789e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_50G 0x2 8799e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_25G 0x3 8809e4ab4c2SBrett Creeley /* ITR granularity for different speeds */ 8819e4ab4c2SBrett Creeley #define ICE_ITR_GRAN_ABOVE_25 2 8829e4ab4c2SBrett Creeley #define ICE_ITR_GRAN_MAX_25 4 883940b61afSAnirudh Venkataramanan /* ITR granularity in 1 us */ 8849e4ab4c2SBrett Creeley u8 itr_gran; 8859e4ab4c2SBrett Creeley /* INTRL granularity for different speeds */ 8869e4ab4c2SBrett Creeley #define ICE_INTRL_GRAN_ABOVE_25 4 8879e4ab4c2SBrett Creeley #define ICE_INTRL_GRAN_MAX_25 8 8889e4ab4c2SBrett Creeley /* INTRL granularity in 1 us */ 8899e4ab4c2SBrett Creeley u8 intrl_gran; 8909e4ab4c2SBrett Creeley 89143f8b224SBruce Allan u8 ucast_shared; /* true if VSIs can share unicast addr */ 8929daf8208SAnirudh Venkataramanan 89303cb4473SJacob Keller #define ICE_PHY_PER_NAC 1 89403cb4473SJacob Keller #define ICE_MAX_QUAD 2 89503cb4473SJacob Keller #define ICE_NUM_QUAD_TYPE 2 89603cb4473SJacob Keller #define ICE_PORTS_PER_QUAD 4 89703cb4473SJacob Keller #define ICE_PHY_0_LAST_QUAD 1 89803cb4473SJacob Keller #define ICE_PORTS_PER_PHY 8 89903cb4473SJacob Keller #define ICE_NUM_EXTERNAL_PORTS ICE_PORTS_PER_PHY 90003cb4473SJacob Keller 901c7648810STony Nguyen /* Active package version (currently active) */ 902c7648810STony Nguyen struct ice_pkg_ver active_pkg_ver; 903b8272919SVictor Raj u32 active_track_id; 904c7648810STony Nguyen u8 active_pkg_name[ICE_PKG_NAME_SIZE]; 905c7648810STony Nguyen u8 active_pkg_in_nvm; 906c7648810STony Nguyen 907a05983c3SDan Nowlin /* Driver's package ver - (from the Ice Metadata section) */ 908c7648810STony Nguyen struct ice_pkg_ver pkg_ver; 909c7648810STony Nguyen u8 pkg_name[ICE_PKG_NAME_SIZE]; 910c7648810STony Nguyen 911a05983c3SDan Nowlin /* Driver's Ice segment format version and ID (from the Ice seg) */ 912a05983c3SDan Nowlin struct ice_pkg_ver ice_seg_fmt_ver; 913a05983c3SDan Nowlin u8 ice_seg_id[ICE_SEG_ID_SIZE]; 914c7648810STony Nguyen 915c7648810STony Nguyen /* Pointer to the ice segment */ 916c7648810STony Nguyen struct ice_seg *seg; 917c7648810STony Nguyen 918c7648810STony Nguyen /* Pointer to allocated copy of pkg memory */ 919c7648810STony Nguyen u8 *pkg_copy; 920c7648810STony Nguyen u32 pkg_size; 921c7648810STony Nguyen 922a4e82a81STony Nguyen /* tunneling info */ 923a4e82a81STony Nguyen struct mutex tnl_lock; 924a4e82a81STony Nguyen struct ice_tunnel_table tnl; 925a4e82a81STony Nguyen 926b20e6c17SJakub Kicinski struct udp_tunnel_nic_shared udp_tunnel_shared; 927b20e6c17SJakub Kicinski struct udp_tunnel_nic_info udp_tunnel_nic; 928b20e6c17SJakub Kicinski 929*a1ffafb0SBrett Creeley /* dvm boost update information */ 930*a1ffafb0SBrett Creeley struct ice_dvm_table dvm_upd; 931*a1ffafb0SBrett Creeley 932c7648810STony Nguyen /* HW block tables */ 933c7648810STony Nguyen struct ice_blk_info blk[ICE_BLK_COUNT]; 934c90ed40cSTony Nguyen struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */ 935c90ed40cSTony Nguyen struct list_head fl_profs[ICE_BLK_COUNT]; 936148beb61SHenry Tieman 937148beb61SHenry Tieman /* Flow Director filter info */ 938148beb61SHenry Tieman int fdir_active_fltr; 939148beb61SHenry Tieman 940148beb61SHenry Tieman struct mutex fdir_fltr_lock; /* protect Flow Director */ 941148beb61SHenry Tieman struct list_head fdir_list_head; 942148beb61SHenry Tieman 943cac2a27cSHenry Tieman /* Book-keeping of side-band filter count per flow-type. 944cac2a27cSHenry Tieman * This is used to detect and handle input set changes for 945cac2a27cSHenry Tieman * respective flow-type. 946cac2a27cSHenry Tieman */ 947cac2a27cSHenry Tieman u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX]; 948cac2a27cSHenry Tieman 949148beb61SHenry Tieman struct ice_fd_hw_prof **fdir_prof; 950148beb61SHenry Tieman DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX); 951c90ed40cSTony Nguyen struct mutex rss_locks; /* protect RSS configuration */ 952c90ed40cSTony Nguyen struct list_head rss_list_head; 9530891c896SVignesh Sridhar struct ice_mbx_snapshot mbx_snapshot; 9548818b954SHaiyue Wang DECLARE_BITMAP(hw_ptype, ICE_FLOW_PTYPE_MAX); 955*a1ffafb0SBrett Creeley u8 dvm_ena; 956885fe693SMaciej Machnikowski u16 io_expander_handle; 957837f08fdSAnirudh Venkataramanan }; 958837f08fdSAnirudh Venkataramanan 959fcea6f3dSAnirudh Venkataramanan /* Statistics collected by each port, VSI, VEB, and S-channel */ 960fcea6f3dSAnirudh Venkataramanan struct ice_eth_stats { 961fcea6f3dSAnirudh Venkataramanan u64 rx_bytes; /* gorc */ 962fcea6f3dSAnirudh Venkataramanan u64 rx_unicast; /* uprc */ 963fcea6f3dSAnirudh Venkataramanan u64 rx_multicast; /* mprc */ 964fcea6f3dSAnirudh Venkataramanan u64 rx_broadcast; /* bprc */ 965fcea6f3dSAnirudh Venkataramanan u64 rx_discards; /* rdpc */ 966fcea6f3dSAnirudh Venkataramanan u64 rx_unknown_protocol; /* rupp */ 967fcea6f3dSAnirudh Venkataramanan u64 tx_bytes; /* gotc */ 968fcea6f3dSAnirudh Venkataramanan u64 tx_unicast; /* uptc */ 969fcea6f3dSAnirudh Venkataramanan u64 tx_multicast; /* mptc */ 970fcea6f3dSAnirudh Venkataramanan u64 tx_broadcast; /* bptc */ 971fcea6f3dSAnirudh Venkataramanan u64 tx_discards; /* tdpc */ 972fcea6f3dSAnirudh Venkataramanan u64 tx_errors; /* tepc */ 973fcea6f3dSAnirudh Venkataramanan }; 974fcea6f3dSAnirudh Venkataramanan 975610ed0e9SAvinash JD #define ICE_MAX_UP 8 976610ed0e9SAvinash JD 977fcea6f3dSAnirudh Venkataramanan /* Statistics collected by the MAC */ 978fcea6f3dSAnirudh Venkataramanan struct ice_hw_port_stats { 979fcea6f3dSAnirudh Venkataramanan /* eth stats collected by the port */ 980fcea6f3dSAnirudh Venkataramanan struct ice_eth_stats eth; 981fcea6f3dSAnirudh Venkataramanan /* additional port specific stats */ 982fcea6f3dSAnirudh Venkataramanan u64 tx_dropped_link_down; /* tdold */ 983fcea6f3dSAnirudh Venkataramanan u64 crc_errors; /* crcerrs */ 984fcea6f3dSAnirudh Venkataramanan u64 illegal_bytes; /* illerrc */ 985fcea6f3dSAnirudh Venkataramanan u64 error_bytes; /* errbc */ 986fcea6f3dSAnirudh Venkataramanan u64 mac_local_faults; /* mlfc */ 987fcea6f3dSAnirudh Venkataramanan u64 mac_remote_faults; /* mrfc */ 988fcea6f3dSAnirudh Venkataramanan u64 rx_len_errors; /* rlec */ 989fcea6f3dSAnirudh Venkataramanan u64 link_xon_rx; /* lxonrxc */ 990fcea6f3dSAnirudh Venkataramanan u64 link_xoff_rx; /* lxoffrxc */ 991fcea6f3dSAnirudh Venkataramanan u64 link_xon_tx; /* lxontxc */ 992fcea6f3dSAnirudh Venkataramanan u64 link_xoff_tx; /* lxofftxc */ 9934b0fdcebSAnirudh Venkataramanan u64 priority_xon_rx[8]; /* pxonrxc[8] */ 9944b0fdcebSAnirudh Venkataramanan u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 9954b0fdcebSAnirudh Venkataramanan u64 priority_xon_tx[8]; /* pxontxc[8] */ 9964b0fdcebSAnirudh Venkataramanan u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 9974b0fdcebSAnirudh Venkataramanan u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 998fcea6f3dSAnirudh Venkataramanan u64 rx_size_64; /* prc64 */ 999fcea6f3dSAnirudh Venkataramanan u64 rx_size_127; /* prc127 */ 1000fcea6f3dSAnirudh Venkataramanan u64 rx_size_255; /* prc255 */ 1001fcea6f3dSAnirudh Venkataramanan u64 rx_size_511; /* prc511 */ 1002fcea6f3dSAnirudh Venkataramanan u64 rx_size_1023; /* prc1023 */ 1003fcea6f3dSAnirudh Venkataramanan u64 rx_size_1522; /* prc1522 */ 1004fcea6f3dSAnirudh Venkataramanan u64 rx_size_big; /* prc9522 */ 1005fcea6f3dSAnirudh Venkataramanan u64 rx_undersize; /* ruc */ 1006fcea6f3dSAnirudh Venkataramanan u64 rx_fragments; /* rfc */ 1007fcea6f3dSAnirudh Venkataramanan u64 rx_oversize; /* roc */ 1008fcea6f3dSAnirudh Venkataramanan u64 rx_jabber; /* rjc */ 1009fcea6f3dSAnirudh Venkataramanan u64 tx_size_64; /* ptc64 */ 1010fcea6f3dSAnirudh Venkataramanan u64 tx_size_127; /* ptc127 */ 1011fcea6f3dSAnirudh Venkataramanan u64 tx_size_255; /* ptc255 */ 1012fcea6f3dSAnirudh Venkataramanan u64 tx_size_511; /* ptc511 */ 1013fcea6f3dSAnirudh Venkataramanan u64 tx_size_1023; /* ptc1023 */ 1014fcea6f3dSAnirudh Venkataramanan u64 tx_size_1522; /* ptc1522 */ 1015fcea6f3dSAnirudh Venkataramanan u64 tx_size_big; /* ptc9522 */ 10164ab95646SHenry Tieman /* flow director stats */ 10174ab95646SHenry Tieman u32 fd_sb_status; 10184ab95646SHenry Tieman u64 fd_sb_match; 1019fcea6f3dSAnirudh Venkataramanan }; 1020fcea6f3dSAnirudh Venkataramanan 1021bc42afa9SBrett Creeley enum ice_sw_fwd_act_type { 1022bc42afa9SBrett Creeley ICE_FWD_TO_VSI = 0, 1023bc42afa9SBrett Creeley ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */ 1024bc42afa9SBrett Creeley ICE_FWD_TO_Q, 1025bc42afa9SBrett Creeley ICE_FWD_TO_QGRP, 1026bc42afa9SBrett Creeley ICE_DROP_PACKET, 1027bc42afa9SBrett Creeley ICE_INVAL_ACT 1028bc42afa9SBrett Creeley }; 1029bc42afa9SBrett Creeley 1030e3c53928SBrett Creeley struct ice_aq_get_set_rss_lut_params { 1031e3c53928SBrett Creeley u16 vsi_handle; /* software VSI handle */ 1032e3c53928SBrett Creeley u16 lut_size; /* size of the LUT buffer */ 1033e3c53928SBrett Creeley u8 lut_type; /* type of the LUT (i.e. VSI, PF, Global) */ 1034e3c53928SBrett Creeley u8 *lut; /* input RSS LUT for set and output RSS LUT for get */ 1035e3c53928SBrett Creeley u8 global_lut_id; /* only valid when lut_type is global */ 1036e3c53928SBrett Creeley }; 1037e3c53928SBrett Creeley 1038f31e4b6fSAnirudh Venkataramanan /* Checksum and Shadow RAM pointers */ 10391fa95e01SJacob Keller #define ICE_SR_NVM_CTRL_WORD 0x00 1040031f2147SMd Fahad Iqbal Polash #define ICE_SR_BOOT_CFG_PTR 0x132 1041769c500dSAkeem G Abodunrin #define ICE_SR_NVM_WOL_CFG 0x19 1042d4e87444SJacob Keller #define ICE_NVM_OROM_VER_OFF 0x02 1043e961b679SJacob Keller #define ICE_SR_PBA_BLOCK_PTR 0x16 1044f31e4b6fSAnirudh Venkataramanan #define ICE_SR_NVM_DEV_STARTER_VER 0x18 1045f31e4b6fSAnirudh Venkataramanan #define ICE_SR_NVM_EETRACK_LO 0x2D 1046f31e4b6fSAnirudh Venkataramanan #define ICE_SR_NVM_EETRACK_HI 0x2E 1047fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_LO_SHIFT 0 1048fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT) 1049fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_HI_SHIFT 12 1050fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT) 1051d4e87444SJacob Keller #define ICE_OROM_VER_PATCH_SHIFT 0 1052d4e87444SJacob Keller #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT) 1053d4e87444SJacob Keller #define ICE_OROM_VER_BUILD_SHIFT 8 1054d4e87444SJacob Keller #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT) 1055d4e87444SJacob Keller #define ICE_OROM_VER_SHIFT 24 1056d4e87444SJacob Keller #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT) 1057031f2147SMd Fahad Iqbal Polash #define ICE_SR_PFA_PTR 0x40 1058544cd2acSCudzilo, Szymon T #define ICE_SR_1ST_NVM_BANK_PTR 0x42 10591fa95e01SJacob Keller #define ICE_SR_NVM_BANK_SIZE 0x43 1060544cd2acSCudzilo, Szymon T #define ICE_SR_1ST_OROM_BANK_PTR 0x44 10611fa95e01SJacob Keller #define ICE_SR_OROM_BANK_SIZE 0x45 1062544cd2acSCudzilo, Szymon T #define ICE_SR_NETLIST_BANK_PTR 0x46 10631fa95e01SJacob Keller #define ICE_SR_NETLIST_BANK_SIZE 0x47 1064f31e4b6fSAnirudh Venkataramanan #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800 1065ea78ce4dSPaul Greenwalt 10660ce50c70SJacob Keller /* CSS Header words */ 10670ce50c70SJacob Keller #define ICE_NVM_CSS_SREV_L 0x14 10680ce50c70SJacob Keller #define ICE_NVM_CSS_SREV_H 0x15 10690ce50c70SJacob Keller 10700ce50c70SJacob Keller /* Length of CSS header section in words */ 10710ce50c70SJacob Keller #define ICE_CSS_HEADER_LENGTH 330 10720ce50c70SJacob Keller 10730ce50c70SJacob Keller /* Offset of Shadow RAM copy in the NVM bank area. */ 10740ce50c70SJacob Keller #define ICE_NVM_SR_COPY_WORD_OFFSET roundup(ICE_CSS_HEADER_LENGTH, 32) 10750ce50c70SJacob Keller 10760ce50c70SJacob Keller /* Size in bytes of Option ROM trailer */ 10770ce50c70SJacob Keller #define ICE_NVM_OROM_TRAILER_LENGTH (2 * ICE_CSS_HEADER_LENGTH) 10780ce50c70SJacob Keller 1079e120a9abSJacob Keller /* The Link Topology Netlist section is stored as a series of words. It is 1080e120a9abSJacob Keller * stored in the NVM as a TLV, with the first two words containing the type 1081e120a9abSJacob Keller * and length. 1082e120a9abSJacob Keller */ 1083e120a9abSJacob Keller #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B 1084e120a9abSJacob Keller #define ICE_NETLIST_TYPE_OFFSET 0x0000 1085e120a9abSJacob Keller #define ICE_NETLIST_LEN_OFFSET 0x0001 1086e120a9abSJacob Keller 1087e120a9abSJacob Keller /* The Link Topology section follows the TLV header. When reading the netlist 1088e120a9abSJacob Keller * using ice_read_netlist_module, we need to account for the 2-word TLV 1089e120a9abSJacob Keller * header. 1090e120a9abSJacob Keller */ 1091e120a9abSJacob Keller #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2) 1092e120a9abSJacob Keller 1093e120a9abSJacob Keller #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000) 1094e120a9abSJacob Keller #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001) 1095e120a9abSJacob Keller 1096e120a9abSJacob Keller #define ICE_LINK_TOPO_NODE_COUNT_M ICE_M(0x3FF, 0) 1097e120a9abSJacob Keller 1098e120a9abSJacob Keller /* The Netlist ID Block is located after all of the Link Topology nodes. */ 1099e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_SIZE 0x30 1100e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n)) 1101e120a9abSJacob Keller 1102e120a9abSJacob Keller /* netlist ID block field offsets (word offsets) */ 1103e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02 1104e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03 1105e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04 1106e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05 1107e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06 1108e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07 1109e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_REV_LOW 0x08 1110e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09 1111e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n)) 1112e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F 1113e120a9abSJacob Keller 11141fa95e01SJacob Keller /* Auxiliary field, mask, and shift definition for Shadow RAM and NVM Flash */ 11151fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_1_S 0x06 11161fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S) 11171fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_VALID 0x1 11181fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3) 11191fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4) 11201fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5) 11211fa95e01SJacob Keller 11221fa95e01SJacob Keller #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15) 11231fa95e01SJacob Keller 1124ea78ce4dSPaul Greenwalt /* Link override related */ 1125ea78ce4dSPaul Greenwalt #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10 1126ea78ce4dSPaul Greenwalt #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4 1127ea78ce4dSPaul Greenwalt #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2 1128ea78ce4dSPaul Greenwalt #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1 1129ea78ce4dSPaul Greenwalt #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2 1130ea78ce4dSPaul Greenwalt #define ICE_FW_API_LINK_OVERRIDE_MAJ 1 1131ea78ce4dSPaul Greenwalt #define ICE_FW_API_LINK_OVERRIDE_MIN 5 1132ea78ce4dSPaul Greenwalt #define ICE_FW_API_LINK_OVERRIDE_PATCH 2 1133ea78ce4dSPaul Greenwalt 1134f31e4b6fSAnirudh Venkataramanan #define ICE_SR_WORDS_IN_1KB 512 1135f31e4b6fSAnirudh Venkataramanan 11368ede0178SAnirudh Venkataramanan /* Hash redirection LUT for VSI - maximum array size */ 11378ede0178SAnirudh Venkataramanan #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4) 11388ede0178SAnirudh Venkataramanan 113934295a36SDave Ertman /* AQ API version for LLDP_FILTER_CONTROL */ 114034295a36SDave Ertman #define ICE_FW_API_LLDP_FLTR_MAJ 1 114134295a36SDave Ertman #define ICE_FW_API_LLDP_FLTR_MIN 7 114234295a36SDave Ertman #define ICE_FW_API_LLDP_FLTR_PATCH 1 114334295a36SDave Ertman 11440a02944fSAnirudh Venkataramanan /* AQ API version for report default configuration */ 11450a02944fSAnirudh Venkataramanan #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1 11460a02944fSAnirudh Venkataramanan #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7 11470a02944fSAnirudh Venkataramanan #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3 11480a02944fSAnirudh Venkataramanan 1149837f08fdSAnirudh Venkataramanan #endif /* _ICE_TYPE_H_ */ 1150