1837f08fdSAnirudh Venkataramanan /* SPDX-License-Identifier: GPL-2.0 */ 2837f08fdSAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */ 3837f08fdSAnirudh Venkataramanan 4837f08fdSAnirudh Venkataramanan #ifndef _ICE_TYPE_H_ 5837f08fdSAnirudh Venkataramanan #define _ICE_TYPE_H_ 6837f08fdSAnirudh Venkataramanan 77ec59eeaSAnirudh Venkataramanan #include "ice_status.h" 87ec59eeaSAnirudh Venkataramanan #include "ice_hw_autogen.h" 97ec59eeaSAnirudh Venkataramanan #include "ice_osdep.h" 107ec59eeaSAnirudh Venkataramanan #include "ice_controlq.h" 11cdedef59SAnirudh Venkataramanan #include "ice_lan_tx_rx.h" 127ec59eeaSAnirudh Venkataramanan 13e94d4478SAnirudh Venkataramanan #define ICE_BYTES_PER_WORD 2 14e94d4478SAnirudh Venkataramanan #define ICE_BYTES_PER_DWORD 4 15e94d4478SAnirudh Venkataramanan 165513b920SAnirudh Venkataramanan static inline bool ice_is_tc_ena(u8 bitmap, u8 tc) 175513b920SAnirudh Venkataramanan { 185513b920SAnirudh Venkataramanan return test_bit(tc, (unsigned long *)&bitmap); 195513b920SAnirudh Venkataramanan } 205513b920SAnirudh Venkataramanan 21334cb062SAnirudh Venkataramanan /* Driver always calls main vsi_handle first */ 22334cb062SAnirudh Venkataramanan #define ICE_MAIN_VSI_HANDLE 0 23334cb062SAnirudh Venkataramanan 247ec59eeaSAnirudh Venkataramanan /* debug masks - set these bits in hw->debug_mask to control output */ 25f31e4b6fSAnirudh Venkataramanan #define ICE_DBG_INIT BIT_ULL(1) 260b28b702SAnirudh Venkataramanan #define ICE_DBG_LINK BIT_ULL(4) 27cdedef59SAnirudh Venkataramanan #define ICE_DBG_QCTX BIT_ULL(6) 28f31e4b6fSAnirudh Venkataramanan #define ICE_DBG_NVM BIT_ULL(7) 29dc49c772SAnirudh Venkataramanan #define ICE_DBG_LAN BIT_ULL(8) 309c20346bSAnirudh Venkataramanan #define ICE_DBG_SW BIT_ULL(13) 319c20346bSAnirudh Venkataramanan #define ICE_DBG_SCHED BIT_ULL(14) 32f31e4b6fSAnirudh Venkataramanan #define ICE_DBG_RES BIT_ULL(17) 337ec59eeaSAnirudh Venkataramanan #define ICE_DBG_AQ_MSG BIT_ULL(24) 347ec59eeaSAnirudh Venkataramanan #define ICE_DBG_AQ_CMD BIT_ULL(27) 35fcea6f3dSAnirudh Venkataramanan #define ICE_DBG_USER BIT_ULL(31) 367ec59eeaSAnirudh Venkataramanan 37f31e4b6fSAnirudh Venkataramanan enum ice_aq_res_ids { 38f31e4b6fSAnirudh Venkataramanan ICE_NVM_RES_ID = 1, 39f31e4b6fSAnirudh Venkataramanan ICE_SPD_RES_ID, 40ff2b1321SDan Nowlin ICE_CHANGE_LOCK_RES_ID, 41ff2b1321SDan Nowlin ICE_GLOBAL_CFG_LOCK_RES_ID 42f31e4b6fSAnirudh Venkataramanan }; 43f31e4b6fSAnirudh Venkataramanan 44ff2b1321SDan Nowlin /* FW update timeout definitions are in milliseconds */ 45ff2b1321SDan Nowlin #define ICE_NVM_TIMEOUT 180000 46ff2b1321SDan Nowlin #define ICE_CHANGE_LOCK_TIMEOUT 1000 47ff2b1321SDan Nowlin #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000 48ff2b1321SDan Nowlin 49f31e4b6fSAnirudh Venkataramanan enum ice_aq_res_access_type { 50f31e4b6fSAnirudh Venkataramanan ICE_RES_READ = 1, 51f31e4b6fSAnirudh Venkataramanan ICE_RES_WRITE 52f31e4b6fSAnirudh Venkataramanan }; 53f31e4b6fSAnirudh Venkataramanan 54dc49c772SAnirudh Venkataramanan enum ice_fc_mode { 55dc49c772SAnirudh Venkataramanan ICE_FC_NONE = 0, 56dc49c772SAnirudh Venkataramanan ICE_FC_RX_PAUSE, 57dc49c772SAnirudh Venkataramanan ICE_FC_TX_PAUSE, 58dc49c772SAnirudh Venkataramanan ICE_FC_FULL, 59dc49c772SAnirudh Venkataramanan ICE_FC_PFC, 60dc49c772SAnirudh Venkataramanan ICE_FC_DFLT 61dc49c772SAnirudh Venkataramanan }; 62dc49c772SAnirudh Venkataramanan 63fcea6f3dSAnirudh Venkataramanan enum ice_set_fc_aq_failures { 64fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_NONE = 0, 65fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_GET, 66fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_SET, 67fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_UPDATE 68fcea6f3dSAnirudh Venkataramanan }; 69fcea6f3dSAnirudh Venkataramanan 70f31e4b6fSAnirudh Venkataramanan /* Various MAC types */ 71f31e4b6fSAnirudh Venkataramanan enum ice_mac_type { 72f31e4b6fSAnirudh Venkataramanan ICE_MAC_UNKNOWN = 0, 73f31e4b6fSAnirudh Venkataramanan ICE_MAC_GENERIC, 74f31e4b6fSAnirudh Venkataramanan }; 75f31e4b6fSAnirudh Venkataramanan 76dc49c772SAnirudh Venkataramanan /* Media Types */ 77dc49c772SAnirudh Venkataramanan enum ice_media_type { 78dc49c772SAnirudh Venkataramanan ICE_MEDIA_UNKNOWN = 0, 79dc49c772SAnirudh Venkataramanan ICE_MEDIA_FIBER, 80dc49c772SAnirudh Venkataramanan ICE_MEDIA_BASET, 81dc49c772SAnirudh Venkataramanan ICE_MEDIA_BACKPLANE, 82dc49c772SAnirudh Venkataramanan ICE_MEDIA_DA, 83dc49c772SAnirudh Venkataramanan }; 84dc49c772SAnirudh Venkataramanan 853a858ba3SAnirudh Venkataramanan enum ice_vsi_type { 863a858ba3SAnirudh Venkataramanan ICE_VSI_PF = 0, 8775d2b253SAnirudh Venkataramanan ICE_VSI_VF, 883a858ba3SAnirudh Venkataramanan }; 893a858ba3SAnirudh Venkataramanan 90dc49c772SAnirudh Venkataramanan struct ice_link_status { 91dc49c772SAnirudh Venkataramanan /* Refer to ice_aq_phy_type for bits definition */ 92dc49c772SAnirudh Venkataramanan u64 phy_type_low; 93dc49c772SAnirudh Venkataramanan u16 max_frame_size; 94dc49c772SAnirudh Venkataramanan u16 link_speed; 95ffe49823SChinh T Cao u16 req_speeds; 9643f8b224SBruce Allan u8 lse_ena; /* Link Status Event notification */ 97dc49c772SAnirudh Venkataramanan u8 link_info; 98dc49c772SAnirudh Venkataramanan u8 an_info; 99dc49c772SAnirudh Venkataramanan u8 ext_info; 100dc49c772SAnirudh Venkataramanan u8 pacing; 101dc49c772SAnirudh Venkataramanan /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of 102dc49c772SAnirudh Venkataramanan * ice_aqc_get_phy_caps structure 103dc49c772SAnirudh Venkataramanan */ 104dc49c772SAnirudh Venkataramanan u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 105dc49c772SAnirudh Venkataramanan }; 106dc49c772SAnirudh Venkataramanan 107ddf30f7fSAnirudh Venkataramanan /* Different reset sources for which a disable queue AQ call has to be made in 108ddf30f7fSAnirudh Venkataramanan * order to clean the TX scheduler as a part of the reset 109ddf30f7fSAnirudh Venkataramanan */ 110ddf30f7fSAnirudh Venkataramanan enum ice_disq_rst_src { 111ddf30f7fSAnirudh Venkataramanan ICE_NO_RESET = 0, 112ddf30f7fSAnirudh Venkataramanan ICE_VM_RESET, 113ddf30f7fSAnirudh Venkataramanan ICE_VF_RESET, 114ddf30f7fSAnirudh Venkataramanan }; 115ddf30f7fSAnirudh Venkataramanan 116dc49c772SAnirudh Venkataramanan /* PHY info such as phy_type, etc... */ 117dc49c772SAnirudh Venkataramanan struct ice_phy_info { 118dc49c772SAnirudh Venkataramanan struct ice_link_status link_info; 119dc49c772SAnirudh Venkataramanan struct ice_link_status link_info_old; 120dc49c772SAnirudh Venkataramanan u64 phy_type_low; 121dc49c772SAnirudh Venkataramanan enum ice_media_type media_type; 12243f8b224SBruce Allan u8 get_link_info; 123dc49c772SAnirudh Venkataramanan }; 124dc49c772SAnirudh Venkataramanan 1259c20346bSAnirudh Venkataramanan /* Common HW capabilities for SW use */ 1269c20346bSAnirudh Venkataramanan struct ice_hw_common_caps { 127995c90f2SAnirudh Venkataramanan u32 valid_functions; 128995c90f2SAnirudh Venkataramanan 1299c20346bSAnirudh Venkataramanan /* TX/RX queues */ 1309c20346bSAnirudh Venkataramanan u16 num_rxq; /* Number/Total RX queues */ 1319c20346bSAnirudh Venkataramanan u16 rxq_first_id; /* First queue ID for RX queues */ 1329c20346bSAnirudh Venkataramanan u16 num_txq; /* Number/Total TX queues */ 1339c20346bSAnirudh Venkataramanan u16 txq_first_id; /* First queue ID for TX queues */ 1349c20346bSAnirudh Venkataramanan 1359c20346bSAnirudh Venkataramanan /* MSI-X vectors */ 1369c20346bSAnirudh Venkataramanan u16 num_msix_vectors; 1379c20346bSAnirudh Venkataramanan u16 msix_vector_first_id; 1389c20346bSAnirudh Venkataramanan 1399c20346bSAnirudh Venkataramanan /* Max MTU for function or device */ 1409c20346bSAnirudh Venkataramanan u16 max_mtu; 1419c20346bSAnirudh Venkataramanan 14275d2b253SAnirudh Venkataramanan /* Virtualization support */ 14375d2b253SAnirudh Venkataramanan u8 sr_iov_1_1; /* SR-IOV enabled */ 144ddf30f7fSAnirudh Venkataramanan 1459c20346bSAnirudh Venkataramanan /* RSS related capabilities */ 1469c20346bSAnirudh Venkataramanan u16 rss_table_size; /* 512 for PFs and 64 for VFs */ 1479c20346bSAnirudh Venkataramanan u8 rss_table_entry_width; /* RSS Entry width in bits */ 1489c20346bSAnirudh Venkataramanan }; 1499c20346bSAnirudh Venkataramanan 1509c20346bSAnirudh Venkataramanan /* Function specific capabilities */ 1519c20346bSAnirudh Venkataramanan struct ice_hw_func_caps { 1529c20346bSAnirudh Venkataramanan struct ice_hw_common_caps common_cap; 15375d2b253SAnirudh Venkataramanan u32 num_allocd_vfs; /* Number of allocated VFs */ 15475d2b253SAnirudh Venkataramanan u32 vf_base_id; /* Logical ID of the first VF */ 155995c90f2SAnirudh Venkataramanan u32 guar_num_vsi; 1569c20346bSAnirudh Venkataramanan }; 1579c20346bSAnirudh Venkataramanan 1589c20346bSAnirudh Venkataramanan /* Device wide capabilities */ 1599c20346bSAnirudh Venkataramanan struct ice_hw_dev_caps { 1609c20346bSAnirudh Venkataramanan struct ice_hw_common_caps common_cap; 16175d2b253SAnirudh Venkataramanan u32 num_vfs_exposed; /* Total number of VFs exposed */ 1629c20346bSAnirudh Venkataramanan u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ 1639c20346bSAnirudh Venkataramanan }; 1649c20346bSAnirudh Venkataramanan 165dc49c772SAnirudh Venkataramanan /* MAC info */ 166dc49c772SAnirudh Venkataramanan struct ice_mac_info { 167dc49c772SAnirudh Venkataramanan u8 lan_addr[ETH_ALEN]; 168dc49c772SAnirudh Venkataramanan u8 perm_addr[ETH_ALEN]; 169dc49c772SAnirudh Venkataramanan }; 170dc49c772SAnirudh Venkataramanan 171ca4929b6SBrett Creeley /* Reset types used to determine which kind of reset was requested. These 172ca4929b6SBrett Creeley * defines match what the RESET_TYPE field of the GLGEN_RSTAT register. 173ca4929b6SBrett Creeley * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register 174ca4929b6SBrett Creeley * because its reset source is different than the other types listed. 175ca4929b6SBrett Creeley */ 176f31e4b6fSAnirudh Venkataramanan enum ice_reset_req { 177ca4929b6SBrett Creeley ICE_RESET_POR = 0, 1780f9d5027SAnirudh Venkataramanan ICE_RESET_INVAL = 0, 179ca4929b6SBrett Creeley ICE_RESET_CORER = 1, 180ca4929b6SBrett Creeley ICE_RESET_GLOBR = 2, 181ca4929b6SBrett Creeley ICE_RESET_EMPR = 3, 182ca4929b6SBrett Creeley ICE_RESET_PFR = 4, 183f31e4b6fSAnirudh Venkataramanan }; 184f31e4b6fSAnirudh Venkataramanan 185837f08fdSAnirudh Venkataramanan /* Bus parameters */ 186837f08fdSAnirudh Venkataramanan struct ice_bus_info { 187837f08fdSAnirudh Venkataramanan u16 device; 188837f08fdSAnirudh Venkataramanan u8 func; 189837f08fdSAnirudh Venkataramanan }; 190837f08fdSAnirudh Venkataramanan 191dc49c772SAnirudh Venkataramanan /* Flow control (FC) parameters */ 192dc49c772SAnirudh Venkataramanan struct ice_fc_info { 193dc49c772SAnirudh Venkataramanan enum ice_fc_mode current_mode; /* FC mode in effect */ 194dc49c772SAnirudh Venkataramanan enum ice_fc_mode req_mode; /* FC mode requested by caller */ 195dc49c772SAnirudh Venkataramanan }; 196dc49c772SAnirudh Venkataramanan 197f31e4b6fSAnirudh Venkataramanan /* NVM Information */ 198f31e4b6fSAnirudh Venkataramanan struct ice_nvm_info { 199f31e4b6fSAnirudh Venkataramanan u32 eetrack; /* NVM data version */ 200f31e4b6fSAnirudh Venkataramanan u32 oem_ver; /* OEM version info */ 201f31e4b6fSAnirudh Venkataramanan u16 sr_words; /* Shadow RAM size in words */ 202f31e4b6fSAnirudh Venkataramanan u16 ver; /* NVM package version */ 20343f8b224SBruce Allan u8 blank_nvm_mode; /* is NVM empty (no FW present) */ 204f31e4b6fSAnirudh Venkataramanan }; 205f31e4b6fSAnirudh Venkataramanan 2069c20346bSAnirudh Venkataramanan /* Max number of port to queue branches w.r.t topology */ 2079c20346bSAnirudh Venkataramanan #define ICE_MAX_TRAFFIC_CLASS 8 208dc49c772SAnirudh Venkataramanan #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS 2099c20346bSAnirudh Venkataramanan 2109c20346bSAnirudh Venkataramanan struct ice_sched_node { 2119c20346bSAnirudh Venkataramanan struct ice_sched_node *parent; 2129c20346bSAnirudh Venkataramanan struct ice_sched_node *sibling; /* next sibling in the same layer */ 2139c20346bSAnirudh Venkataramanan struct ice_sched_node **children; 2149c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_elem_data info; 2159c20346bSAnirudh Venkataramanan u32 agg_id; /* aggregator group id */ 2164fb33f31SAnirudh Venkataramanan u16 vsi_handle; 21743f8b224SBruce Allan u8 in_use; /* suspended or in use */ 2189c20346bSAnirudh Venkataramanan u8 tx_sched_layer; /* Logical Layer (1-9) */ 2199c20346bSAnirudh Venkataramanan u8 num_children; 2209c20346bSAnirudh Venkataramanan u8 tc_num; 2219c20346bSAnirudh Venkataramanan u8 owner; 2229c20346bSAnirudh Venkataramanan #define ICE_SCHED_NODE_OWNER_LAN 0 2239c20346bSAnirudh Venkataramanan }; 2249c20346bSAnirudh Venkataramanan 225dc49c772SAnirudh Venkataramanan /* Access Macros for Tx Sched Elements data */ 226dc49c772SAnirudh Venkataramanan #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid) 227dc49c772SAnirudh Venkataramanan 2289c20346bSAnirudh Venkataramanan /* The aggregator type determines if identifier is for a VSI group, 2299c20346bSAnirudh Venkataramanan * aggregator group, aggregator of queues, or queue group. 2309c20346bSAnirudh Venkataramanan */ 2319c20346bSAnirudh Venkataramanan enum ice_agg_type { 2329c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_UNKNOWN = 0, 2339c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_VSI, 2349c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_AGG, /* aggregator */ 2359c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_Q, 2369c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_QG 2379c20346bSAnirudh Venkataramanan }; 2389c20346bSAnirudh Venkataramanan 2395513b920SAnirudh Venkataramanan #define ICE_SCHED_DFLT_RL_PROF_ID 0 240b36c598cSAnirudh Venkataramanan #define ICE_SCHED_DFLT_BW_WT 1 2415513b920SAnirudh Venkataramanan 2429c20346bSAnirudh Venkataramanan /* vsi type list entry to locate corresponding vsi/ag nodes */ 2439c20346bSAnirudh Venkataramanan struct ice_sched_vsi_info { 2449c20346bSAnirudh Venkataramanan struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS]; 2459c20346bSAnirudh Venkataramanan struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS]; 2469c20346bSAnirudh Venkataramanan struct list_head list_entry; 2479c20346bSAnirudh Venkataramanan u16 max_lanq[ICE_MAX_TRAFFIC_CLASS]; 2489c20346bSAnirudh Venkataramanan u16 vsi_id; 2499c20346bSAnirudh Venkataramanan }; 2509c20346bSAnirudh Venkataramanan 2519c20346bSAnirudh Venkataramanan /* driver defines the policy */ 2529c20346bSAnirudh Venkataramanan struct ice_sched_tx_policy { 2539c20346bSAnirudh Venkataramanan u16 max_num_vsis; 2549c20346bSAnirudh Venkataramanan u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS]; 25543f8b224SBruce Allan u8 rdma_ena; 2569c20346bSAnirudh Venkataramanan }; 2579c20346bSAnirudh Venkataramanan 2589c20346bSAnirudh Venkataramanan struct ice_port_info { 2599c20346bSAnirudh Venkataramanan struct ice_sched_node *root; /* Root Node per Port */ 2609c20346bSAnirudh Venkataramanan struct ice_hw *hw; /* back pointer to hw instance */ 261dc49c772SAnirudh Venkataramanan u32 last_node_teid; /* scheduler last node info */ 2629c20346bSAnirudh Venkataramanan u16 sw_id; /* Initial switch ID belongs to port */ 2639c20346bSAnirudh Venkataramanan u16 pf_vf_num; 2649c20346bSAnirudh Venkataramanan u8 port_state; 2659c20346bSAnirudh Venkataramanan #define ICE_SCHED_PORT_STATE_INIT 0x0 2669c20346bSAnirudh Venkataramanan #define ICE_SCHED_PORT_STATE_READY 0x1 267e94d4478SAnirudh Venkataramanan u16 dflt_tx_vsi_rule_id; 2689c20346bSAnirudh Venkataramanan u16 dflt_tx_vsi_num; 269e94d4478SAnirudh Venkataramanan u16 dflt_rx_vsi_rule_id; 2709c20346bSAnirudh Venkataramanan u16 dflt_rx_vsi_num; 271dc49c772SAnirudh Venkataramanan struct ice_fc_info fc; 272dc49c772SAnirudh Venkataramanan struct ice_mac_info mac; 273dc49c772SAnirudh Venkataramanan struct ice_phy_info phy; 2749c20346bSAnirudh Venkataramanan struct mutex sched_lock; /* protect access to TXSched tree */ 2759c20346bSAnirudh Venkataramanan u8 lport; 2769c20346bSAnirudh Venkataramanan #define ICE_LPORT_MASK 0xff 27743f8b224SBruce Allan u8 is_vf; 2789c20346bSAnirudh Venkataramanan }; 2799c20346bSAnirudh Venkataramanan 2809daf8208SAnirudh Venkataramanan struct ice_switch_info { 2819daf8208SAnirudh Venkataramanan struct list_head vsi_list_map_head; 28280d144c9SAnirudh Venkataramanan struct ice_sw_recipe *recp_list; 2839daf8208SAnirudh Venkataramanan }; 2849daf8208SAnirudh Venkataramanan 2858b97ceb1SHieu Tran /* FW logging configuration */ 2868b97ceb1SHieu Tran struct ice_fw_log_evnt { 2878b97ceb1SHieu Tran u8 cfg : 4; /* New event enables to configure */ 2888b97ceb1SHieu Tran u8 cur : 4; /* Current/active event enables */ 2898b97ceb1SHieu Tran }; 2908b97ceb1SHieu Tran 2918b97ceb1SHieu Tran struct ice_fw_log_cfg { 2928b97ceb1SHieu Tran u8 cq_en : 1; /* FW logging is enabled via the control queue */ 2938b97ceb1SHieu Tran u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */ 2948b97ceb1SHieu Tran u8 actv_evnts; /* Cumulation of currently enabled log events */ 2958b97ceb1SHieu Tran 2968b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S) 2978b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S) 2988b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S) 2998b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S) 3008b97ceb1SHieu Tran struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX]; 3018b97ceb1SHieu Tran }; 3028b97ceb1SHieu Tran 303837f08fdSAnirudh Venkataramanan /* Port hardware description */ 304837f08fdSAnirudh Venkataramanan struct ice_hw { 305837f08fdSAnirudh Venkataramanan u8 __iomem *hw_addr; 306837f08fdSAnirudh Venkataramanan void *back; 3079c20346bSAnirudh Venkataramanan struct ice_aqc_layer_props *layer_info; 3089c20346bSAnirudh Venkataramanan struct ice_port_info *port_info; 3097ec59eeaSAnirudh Venkataramanan u64 debug_mask; /* bitmap for debug mask */ 310f31e4b6fSAnirudh Venkataramanan enum ice_mac_type mac_type; 311837f08fdSAnirudh Venkataramanan 312837f08fdSAnirudh Venkataramanan /* pci info */ 313837f08fdSAnirudh Venkataramanan u16 device_id; 314837f08fdSAnirudh Venkataramanan u16 vendor_id; 315837f08fdSAnirudh Venkataramanan u16 subsystem_device_id; 316837f08fdSAnirudh Venkataramanan u16 subsystem_vendor_id; 317837f08fdSAnirudh Venkataramanan u8 revision_id; 318837f08fdSAnirudh Venkataramanan 319f31e4b6fSAnirudh Venkataramanan u8 pf_id; /* device profile info */ 320f31e4b6fSAnirudh Venkataramanan 3219c20346bSAnirudh Venkataramanan /* TX Scheduler values */ 3229c20346bSAnirudh Venkataramanan u16 num_tx_sched_layers; 3239c20346bSAnirudh Venkataramanan u16 num_tx_sched_phys_layers; 3249c20346bSAnirudh Venkataramanan u8 flattened_layers; 3259c20346bSAnirudh Venkataramanan u8 max_cgds; 3269c20346bSAnirudh Venkataramanan u8 sw_entry_point_layer; 327b36c598cSAnirudh Venkataramanan u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 3289be1d6f8SAnirudh Venkataramanan struct list_head agg_list; /* lists all aggregator */ 3299c20346bSAnirudh Venkataramanan 3300f9d5027SAnirudh Venkataramanan struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI]; 33143f8b224SBruce Allan u8 evb_veb; /* true for VEB, false for VEPA */ 332fd2a9817SAnirudh Venkataramanan u8 reset_ongoing; /* true if hw is in reset, false otherwise */ 333837f08fdSAnirudh Venkataramanan struct ice_bus_info bus; 334f31e4b6fSAnirudh Venkataramanan struct ice_nvm_info nvm; 3359c20346bSAnirudh Venkataramanan struct ice_hw_dev_caps dev_caps; /* device capabilities */ 3369c20346bSAnirudh Venkataramanan struct ice_hw_func_caps func_caps; /* function capabilities */ 337f31e4b6fSAnirudh Venkataramanan 3389daf8208SAnirudh Venkataramanan struct ice_switch_info *switch_info; /* switch filter lists */ 3399daf8208SAnirudh Venkataramanan 3407ec59eeaSAnirudh Venkataramanan /* Control Queue info */ 3417ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_info adminq; 34275d2b253SAnirudh Venkataramanan struct ice_ctl_q_info mailboxq; 3437ec59eeaSAnirudh Venkataramanan 3447ec59eeaSAnirudh Venkataramanan u8 api_branch; /* API branch version */ 3457ec59eeaSAnirudh Venkataramanan u8 api_maj_ver; /* API major version */ 3467ec59eeaSAnirudh Venkataramanan u8 api_min_ver; /* API minor version */ 3477ec59eeaSAnirudh Venkataramanan u8 api_patch; /* API patch version */ 3487ec59eeaSAnirudh Venkataramanan u8 fw_branch; /* firmware branch version */ 3497ec59eeaSAnirudh Venkataramanan u8 fw_maj_ver; /* firmware major version */ 3507ec59eeaSAnirudh Venkataramanan u8 fw_min_ver; /* firmware minor version */ 3517ec59eeaSAnirudh Venkataramanan u8 fw_patch; /* firmware patch version */ 3527ec59eeaSAnirudh Venkataramanan u32 fw_build; /* firmware build number */ 353940b61afSAnirudh Venkataramanan 3548b97ceb1SHieu Tran struct ice_fw_log_cfg fw_log; 3559e4ab4c2SBrett Creeley 3569e4ab4c2SBrett Creeley /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL 3579e4ab4c2SBrett Creeley * register. Used for determining the itr/intrl granularity during 3589e4ab4c2SBrett Creeley * initialization. 3599e4ab4c2SBrett Creeley */ 3609e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_200G 0x0 3619e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_100G 0X1 3629e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_50G 0x2 3639e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_25G 0x3 3649e4ab4c2SBrett Creeley /* ITR granularity for different speeds */ 3659e4ab4c2SBrett Creeley #define ICE_ITR_GRAN_ABOVE_25 2 3669e4ab4c2SBrett Creeley #define ICE_ITR_GRAN_MAX_25 4 367940b61afSAnirudh Venkataramanan /* ITR granularity in 1 us */ 3689e4ab4c2SBrett Creeley u8 itr_gran; 3699e4ab4c2SBrett Creeley /* INTRL granularity for different speeds */ 3709e4ab4c2SBrett Creeley #define ICE_INTRL_GRAN_ABOVE_25 4 3719e4ab4c2SBrett Creeley #define ICE_INTRL_GRAN_MAX_25 8 3729e4ab4c2SBrett Creeley /* INTRL granularity in 1 us */ 3739e4ab4c2SBrett Creeley u8 intrl_gran; 3749e4ab4c2SBrett Creeley 37543f8b224SBruce Allan u8 ucast_shared; /* true if VSIs can share unicast addr */ 3769daf8208SAnirudh Venkataramanan 377837f08fdSAnirudh Venkataramanan }; 378837f08fdSAnirudh Venkataramanan 379fcea6f3dSAnirudh Venkataramanan /* Statistics collected by each port, VSI, VEB, and S-channel */ 380fcea6f3dSAnirudh Venkataramanan struct ice_eth_stats { 381fcea6f3dSAnirudh Venkataramanan u64 rx_bytes; /* gorc */ 382fcea6f3dSAnirudh Venkataramanan u64 rx_unicast; /* uprc */ 383fcea6f3dSAnirudh Venkataramanan u64 rx_multicast; /* mprc */ 384fcea6f3dSAnirudh Venkataramanan u64 rx_broadcast; /* bprc */ 385fcea6f3dSAnirudh Venkataramanan u64 rx_discards; /* rdpc */ 386fcea6f3dSAnirudh Venkataramanan u64 rx_unknown_protocol; /* rupp */ 387fcea6f3dSAnirudh Venkataramanan u64 tx_bytes; /* gotc */ 388fcea6f3dSAnirudh Venkataramanan u64 tx_unicast; /* uptc */ 389fcea6f3dSAnirudh Venkataramanan u64 tx_multicast; /* mptc */ 390fcea6f3dSAnirudh Venkataramanan u64 tx_broadcast; /* bptc */ 391fcea6f3dSAnirudh Venkataramanan u64 tx_discards; /* tdpc */ 392fcea6f3dSAnirudh Venkataramanan u64 tx_errors; /* tepc */ 393fcea6f3dSAnirudh Venkataramanan }; 394fcea6f3dSAnirudh Venkataramanan 395fcea6f3dSAnirudh Venkataramanan /* Statistics collected by the MAC */ 396fcea6f3dSAnirudh Venkataramanan struct ice_hw_port_stats { 397fcea6f3dSAnirudh Venkataramanan /* eth stats collected by the port */ 398fcea6f3dSAnirudh Venkataramanan struct ice_eth_stats eth; 399fcea6f3dSAnirudh Venkataramanan /* additional port specific stats */ 400fcea6f3dSAnirudh Venkataramanan u64 tx_dropped_link_down; /* tdold */ 401fcea6f3dSAnirudh Venkataramanan u64 crc_errors; /* crcerrs */ 402fcea6f3dSAnirudh Venkataramanan u64 illegal_bytes; /* illerrc */ 403fcea6f3dSAnirudh Venkataramanan u64 error_bytes; /* errbc */ 404fcea6f3dSAnirudh Venkataramanan u64 mac_local_faults; /* mlfc */ 405fcea6f3dSAnirudh Venkataramanan u64 mac_remote_faults; /* mrfc */ 406fcea6f3dSAnirudh Venkataramanan u64 rx_len_errors; /* rlec */ 407fcea6f3dSAnirudh Venkataramanan u64 link_xon_rx; /* lxonrxc */ 408fcea6f3dSAnirudh Venkataramanan u64 link_xoff_rx; /* lxoffrxc */ 409fcea6f3dSAnirudh Venkataramanan u64 link_xon_tx; /* lxontxc */ 410fcea6f3dSAnirudh Venkataramanan u64 link_xoff_tx; /* lxofftxc */ 411fcea6f3dSAnirudh Venkataramanan u64 rx_size_64; /* prc64 */ 412fcea6f3dSAnirudh Venkataramanan u64 rx_size_127; /* prc127 */ 413fcea6f3dSAnirudh Venkataramanan u64 rx_size_255; /* prc255 */ 414fcea6f3dSAnirudh Venkataramanan u64 rx_size_511; /* prc511 */ 415fcea6f3dSAnirudh Venkataramanan u64 rx_size_1023; /* prc1023 */ 416fcea6f3dSAnirudh Venkataramanan u64 rx_size_1522; /* prc1522 */ 417fcea6f3dSAnirudh Venkataramanan u64 rx_size_big; /* prc9522 */ 418fcea6f3dSAnirudh Venkataramanan u64 rx_undersize; /* ruc */ 419fcea6f3dSAnirudh Venkataramanan u64 rx_fragments; /* rfc */ 420fcea6f3dSAnirudh Venkataramanan u64 rx_oversize; /* roc */ 421fcea6f3dSAnirudh Venkataramanan u64 rx_jabber; /* rjc */ 422fcea6f3dSAnirudh Venkataramanan u64 tx_size_64; /* ptc64 */ 423fcea6f3dSAnirudh Venkataramanan u64 tx_size_127; /* ptc127 */ 424fcea6f3dSAnirudh Venkataramanan u64 tx_size_255; /* ptc255 */ 425fcea6f3dSAnirudh Venkataramanan u64 tx_size_511; /* ptc511 */ 426fcea6f3dSAnirudh Venkataramanan u64 tx_size_1023; /* ptc1023 */ 427fcea6f3dSAnirudh Venkataramanan u64 tx_size_1522; /* ptc1522 */ 428fcea6f3dSAnirudh Venkataramanan u64 tx_size_big; /* ptc9522 */ 429fcea6f3dSAnirudh Venkataramanan }; 430fcea6f3dSAnirudh Venkataramanan 431f31e4b6fSAnirudh Venkataramanan /* Checksum and Shadow RAM pointers */ 432f31e4b6fSAnirudh Venkataramanan #define ICE_SR_NVM_DEV_STARTER_VER 0x18 433f31e4b6fSAnirudh Venkataramanan #define ICE_SR_NVM_EETRACK_LO 0x2D 434f31e4b6fSAnirudh Venkataramanan #define ICE_SR_NVM_EETRACK_HI 0x2E 435fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_LO_SHIFT 0 436fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT) 437fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_HI_SHIFT 12 438fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT) 439fcea6f3dSAnirudh Venkataramanan #define ICE_OEM_VER_PATCH_SHIFT 0 440fcea6f3dSAnirudh Venkataramanan #define ICE_OEM_VER_PATCH_MASK (0xff << ICE_OEM_VER_PATCH_SHIFT) 441fcea6f3dSAnirudh Venkataramanan #define ICE_OEM_VER_BUILD_SHIFT 8 442fcea6f3dSAnirudh Venkataramanan #define ICE_OEM_VER_BUILD_MASK (0xffff << ICE_OEM_VER_BUILD_SHIFT) 443fcea6f3dSAnirudh Venkataramanan #define ICE_OEM_VER_SHIFT 24 444fcea6f3dSAnirudh Venkataramanan #define ICE_OEM_VER_MASK (0xff << ICE_OEM_VER_SHIFT) 445f31e4b6fSAnirudh Venkataramanan #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800 446f31e4b6fSAnirudh Venkataramanan #define ICE_SR_WORDS_IN_1KB 512 447f31e4b6fSAnirudh Venkataramanan 4488ede0178SAnirudh Venkataramanan /* Hash redirection LUT for VSI - maximum array size */ 4498ede0178SAnirudh Venkataramanan #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4) 4508ede0178SAnirudh Venkataramanan 451837f08fdSAnirudh Venkataramanan #endif /* _ICE_TYPE_H_ */ 452