1837f08fdSAnirudh Venkataramanan /* SPDX-License-Identifier: GPL-2.0 */ 2837f08fdSAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */ 3837f08fdSAnirudh Venkataramanan 4837f08fdSAnirudh Venkataramanan #ifndef _ICE_TYPE_H_ 5837f08fdSAnirudh Venkataramanan #define _ICE_TYPE_H_ 6837f08fdSAnirudh Venkataramanan 77ec59eeaSAnirudh Venkataramanan #include "ice_status.h" 87ec59eeaSAnirudh Venkataramanan #include "ice_hw_autogen.h" 97ec59eeaSAnirudh Venkataramanan #include "ice_osdep.h" 107ec59eeaSAnirudh Venkataramanan #include "ice_controlq.h" 11cdedef59SAnirudh Venkataramanan #include "ice_lan_tx_rx.h" 127ec59eeaSAnirudh Venkataramanan 13e94d4478SAnirudh Venkataramanan #define ICE_BYTES_PER_WORD 2 14e94d4478SAnirudh Venkataramanan #define ICE_BYTES_PER_DWORD 4 15e94d4478SAnirudh Venkataramanan 165513b920SAnirudh Venkataramanan static inline bool ice_is_tc_ena(u8 bitmap, u8 tc) 175513b920SAnirudh Venkataramanan { 185513b920SAnirudh Venkataramanan return test_bit(tc, (unsigned long *)&bitmap); 195513b920SAnirudh Venkataramanan } 205513b920SAnirudh Venkataramanan 21334cb062SAnirudh Venkataramanan /* Driver always calls main vsi_handle first */ 22334cb062SAnirudh Venkataramanan #define ICE_MAIN_VSI_HANDLE 0 23334cb062SAnirudh Venkataramanan 247ec59eeaSAnirudh Venkataramanan /* debug masks - set these bits in hw->debug_mask to control output */ 25f31e4b6fSAnirudh Venkataramanan #define ICE_DBG_INIT BIT_ULL(1) 264f70daa0SJacob Keller #define ICE_DBG_FW_LOG BIT_ULL(3) 270b28b702SAnirudh Venkataramanan #define ICE_DBG_LINK BIT_ULL(4) 28d8df260aSChinh T Cao #define ICE_DBG_PHY BIT_ULL(5) 29cdedef59SAnirudh Venkataramanan #define ICE_DBG_QCTX BIT_ULL(6) 30f31e4b6fSAnirudh Venkataramanan #define ICE_DBG_NVM BIT_ULL(7) 31dc49c772SAnirudh Venkataramanan #define ICE_DBG_LAN BIT_ULL(8) 329c20346bSAnirudh Venkataramanan #define ICE_DBG_SW BIT_ULL(13) 339c20346bSAnirudh Venkataramanan #define ICE_DBG_SCHED BIT_ULL(14) 34f31e4b6fSAnirudh Venkataramanan #define ICE_DBG_RES BIT_ULL(17) 357ec59eeaSAnirudh Venkataramanan #define ICE_DBG_AQ_MSG BIT_ULL(24) 367ec59eeaSAnirudh Venkataramanan #define ICE_DBG_AQ_CMD BIT_ULL(27) 37fcea6f3dSAnirudh Venkataramanan #define ICE_DBG_USER BIT_ULL(31) 387ec59eeaSAnirudh Venkataramanan 39f31e4b6fSAnirudh Venkataramanan enum ice_aq_res_ids { 40f31e4b6fSAnirudh Venkataramanan ICE_NVM_RES_ID = 1, 41f31e4b6fSAnirudh Venkataramanan ICE_SPD_RES_ID, 42ff2b1321SDan Nowlin ICE_CHANGE_LOCK_RES_ID, 43ff2b1321SDan Nowlin ICE_GLOBAL_CFG_LOCK_RES_ID 44f31e4b6fSAnirudh Venkataramanan }; 45f31e4b6fSAnirudh Venkataramanan 46ff2b1321SDan Nowlin /* FW update timeout definitions are in milliseconds */ 47ff2b1321SDan Nowlin #define ICE_NVM_TIMEOUT 180000 48ff2b1321SDan Nowlin #define ICE_CHANGE_LOCK_TIMEOUT 1000 49ff2b1321SDan Nowlin #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000 50ff2b1321SDan Nowlin 51f31e4b6fSAnirudh Venkataramanan enum ice_aq_res_access_type { 52f31e4b6fSAnirudh Venkataramanan ICE_RES_READ = 1, 53f31e4b6fSAnirudh Venkataramanan ICE_RES_WRITE 54f31e4b6fSAnirudh Venkataramanan }; 55f31e4b6fSAnirudh Venkataramanan 56dc49c772SAnirudh Venkataramanan enum ice_fc_mode { 57dc49c772SAnirudh Venkataramanan ICE_FC_NONE = 0, 58dc49c772SAnirudh Venkataramanan ICE_FC_RX_PAUSE, 59dc49c772SAnirudh Venkataramanan ICE_FC_TX_PAUSE, 60dc49c772SAnirudh Venkataramanan ICE_FC_FULL, 61dc49c772SAnirudh Venkataramanan ICE_FC_PFC, 62dc49c772SAnirudh Venkataramanan ICE_FC_DFLT 63dc49c772SAnirudh Venkataramanan }; 64dc49c772SAnirudh Venkataramanan 65f776b3acSPaul Greenwalt enum ice_fec_mode { 66f776b3acSPaul Greenwalt ICE_FEC_NONE = 0, 67f776b3acSPaul Greenwalt ICE_FEC_RS, 68f776b3acSPaul Greenwalt ICE_FEC_BASER, 69f776b3acSPaul Greenwalt ICE_FEC_AUTO 70f776b3acSPaul Greenwalt }; 71f776b3acSPaul Greenwalt 72fcea6f3dSAnirudh Venkataramanan enum ice_set_fc_aq_failures { 73fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_NONE = 0, 74fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_GET, 75fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_SET, 76fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_UPDATE 77fcea6f3dSAnirudh Venkataramanan }; 78fcea6f3dSAnirudh Venkataramanan 79f31e4b6fSAnirudh Venkataramanan /* Various MAC types */ 80f31e4b6fSAnirudh Venkataramanan enum ice_mac_type { 81f31e4b6fSAnirudh Venkataramanan ICE_MAC_UNKNOWN = 0, 82f31e4b6fSAnirudh Venkataramanan ICE_MAC_GENERIC, 83f31e4b6fSAnirudh Venkataramanan }; 84f31e4b6fSAnirudh Venkataramanan 85dc49c772SAnirudh Venkataramanan /* Media Types */ 86dc49c772SAnirudh Venkataramanan enum ice_media_type { 87dc49c772SAnirudh Venkataramanan ICE_MEDIA_UNKNOWN = 0, 88dc49c772SAnirudh Venkataramanan ICE_MEDIA_FIBER, 89dc49c772SAnirudh Venkataramanan ICE_MEDIA_BASET, 90dc49c772SAnirudh Venkataramanan ICE_MEDIA_BACKPLANE, 91dc49c772SAnirudh Venkataramanan ICE_MEDIA_DA, 92dc49c772SAnirudh Venkataramanan }; 93dc49c772SAnirudh Venkataramanan 943a858ba3SAnirudh Venkataramanan enum ice_vsi_type { 953a858ba3SAnirudh Venkataramanan ICE_VSI_PF = 0, 9675d2b253SAnirudh Venkataramanan ICE_VSI_VF, 970e674aebSAnirudh Venkataramanan ICE_VSI_LB = 6, 983a858ba3SAnirudh Venkataramanan }; 993a858ba3SAnirudh Venkataramanan 100dc49c772SAnirudh Venkataramanan struct ice_link_status { 101dc49c772SAnirudh Venkataramanan /* Refer to ice_aq_phy_type for bits definition */ 102dc49c772SAnirudh Venkataramanan u64 phy_type_low; 103aef74145SAnirudh Venkataramanan u64 phy_type_high; 104f776b3acSPaul Greenwalt u8 topo_media_conflict; 105dc49c772SAnirudh Venkataramanan u16 max_frame_size; 106dc49c772SAnirudh Venkataramanan u16 link_speed; 107ffe49823SChinh T Cao u16 req_speeds; 10843f8b224SBruce Allan u8 lse_ena; /* Link Status Event notification */ 109dc49c772SAnirudh Venkataramanan u8 link_info; 110dc49c772SAnirudh Venkataramanan u8 an_info; 111dc49c772SAnirudh Venkataramanan u8 ext_info; 112f776b3acSPaul Greenwalt u8 fec_info; 113dc49c772SAnirudh Venkataramanan u8 pacing; 114dc49c772SAnirudh Venkataramanan /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of 115dc49c772SAnirudh Venkataramanan * ice_aqc_get_phy_caps structure 116dc49c772SAnirudh Venkataramanan */ 117dc49c772SAnirudh Venkataramanan u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; 118dc49c772SAnirudh Venkataramanan }; 119dc49c772SAnirudh Venkataramanan 120ddf30f7fSAnirudh Venkataramanan /* Different reset sources for which a disable queue AQ call has to be made in 121f9867df6SAnirudh Venkataramanan * order to clean the Tx scheduler as a part of the reset 122ddf30f7fSAnirudh Venkataramanan */ 123ddf30f7fSAnirudh Venkataramanan enum ice_disq_rst_src { 124ddf30f7fSAnirudh Venkataramanan ICE_NO_RESET = 0, 125ddf30f7fSAnirudh Venkataramanan ICE_VM_RESET, 126ddf30f7fSAnirudh Venkataramanan ICE_VF_RESET, 127ddf30f7fSAnirudh Venkataramanan }; 128ddf30f7fSAnirudh Venkataramanan 129dc49c772SAnirudh Venkataramanan /* PHY info such as phy_type, etc... */ 130dc49c772SAnirudh Venkataramanan struct ice_phy_info { 131dc49c772SAnirudh Venkataramanan struct ice_link_status link_info; 132dc49c772SAnirudh Venkataramanan struct ice_link_status link_info_old; 133dc49c772SAnirudh Venkataramanan u64 phy_type_low; 134aef74145SAnirudh Venkataramanan u64 phy_type_high; 135dc49c772SAnirudh Venkataramanan enum ice_media_type media_type; 13643f8b224SBruce Allan u8 get_link_info; 137dc49c772SAnirudh Venkataramanan }; 138dc49c772SAnirudh Venkataramanan 1399c20346bSAnirudh Venkataramanan /* Common HW capabilities for SW use */ 1409c20346bSAnirudh Venkataramanan struct ice_hw_common_caps { 141995c90f2SAnirudh Venkataramanan u32 valid_functions; 142995c90f2SAnirudh Venkataramanan 143f9867df6SAnirudh Venkataramanan /* Tx/Rx queues */ 144f9867df6SAnirudh Venkataramanan u16 num_rxq; /* Number/Total Rx queues */ 145f9867df6SAnirudh Venkataramanan u16 rxq_first_id; /* First queue ID for Rx queues */ 146f9867df6SAnirudh Venkataramanan u16 num_txq; /* Number/Total Tx queues */ 147f9867df6SAnirudh Venkataramanan u16 txq_first_id; /* First queue ID for Tx queues */ 1489c20346bSAnirudh Venkataramanan 1499c20346bSAnirudh Venkataramanan /* MSI-X vectors */ 1509c20346bSAnirudh Venkataramanan u16 num_msix_vectors; 1519c20346bSAnirudh Venkataramanan u16 msix_vector_first_id; 1529c20346bSAnirudh Venkataramanan 1539c20346bSAnirudh Venkataramanan /* Max MTU for function or device */ 1549c20346bSAnirudh Venkataramanan u16 max_mtu; 1559c20346bSAnirudh Venkataramanan 15675d2b253SAnirudh Venkataramanan /* Virtualization support */ 15775d2b253SAnirudh Venkataramanan u8 sr_iov_1_1; /* SR-IOV enabled */ 158ddf30f7fSAnirudh Venkataramanan 1599c20346bSAnirudh Venkataramanan /* RSS related capabilities */ 1609c20346bSAnirudh Venkataramanan u16 rss_table_size; /* 512 for PFs and 64 for VFs */ 1619c20346bSAnirudh Venkataramanan u8 rss_table_entry_width; /* RSS Entry width in bits */ 16237b6f646SAnirudh Venkataramanan 16337b6f646SAnirudh Venkataramanan u8 dcb; 1649c20346bSAnirudh Venkataramanan }; 1659c20346bSAnirudh Venkataramanan 1669c20346bSAnirudh Venkataramanan /* Function specific capabilities */ 1679c20346bSAnirudh Venkataramanan struct ice_hw_func_caps { 1689c20346bSAnirudh Venkataramanan struct ice_hw_common_caps common_cap; 16975d2b253SAnirudh Venkataramanan u32 num_allocd_vfs; /* Number of allocated VFs */ 17075d2b253SAnirudh Venkataramanan u32 vf_base_id; /* Logical ID of the first VF */ 171995c90f2SAnirudh Venkataramanan u32 guar_num_vsi; 1729c20346bSAnirudh Venkataramanan }; 1739c20346bSAnirudh Venkataramanan 1749c20346bSAnirudh Venkataramanan /* Device wide capabilities */ 1759c20346bSAnirudh Venkataramanan struct ice_hw_dev_caps { 1769c20346bSAnirudh Venkataramanan struct ice_hw_common_caps common_cap; 17775d2b253SAnirudh Venkataramanan u32 num_vfs_exposed; /* Total number of VFs exposed */ 1789c20346bSAnirudh Venkataramanan u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ 1799c20346bSAnirudh Venkataramanan }; 1809c20346bSAnirudh Venkataramanan 181dc49c772SAnirudh Venkataramanan /* MAC info */ 182dc49c772SAnirudh Venkataramanan struct ice_mac_info { 183dc49c772SAnirudh Venkataramanan u8 lan_addr[ETH_ALEN]; 184dc49c772SAnirudh Venkataramanan u8 perm_addr[ETH_ALEN]; 185dc49c772SAnirudh Venkataramanan }; 186dc49c772SAnirudh Venkataramanan 187ca4929b6SBrett Creeley /* Reset types used to determine which kind of reset was requested. These 188ca4929b6SBrett Creeley * defines match what the RESET_TYPE field of the GLGEN_RSTAT register. 189ca4929b6SBrett Creeley * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register 190ca4929b6SBrett Creeley * because its reset source is different than the other types listed. 191ca4929b6SBrett Creeley */ 192f31e4b6fSAnirudh Venkataramanan enum ice_reset_req { 193ca4929b6SBrett Creeley ICE_RESET_POR = 0, 1940f9d5027SAnirudh Venkataramanan ICE_RESET_INVAL = 0, 195ca4929b6SBrett Creeley ICE_RESET_CORER = 1, 196ca4929b6SBrett Creeley ICE_RESET_GLOBR = 2, 197ca4929b6SBrett Creeley ICE_RESET_EMPR = 3, 198ca4929b6SBrett Creeley ICE_RESET_PFR = 4, 199f31e4b6fSAnirudh Venkataramanan }; 200f31e4b6fSAnirudh Venkataramanan 201837f08fdSAnirudh Venkataramanan /* Bus parameters */ 202837f08fdSAnirudh Venkataramanan struct ice_bus_info { 203837f08fdSAnirudh Venkataramanan u16 device; 204837f08fdSAnirudh Venkataramanan u8 func; 205837f08fdSAnirudh Venkataramanan }; 206837f08fdSAnirudh Venkataramanan 207dc49c772SAnirudh Venkataramanan /* Flow control (FC) parameters */ 208dc49c772SAnirudh Venkataramanan struct ice_fc_info { 209dc49c772SAnirudh Venkataramanan enum ice_fc_mode current_mode; /* FC mode in effect */ 210dc49c772SAnirudh Venkataramanan enum ice_fc_mode req_mode; /* FC mode requested by caller */ 211dc49c772SAnirudh Venkataramanan }; 212dc49c772SAnirudh Venkataramanan 213f31e4b6fSAnirudh Venkataramanan /* NVM Information */ 214f31e4b6fSAnirudh Venkataramanan struct ice_nvm_info { 215f31e4b6fSAnirudh Venkataramanan u32 eetrack; /* NVM data version */ 216f31e4b6fSAnirudh Venkataramanan u32 oem_ver; /* OEM version info */ 217f31e4b6fSAnirudh Venkataramanan u16 sr_words; /* Shadow RAM size in words */ 218f31e4b6fSAnirudh Venkataramanan u16 ver; /* NVM package version */ 21943f8b224SBruce Allan u8 blank_nvm_mode; /* is NVM empty (no FW present) */ 220f31e4b6fSAnirudh Venkataramanan }; 221f31e4b6fSAnirudh Venkataramanan 2229c20346bSAnirudh Venkataramanan /* Max number of port to queue branches w.r.t topology */ 2239c20346bSAnirudh Venkataramanan #define ICE_MAX_TRAFFIC_CLASS 8 224dc49c772SAnirudh Venkataramanan #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS 2259c20346bSAnirudh Venkataramanan 2262bdc97beSBruce Allan #define ice_for_each_traffic_class(_i) \ 2272bdc97beSBruce Allan for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++) 2282bdc97beSBruce Allan 2297b9ffc76SAnirudh Venkataramanan #define ICE_INVAL_TEID 0xFFFFFFFF 2307b9ffc76SAnirudh Venkataramanan 2319c20346bSAnirudh Venkataramanan struct ice_sched_node { 2329c20346bSAnirudh Venkataramanan struct ice_sched_node *parent; 2339c20346bSAnirudh Venkataramanan struct ice_sched_node *sibling; /* next sibling in the same layer */ 2349c20346bSAnirudh Venkataramanan struct ice_sched_node **children; 2359c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_elem_data info; 236f9867df6SAnirudh Venkataramanan u32 agg_id; /* aggregator group ID */ 2374fb33f31SAnirudh Venkataramanan u16 vsi_handle; 23843f8b224SBruce Allan u8 in_use; /* suspended or in use */ 2399c20346bSAnirudh Venkataramanan u8 tx_sched_layer; /* Logical Layer (1-9) */ 2409c20346bSAnirudh Venkataramanan u8 num_children; 2419c20346bSAnirudh Venkataramanan u8 tc_num; 2429c20346bSAnirudh Venkataramanan u8 owner; 2439c20346bSAnirudh Venkataramanan #define ICE_SCHED_NODE_OWNER_LAN 0 2449c20346bSAnirudh Venkataramanan }; 2459c20346bSAnirudh Venkataramanan 246dc49c772SAnirudh Venkataramanan /* Access Macros for Tx Sched Elements data */ 247dc49c772SAnirudh Venkataramanan #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid) 248dc49c772SAnirudh Venkataramanan 2499c20346bSAnirudh Venkataramanan /* The aggregator type determines if identifier is for a VSI group, 2509c20346bSAnirudh Venkataramanan * aggregator group, aggregator of queues, or queue group. 2519c20346bSAnirudh Venkataramanan */ 2529c20346bSAnirudh Venkataramanan enum ice_agg_type { 2539c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_UNKNOWN = 0, 2549c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_VSI, 2559c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_AGG, /* aggregator */ 2569c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_Q, 2579c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_QG 2589c20346bSAnirudh Venkataramanan }; 2599c20346bSAnirudh Venkataramanan 2605513b920SAnirudh Venkataramanan #define ICE_SCHED_DFLT_RL_PROF_ID 0 261b36c598cSAnirudh Venkataramanan #define ICE_SCHED_DFLT_BW_WT 1 2625513b920SAnirudh Venkataramanan 263f9867df6SAnirudh Venkataramanan /* VSI type list entry to locate corresponding VSI/ag nodes */ 2649c20346bSAnirudh Venkataramanan struct ice_sched_vsi_info { 2659c20346bSAnirudh Venkataramanan struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS]; 2669c20346bSAnirudh Venkataramanan struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS]; 2679c20346bSAnirudh Venkataramanan struct list_head list_entry; 2689c20346bSAnirudh Venkataramanan u16 max_lanq[ICE_MAX_TRAFFIC_CLASS]; 2699c20346bSAnirudh Venkataramanan }; 2709c20346bSAnirudh Venkataramanan 2719c20346bSAnirudh Venkataramanan /* driver defines the policy */ 2729c20346bSAnirudh Venkataramanan struct ice_sched_tx_policy { 2739c20346bSAnirudh Venkataramanan u16 max_num_vsis; 2749c20346bSAnirudh Venkataramanan u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS]; 27543f8b224SBruce Allan u8 rdma_ena; 2769c20346bSAnirudh Venkataramanan }; 2779c20346bSAnirudh Venkataramanan 2780ebd3ff1SAnirudh Venkataramanan /* CEE or IEEE 802.1Qaz ETS Configuration data */ 2790ebd3ff1SAnirudh Venkataramanan struct ice_dcb_ets_cfg { 2800ebd3ff1SAnirudh Venkataramanan u8 willing; 2810ebd3ff1SAnirudh Venkataramanan u8 cbs; 2820ebd3ff1SAnirudh Venkataramanan u8 maxtcs; 2830ebd3ff1SAnirudh Venkataramanan u8 prio_table[ICE_MAX_TRAFFIC_CLASS]; 2840ebd3ff1SAnirudh Venkataramanan u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS]; 2850ebd3ff1SAnirudh Venkataramanan u8 tsatable[ICE_MAX_TRAFFIC_CLASS]; 2860ebd3ff1SAnirudh Venkataramanan }; 2870ebd3ff1SAnirudh Venkataramanan 2880ebd3ff1SAnirudh Venkataramanan /* CEE or IEEE 802.1Qaz PFC Configuration data */ 2890ebd3ff1SAnirudh Venkataramanan struct ice_dcb_pfc_cfg { 2900ebd3ff1SAnirudh Venkataramanan u8 willing; 2910ebd3ff1SAnirudh Venkataramanan u8 mbc; 2920ebd3ff1SAnirudh Venkataramanan u8 pfccap; 2930ebd3ff1SAnirudh Venkataramanan u8 pfcena; 2940ebd3ff1SAnirudh Venkataramanan }; 2950ebd3ff1SAnirudh Venkataramanan 2960ebd3ff1SAnirudh Venkataramanan /* CEE or IEEE 802.1Qaz Application Priority data */ 2970ebd3ff1SAnirudh Venkataramanan struct ice_dcb_app_priority_table { 2980ebd3ff1SAnirudh Venkataramanan u16 prot_id; 2990ebd3ff1SAnirudh Venkataramanan u8 priority; 3000ebd3ff1SAnirudh Venkataramanan u8 selector; 3010ebd3ff1SAnirudh Venkataramanan }; 3020ebd3ff1SAnirudh Venkataramanan 3030ebd3ff1SAnirudh Venkataramanan #define ICE_MAX_USER_PRIORITY 8 3040ebd3ff1SAnirudh Venkataramanan #define ICE_DCBX_MAX_APPS 32 3050ebd3ff1SAnirudh Venkataramanan #define ICE_LLDPDU_SIZE 1500 3060ebd3ff1SAnirudh Venkataramanan #define ICE_TLV_STATUS_OPER 0x1 3070ebd3ff1SAnirudh Venkataramanan #define ICE_TLV_STATUS_SYNC 0x2 3080ebd3ff1SAnirudh Venkataramanan #define ICE_TLV_STATUS_ERR 0x4 3090ebd3ff1SAnirudh Venkataramanan #define ICE_APP_PROT_ID_FCOE 0x8906 3100ebd3ff1SAnirudh Venkataramanan #define ICE_APP_PROT_ID_ISCSI 0x0cbc 3110ebd3ff1SAnirudh Venkataramanan #define ICE_APP_PROT_ID_FIP 0x8914 3120ebd3ff1SAnirudh Venkataramanan #define ICE_APP_SEL_ETHTYPE 0x1 3130ebd3ff1SAnirudh Venkataramanan #define ICE_APP_SEL_TCPIP 0x2 3140ebd3ff1SAnirudh Venkataramanan #define ICE_CEE_APP_SEL_ETHTYPE 0x0 3150ebd3ff1SAnirudh Venkataramanan #define ICE_CEE_APP_SEL_TCPIP 0x1 3160ebd3ff1SAnirudh Venkataramanan 3170ebd3ff1SAnirudh Venkataramanan struct ice_dcbx_cfg { 3180ebd3ff1SAnirudh Venkataramanan u32 numapps; 3190ebd3ff1SAnirudh Venkataramanan u32 tlv_status; /* CEE mode TLV status */ 3200ebd3ff1SAnirudh Venkataramanan struct ice_dcb_ets_cfg etscfg; 3210ebd3ff1SAnirudh Venkataramanan struct ice_dcb_ets_cfg etsrec; 3220ebd3ff1SAnirudh Venkataramanan struct ice_dcb_pfc_cfg pfc; 3230ebd3ff1SAnirudh Venkataramanan struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS]; 3240ebd3ff1SAnirudh Venkataramanan u8 dcbx_mode; 3250ebd3ff1SAnirudh Venkataramanan #define ICE_DCBX_MODE_CEE 0x1 3260ebd3ff1SAnirudh Venkataramanan #define ICE_DCBX_MODE_IEEE 0x2 3270ebd3ff1SAnirudh Venkataramanan u8 app_mode; 3280ebd3ff1SAnirudh Venkataramanan #define ICE_DCBX_APPS_NON_WILLING 0x1 3290ebd3ff1SAnirudh Venkataramanan }; 3300ebd3ff1SAnirudh Venkataramanan 3319c20346bSAnirudh Venkataramanan struct ice_port_info { 3329c20346bSAnirudh Venkataramanan struct ice_sched_node *root; /* Root Node per Port */ 333f9867df6SAnirudh Venkataramanan struct ice_hw *hw; /* back pointer to HW instance */ 334dc49c772SAnirudh Venkataramanan u32 last_node_teid; /* scheduler last node info */ 3359c20346bSAnirudh Venkataramanan u16 sw_id; /* Initial switch ID belongs to port */ 3369c20346bSAnirudh Venkataramanan u16 pf_vf_num; 3379c20346bSAnirudh Venkataramanan u8 port_state; 3389c20346bSAnirudh Venkataramanan #define ICE_SCHED_PORT_STATE_INIT 0x0 3399c20346bSAnirudh Venkataramanan #define ICE_SCHED_PORT_STATE_READY 0x1 3400437f1a9SJesse Brandeburg u8 lport; 3410437f1a9SJesse Brandeburg #define ICE_LPORT_MASK 0xff 342e94d4478SAnirudh Venkataramanan u16 dflt_tx_vsi_rule_id; 3439c20346bSAnirudh Venkataramanan u16 dflt_tx_vsi_num; 344e94d4478SAnirudh Venkataramanan u16 dflt_rx_vsi_rule_id; 3459c20346bSAnirudh Venkataramanan u16 dflt_rx_vsi_num; 346dc49c772SAnirudh Venkataramanan struct ice_fc_info fc; 347dc49c772SAnirudh Venkataramanan struct ice_mac_info mac; 348dc49c772SAnirudh Venkataramanan struct ice_phy_info phy; 3499c20346bSAnirudh Venkataramanan struct mutex sched_lock; /* protect access to TXSched tree */ 3500ebd3ff1SAnirudh Venkataramanan struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */ 3510ebd3ff1SAnirudh Venkataramanan /* DCBX info */ 3520ebd3ff1SAnirudh Venkataramanan struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */ 3530ebd3ff1SAnirudh Venkataramanan struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */ 35437b6f646SAnirudh Venkataramanan /* LLDP/DCBX Status */ 3550437f1a9SJesse Brandeburg u8 dcbx_status:3; /* see ICE_DCBX_STATUS_DIS */ 3560437f1a9SJesse Brandeburg u8 is_sw_lldp:1; 3570437f1a9SJesse Brandeburg u8 is_vf:1; 3589c20346bSAnirudh Venkataramanan }; 3599c20346bSAnirudh Venkataramanan 3609daf8208SAnirudh Venkataramanan struct ice_switch_info { 3619daf8208SAnirudh Venkataramanan struct list_head vsi_list_map_head; 36280d144c9SAnirudh Venkataramanan struct ice_sw_recipe *recp_list; 3639daf8208SAnirudh Venkataramanan }; 3649daf8208SAnirudh Venkataramanan 3658b97ceb1SHieu Tran /* FW logging configuration */ 3668b97ceb1SHieu Tran struct ice_fw_log_evnt { 3678b97ceb1SHieu Tran u8 cfg : 4; /* New event enables to configure */ 3688b97ceb1SHieu Tran u8 cur : 4; /* Current/active event enables */ 3698b97ceb1SHieu Tran }; 3708b97ceb1SHieu Tran 3718b97ceb1SHieu Tran struct ice_fw_log_cfg { 3728b97ceb1SHieu Tran u8 cq_en : 1; /* FW logging is enabled via the control queue */ 3738b97ceb1SHieu Tran u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */ 3748b97ceb1SHieu Tran u8 actv_evnts; /* Cumulation of currently enabled log events */ 3758b97ceb1SHieu Tran 3768b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S) 3778b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S) 3788b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S) 3798b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S) 3808b97ceb1SHieu Tran struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX]; 3818b97ceb1SHieu Tran }; 3828b97ceb1SHieu Tran 383837f08fdSAnirudh Venkataramanan /* Port hardware description */ 384837f08fdSAnirudh Venkataramanan struct ice_hw { 385837f08fdSAnirudh Venkataramanan u8 __iomem *hw_addr; 386837f08fdSAnirudh Venkataramanan void *back; 3879c20346bSAnirudh Venkataramanan struct ice_aqc_layer_props *layer_info; 3889c20346bSAnirudh Venkataramanan struct ice_port_info *port_info; 3897ec59eeaSAnirudh Venkataramanan u64 debug_mask; /* bitmap for debug mask */ 390f31e4b6fSAnirudh Venkataramanan enum ice_mac_type mac_type; 391837f08fdSAnirudh Venkataramanan 392837f08fdSAnirudh Venkataramanan /* pci info */ 393837f08fdSAnirudh Venkataramanan u16 device_id; 394837f08fdSAnirudh Venkataramanan u16 vendor_id; 395837f08fdSAnirudh Venkataramanan u16 subsystem_device_id; 396837f08fdSAnirudh Venkataramanan u16 subsystem_vendor_id; 397837f08fdSAnirudh Venkataramanan u8 revision_id; 398837f08fdSAnirudh Venkataramanan 399f31e4b6fSAnirudh Venkataramanan u8 pf_id; /* device profile info */ 400f31e4b6fSAnirudh Venkataramanan 401f9867df6SAnirudh Venkataramanan /* Tx Scheduler values */ 4029c20346bSAnirudh Venkataramanan u16 num_tx_sched_layers; 4039c20346bSAnirudh Venkataramanan u16 num_tx_sched_phys_layers; 4049c20346bSAnirudh Venkataramanan u8 flattened_layers; 4059c20346bSAnirudh Venkataramanan u8 max_cgds; 4069c20346bSAnirudh Venkataramanan u8 sw_entry_point_layer; 407b36c598cSAnirudh Venkataramanan u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM]; 4089be1d6f8SAnirudh Venkataramanan struct list_head agg_list; /* lists all aggregator */ 4099c20346bSAnirudh Venkataramanan 4100f9d5027SAnirudh Venkataramanan struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI]; 41143f8b224SBruce Allan u8 evb_veb; /* true for VEB, false for VEPA */ 412f9867df6SAnirudh Venkataramanan u8 reset_ongoing; /* true if HW is in reset, false otherwise */ 413837f08fdSAnirudh Venkataramanan struct ice_bus_info bus; 414f31e4b6fSAnirudh Venkataramanan struct ice_nvm_info nvm; 4159c20346bSAnirudh Venkataramanan struct ice_hw_dev_caps dev_caps; /* device capabilities */ 4169c20346bSAnirudh Venkataramanan struct ice_hw_func_caps func_caps; /* function capabilities */ 417f31e4b6fSAnirudh Venkataramanan 4189daf8208SAnirudh Venkataramanan struct ice_switch_info *switch_info; /* switch filter lists */ 4199daf8208SAnirudh Venkataramanan 4207ec59eeaSAnirudh Venkataramanan /* Control Queue info */ 4217ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_info adminq; 42275d2b253SAnirudh Venkataramanan struct ice_ctl_q_info mailboxq; 4237ec59eeaSAnirudh Venkataramanan 4247ec59eeaSAnirudh Venkataramanan u8 api_branch; /* API branch version */ 4257ec59eeaSAnirudh Venkataramanan u8 api_maj_ver; /* API major version */ 4267ec59eeaSAnirudh Venkataramanan u8 api_min_ver; /* API minor version */ 4277ec59eeaSAnirudh Venkataramanan u8 api_patch; /* API patch version */ 4287ec59eeaSAnirudh Venkataramanan u8 fw_branch; /* firmware branch version */ 4297ec59eeaSAnirudh Venkataramanan u8 fw_maj_ver; /* firmware major version */ 4307ec59eeaSAnirudh Venkataramanan u8 fw_min_ver; /* firmware minor version */ 4317ec59eeaSAnirudh Venkataramanan u8 fw_patch; /* firmware patch version */ 4327ec59eeaSAnirudh Venkataramanan u32 fw_build; /* firmware build number */ 433940b61afSAnirudh Venkataramanan 4348b97ceb1SHieu Tran struct ice_fw_log_cfg fw_log; 4359e4ab4c2SBrett Creeley 4369e4ab4c2SBrett Creeley /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL 4379e4ab4c2SBrett Creeley * register. Used for determining the itr/intrl granularity during 4389e4ab4c2SBrett Creeley * initialization. 4399e4ab4c2SBrett Creeley */ 4409e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_200G 0x0 4419e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_100G 0X1 4429e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_50G 0x2 4439e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_25G 0x3 4449e4ab4c2SBrett Creeley /* ITR granularity for different speeds */ 4459e4ab4c2SBrett Creeley #define ICE_ITR_GRAN_ABOVE_25 2 4469e4ab4c2SBrett Creeley #define ICE_ITR_GRAN_MAX_25 4 447940b61afSAnirudh Venkataramanan /* ITR granularity in 1 us */ 4489e4ab4c2SBrett Creeley u8 itr_gran; 4499e4ab4c2SBrett Creeley /* INTRL granularity for different speeds */ 4509e4ab4c2SBrett Creeley #define ICE_INTRL_GRAN_ABOVE_25 4 4519e4ab4c2SBrett Creeley #define ICE_INTRL_GRAN_MAX_25 8 4529e4ab4c2SBrett Creeley /* INTRL granularity in 1 us */ 4539e4ab4c2SBrett Creeley u8 intrl_gran; 4549e4ab4c2SBrett Creeley 45543f8b224SBruce Allan u8 ucast_shared; /* true if VSIs can share unicast addr */ 4569daf8208SAnirudh Venkataramanan 457837f08fdSAnirudh Venkataramanan }; 458837f08fdSAnirudh Venkataramanan 459fcea6f3dSAnirudh Venkataramanan /* Statistics collected by each port, VSI, VEB, and S-channel */ 460fcea6f3dSAnirudh Venkataramanan struct ice_eth_stats { 461fcea6f3dSAnirudh Venkataramanan u64 rx_bytes; /* gorc */ 462fcea6f3dSAnirudh Venkataramanan u64 rx_unicast; /* uprc */ 463fcea6f3dSAnirudh Venkataramanan u64 rx_multicast; /* mprc */ 464fcea6f3dSAnirudh Venkataramanan u64 rx_broadcast; /* bprc */ 465fcea6f3dSAnirudh Venkataramanan u64 rx_discards; /* rdpc */ 466fcea6f3dSAnirudh Venkataramanan u64 rx_unknown_protocol; /* rupp */ 467fcea6f3dSAnirudh Venkataramanan u64 tx_bytes; /* gotc */ 468fcea6f3dSAnirudh Venkataramanan u64 tx_unicast; /* uptc */ 469fcea6f3dSAnirudh Venkataramanan u64 tx_multicast; /* mptc */ 470fcea6f3dSAnirudh Venkataramanan u64 tx_broadcast; /* bptc */ 471fcea6f3dSAnirudh Venkataramanan u64 tx_discards; /* tdpc */ 472fcea6f3dSAnirudh Venkataramanan u64 tx_errors; /* tepc */ 473fcea6f3dSAnirudh Venkataramanan }; 474fcea6f3dSAnirudh Venkataramanan 475fcea6f3dSAnirudh Venkataramanan /* Statistics collected by the MAC */ 476fcea6f3dSAnirudh Venkataramanan struct ice_hw_port_stats { 477fcea6f3dSAnirudh Venkataramanan /* eth stats collected by the port */ 478fcea6f3dSAnirudh Venkataramanan struct ice_eth_stats eth; 479fcea6f3dSAnirudh Venkataramanan /* additional port specific stats */ 480fcea6f3dSAnirudh Venkataramanan u64 tx_dropped_link_down; /* tdold */ 481fcea6f3dSAnirudh Venkataramanan u64 crc_errors; /* crcerrs */ 482fcea6f3dSAnirudh Venkataramanan u64 illegal_bytes; /* illerrc */ 483fcea6f3dSAnirudh Venkataramanan u64 error_bytes; /* errbc */ 484fcea6f3dSAnirudh Venkataramanan u64 mac_local_faults; /* mlfc */ 485fcea6f3dSAnirudh Venkataramanan u64 mac_remote_faults; /* mrfc */ 486fcea6f3dSAnirudh Venkataramanan u64 rx_len_errors; /* rlec */ 487fcea6f3dSAnirudh Venkataramanan u64 link_xon_rx; /* lxonrxc */ 488fcea6f3dSAnirudh Venkataramanan u64 link_xoff_rx; /* lxoffrxc */ 489fcea6f3dSAnirudh Venkataramanan u64 link_xon_tx; /* lxontxc */ 490fcea6f3dSAnirudh Venkataramanan u64 link_xoff_tx; /* lxofftxc */ 4914b0fdcebSAnirudh Venkataramanan u64 priority_xon_rx[8]; /* pxonrxc[8] */ 4924b0fdcebSAnirudh Venkataramanan u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ 4934b0fdcebSAnirudh Venkataramanan u64 priority_xon_tx[8]; /* pxontxc[8] */ 4944b0fdcebSAnirudh Venkataramanan u64 priority_xoff_tx[8]; /* pxofftxc[8] */ 4954b0fdcebSAnirudh Venkataramanan u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ 496fcea6f3dSAnirudh Venkataramanan u64 rx_size_64; /* prc64 */ 497fcea6f3dSAnirudh Venkataramanan u64 rx_size_127; /* prc127 */ 498fcea6f3dSAnirudh Venkataramanan u64 rx_size_255; /* prc255 */ 499fcea6f3dSAnirudh Venkataramanan u64 rx_size_511; /* prc511 */ 500fcea6f3dSAnirudh Venkataramanan u64 rx_size_1023; /* prc1023 */ 501fcea6f3dSAnirudh Venkataramanan u64 rx_size_1522; /* prc1522 */ 502fcea6f3dSAnirudh Venkataramanan u64 rx_size_big; /* prc9522 */ 503fcea6f3dSAnirudh Venkataramanan u64 rx_undersize; /* ruc */ 504fcea6f3dSAnirudh Venkataramanan u64 rx_fragments; /* rfc */ 505fcea6f3dSAnirudh Venkataramanan u64 rx_oversize; /* roc */ 506fcea6f3dSAnirudh Venkataramanan u64 rx_jabber; /* rjc */ 507fcea6f3dSAnirudh Venkataramanan u64 tx_size_64; /* ptc64 */ 508fcea6f3dSAnirudh Venkataramanan u64 tx_size_127; /* ptc127 */ 509fcea6f3dSAnirudh Venkataramanan u64 tx_size_255; /* ptc255 */ 510fcea6f3dSAnirudh Venkataramanan u64 tx_size_511; /* ptc511 */ 511fcea6f3dSAnirudh Venkataramanan u64 tx_size_1023; /* ptc1023 */ 512fcea6f3dSAnirudh Venkataramanan u64 tx_size_1522; /* ptc1522 */ 513fcea6f3dSAnirudh Venkataramanan u64 tx_size_big; /* ptc9522 */ 514fcea6f3dSAnirudh Venkataramanan }; 515fcea6f3dSAnirudh Venkataramanan 516f31e4b6fSAnirudh Venkataramanan /* Checksum and Shadow RAM pointers */ 517f31e4b6fSAnirudh Venkataramanan #define ICE_SR_NVM_DEV_STARTER_VER 0x18 518f31e4b6fSAnirudh Venkataramanan #define ICE_SR_NVM_EETRACK_LO 0x2D 519f31e4b6fSAnirudh Venkataramanan #define ICE_SR_NVM_EETRACK_HI 0x2E 520fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_LO_SHIFT 0 521fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT) 522fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_HI_SHIFT 12 523fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT) 524fcea6f3dSAnirudh Venkataramanan #define ICE_OEM_VER_PATCH_SHIFT 0 525fcea6f3dSAnirudh Venkataramanan #define ICE_OEM_VER_PATCH_MASK (0xff << ICE_OEM_VER_PATCH_SHIFT) 526fcea6f3dSAnirudh Venkataramanan #define ICE_OEM_VER_BUILD_SHIFT 8 527fcea6f3dSAnirudh Venkataramanan #define ICE_OEM_VER_BUILD_MASK (0xffff << ICE_OEM_VER_BUILD_SHIFT) 528fcea6f3dSAnirudh Venkataramanan #define ICE_OEM_VER_SHIFT 24 529fcea6f3dSAnirudh Venkataramanan #define ICE_OEM_VER_MASK (0xff << ICE_OEM_VER_SHIFT) 530f31e4b6fSAnirudh Venkataramanan #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800 531f31e4b6fSAnirudh Venkataramanan #define ICE_SR_WORDS_IN_1KB 512 532f31e4b6fSAnirudh Venkataramanan 5338ede0178SAnirudh Venkataramanan /* Hash redirection LUT for VSI - maximum array size */ 5348ede0178SAnirudh Venkataramanan #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4) 5358ede0178SAnirudh Venkataramanan 536837f08fdSAnirudh Venkataramanan #endif /* _ICE_TYPE_H_ */ 537