1837f08fdSAnirudh Venkataramanan /* SPDX-License-Identifier: GPL-2.0 */
2837f08fdSAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */
3837f08fdSAnirudh Venkataramanan
4837f08fdSAnirudh Venkataramanan #ifndef _ICE_TYPE_H_
5837f08fdSAnirudh Venkataramanan #define _ICE_TYPE_H_
6837f08fdSAnirudh Venkataramanan
76a025730STony Nguyen #define ICE_BYTES_PER_WORD 2
86a025730STony Nguyen #define ICE_BYTES_PER_DWORD 4
940319796SKiran Patil #define ICE_CHNL_MAX_TC 16
106a025730STony Nguyen
117ec59eeaSAnirudh Venkataramanan #include "ice_hw_autogen.h"
12649c87c6SJacob Keller #include "ice_devids.h"
137ec59eeaSAnirudh Venkataramanan #include "ice_osdep.h"
147ec59eeaSAnirudh Venkataramanan #include "ice_controlq.h"
15cdedef59SAnirudh Venkataramanan #include "ice_lan_tx_rx.h"
16c7648810STony Nguyen #include "ice_flex_type.h"
1731ad4e4eSTony Nguyen #include "ice_protocol_type.h"
188f5ee3c4SJacob Keller #include "ice_sbq_cmd.h"
19a1ffafb0SBrett Creeley #include "ice_vlan_mode.h"
207ec59eeaSAnirudh Venkataramanan
ice_is_tc_ena(unsigned long bitmap,u8 tc)2135b4f437SJacob Keller static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc)
225513b920SAnirudh Venkataramanan {
2335b4f437SJacob Keller return test_bit(tc, &bitmap);
245513b920SAnirudh Venkataramanan }
255513b920SAnirudh Venkataramanan
round_up_64bit(u64 a,u32 b)261ddef455SUsha Ketineni static inline u64 round_up_64bit(u64 a, u32 b)
271ddef455SUsha Ketineni {
281ddef455SUsha Ketineni return div64_long(((a) + (b) / 2), (b));
291ddef455SUsha Ketineni }
301ddef455SUsha Ketineni
ice_round_to_num(u32 N,u32 R)311ddef455SUsha Ketineni static inline u32 ice_round_to_num(u32 N, u32 R)
321ddef455SUsha Ketineni {
331ddef455SUsha Ketineni return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
341ddef455SUsha Ketineni ((((N) + (R) - 1) / (R)) * (R)));
351ddef455SUsha Ketineni }
361ddef455SUsha Ketineni
37334cb062SAnirudh Venkataramanan /* Driver always calls main vsi_handle first */
38334cb062SAnirudh Venkataramanan #define ICE_MAIN_VSI_HANDLE 0
39334cb062SAnirudh Venkataramanan
407ec59eeaSAnirudh Venkataramanan /* debug masks - set these bits in hw->debug_mask to control output */
41f31e4b6fSAnirudh Venkataramanan #define ICE_DBG_INIT BIT_ULL(1)
424f70daa0SJacob Keller #define ICE_DBG_FW_LOG BIT_ULL(3)
430b28b702SAnirudh Venkataramanan #define ICE_DBG_LINK BIT_ULL(4)
44d8df260aSChinh T Cao #define ICE_DBG_PHY BIT_ULL(5)
45cdedef59SAnirudh Venkataramanan #define ICE_DBG_QCTX BIT_ULL(6)
46f31e4b6fSAnirudh Venkataramanan #define ICE_DBG_NVM BIT_ULL(7)
47dc49c772SAnirudh Venkataramanan #define ICE_DBG_LAN BIT_ULL(8)
4831ad4e4eSTony Nguyen #define ICE_DBG_FLOW BIT_ULL(9)
499c20346bSAnirudh Venkataramanan #define ICE_DBG_SW BIT_ULL(13)
509c20346bSAnirudh Venkataramanan #define ICE_DBG_SCHED BIT_ULL(14)
51348048e7SDave Ertman #define ICE_DBG_RDMA BIT_ULL(15)
52c7648810STony Nguyen #define ICE_DBG_PKG BIT_ULL(16)
53f31e4b6fSAnirudh Venkataramanan #define ICE_DBG_RES BIT_ULL(17)
5403cb4473SJacob Keller #define ICE_DBG_PTP BIT_ULL(19)
557ec59eeaSAnirudh Venkataramanan #define ICE_DBG_AQ_MSG BIT_ULL(24)
56faa01721SJacob Keller #define ICE_DBG_AQ_DESC BIT_ULL(25)
57faa01721SJacob Keller #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
587ec59eeaSAnirudh Venkataramanan #define ICE_DBG_AQ_CMD BIT_ULL(27)
59a1ffafb0SBrett Creeley #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
60a1ffafb0SBrett Creeley ICE_DBG_AQ_DESC | \
61a1ffafb0SBrett Creeley ICE_DBG_AQ_DESC_BUF | \
62a1ffafb0SBrett Creeley ICE_DBG_AQ_CMD)
63a1ffafb0SBrett Creeley
64fcea6f3dSAnirudh Venkataramanan #define ICE_DBG_USER BIT_ULL(31)
657ec59eeaSAnirudh Venkataramanan
66f31e4b6fSAnirudh Venkataramanan enum ice_aq_res_ids {
67f31e4b6fSAnirudh Venkataramanan ICE_NVM_RES_ID = 1,
68f31e4b6fSAnirudh Venkataramanan ICE_SPD_RES_ID,
69ff2b1321SDan Nowlin ICE_CHANGE_LOCK_RES_ID,
70ff2b1321SDan Nowlin ICE_GLOBAL_CFG_LOCK_RES_ID
71f31e4b6fSAnirudh Venkataramanan };
72f31e4b6fSAnirudh Venkataramanan
73ff2b1321SDan Nowlin /* FW update timeout definitions are in milliseconds */
74ff2b1321SDan Nowlin #define ICE_NVM_TIMEOUT 180000
75ff2b1321SDan Nowlin #define ICE_CHANGE_LOCK_TIMEOUT 1000
76fb361284SLiwei Song #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 5000
77ff2b1321SDan Nowlin
78f31e4b6fSAnirudh Venkataramanan enum ice_aq_res_access_type {
79f31e4b6fSAnirudh Venkataramanan ICE_RES_READ = 1,
80f31e4b6fSAnirudh Venkataramanan ICE_RES_WRITE
81f31e4b6fSAnirudh Venkataramanan };
82f31e4b6fSAnirudh Venkataramanan
83e3710a01SPaul M Stillwell Jr struct ice_driver_ver {
84e3710a01SPaul M Stillwell Jr u8 major_ver;
85e3710a01SPaul M Stillwell Jr u8 minor_ver;
86e3710a01SPaul M Stillwell Jr u8 build_ver;
87e3710a01SPaul M Stillwell Jr u8 subbuild_ver;
88e3710a01SPaul M Stillwell Jr u8 driver_string[32];
89e3710a01SPaul M Stillwell Jr };
90e3710a01SPaul M Stillwell Jr
91dc49c772SAnirudh Venkataramanan enum ice_fc_mode {
92dc49c772SAnirudh Venkataramanan ICE_FC_NONE = 0,
93dc49c772SAnirudh Venkataramanan ICE_FC_RX_PAUSE,
94dc49c772SAnirudh Venkataramanan ICE_FC_TX_PAUSE,
95dc49c772SAnirudh Venkataramanan ICE_FC_FULL,
96dc49c772SAnirudh Venkataramanan ICE_FC_PFC,
97dc49c772SAnirudh Venkataramanan ICE_FC_DFLT
98dc49c772SAnirudh Venkataramanan };
99dc49c772SAnirudh Venkataramanan
1001a3571b5SPaul Greenwalt enum ice_phy_cache_mode {
1011a3571b5SPaul Greenwalt ICE_FC_MODE = 0,
1021a3571b5SPaul Greenwalt ICE_SPEED_MODE,
1031a3571b5SPaul Greenwalt ICE_FEC_MODE
1041a3571b5SPaul Greenwalt };
1051a3571b5SPaul Greenwalt
106f776b3acSPaul Greenwalt enum ice_fec_mode {
107f776b3acSPaul Greenwalt ICE_FEC_NONE = 0,
108f776b3acSPaul Greenwalt ICE_FEC_RS,
109f776b3acSPaul Greenwalt ICE_FEC_BASER,
110f776b3acSPaul Greenwalt ICE_FEC_AUTO
111f776b3acSPaul Greenwalt };
112f776b3acSPaul Greenwalt
1131a3571b5SPaul Greenwalt struct ice_phy_cache_mode_data {
1141a3571b5SPaul Greenwalt union {
1151a3571b5SPaul Greenwalt enum ice_fec_mode curr_user_fec_req;
1161a3571b5SPaul Greenwalt enum ice_fc_mode curr_user_fc_req;
1171a3571b5SPaul Greenwalt u16 curr_user_speed_req;
1181a3571b5SPaul Greenwalt } data;
1191a3571b5SPaul Greenwalt };
1201a3571b5SPaul Greenwalt
121fcea6f3dSAnirudh Venkataramanan enum ice_set_fc_aq_failures {
122fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_NONE = 0,
123fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_GET,
124fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_SET,
125fcea6f3dSAnirudh Venkataramanan ICE_SET_FC_AQ_FAIL_UPDATE
126fcea6f3dSAnirudh Venkataramanan };
127fcea6f3dSAnirudh Venkataramanan
128f31e4b6fSAnirudh Venkataramanan /* Various MAC types */
129f31e4b6fSAnirudh Venkataramanan enum ice_mac_type {
130f31e4b6fSAnirudh Venkataramanan ICE_MAC_UNKNOWN = 0,
131ea78ce4dSPaul Greenwalt ICE_MAC_E810,
132f31e4b6fSAnirudh Venkataramanan ICE_MAC_GENERIC,
133f31e4b6fSAnirudh Venkataramanan };
134f31e4b6fSAnirudh Venkataramanan
135dc49c772SAnirudh Venkataramanan /* Media Types */
136dc49c772SAnirudh Venkataramanan enum ice_media_type {
137dc49c772SAnirudh Venkataramanan ICE_MEDIA_UNKNOWN = 0,
138dc49c772SAnirudh Venkataramanan ICE_MEDIA_FIBER,
139dc49c772SAnirudh Venkataramanan ICE_MEDIA_BASET,
140dc49c772SAnirudh Venkataramanan ICE_MEDIA_BACKPLANE,
141dc49c772SAnirudh Venkataramanan ICE_MEDIA_DA,
142dc49c772SAnirudh Venkataramanan };
143dc49c772SAnirudh Venkataramanan
1443a858ba3SAnirudh Venkataramanan enum ice_vsi_type {
1453a858ba3SAnirudh Venkataramanan ICE_VSI_PF = 0,
146148beb61SHenry Tieman ICE_VSI_VF = 1,
147148beb61SHenry Tieman ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
1480754d65bSKiran Patil ICE_VSI_CHNL = 4,
1490e674aebSAnirudh Venkataramanan ICE_VSI_LB = 6,
150f66756e0SGrzegorz Nitka ICE_VSI_SWITCHDEV_CTRL = 7,
1513a858ba3SAnirudh Venkataramanan };
1523a858ba3SAnirudh Venkataramanan
153dc49c772SAnirudh Venkataramanan struct ice_link_status {
154dc49c772SAnirudh Venkataramanan /* Refer to ice_aq_phy_type for bits definition */
155dc49c772SAnirudh Venkataramanan u64 phy_type_low;
156aef74145SAnirudh Venkataramanan u64 phy_type_high;
157f776b3acSPaul Greenwalt u8 topo_media_conflict;
158dc49c772SAnirudh Venkataramanan u16 max_frame_size;
159dc49c772SAnirudh Venkataramanan u16 link_speed;
160ffe49823SChinh T Cao u16 req_speeds;
161c77849f5SAnirudh Venkataramanan u8 link_cfg_err;
16243f8b224SBruce Allan u8 lse_ena; /* Link Status Event notification */
163dc49c772SAnirudh Venkataramanan u8 link_info;
164dc49c772SAnirudh Venkataramanan u8 an_info;
165dc49c772SAnirudh Venkataramanan u8 ext_info;
166f776b3acSPaul Greenwalt u8 fec_info;
167dc49c772SAnirudh Venkataramanan u8 pacing;
168dc49c772SAnirudh Venkataramanan /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
169dc49c772SAnirudh Venkataramanan * ice_aqc_get_phy_caps structure
170dc49c772SAnirudh Venkataramanan */
171dc49c772SAnirudh Venkataramanan u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
172dc49c772SAnirudh Venkataramanan };
173dc49c772SAnirudh Venkataramanan
174ddf30f7fSAnirudh Venkataramanan /* Different reset sources for which a disable queue AQ call has to be made in
175f9867df6SAnirudh Venkataramanan * order to clean the Tx scheduler as a part of the reset
176ddf30f7fSAnirudh Venkataramanan */
177ddf30f7fSAnirudh Venkataramanan enum ice_disq_rst_src {
178ddf30f7fSAnirudh Venkataramanan ICE_NO_RESET = 0,
179ddf30f7fSAnirudh Venkataramanan ICE_VM_RESET,
180ddf30f7fSAnirudh Venkataramanan ICE_VF_RESET,
181ddf30f7fSAnirudh Venkataramanan };
182ddf30f7fSAnirudh Venkataramanan
183dc49c772SAnirudh Venkataramanan /* PHY info such as phy_type, etc... */
184dc49c772SAnirudh Venkataramanan struct ice_phy_info {
185dc49c772SAnirudh Venkataramanan struct ice_link_status link_info;
186dc49c772SAnirudh Venkataramanan struct ice_link_status link_info_old;
187dc49c772SAnirudh Venkataramanan u64 phy_type_low;
188aef74145SAnirudh Venkataramanan u64 phy_type_high;
189dc49c772SAnirudh Venkataramanan enum ice_media_type media_type;
19043f8b224SBruce Allan u8 get_link_info;
1911a3571b5SPaul Greenwalt /* Please refer to struct ice_aqc_get_link_status_data to get
1921a3571b5SPaul Greenwalt * detail of enable bit in curr_user_speed_req
1931a3571b5SPaul Greenwalt */
1941a3571b5SPaul Greenwalt u16 curr_user_speed_req;
1951a3571b5SPaul Greenwalt enum ice_fec_mode curr_user_fec_req;
1961a3571b5SPaul Greenwalt enum ice_fc_mode curr_user_fc_req;
1971a3571b5SPaul Greenwalt struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
198dc49c772SAnirudh Venkataramanan };
199dc49c772SAnirudh Venkataramanan
200148beb61SHenry Tieman /* protocol enumeration for filters */
201148beb61SHenry Tieman enum ice_fltr_ptype {
202148beb61SHenry Tieman /* NONE - used for undef/error */
203148beb61SHenry Tieman ICE_FLTR_PTYPE_NONF_NONE = 0,
204148beb61SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV4_UDP,
205148beb61SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV4_TCP,
206148beb61SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
207148beb61SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
208ef9e4cc5SQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
209ef9e4cc5SQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
210ef9e4cc5SQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP,
211ef9e4cc5SQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER,
212213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER,
213213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3,
214213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3,
215213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_ESP,
216213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV6_ESP,
217213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_AH,
218213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV6_AH,
219213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP,
220213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP,
221213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE,
222213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION,
223213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE,
224213528feSQi Zhang ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION,
22521606584SQi Zhang ICE_FLTR_PTYPE_NON_IP_L2,
226148beb61SHenry Tieman ICE_FLTR_PTYPE_FRAG_IPV4,
227165d80d6SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV6_UDP,
228165d80d6SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV6_TCP,
229165d80d6SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
230165d80d6SHenry Tieman ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
231148beb61SHenry Tieman ICE_FLTR_PTYPE_MAX,
232148beb61SHenry Tieman };
233148beb61SHenry Tieman
234148beb61SHenry Tieman enum ice_fd_hw_seg {
235148beb61SHenry Tieman ICE_FD_HW_SEG_NON_TUN = 0,
236148beb61SHenry Tieman ICE_FD_HW_SEG_TUN,
237148beb61SHenry Tieman ICE_FD_HW_SEG_MAX,
238148beb61SHenry Tieman };
239148beb61SHenry Tieman
24040319796SKiran Patil /* 1 ICE_VSI_PF + 1 ICE_VSI_CTRL + ICE_CHNL_MAX_TC */
24140319796SKiran Patil #define ICE_MAX_FDIR_VSI_PER_FILTER (2 + ICE_CHNL_MAX_TC)
242148beb61SHenry Tieman
243148beb61SHenry Tieman struct ice_fd_hw_prof {
244148beb61SHenry Tieman struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
245148beb61SHenry Tieman int cnt;
246148beb61SHenry Tieman u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
247148beb61SHenry Tieman u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
248148beb61SHenry Tieman };
249148beb61SHenry Tieman
2509c20346bSAnirudh Venkataramanan /* Common HW capabilities for SW use */
2519c20346bSAnirudh Venkataramanan struct ice_hw_common_caps {
252995c90f2SAnirudh Venkataramanan u32 valid_functions;
253a257f188SUsha Ketineni /* DCB capabilities */
254a257f188SUsha Ketineni u32 active_tc_bitmap;
255a257f188SUsha Ketineni u32 maxtc;
256995c90f2SAnirudh Venkataramanan
257f9867df6SAnirudh Venkataramanan /* Tx/Rx queues */
258f9867df6SAnirudh Venkataramanan u16 num_rxq; /* Number/Total Rx queues */
259f9867df6SAnirudh Venkataramanan u16 rxq_first_id; /* First queue ID for Rx queues */
260f9867df6SAnirudh Venkataramanan u16 num_txq; /* Number/Total Tx queues */
261f9867df6SAnirudh Venkataramanan u16 txq_first_id; /* First queue ID for Tx queues */
2629c20346bSAnirudh Venkataramanan
2639c20346bSAnirudh Venkataramanan /* MSI-X vectors */
2649c20346bSAnirudh Venkataramanan u16 num_msix_vectors;
2659c20346bSAnirudh Venkataramanan u16 msix_vector_first_id;
2669c20346bSAnirudh Venkataramanan
2679c20346bSAnirudh Venkataramanan /* Max MTU for function or device */
2689c20346bSAnirudh Venkataramanan u16 max_mtu;
2699c20346bSAnirudh Venkataramanan
27075d2b253SAnirudh Venkataramanan /* Virtualization support */
27175d2b253SAnirudh Venkataramanan u8 sr_iov_1_1; /* SR-IOV enabled */
272ddf30f7fSAnirudh Venkataramanan
2739c20346bSAnirudh Venkataramanan /* RSS related capabilities */
2749c20346bSAnirudh Venkataramanan u16 rss_table_size; /* 512 for PFs and 64 for VFs */
2759c20346bSAnirudh Venkataramanan u8 rss_table_entry_width; /* RSS Entry width in bits */
27637b6f646SAnirudh Venkataramanan
27737b6f646SAnirudh Venkataramanan u8 dcb;
2789733cc94SJacob Keller u8 ieee_1588;
279d25a0fc4SDave Ertman u8 rdma;
280bb52f42aSDave Ertman u8 roce_lag;
281bb52f42aSDave Ertman u8 sriov_lag;
282de9b277eSJacek Naczyk
2832ab560a7SJacob Keller bool nvm_update_pending_nvm;
2842ab560a7SJacob Keller bool nvm_update_pending_orom;
2852ab560a7SJacob Keller bool nvm_update_pending_netlist;
2862ab560a7SJacob Keller #define ICE_NVM_PENDING_NVM_IMAGE BIT(0)
2872ab560a7SJacob Keller #define ICE_NVM_PENDING_OROM BIT(1)
2882ab560a7SJacob Keller #define ICE_NVM_PENDING_NETLIST BIT(2)
289de9b277eSJacek Naczyk bool nvm_unified_update;
290de9b277eSJacek Naczyk #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
291399e27dbSJacob Keller /* PCIe reset avoidance */
292399e27dbSJacob Keller bool pcie_reset_avoidance;
293399e27dbSJacob Keller /* Post update reset restriction */
294399e27dbSJacob Keller bool reset_restrict_support;
2959c20346bSAnirudh Venkataramanan };
2969c20346bSAnirudh Venkataramanan
2979733cc94SJacob Keller /* IEEE 1588 TIME_SYNC specific info */
2989733cc94SJacob Keller /* Function specific definitions */
2999733cc94SJacob Keller #define ICE_TS_FUNC_ENA_M BIT(0)
3009733cc94SJacob Keller #define ICE_TS_SRC_TMR_OWND_M BIT(1)
3019733cc94SJacob Keller #define ICE_TS_TMR_ENA_M BIT(2)
3029733cc94SJacob Keller #define ICE_TS_TMR_IDX_OWND_S 4
3039733cc94SJacob Keller #define ICE_TS_TMR_IDX_OWND_M BIT(4)
3049733cc94SJacob Keller #define ICE_TS_CLK_FREQ_S 16
3059733cc94SJacob Keller #define ICE_TS_CLK_FREQ_M ICE_M(0x7, ICE_TS_CLK_FREQ_S)
3069733cc94SJacob Keller #define ICE_TS_CLK_SRC_S 20
3079733cc94SJacob Keller #define ICE_TS_CLK_SRC_M BIT(20)
3089733cc94SJacob Keller #define ICE_TS_TMR_IDX_ASSOC_S 24
3099733cc94SJacob Keller #define ICE_TS_TMR_IDX_ASSOC_M BIT(24)
3109733cc94SJacob Keller
311405efa49SJacob Keller /* TIME_REF clock rate specification */
312405efa49SJacob Keller enum ice_time_ref_freq {
313405efa49SJacob Keller ICE_TIME_REF_FREQ_25_000 = 0,
314405efa49SJacob Keller ICE_TIME_REF_FREQ_122_880 = 1,
315405efa49SJacob Keller ICE_TIME_REF_FREQ_125_000 = 2,
316405efa49SJacob Keller ICE_TIME_REF_FREQ_153_600 = 3,
317405efa49SJacob Keller ICE_TIME_REF_FREQ_156_250 = 4,
318405efa49SJacob Keller ICE_TIME_REF_FREQ_245_760 = 5,
319405efa49SJacob Keller
320405efa49SJacob Keller NUM_ICE_TIME_REF_FREQ
321405efa49SJacob Keller };
322405efa49SJacob Keller
323405efa49SJacob Keller /* Clock source specification */
324405efa49SJacob Keller enum ice_clk_src {
325405efa49SJacob Keller ICE_CLK_SRC_TCX0 = 0, /* Temperature compensated oscillator */
326405efa49SJacob Keller ICE_CLK_SRC_TIME_REF = 1, /* Use TIME_REF reference clock */
327405efa49SJacob Keller
328405efa49SJacob Keller NUM_ICE_CLK_SRC
329405efa49SJacob Keller };
330405efa49SJacob Keller
3319733cc94SJacob Keller struct ice_ts_func_info {
3329733cc94SJacob Keller /* Function specific info */
333405efa49SJacob Keller enum ice_time_ref_freq time_ref;
334405efa49SJacob Keller u8 clk_freq;
3359733cc94SJacob Keller u8 clk_src;
3369733cc94SJacob Keller u8 tmr_index_assoc;
3379733cc94SJacob Keller u8 ena;
3389733cc94SJacob Keller u8 tmr_index_owned;
3399733cc94SJacob Keller u8 src_tmr_owned;
3409733cc94SJacob Keller u8 tmr_ena;
3419733cc94SJacob Keller };
3429733cc94SJacob Keller
3439733cc94SJacob Keller /* Device specific definitions */
3449733cc94SJacob Keller #define ICE_TS_TMR0_OWNR_M 0x7
3459733cc94SJacob Keller #define ICE_TS_TMR0_OWND_M BIT(3)
3469733cc94SJacob Keller #define ICE_TS_TMR1_OWNR_S 4
3479733cc94SJacob Keller #define ICE_TS_TMR1_OWNR_M ICE_M(0x7, ICE_TS_TMR1_OWNR_S)
3489733cc94SJacob Keller #define ICE_TS_TMR1_OWND_M BIT(7)
3499733cc94SJacob Keller #define ICE_TS_DEV_ENA_M BIT(24)
3509733cc94SJacob Keller #define ICE_TS_TMR0_ENA_M BIT(25)
3519733cc94SJacob Keller #define ICE_TS_TMR1_ENA_M BIT(26)
3521229b339SKarol Kolacinski #define ICE_TS_LL_TX_TS_READ_M BIT(28)
3539733cc94SJacob Keller
3549733cc94SJacob Keller struct ice_ts_dev_info {
3559733cc94SJacob Keller /* Device specific info */
3569733cc94SJacob Keller u32 ena_ports;
3579733cc94SJacob Keller u32 tmr_own_map;
3589733cc94SJacob Keller u32 tmr0_owner;
3599733cc94SJacob Keller u32 tmr1_owner;
3609733cc94SJacob Keller u8 tmr0_owned;
3619733cc94SJacob Keller u8 tmr1_owned;
3629733cc94SJacob Keller u8 ena;
3639733cc94SJacob Keller u8 tmr0_ena;
3649733cc94SJacob Keller u8 tmr1_ena;
3651229b339SKarol Kolacinski u8 ts_ll_read;
3669733cc94SJacob Keller };
3679733cc94SJacob Keller
3689c20346bSAnirudh Venkataramanan /* Function specific capabilities */
3699c20346bSAnirudh Venkataramanan struct ice_hw_func_caps {
3709c20346bSAnirudh Venkataramanan struct ice_hw_common_caps common_cap;
37175d2b253SAnirudh Venkataramanan u32 num_allocd_vfs; /* Number of allocated VFs */
37275d2b253SAnirudh Venkataramanan u32 vf_base_id; /* Logical ID of the first VF */
373995c90f2SAnirudh Venkataramanan u32 guar_num_vsi;
374148beb61SHenry Tieman u32 fd_fltr_guar; /* Number of filters guaranteed */
375148beb61SHenry Tieman u32 fd_fltr_best_effort; /* Number of best effort filters */
3769733cc94SJacob Keller struct ice_ts_func_info ts_func_info;
3779c20346bSAnirudh Venkataramanan };
3789c20346bSAnirudh Venkataramanan
3799c20346bSAnirudh Venkataramanan /* Device wide capabilities */
3809c20346bSAnirudh Venkataramanan struct ice_hw_dev_caps {
3819c20346bSAnirudh Venkataramanan struct ice_hw_common_caps common_cap;
38275d2b253SAnirudh Venkataramanan u32 num_vfs_exposed; /* Total number of VFs exposed */
3839c20346bSAnirudh Venkataramanan u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
384148beb61SHenry Tieman u32 num_flow_director_fltr; /* Number of FD filters available */
3859733cc94SJacob Keller struct ice_ts_dev_info ts_dev_info;
386eae1bbb2SBruce Allan u32 num_funcs;
3879c20346bSAnirudh Venkataramanan };
3889c20346bSAnirudh Venkataramanan
389dc49c772SAnirudh Venkataramanan /* MAC info */
390dc49c772SAnirudh Venkataramanan struct ice_mac_info {
391dc49c772SAnirudh Venkataramanan u8 lan_addr[ETH_ALEN];
392dc49c772SAnirudh Venkataramanan u8 perm_addr[ETH_ALEN];
393dc49c772SAnirudh Venkataramanan };
394dc49c772SAnirudh Venkataramanan
395ca4929b6SBrett Creeley /* Reset types used to determine which kind of reset was requested. These
396ca4929b6SBrett Creeley * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
397ca4929b6SBrett Creeley * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
398ca4929b6SBrett Creeley * because its reset source is different than the other types listed.
399ca4929b6SBrett Creeley */
400f31e4b6fSAnirudh Venkataramanan enum ice_reset_req {
401ca4929b6SBrett Creeley ICE_RESET_POR = 0,
4020f9d5027SAnirudh Venkataramanan ICE_RESET_INVAL = 0,
403ca4929b6SBrett Creeley ICE_RESET_CORER = 1,
404ca4929b6SBrett Creeley ICE_RESET_GLOBR = 2,
405ca4929b6SBrett Creeley ICE_RESET_EMPR = 3,
406ca4929b6SBrett Creeley ICE_RESET_PFR = 4,
407f31e4b6fSAnirudh Venkataramanan };
408f31e4b6fSAnirudh Venkataramanan
409837f08fdSAnirudh Venkataramanan /* Bus parameters */
410837f08fdSAnirudh Venkataramanan struct ice_bus_info {
411837f08fdSAnirudh Venkataramanan u16 device;
412837f08fdSAnirudh Venkataramanan u8 func;
413837f08fdSAnirudh Venkataramanan };
414837f08fdSAnirudh Venkataramanan
415dc49c772SAnirudh Venkataramanan /* Flow control (FC) parameters */
416dc49c772SAnirudh Venkataramanan struct ice_fc_info {
417dc49c772SAnirudh Venkataramanan enum ice_fc_mode current_mode; /* FC mode in effect */
418dc49c772SAnirudh Venkataramanan enum ice_fc_mode req_mode; /* FC mode requested by caller */
419dc49c772SAnirudh Venkataramanan };
420dc49c772SAnirudh Venkataramanan
421d4e87444SJacob Keller /* Option ROM version information */
422d4e87444SJacob Keller struct ice_orom_info {
423d4e87444SJacob Keller u8 major; /* Major version of OROM */
424d4e87444SJacob Keller u8 patch; /* Patch version of OROM */
425d4e87444SJacob Keller u16 build; /* Build version of OROM */
426d4e87444SJacob Keller };
427d4e87444SJacob Keller
4289af368faSJacob Keller /* NVM version information */
429f31e4b6fSAnirudh Venkataramanan struct ice_nvm_info {
4309af368faSJacob Keller u32 eetrack;
4319af368faSJacob Keller u8 major;
4329af368faSJacob Keller u8 minor;
4339af368faSJacob Keller };
4349af368faSJacob Keller
4359af368faSJacob Keller /* netlist version information */
4369af368faSJacob Keller struct ice_netlist_info {
4379af368faSJacob Keller u32 major; /* major high/low */
4389af368faSJacob Keller u32 minor; /* minor high/low */
4399af368faSJacob Keller u32 type; /* type high/low */
4409af368faSJacob Keller u32 rev; /* revision high/low */
4419af368faSJacob Keller u32 hash; /* SHA-1 hash word */
4429af368faSJacob Keller u16 cust_ver; /* customer version */
4439af368faSJacob Keller };
4449af368faSJacob Keller
4451fa95e01SJacob Keller /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules
4461fa95e01SJacob Keller * of the flash image.
4471fa95e01SJacob Keller */
4481fa95e01SJacob Keller enum ice_flash_bank {
4491fa95e01SJacob Keller ICE_INVALID_FLASH_BANK,
4501fa95e01SJacob Keller ICE_1ST_FLASH_BANK,
4511fa95e01SJacob Keller ICE_2ND_FLASH_BANK,
4521fa95e01SJacob Keller };
4531fa95e01SJacob Keller
4540ce50c70SJacob Keller /* Enumeration of which flash bank is desired to read from, either the active
4550ce50c70SJacob Keller * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from
4560ce50c70SJacob Keller * code which just wants to read the active or inactive flash bank.
4570ce50c70SJacob Keller */
4580ce50c70SJacob Keller enum ice_bank_select {
4590ce50c70SJacob Keller ICE_ACTIVE_FLASH_BANK,
4600ce50c70SJacob Keller ICE_INACTIVE_FLASH_BANK,
4610ce50c70SJacob Keller };
4620ce50c70SJacob Keller
4631fa95e01SJacob Keller /* information for accessing NVM, OROM, and Netlist flash banks */
4641fa95e01SJacob Keller struct ice_bank_info {
4651fa95e01SJacob Keller u32 nvm_ptr; /* Pointer to 1st NVM bank */
4661fa95e01SJacob Keller u32 nvm_size; /* Size of NVM bank */
4671fa95e01SJacob Keller u32 orom_ptr; /* Pointer to 1st OROM bank */
4681fa95e01SJacob Keller u32 orom_size; /* Size of OROM bank */
4691fa95e01SJacob Keller u32 netlist_ptr; /* Pointer to 1st Netlist bank */
4701fa95e01SJacob Keller u32 netlist_size; /* Size of Netlist bank */
4711fa95e01SJacob Keller enum ice_flash_bank nvm_bank; /* Active NVM bank */
4721fa95e01SJacob Keller enum ice_flash_bank orom_bank; /* Active OROM bank */
4731fa95e01SJacob Keller enum ice_flash_bank netlist_bank; /* Active Netlist bank */
4741fa95e01SJacob Keller };
4751fa95e01SJacob Keller
4769af368faSJacob Keller /* Flash Chip Information */
4779af368faSJacob Keller struct ice_flash_info {
478d4e87444SJacob Keller struct ice_orom_info orom; /* Option ROM version info */
4799af368faSJacob Keller struct ice_nvm_info nvm; /* NVM version information */
4809af368faSJacob Keller struct ice_netlist_info netlist;/* Netlist version info */
4811fa95e01SJacob Keller struct ice_bank_info banks; /* Flash Bank information */
482f31e4b6fSAnirudh Venkataramanan u16 sr_words; /* Shadow RAM size in words */
48381f07491SJacob Keller u32 flash_size; /* Size of available flash in bytes */
48443f8b224SBruce Allan u8 blank_nvm_mode; /* is NVM empty (no FW present) */
485f31e4b6fSAnirudh Venkataramanan };
486f31e4b6fSAnirudh Venkataramanan
487ea78ce4dSPaul Greenwalt struct ice_link_default_override_tlv {
488ea78ce4dSPaul Greenwalt u8 options;
489ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_OPT_M 0x3F
490ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
491ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
492ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
493ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_EN BIT(3)
494ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
495ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
496ea78ce4dSPaul Greenwalt u8 phy_config;
497ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_PHY_CFG_S 8
498ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
499ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_PAUSE_M 0x3
500ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
501ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
502ea78ce4dSPaul Greenwalt u8 fec_options;
503ea78ce4dSPaul Greenwalt #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF
504ea78ce4dSPaul Greenwalt u8 rsvd1;
505ea78ce4dSPaul Greenwalt u64 phy_type_low;
506ea78ce4dSPaul Greenwalt u64 phy_type_high;
507ea78ce4dSPaul Greenwalt };
508ea78ce4dSPaul Greenwalt
509870f805eSLukasz Czapnik #define ICE_NVM_VER_LEN 32
510870f805eSLukasz Czapnik
5119c20346bSAnirudh Venkataramanan /* Max number of port to queue branches w.r.t topology */
5129c20346bSAnirudh Venkataramanan #define ICE_MAX_TRAFFIC_CLASS 8
513dc49c772SAnirudh Venkataramanan #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
5149c20346bSAnirudh Venkataramanan
5152bdc97beSBruce Allan #define ice_for_each_traffic_class(_i) \
5162bdc97beSBruce Allan for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
5172bdc97beSBruce Allan
518b126bd6bSKiran Patil /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
519b126bd6bSKiran Patil * to driver defined policy for default aggregator
520b126bd6bSKiran Patil */
5217b9ffc76SAnirudh Venkataramanan #define ICE_INVAL_TEID 0xFFFFFFFF
522b126bd6bSKiran Patil #define ICE_DFLT_AGG_ID 0
5237b9ffc76SAnirudh Venkataramanan
5249c20346bSAnirudh Venkataramanan struct ice_sched_node {
5259c20346bSAnirudh Venkataramanan struct ice_sched_node *parent;
5269c20346bSAnirudh Venkataramanan struct ice_sched_node *sibling; /* next sibling in the same layer */
5279c20346bSAnirudh Venkataramanan struct ice_sched_node **children;
5289c20346bSAnirudh Venkataramanan struct ice_aqc_txsched_elem_data info;
52916dfa494SMichal Wilczynski char *name;
53016dfa494SMichal Wilczynski struct devlink_rate *rate_node;
53116dfa494SMichal Wilczynski u64 tx_max;
53216dfa494SMichal Wilczynski u64 tx_share;
533f9867df6SAnirudh Venkataramanan u32 agg_id; /* aggregator group ID */
53416dfa494SMichal Wilczynski u32 id;
53516dfa494SMichal Wilczynski u32 tx_priority;
53616dfa494SMichal Wilczynski u32 tx_weight;
5374fb33f31SAnirudh Venkataramanan u16 vsi_handle;
53843f8b224SBruce Allan u8 in_use; /* suspended or in use */
5399c20346bSAnirudh Venkataramanan u8 tx_sched_layer; /* Logical Layer (1-9) */
5409c20346bSAnirudh Venkataramanan u8 num_children;
5419c20346bSAnirudh Venkataramanan u8 tc_num;
5429c20346bSAnirudh Venkataramanan u8 owner;
5439c20346bSAnirudh Venkataramanan #define ICE_SCHED_NODE_OWNER_LAN 0
544348048e7SDave Ertman #define ICE_SCHED_NODE_OWNER_RDMA 2
5459c20346bSAnirudh Venkataramanan };
5469c20346bSAnirudh Venkataramanan
547dc49c772SAnirudh Venkataramanan /* Access Macros for Tx Sched Elements data */
548dc49c772SAnirudh Venkataramanan #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid)
549dc49c772SAnirudh Venkataramanan
5509c20346bSAnirudh Venkataramanan /* The aggregator type determines if identifier is for a VSI group,
5519c20346bSAnirudh Venkataramanan * aggregator group, aggregator of queues, or queue group.
5529c20346bSAnirudh Venkataramanan */
5539c20346bSAnirudh Venkataramanan enum ice_agg_type {
5549c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_UNKNOWN = 0,
5559c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_VSI,
5569c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_AGG, /* aggregator */
5579c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_Q,
5589c20346bSAnirudh Venkataramanan ICE_AGG_TYPE_QG
5599c20346bSAnirudh Venkataramanan };
5609c20346bSAnirudh Venkataramanan
5611ddef455SUsha Ketineni /* Rate limit types */
5621ddef455SUsha Ketineni enum ice_rl_type {
5631ddef455SUsha Ketineni ICE_UNKNOWN_BW = 0,
5641ddef455SUsha Ketineni ICE_MIN_BW, /* for CIR profile */
5651ddef455SUsha Ketineni ICE_MAX_BW, /* for EIR profile */
5661ddef455SUsha Ketineni ICE_SHARED_BW /* for shared profile */
5671ddef455SUsha Ketineni };
5685513b920SAnirudh Venkataramanan
5691ddef455SUsha Ketineni #define ICE_SCHED_MIN_BW 500 /* in Kbps */
5701ddef455SUsha Ketineni #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
5711ddef455SUsha Ketineni #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
5721ddef455SUsha Ketineni #define ICE_SCHED_DFLT_RL_PROF_ID 0
5731ddef455SUsha Ketineni #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
574984824a2STarun Singh #define ICE_SCHED_DFLT_BW_WT 4
5751ddef455SUsha Ketineni #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
5761ddef455SUsha Ketineni #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
5771ddef455SUsha Ketineni
57826d1c571SAnatolii Gerasymenko #define ICE_MAX_PORT_PER_PCI_DEV 8
57926d1c571SAnatolii Gerasymenko
5801ddef455SUsha Ketineni /* Data structure for saving BW information */
5811ddef455SUsha Ketineni enum ice_bw_type {
5821ddef455SUsha Ketineni ICE_BW_TYPE_PRIO,
5831ddef455SUsha Ketineni ICE_BW_TYPE_CIR,
5841ddef455SUsha Ketineni ICE_BW_TYPE_CIR_WT,
5851ddef455SUsha Ketineni ICE_BW_TYPE_EIR,
5861ddef455SUsha Ketineni ICE_BW_TYPE_EIR_WT,
5871ddef455SUsha Ketineni ICE_BW_TYPE_SHARED,
5881ddef455SUsha Ketineni ICE_BW_TYPE_CNT /* This must be last */
5891ddef455SUsha Ketineni };
5901ddef455SUsha Ketineni
5911ddef455SUsha Ketineni struct ice_bw {
5921ddef455SUsha Ketineni u32 bw;
5931ddef455SUsha Ketineni u16 bw_alloc;
5941ddef455SUsha Ketineni };
5951ddef455SUsha Ketineni
5961ddef455SUsha Ketineni struct ice_bw_type_info {
5971ddef455SUsha Ketineni DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT);
5981ddef455SUsha Ketineni u8 generic;
5991ddef455SUsha Ketineni struct ice_bw cir_bw;
6001ddef455SUsha Ketineni struct ice_bw eir_bw;
6011ddef455SUsha Ketineni u32 shared_bw;
6021ddef455SUsha Ketineni };
6031ddef455SUsha Ketineni
6041ddef455SUsha Ketineni /* VSI queue context structure for given TC */
6051ddef455SUsha Ketineni struct ice_q_ctx {
6061ddef455SUsha Ketineni u16 q_handle;
6071ddef455SUsha Ketineni u32 q_teid;
6081ddef455SUsha Ketineni /* bw_t_info saves queue BW information */
6091ddef455SUsha Ketineni struct ice_bw_type_info bw_t_info;
6101ddef455SUsha Ketineni };
6111ddef455SUsha Ketineni
6121ddef455SUsha Ketineni /* VSI type list entry to locate corresponding VSI/aggregator nodes */
6139c20346bSAnirudh Venkataramanan struct ice_sched_vsi_info {
6149c20346bSAnirudh Venkataramanan struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
6159c20346bSAnirudh Venkataramanan struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
6169c20346bSAnirudh Venkataramanan struct list_head list_entry;
6179c20346bSAnirudh Venkataramanan u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
618348048e7SDave Ertman u16 max_rdmaq[ICE_MAX_TRAFFIC_CLASS];
6190754d65bSKiran Patil /* bw_t_info saves VSI BW information */
6200754d65bSKiran Patil struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
6219c20346bSAnirudh Venkataramanan };
6229c20346bSAnirudh Venkataramanan
6239c20346bSAnirudh Venkataramanan /* driver defines the policy */
6249c20346bSAnirudh Venkataramanan struct ice_sched_tx_policy {
6259c20346bSAnirudh Venkataramanan u16 max_num_vsis;
6269c20346bSAnirudh Venkataramanan u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS];
62743f8b224SBruce Allan u8 rdma_ena;
6289c20346bSAnirudh Venkataramanan };
6299c20346bSAnirudh Venkataramanan
6300ebd3ff1SAnirudh Venkataramanan /* CEE or IEEE 802.1Qaz ETS Configuration data */
6310ebd3ff1SAnirudh Venkataramanan struct ice_dcb_ets_cfg {
6320ebd3ff1SAnirudh Venkataramanan u8 willing;
6330ebd3ff1SAnirudh Venkataramanan u8 cbs;
6340ebd3ff1SAnirudh Venkataramanan u8 maxtcs;
6350ebd3ff1SAnirudh Venkataramanan u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
6360ebd3ff1SAnirudh Venkataramanan u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
6370ebd3ff1SAnirudh Venkataramanan u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
6380ebd3ff1SAnirudh Venkataramanan };
6390ebd3ff1SAnirudh Venkataramanan
6400ebd3ff1SAnirudh Venkataramanan /* CEE or IEEE 802.1Qaz PFC Configuration data */
6410ebd3ff1SAnirudh Venkataramanan struct ice_dcb_pfc_cfg {
6420ebd3ff1SAnirudh Venkataramanan u8 willing;
6430ebd3ff1SAnirudh Venkataramanan u8 mbc;
6440ebd3ff1SAnirudh Venkataramanan u8 pfccap;
6450ebd3ff1SAnirudh Venkataramanan u8 pfcena;
6460ebd3ff1SAnirudh Venkataramanan };
6470ebd3ff1SAnirudh Venkataramanan
6480ebd3ff1SAnirudh Venkataramanan /* CEE or IEEE 802.1Qaz Application Priority data */
6490ebd3ff1SAnirudh Venkataramanan struct ice_dcb_app_priority_table {
6500ebd3ff1SAnirudh Venkataramanan u16 prot_id;
6510ebd3ff1SAnirudh Venkataramanan u8 priority;
6520ebd3ff1SAnirudh Venkataramanan u8 selector;
6530ebd3ff1SAnirudh Venkataramanan };
6540ebd3ff1SAnirudh Venkataramanan
6550ebd3ff1SAnirudh Venkataramanan #define ICE_MAX_USER_PRIORITY 8
6562a87bd73SDave Ertman #define ICE_DCBX_MAX_APPS 64
6572a87bd73SDave Ertman #define ICE_DSCP_NUM_VAL 64
6580ebd3ff1SAnirudh Venkataramanan #define ICE_LLDPDU_SIZE 1500
6590ebd3ff1SAnirudh Venkataramanan #define ICE_TLV_STATUS_OPER 0x1
6600ebd3ff1SAnirudh Venkataramanan #define ICE_TLV_STATUS_SYNC 0x2
6610ebd3ff1SAnirudh Venkataramanan #define ICE_TLV_STATUS_ERR 0x4
662aeac8ce8SChinh T Cao #define ICE_APP_PROT_ID_ISCSI_860 0x035c
6630ebd3ff1SAnirudh Venkataramanan #define ICE_APP_SEL_ETHTYPE 0x1
6640ebd3ff1SAnirudh Venkataramanan #define ICE_APP_SEL_TCPIP 0x2
6650ebd3ff1SAnirudh Venkataramanan #define ICE_CEE_APP_SEL_ETHTYPE 0x0
666ea78ce4dSPaul Greenwalt #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134
6670ebd3ff1SAnirudh Venkataramanan #define ICE_CEE_APP_SEL_TCPIP 0x1
6680ebd3ff1SAnirudh Venkataramanan
6690ebd3ff1SAnirudh Venkataramanan struct ice_dcbx_cfg {
6700ebd3ff1SAnirudh Venkataramanan u32 numapps;
6710ebd3ff1SAnirudh Venkataramanan u32 tlv_status; /* CEE mode TLV status */
6720ebd3ff1SAnirudh Venkataramanan struct ice_dcb_ets_cfg etscfg;
6730ebd3ff1SAnirudh Venkataramanan struct ice_dcb_ets_cfg etsrec;
6740ebd3ff1SAnirudh Venkataramanan struct ice_dcb_pfc_cfg pfc;
6752a87bd73SDave Ertman #define ICE_QOS_MODE_VLAN 0x0
6762a87bd73SDave Ertman #define ICE_QOS_MODE_DSCP 0x1
6772a87bd73SDave Ertman u8 pfc_mode;
6780ebd3ff1SAnirudh Venkataramanan struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
6792a87bd73SDave Ertman /* when DSCP mapping defined by user set its bit to 1 */
6802a87bd73SDave Ertman DECLARE_BITMAP(dscp_mapped, ICE_DSCP_NUM_VAL);
6812a87bd73SDave Ertman /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */
6822a87bd73SDave Ertman u8 dscp_map[ICE_DSCP_NUM_VAL];
6830ebd3ff1SAnirudh Venkataramanan u8 dcbx_mode;
6840ebd3ff1SAnirudh Venkataramanan #define ICE_DCBX_MODE_CEE 0x1
6850ebd3ff1SAnirudh Venkataramanan #define ICE_DCBX_MODE_IEEE 0x2
6860ebd3ff1SAnirudh Venkataramanan u8 app_mode;
6870ebd3ff1SAnirudh Venkataramanan #define ICE_DCBX_APPS_NON_WILLING 0x1
6880ebd3ff1SAnirudh Venkataramanan };
6890ebd3ff1SAnirudh Venkataramanan
690fc2d1165SChinh T Cao struct ice_qos_cfg {
691fc2d1165SChinh T Cao struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
692fc2d1165SChinh T Cao struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
693fc2d1165SChinh T Cao struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
694fc2d1165SChinh T Cao u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */
695fc2d1165SChinh T Cao u8 is_sw_lldp : 1;
696fc2d1165SChinh T Cao };
697fc2d1165SChinh T Cao
6989c20346bSAnirudh Venkataramanan struct ice_port_info {
6999c20346bSAnirudh Venkataramanan struct ice_sched_node *root; /* Root Node per Port */
700f9867df6SAnirudh Venkataramanan struct ice_hw *hw; /* back pointer to HW instance */
701dc49c772SAnirudh Venkataramanan u32 last_node_teid; /* scheduler last node info */
7029c20346bSAnirudh Venkataramanan u16 sw_id; /* Initial switch ID belongs to port */
7039c20346bSAnirudh Venkataramanan u16 pf_vf_num;
7049c20346bSAnirudh Venkataramanan u8 port_state;
7059c20346bSAnirudh Venkataramanan #define ICE_SCHED_PORT_STATE_INIT 0x0
7069c20346bSAnirudh Venkataramanan #define ICE_SCHED_PORT_STATE_READY 0x1
7070437f1a9SJesse Brandeburg u8 lport;
7080437f1a9SJesse Brandeburg #define ICE_LPORT_MASK 0xff
709dc49c772SAnirudh Venkataramanan struct ice_fc_info fc;
710dc49c772SAnirudh Venkataramanan struct ice_mac_info mac;
711dc49c772SAnirudh Venkataramanan struct ice_phy_info phy;
7129c20346bSAnirudh Venkataramanan struct mutex sched_lock; /* protect access to TXSched tree */
71329358248SVictor Raj struct ice_sched_node *
71429358248SVictor Raj sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
7151ddef455SUsha Ketineni /* List contain profile ID(s) and other params per layer */
7161ddef455SUsha Ketineni struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
717fc2d1165SChinh T Cao struct ice_qos_cfg qos_cfg;
71816dfa494SMichal Wilczynski struct xarray sched_node_ids;
7190437f1a9SJesse Brandeburg u8 is_vf:1;
72080fe30a8SMichal Wilczynski u8 is_custom_tx_enabled:1;
7219c20346bSAnirudh Venkataramanan };
7229c20346bSAnirudh Venkataramanan
7239daf8208SAnirudh Venkataramanan struct ice_switch_info {
7249daf8208SAnirudh Venkataramanan struct list_head vsi_list_map_head;
72580d144c9SAnirudh Venkataramanan struct ice_sw_recipe *recp_list;
7260f94570dSGrishma Kotecha u16 prof_res_bm_init;
727450052a4SDan Nowlin u16 max_used_prof_index;
728450052a4SDan Nowlin
729450052a4SDan Nowlin DECLARE_BITMAP(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);
7309daf8208SAnirudh Venkataramanan };
7319daf8208SAnirudh Venkataramanan
7328b97ceb1SHieu Tran /* FW logging configuration */
7338b97ceb1SHieu Tran struct ice_fw_log_evnt {
7348b97ceb1SHieu Tran u8 cfg : 4; /* New event enables to configure */
7358b97ceb1SHieu Tran u8 cur : 4; /* Current/active event enables */
7368b97ceb1SHieu Tran };
7378b97ceb1SHieu Tran
7388b97ceb1SHieu Tran struct ice_fw_log_cfg {
7398b97ceb1SHieu Tran u8 cq_en : 1; /* FW logging is enabled via the control queue */
7408b97ceb1SHieu Tran u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */
7418b97ceb1SHieu Tran u8 actv_evnts; /* Cumulation of currently enabled log events */
7428b97ceb1SHieu Tran
7438b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S)
7448b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S)
7458b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S)
7468b97ceb1SHieu Tran #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S)
7478b97ceb1SHieu Tran struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX];
7488b97ceb1SHieu Tran };
7498b97ceb1SHieu Tran
7500891c896SVignesh Sridhar /* Enum defining the different states of the mailbox snapshot in the
7510891c896SVignesh Sridhar * PF-VF mailbox overflow detection algorithm. The snapshot can be in
7520891c896SVignesh Sridhar * states:
7530891c896SVignesh Sridhar * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot
7540891c896SVignesh Sridhar * within the mailbox buffer.
7550891c896SVignesh Sridhar * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot
7560891c896SVignesh Sridhar * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the
7570891c896SVignesh Sridhar * mailbox and mark any VFs sending more messages than the threshold limit set.
7580891c896SVignesh Sridhar * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF.
7590891c896SVignesh Sridhar */
7600891c896SVignesh Sridhar enum ice_mbx_snapshot_state {
7610891c896SVignesh Sridhar ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0,
7620891c896SVignesh Sridhar ICE_MAL_VF_DETECT_STATE_TRAVERSE,
7630891c896SVignesh Sridhar ICE_MAL_VF_DETECT_STATE_DETECT,
7640891c896SVignesh Sridhar ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF,
7650891c896SVignesh Sridhar };
7660891c896SVignesh Sridhar
7670891c896SVignesh Sridhar /* Structure to hold information of the static snapshot and the mailbox
7680891c896SVignesh Sridhar * buffer data used to generate and track the snapshot.
7690891c896SVignesh Sridhar * 1. state: the state of the mailbox snapshot in the malicious VF
7700891c896SVignesh Sridhar * detection state handler ice_mbx_vf_state_handler()
7710891c896SVignesh Sridhar * 2. head: head of the mailbox snapshot in a circular mailbox buffer
7720891c896SVignesh Sridhar * 3. tail: tail of the mailbox snapshot in a circular mailbox buffer
7730891c896SVignesh Sridhar * 4. num_iterations: number of messages traversed in circular mailbox buffer
7740891c896SVignesh Sridhar * 5. num_msg_proc: number of messages processed in mailbox
7750891c896SVignesh Sridhar * 6. num_pending_arq: number of pending asynchronous messages
7760891c896SVignesh Sridhar * 7. max_num_msgs_mbx: maximum messages in mailbox for currently
7770891c896SVignesh Sridhar * serviced work item or interrupt.
7780891c896SVignesh Sridhar */
7790891c896SVignesh Sridhar struct ice_mbx_snap_buffer_data {
7800891c896SVignesh Sridhar enum ice_mbx_snapshot_state state;
7810891c896SVignesh Sridhar u32 head;
7820891c896SVignesh Sridhar u32 tail;
7830891c896SVignesh Sridhar u32 num_iterations;
7840891c896SVignesh Sridhar u16 num_msg_proc;
7850891c896SVignesh Sridhar u16 num_pending_arq;
7860891c896SVignesh Sridhar u16 max_num_msgs_mbx;
7870891c896SVignesh Sridhar };
7880891c896SVignesh Sridhar
789e4eaf893SJacob Keller /* Structure used to track a single VF's messages on the mailbox:
7908cd8a6b1SJacob Keller * 1. list_entry: linked list entry node
7918cd8a6b1SJacob Keller * 2. msg_count: the number of asynchronous messages sent by this VF
7928cd8a6b1SJacob Keller * 3. malicious: whether this VF has been detected as malicious before
793e4eaf893SJacob Keller */
794e4eaf893SJacob Keller struct ice_mbx_vf_info {
7958cd8a6b1SJacob Keller struct list_head list_entry;
7968cd8a6b1SJacob Keller u32 msg_count;
797e4eaf893SJacob Keller u8 malicious : 1;
798e4eaf893SJacob Keller };
799e4eaf893SJacob Keller
8000891c896SVignesh Sridhar /* Structure to hold data relevant to the captured static snapshot
8010891c896SVignesh Sridhar * of the PF-VF mailbox.
8020891c896SVignesh Sridhar */
8030891c896SVignesh Sridhar struct ice_mbx_snapshot {
8040891c896SVignesh Sridhar struct ice_mbx_snap_buffer_data mbx_buf;
8058cd8a6b1SJacob Keller struct list_head mbx_vf;
8060891c896SVignesh Sridhar };
8070891c896SVignesh Sridhar
8080891c896SVignesh Sridhar /* Structure to hold data to be used for capturing or updating a
8090891c896SVignesh Sridhar * static snapshot.
8100891c896SVignesh Sridhar * 1. num_msg_proc: number of messages processed in mailbox
8110891c896SVignesh Sridhar * 2. num_pending_arq: number of pending asynchronous messages
8120891c896SVignesh Sridhar * 3. max_num_msgs_mbx: maximum messages in mailbox for currently
8130891c896SVignesh Sridhar * serviced work item or interrupt.
8140891c896SVignesh Sridhar * 4. async_watermark_val: An upper threshold set by caller to determine
8150891c896SVignesh Sridhar * if the pending arq count is large enough to assume that there is
8160891c896SVignesh Sridhar * the possibility of a mailicious VF.
8170891c896SVignesh Sridhar */
8180891c896SVignesh Sridhar struct ice_mbx_data {
8190891c896SVignesh Sridhar u16 num_msg_proc;
8200891c896SVignesh Sridhar u16 num_pending_arq;
8210891c896SVignesh Sridhar u16 max_num_msgs_mbx;
8220891c896SVignesh Sridhar u16 async_watermark_val;
8230891c896SVignesh Sridhar };
8240891c896SVignesh Sridhar
825837f08fdSAnirudh Venkataramanan /* Port hardware description */
826837f08fdSAnirudh Venkataramanan struct ice_hw {
827837f08fdSAnirudh Venkataramanan u8 __iomem *hw_addr;
828837f08fdSAnirudh Venkataramanan void *back;
8299c20346bSAnirudh Venkataramanan struct ice_aqc_layer_props *layer_info;
8309c20346bSAnirudh Venkataramanan struct ice_port_info *port_info;
8314f8a1497SBen Shelton /* PSM clock frequency for calculating RL profile params */
8324f8a1497SBen Shelton u32 psm_clk_freq;
8337ec59eeaSAnirudh Venkataramanan u64 debug_mask; /* bitmap for debug mask */
834f31e4b6fSAnirudh Venkataramanan enum ice_mac_type mac_type;
835837f08fdSAnirudh Venkataramanan
836148beb61SHenry Tieman u16 fd_ctr_base; /* FD counter base index */
837148beb61SHenry Tieman
838837f08fdSAnirudh Venkataramanan /* pci info */
839837f08fdSAnirudh Venkataramanan u16 device_id;
840837f08fdSAnirudh Venkataramanan u16 vendor_id;
841837f08fdSAnirudh Venkataramanan u16 subsystem_device_id;
842837f08fdSAnirudh Venkataramanan u16 subsystem_vendor_id;
843837f08fdSAnirudh Venkataramanan u8 revision_id;
844837f08fdSAnirudh Venkataramanan
845f31e4b6fSAnirudh Venkataramanan u8 pf_id; /* device profile info */
846f31e4b6fSAnirudh Venkataramanan
8471ddef455SUsha Ketineni u16 max_burst_size; /* driver sets this value */
8481ddef455SUsha Ketineni
849f9867df6SAnirudh Venkataramanan /* Tx Scheduler values */
85088865fc4SKarol Kolacinski u8 num_tx_sched_layers;
85188865fc4SKarol Kolacinski u8 num_tx_sched_phys_layers;
8529c20346bSAnirudh Venkataramanan u8 flattened_layers;
8539c20346bSAnirudh Venkataramanan u8 max_cgds;
8549c20346bSAnirudh Venkataramanan u8 sw_entry_point_layer;
855b36c598cSAnirudh Venkataramanan u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
8569be1d6f8SAnirudh Venkataramanan struct list_head agg_list; /* lists all aggregator */
8579c20346bSAnirudh Venkataramanan
8580f9d5027SAnirudh Venkataramanan struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
85943f8b224SBruce Allan u8 evb_veb; /* true for VEB, false for VEPA */
860f9867df6SAnirudh Venkataramanan u8 reset_ongoing; /* true if HW is in reset, false otherwise */
861837f08fdSAnirudh Venkataramanan struct ice_bus_info bus;
8629af368faSJacob Keller struct ice_flash_info flash;
8639c20346bSAnirudh Venkataramanan struct ice_hw_dev_caps dev_caps; /* device capabilities */
8649c20346bSAnirudh Venkataramanan struct ice_hw_func_caps func_caps; /* function capabilities */
865f31e4b6fSAnirudh Venkataramanan
8669daf8208SAnirudh Venkataramanan struct ice_switch_info *switch_info; /* switch filter lists */
8679daf8208SAnirudh Venkataramanan
8687ec59eeaSAnirudh Venkataramanan /* Control Queue info */
8697ec59eeaSAnirudh Venkataramanan struct ice_ctl_q_info adminq;
8708f5ee3c4SJacob Keller struct ice_ctl_q_info sbq;
87175d2b253SAnirudh Venkataramanan struct ice_ctl_q_info mailboxq;
8727ec59eeaSAnirudh Venkataramanan
8737ec59eeaSAnirudh Venkataramanan u8 api_branch; /* API branch version */
8747ec59eeaSAnirudh Venkataramanan u8 api_maj_ver; /* API major version */
8757ec59eeaSAnirudh Venkataramanan u8 api_min_ver; /* API minor version */
8767ec59eeaSAnirudh Venkataramanan u8 api_patch; /* API patch version */
8777ec59eeaSAnirudh Venkataramanan u8 fw_branch; /* firmware branch version */
8787ec59eeaSAnirudh Venkataramanan u8 fw_maj_ver; /* firmware major version */
8797ec59eeaSAnirudh Venkataramanan u8 fw_min_ver; /* firmware minor version */
8807ec59eeaSAnirudh Venkataramanan u8 fw_patch; /* firmware patch version */
8817ec59eeaSAnirudh Venkataramanan u32 fw_build; /* firmware build number */
882940b61afSAnirudh Venkataramanan
8838b97ceb1SHieu Tran struct ice_fw_log_cfg fw_log;
8849e4ab4c2SBrett Creeley
8859e4ab4c2SBrett Creeley /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
8864ee656bbSTony Nguyen * register. Used for determining the ITR/INTRL granularity during
8879e4ab4c2SBrett Creeley * initialization.
8889e4ab4c2SBrett Creeley */
8899e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_200G 0x0
8909e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_100G 0X1
8919e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_50G 0x2
8929e4ab4c2SBrett Creeley #define ICE_MAX_AGG_BW_25G 0x3
8939e4ab4c2SBrett Creeley /* ITR granularity for different speeds */
8949e4ab4c2SBrett Creeley #define ICE_ITR_GRAN_ABOVE_25 2
8959e4ab4c2SBrett Creeley #define ICE_ITR_GRAN_MAX_25 4
896940b61afSAnirudh Venkataramanan /* ITR granularity in 1 us */
8979e4ab4c2SBrett Creeley u8 itr_gran;
8989e4ab4c2SBrett Creeley /* INTRL granularity for different speeds */
8999e4ab4c2SBrett Creeley #define ICE_INTRL_GRAN_ABOVE_25 4
9009e4ab4c2SBrett Creeley #define ICE_INTRL_GRAN_MAX_25 8
9019e4ab4c2SBrett Creeley /* INTRL granularity in 1 us */
9029e4ab4c2SBrett Creeley u8 intrl_gran;
9039e4ab4c2SBrett Creeley
90403cb4473SJacob Keller #define ICE_PHY_PER_NAC 1
90503cb4473SJacob Keller #define ICE_MAX_QUAD 2
90603cb4473SJacob Keller #define ICE_NUM_QUAD_TYPE 2
90703cb4473SJacob Keller #define ICE_PORTS_PER_QUAD 4
90803cb4473SJacob Keller #define ICE_PHY_0_LAST_QUAD 1
90903cb4473SJacob Keller #define ICE_PORTS_PER_PHY 8
91003cb4473SJacob Keller #define ICE_NUM_EXTERNAL_PORTS ICE_PORTS_PER_PHY
91103cb4473SJacob Keller
912c7648810STony Nguyen /* Active package version (currently active) */
913c7648810STony Nguyen struct ice_pkg_ver active_pkg_ver;
914b8272919SVictor Raj u32 active_track_id;
915c7648810STony Nguyen u8 active_pkg_name[ICE_PKG_NAME_SIZE];
916c7648810STony Nguyen u8 active_pkg_in_nvm;
917c7648810STony Nguyen
918a05983c3SDan Nowlin /* Driver's package ver - (from the Ice Metadata section) */
919c7648810STony Nguyen struct ice_pkg_ver pkg_ver;
920c7648810STony Nguyen u8 pkg_name[ICE_PKG_NAME_SIZE];
921c7648810STony Nguyen
922a05983c3SDan Nowlin /* Driver's Ice segment format version and ID (from the Ice seg) */
923a05983c3SDan Nowlin struct ice_pkg_ver ice_seg_fmt_ver;
924a05983c3SDan Nowlin u8 ice_seg_id[ICE_SEG_ID_SIZE];
925c7648810STony Nguyen
926c7648810STony Nguyen /* Pointer to the ice segment */
927c7648810STony Nguyen struct ice_seg *seg;
928c7648810STony Nguyen
929c7648810STony Nguyen /* Pointer to allocated copy of pkg memory */
930c7648810STony Nguyen u8 *pkg_copy;
931c7648810STony Nguyen u32 pkg_size;
932c7648810STony Nguyen
933a4e82a81STony Nguyen /* tunneling info */
934a4e82a81STony Nguyen struct mutex tnl_lock;
935a4e82a81STony Nguyen struct ice_tunnel_table tnl;
936a4e82a81STony Nguyen
937b20e6c17SJakub Kicinski struct udp_tunnel_nic_shared udp_tunnel_shared;
938b20e6c17SJakub Kicinski struct udp_tunnel_nic_info udp_tunnel_nic;
939b20e6c17SJakub Kicinski
940a1ffafb0SBrett Creeley /* dvm boost update information */
941a1ffafb0SBrett Creeley struct ice_dvm_table dvm_upd;
942a1ffafb0SBrett Creeley
943c7648810STony Nguyen /* HW block tables */
944c7648810STony Nguyen struct ice_blk_info blk[ICE_BLK_COUNT];
945c90ed40cSTony Nguyen struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
946c90ed40cSTony Nguyen struct list_head fl_profs[ICE_BLK_COUNT];
947148beb61SHenry Tieman
948148beb61SHenry Tieman /* Flow Director filter info */
949148beb61SHenry Tieman int fdir_active_fltr;
950148beb61SHenry Tieman
951148beb61SHenry Tieman struct mutex fdir_fltr_lock; /* protect Flow Director */
952148beb61SHenry Tieman struct list_head fdir_list_head;
953148beb61SHenry Tieman
954cac2a27cSHenry Tieman /* Book-keeping of side-band filter count per flow-type.
955cac2a27cSHenry Tieman * This is used to detect and handle input set changes for
956cac2a27cSHenry Tieman * respective flow-type.
957cac2a27cSHenry Tieman */
958cac2a27cSHenry Tieman u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
959cac2a27cSHenry Tieman
960148beb61SHenry Tieman struct ice_fd_hw_prof **fdir_prof;
961148beb61SHenry Tieman DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
962c90ed40cSTony Nguyen struct mutex rss_locks; /* protect RSS configuration */
963c90ed40cSTony Nguyen struct list_head rss_list_head;
9640891c896SVignesh Sridhar struct ice_mbx_snapshot mbx_snapshot;
9658818b954SHaiyue Wang DECLARE_BITMAP(hw_ptype, ICE_FLOW_PTYPE_MAX);
966a1ffafb0SBrett Creeley u8 dvm_ena;
967885fe693SMaciej Machnikowski u16 io_expander_handle;
968837f08fdSAnirudh Venkataramanan };
969837f08fdSAnirudh Venkataramanan
970fcea6f3dSAnirudh Venkataramanan /* Statistics collected by each port, VSI, VEB, and S-channel */
971fcea6f3dSAnirudh Venkataramanan struct ice_eth_stats {
972fcea6f3dSAnirudh Venkataramanan u64 rx_bytes; /* gorc */
973fcea6f3dSAnirudh Venkataramanan u64 rx_unicast; /* uprc */
974fcea6f3dSAnirudh Venkataramanan u64 rx_multicast; /* mprc */
975fcea6f3dSAnirudh Venkataramanan u64 rx_broadcast; /* bprc */
976fcea6f3dSAnirudh Venkataramanan u64 rx_discards; /* rdpc */
977fcea6f3dSAnirudh Venkataramanan u64 rx_unknown_protocol; /* rupp */
978fcea6f3dSAnirudh Venkataramanan u64 tx_bytes; /* gotc */
979fcea6f3dSAnirudh Venkataramanan u64 tx_unicast; /* uptc */
980fcea6f3dSAnirudh Venkataramanan u64 tx_multicast; /* mptc */
981fcea6f3dSAnirudh Venkataramanan u64 tx_broadcast; /* bptc */
982fcea6f3dSAnirudh Venkataramanan u64 tx_discards; /* tdpc */
983fcea6f3dSAnirudh Venkataramanan u64 tx_errors; /* tepc */
984fcea6f3dSAnirudh Venkataramanan };
985fcea6f3dSAnirudh Venkataramanan
986610ed0e9SAvinash JD #define ICE_MAX_UP 8
987610ed0e9SAvinash JD
988fcea6f3dSAnirudh Venkataramanan /* Statistics collected by the MAC */
989fcea6f3dSAnirudh Venkataramanan struct ice_hw_port_stats {
990fcea6f3dSAnirudh Venkataramanan /* eth stats collected by the port */
991fcea6f3dSAnirudh Venkataramanan struct ice_eth_stats eth;
992fcea6f3dSAnirudh Venkataramanan /* additional port specific stats */
993fcea6f3dSAnirudh Venkataramanan u64 tx_dropped_link_down; /* tdold */
994fcea6f3dSAnirudh Venkataramanan u64 crc_errors; /* crcerrs */
995fcea6f3dSAnirudh Venkataramanan u64 illegal_bytes; /* illerrc */
996fcea6f3dSAnirudh Venkataramanan u64 error_bytes; /* errbc */
997fcea6f3dSAnirudh Venkataramanan u64 mac_local_faults; /* mlfc */
998fcea6f3dSAnirudh Venkataramanan u64 mac_remote_faults; /* mrfc */
999fcea6f3dSAnirudh Venkataramanan u64 rx_len_errors; /* rlec */
1000fcea6f3dSAnirudh Venkataramanan u64 link_xon_rx; /* lxonrxc */
1001fcea6f3dSAnirudh Venkataramanan u64 link_xoff_rx; /* lxoffrxc */
1002fcea6f3dSAnirudh Venkataramanan u64 link_xon_tx; /* lxontxc */
1003fcea6f3dSAnirudh Venkataramanan u64 link_xoff_tx; /* lxofftxc */
10044b0fdcebSAnirudh Venkataramanan u64 priority_xon_rx[8]; /* pxonrxc[8] */
10054b0fdcebSAnirudh Venkataramanan u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
10064b0fdcebSAnirudh Venkataramanan u64 priority_xon_tx[8]; /* pxontxc[8] */
10074b0fdcebSAnirudh Venkataramanan u64 priority_xoff_tx[8]; /* pxofftxc[8] */
10084b0fdcebSAnirudh Venkataramanan u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1009fcea6f3dSAnirudh Venkataramanan u64 rx_size_64; /* prc64 */
1010fcea6f3dSAnirudh Venkataramanan u64 rx_size_127; /* prc127 */
1011fcea6f3dSAnirudh Venkataramanan u64 rx_size_255; /* prc255 */
1012fcea6f3dSAnirudh Venkataramanan u64 rx_size_511; /* prc511 */
1013fcea6f3dSAnirudh Venkataramanan u64 rx_size_1023; /* prc1023 */
1014fcea6f3dSAnirudh Venkataramanan u64 rx_size_1522; /* prc1522 */
1015fcea6f3dSAnirudh Venkataramanan u64 rx_size_big; /* prc9522 */
1016fcea6f3dSAnirudh Venkataramanan u64 rx_undersize; /* ruc */
1017fcea6f3dSAnirudh Venkataramanan u64 rx_fragments; /* rfc */
1018fcea6f3dSAnirudh Venkataramanan u64 rx_oversize; /* roc */
1019fcea6f3dSAnirudh Venkataramanan u64 rx_jabber; /* rjc */
1020fcea6f3dSAnirudh Venkataramanan u64 tx_size_64; /* ptc64 */
1021fcea6f3dSAnirudh Venkataramanan u64 tx_size_127; /* ptc127 */
1022fcea6f3dSAnirudh Venkataramanan u64 tx_size_255; /* ptc255 */
1023fcea6f3dSAnirudh Venkataramanan u64 tx_size_511; /* ptc511 */
1024fcea6f3dSAnirudh Venkataramanan u64 tx_size_1023; /* ptc1023 */
1025fcea6f3dSAnirudh Venkataramanan u64 tx_size_1522; /* ptc1522 */
1026fcea6f3dSAnirudh Venkataramanan u64 tx_size_big; /* ptc9522 */
10274ab95646SHenry Tieman /* flow director stats */
10284ab95646SHenry Tieman u32 fd_sb_status;
10294ab95646SHenry Tieman u64 fd_sb_match;
1030fcea6f3dSAnirudh Venkataramanan };
1031fcea6f3dSAnirudh Venkataramanan
1032bc42afa9SBrett Creeley enum ice_sw_fwd_act_type {
1033bc42afa9SBrett Creeley ICE_FWD_TO_VSI = 0,
1034bc42afa9SBrett Creeley ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
1035bc42afa9SBrett Creeley ICE_FWD_TO_Q,
1036bc42afa9SBrett Creeley ICE_FWD_TO_QGRP,
1037bc42afa9SBrett Creeley ICE_DROP_PACKET,
1038bccd9bceSMarcin Szycik ICE_NOP,
1039bc42afa9SBrett Creeley ICE_INVAL_ACT
1040bc42afa9SBrett Creeley };
1041bc42afa9SBrett Creeley
1042e3c53928SBrett Creeley struct ice_aq_get_set_rss_lut_params {
1043e3c53928SBrett Creeley u8 *lut; /* input RSS LUT for set and output RSS LUT for get */
1044*b6143c9bSPrzemek Kitszel enum ice_lut_size lut_size; /* size of the LUT buffer */
1045*b6143c9bSPrzemek Kitszel enum ice_lut_type lut_type; /* type of the LUT (i.e. VSI, PF, Global) */
1046*b6143c9bSPrzemek Kitszel u16 vsi_handle; /* software VSI handle */
1047e3c53928SBrett Creeley u8 global_lut_id; /* only valid when lut_type is global */
1048e3c53928SBrett Creeley };
1049e3c53928SBrett Creeley
1050f31e4b6fSAnirudh Venkataramanan /* Checksum and Shadow RAM pointers */
10511fa95e01SJacob Keller #define ICE_SR_NVM_CTRL_WORD 0x00
1052031f2147SMd Fahad Iqbal Polash #define ICE_SR_BOOT_CFG_PTR 0x132
1053769c500dSAkeem G Abodunrin #define ICE_SR_NVM_WOL_CFG 0x19
1054d4e87444SJacob Keller #define ICE_NVM_OROM_VER_OFF 0x02
1055e961b679SJacob Keller #define ICE_SR_PBA_BLOCK_PTR 0x16
1056f31e4b6fSAnirudh Venkataramanan #define ICE_SR_NVM_DEV_STARTER_VER 0x18
1057f31e4b6fSAnirudh Venkataramanan #define ICE_SR_NVM_EETRACK_LO 0x2D
1058f31e4b6fSAnirudh Venkataramanan #define ICE_SR_NVM_EETRACK_HI 0x2E
1059fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_LO_SHIFT 0
1060fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
1061fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_HI_SHIFT 12
1062fcea6f3dSAnirudh Venkataramanan #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
1063d4e87444SJacob Keller #define ICE_OROM_VER_PATCH_SHIFT 0
1064d4e87444SJacob Keller #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
1065d4e87444SJacob Keller #define ICE_OROM_VER_BUILD_SHIFT 8
1066d4e87444SJacob Keller #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
1067d4e87444SJacob Keller #define ICE_OROM_VER_SHIFT 24
1068d4e87444SJacob Keller #define ICE_OROM_VER_MASK (0xff << ICE_OROM_VER_SHIFT)
1069031f2147SMd Fahad Iqbal Polash #define ICE_SR_PFA_PTR 0x40
1070544cd2acSCudzilo, Szymon T #define ICE_SR_1ST_NVM_BANK_PTR 0x42
10711fa95e01SJacob Keller #define ICE_SR_NVM_BANK_SIZE 0x43
1072544cd2acSCudzilo, Szymon T #define ICE_SR_1ST_OROM_BANK_PTR 0x44
10731fa95e01SJacob Keller #define ICE_SR_OROM_BANK_SIZE 0x45
1074544cd2acSCudzilo, Szymon T #define ICE_SR_NETLIST_BANK_PTR 0x46
10751fa95e01SJacob Keller #define ICE_SR_NETLIST_BANK_SIZE 0x47
1076f31e4b6fSAnirudh Venkataramanan #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
1077ea78ce4dSPaul Greenwalt
10780ce50c70SJacob Keller /* CSS Header words */
10790ce50c70SJacob Keller #define ICE_NVM_CSS_SREV_L 0x14
10800ce50c70SJacob Keller #define ICE_NVM_CSS_SREV_H 0x15
10810ce50c70SJacob Keller
10820ce50c70SJacob Keller /* Length of CSS header section in words */
10830ce50c70SJacob Keller #define ICE_CSS_HEADER_LENGTH 330
10840ce50c70SJacob Keller
10850ce50c70SJacob Keller /* Offset of Shadow RAM copy in the NVM bank area. */
10860ce50c70SJacob Keller #define ICE_NVM_SR_COPY_WORD_OFFSET roundup(ICE_CSS_HEADER_LENGTH, 32)
10870ce50c70SJacob Keller
10880ce50c70SJacob Keller /* Size in bytes of Option ROM trailer */
10890ce50c70SJacob Keller #define ICE_NVM_OROM_TRAILER_LENGTH (2 * ICE_CSS_HEADER_LENGTH)
10900ce50c70SJacob Keller
1091e120a9abSJacob Keller /* The Link Topology Netlist section is stored as a series of words. It is
1092e120a9abSJacob Keller * stored in the NVM as a TLV, with the first two words containing the type
1093e120a9abSJacob Keller * and length.
1094e120a9abSJacob Keller */
1095e120a9abSJacob Keller #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B
1096e120a9abSJacob Keller #define ICE_NETLIST_TYPE_OFFSET 0x0000
1097e120a9abSJacob Keller #define ICE_NETLIST_LEN_OFFSET 0x0001
1098e120a9abSJacob Keller
1099e120a9abSJacob Keller /* The Link Topology section follows the TLV header. When reading the netlist
1100e120a9abSJacob Keller * using ice_read_netlist_module, we need to account for the 2-word TLV
1101e120a9abSJacob Keller * header.
1102e120a9abSJacob Keller */
1103e120a9abSJacob Keller #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2)
1104e120a9abSJacob Keller
1105e120a9abSJacob Keller #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000)
1106e120a9abSJacob Keller #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001)
1107e120a9abSJacob Keller
1108e120a9abSJacob Keller #define ICE_LINK_TOPO_NODE_COUNT_M ICE_M(0x3FF, 0)
1109e120a9abSJacob Keller
1110e120a9abSJacob Keller /* The Netlist ID Block is located after all of the Link Topology nodes. */
1111e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_SIZE 0x30
1112e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n))
1113e120a9abSJacob Keller
1114e120a9abSJacob Keller /* netlist ID block field offsets (word offsets) */
1115e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02
1116e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03
1117e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04
1118e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05
1119e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06
1120e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07
1121e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_REV_LOW 0x08
1122e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09
1123e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n))
1124e120a9abSJacob Keller #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F
1125e120a9abSJacob Keller
11261fa95e01SJacob Keller /* Auxiliary field, mask, and shift definition for Shadow RAM and NVM Flash */
11271fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_1_S 0x06
11281fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
11291fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_VALID 0x1
11301fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3)
11311fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4)
11321fa95e01SJacob Keller #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5)
11331fa95e01SJacob Keller
11341fa95e01SJacob Keller #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15)
11351fa95e01SJacob Keller
1136ea78ce4dSPaul Greenwalt /* Link override related */
1137ea78ce4dSPaul Greenwalt #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10
1138ea78ce4dSPaul Greenwalt #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4
1139ea78ce4dSPaul Greenwalt #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2
1140ea78ce4dSPaul Greenwalt #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1
1141ea78ce4dSPaul Greenwalt #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2
1142ea78ce4dSPaul Greenwalt #define ICE_FW_API_LINK_OVERRIDE_MAJ 1
1143ea78ce4dSPaul Greenwalt #define ICE_FW_API_LINK_OVERRIDE_MIN 5
1144ea78ce4dSPaul Greenwalt #define ICE_FW_API_LINK_OVERRIDE_PATCH 2
1145ea78ce4dSPaul Greenwalt
1146f31e4b6fSAnirudh Venkataramanan #define ICE_SR_WORDS_IN_1KB 512
1147f31e4b6fSAnirudh Venkataramanan
114834295a36SDave Ertman /* AQ API version for LLDP_FILTER_CONTROL */
114934295a36SDave Ertman #define ICE_FW_API_LLDP_FLTR_MAJ 1
115034295a36SDave Ertman #define ICE_FW_API_LLDP_FLTR_MIN 7
115134295a36SDave Ertman #define ICE_FW_API_LLDP_FLTR_PATCH 1
115234295a36SDave Ertman
11530a02944fSAnirudh Venkataramanan /* AQ API version for report default configuration */
11540a02944fSAnirudh Venkataramanan #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1
11550a02944fSAnirudh Venkataramanan #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7
11560a02944fSAnirudh Venkataramanan #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3
11570a02944fSAnirudh Venkataramanan
1158837f08fdSAnirudh Venkataramanan #endif /* _ICE_TYPE_H_ */
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