1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
3 
4 #ifndef _ICE_TXRX_H_
5 #define _ICE_TXRX_H_
6 
7 #include "ice_type.h"
8 
9 #define ICE_DFLT_IRQ_WORK	256
10 #define ICE_RXBUF_3072		3072
11 #define ICE_RXBUF_2048		2048
12 #define ICE_RXBUF_1536		1536
13 #define ICE_MAX_CHAINED_RX_BUFS	5
14 #define ICE_MAX_BUF_TXD		8
15 #define ICE_MIN_TX_LEN		17
16 
17 /* The size limit for a transmit buffer in a descriptor is (16K - 1).
18  * In order to align with the read requests we will align the value to
19  * the nearest 4K which represents our maximum read request size.
20  */
21 #define ICE_MAX_READ_REQ_SIZE	4096
22 #define ICE_MAX_DATA_PER_TXD	(16 * 1024 - 1)
23 #define ICE_MAX_DATA_PER_TXD_ALIGNED \
24 	(~(ICE_MAX_READ_REQ_SIZE - 1) & ICE_MAX_DATA_PER_TXD)
25 
26 #define ICE_MAX_TXQ_PER_TXQG	128
27 
28 /* Attempt to maximize the headroom available for incoming frames. We use a 2K
29  * buffer for MTUs <= 1500 and need 1536/1534 to store the data for the frame.
30  * This leaves us with 512 bytes of room.  From that we need to deduct the
31  * space needed for the shared info and the padding needed to IP align the
32  * frame.
33  *
34  * Note: For cache line sizes 256 or larger this value is going to end
35  *	 up negative.  In these cases we should fall back to the legacy
36  *	 receive path.
37  */
38 #if (PAGE_SIZE < 8192)
39 #define ICE_2K_TOO_SMALL_WITH_PADDING \
40 	((unsigned int)(NET_SKB_PAD + ICE_RXBUF_1536) > \
41 			SKB_WITH_OVERHEAD(ICE_RXBUF_2048))
42 
43 /**
44  * ice_compute_pad - compute the padding
45  * @rx_buf_len: buffer length
46  *
47  * Figure out the size of half page based on given buffer length and
48  * then subtract the skb_shared_info followed by subtraction of the
49  * actual buffer length; this in turn results in the actual space that
50  * is left for padding usage
51  */
52 static inline int ice_compute_pad(int rx_buf_len)
53 {
54 	int half_page_size;
55 
56 	half_page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2);
57 	return SKB_WITH_OVERHEAD(half_page_size) - rx_buf_len;
58 }
59 
60 /**
61  * ice_skb_pad - determine the padding that we can supply
62  *
63  * Figure out the right Rx buffer size and based on that calculate the
64  * padding
65  */
66 static inline int ice_skb_pad(void)
67 {
68 	int rx_buf_len;
69 
70 	/* If a 2K buffer cannot handle a standard Ethernet frame then
71 	 * optimize padding for a 3K buffer instead of a 1.5K buffer.
72 	 *
73 	 * For a 3K buffer we need to add enough padding to allow for
74 	 * tailroom due to NET_IP_ALIGN possibly shifting us out of
75 	 * cache-line alignment.
76 	 */
77 	if (ICE_2K_TOO_SMALL_WITH_PADDING)
78 		rx_buf_len = ICE_RXBUF_3072 + SKB_DATA_ALIGN(NET_IP_ALIGN);
79 	else
80 		rx_buf_len = ICE_RXBUF_1536;
81 
82 	/* if needed make room for NET_IP_ALIGN */
83 	rx_buf_len -= NET_IP_ALIGN;
84 
85 	return ice_compute_pad(rx_buf_len);
86 }
87 
88 #define ICE_SKB_PAD ice_skb_pad()
89 #else
90 #define ICE_2K_TOO_SMALL_WITH_PADDING false
91 #define ICE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
92 #endif
93 
94 /* We are assuming that the cache line is always 64 Bytes here for ice.
95  * In order to make sure that is a correct assumption there is a check in probe
96  * to print a warning if the read from GLPCI_CNF2 tells us that the cache line
97  * size is 128 bytes. We do it this way because we do not want to read the
98  * GLPCI_CNF2 register or a variable containing the value on every pass through
99  * the Tx path.
100  */
101 #define ICE_CACHE_LINE_BYTES		64
102 #define ICE_DESCS_PER_CACHE_LINE	(ICE_CACHE_LINE_BYTES / \
103 					 sizeof(struct ice_tx_desc))
104 #define ICE_DESCS_FOR_CTX_DESC		1
105 #define ICE_DESCS_FOR_SKB_DATA_PTR	1
106 /* Tx descriptors needed, worst case */
107 #define DESC_NEEDED (MAX_SKB_FRAGS + ICE_DESCS_FOR_CTX_DESC + \
108 		     ICE_DESCS_PER_CACHE_LINE + ICE_DESCS_FOR_SKB_DATA_PTR)
109 #define ICE_DESC_UNUSED(R)	\
110 	(u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
111 	      (R)->next_to_clean - (R)->next_to_use - 1)
112 
113 #define ICE_RING_QUARTER(R) ((R)->count >> 2)
114 
115 #define ICE_TX_FLAGS_TSO	BIT(0)
116 #define ICE_TX_FLAGS_HW_VLAN	BIT(1)
117 #define ICE_TX_FLAGS_SW_VLAN	BIT(2)
118 /* ICE_TX_FLAGS_DUMMY_PKT is used to mark dummy packets that should be
119  * freed instead of returned like skb packets.
120  */
121 #define ICE_TX_FLAGS_DUMMY_PKT	BIT(3)
122 #define ICE_TX_FLAGS_TSYN	BIT(4)
123 #define ICE_TX_FLAGS_IPV4	BIT(5)
124 #define ICE_TX_FLAGS_IPV6	BIT(6)
125 #define ICE_TX_FLAGS_TUNNEL	BIT(7)
126 #define ICE_TX_FLAGS_HW_OUTER_SINGLE_VLAN	BIT(8)
127 #define ICE_TX_FLAGS_VLAN_M	0xffff0000
128 #define ICE_TX_FLAGS_VLAN_PR_M	0xe0000000
129 #define ICE_TX_FLAGS_VLAN_PR_S	29
130 #define ICE_TX_FLAGS_VLAN_S	16
131 
132 #define ICE_XDP_PASS		0
133 #define ICE_XDP_CONSUMED	BIT(0)
134 #define ICE_XDP_TX		BIT(1)
135 #define ICE_XDP_REDIR		BIT(2)
136 
137 #define ICE_RX_DMA_ATTR \
138 	(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
139 
140 #define ICE_ETH_PKT_HDR_PAD	(ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2))
141 
142 #define ICE_TXD_LAST_DESC_CMD (ICE_TX_DESC_CMD_EOP | ICE_TX_DESC_CMD_RS)
143 
144 struct ice_tx_buf {
145 	struct ice_tx_desc *next_to_watch;
146 	union {
147 		struct sk_buff *skb;
148 		void *raw_buf; /* used for XDP */
149 	};
150 	unsigned int bytecount;
151 	unsigned short gso_segs;
152 	u32 tx_flags;
153 	DEFINE_DMA_UNMAP_LEN(len);
154 	DEFINE_DMA_UNMAP_ADDR(dma);
155 };
156 
157 struct ice_tx_offload_params {
158 	u64 cd_qw1;
159 	struct ice_tx_ring *tx_ring;
160 	u32 td_cmd;
161 	u32 td_offset;
162 	u32 td_l2tag1;
163 	u32 cd_tunnel_params;
164 	u16 cd_l2tag2;
165 	u8 header_len;
166 };
167 
168 struct ice_rx_buf {
169 	dma_addr_t dma;
170 	struct page *page;
171 	unsigned int page_offset;
172 	u16 pagecnt_bias;
173 };
174 
175 struct ice_q_stats {
176 	u64 pkts;
177 	u64 bytes;
178 };
179 
180 struct ice_txq_stats {
181 	u64 restart_q;
182 	u64 tx_busy;
183 	u64 tx_linearize;
184 	int prev_pkt; /* negative if no pending Tx descriptors */
185 };
186 
187 struct ice_rxq_stats {
188 	u64 non_eop_descs;
189 	u64 alloc_page_failed;
190 	u64 alloc_buf_failed;
191 };
192 
193 enum ice_ring_state_t {
194 	ICE_TX_XPS_INIT_DONE,
195 	ICE_TX_NBITS,
196 };
197 
198 /* this enum matches hardware bits and is meant to be used by DYN_CTLN
199  * registers and QINT registers or more generally anywhere in the manual
200  * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
201  * register but instead is a special value meaning "don't update" ITR0/1/2.
202  */
203 enum ice_dyn_idx_t {
204 	ICE_IDX_ITR0 = 0,
205 	ICE_IDX_ITR1 = 1,
206 	ICE_IDX_ITR2 = 2,
207 	ICE_ITR_NONE = 3	/* ITR_NONE must not be used as an index */
208 };
209 
210 /* Header split modes defined by DTYPE field of Rx RLAN context */
211 enum ice_rx_dtype {
212 	ICE_RX_DTYPE_NO_SPLIT		= 0,
213 	ICE_RX_DTYPE_HEADER_SPLIT	= 1,
214 	ICE_RX_DTYPE_SPLIT_ALWAYS	= 2,
215 };
216 
217 /* indices into GLINT_ITR registers */
218 #define ICE_RX_ITR	ICE_IDX_ITR0
219 #define ICE_TX_ITR	ICE_IDX_ITR1
220 #define ICE_ITR_8K	124
221 #define ICE_ITR_20K	50
222 #define ICE_ITR_MAX	8160 /* 0x1FE0 */
223 #define ICE_DFLT_TX_ITR	ICE_ITR_20K
224 #define ICE_DFLT_RX_ITR	ICE_ITR_20K
225 enum ice_dynamic_itr {
226 	ITR_STATIC = 0,
227 	ITR_DYNAMIC = 1
228 };
229 
230 #define ITR_IS_DYNAMIC(rc) ((rc)->itr_mode == ITR_DYNAMIC)
231 #define ICE_ITR_GRAN_S		1	/* ITR granularity is always 2us */
232 #define ICE_ITR_GRAN_US		BIT(ICE_ITR_GRAN_S)
233 #define ICE_ITR_MASK		0x1FFE	/* ITR register value alignment mask */
234 #define ITR_REG_ALIGN(setting)	((setting) & ICE_ITR_MASK)
235 
236 #define ICE_DFLT_INTRL	0
237 #define ICE_MAX_INTRL	236
238 
239 #define ICE_IN_WB_ON_ITR_MODE	255
240 /* Sets WB_ON_ITR and assumes INTENA bit is already cleared, which allows
241  * setting the MSK_M bit to tell hardware to ignore the INTENA_M bit. Also,
242  * set the write-back latency to the usecs passed in.
243  */
244 #define ICE_GLINT_DYN_CTL_WB_ON_ITR(usecs, itr_idx)	\
245 	((((usecs) << (GLINT_DYN_CTL_INTERVAL_S - ICE_ITR_GRAN_S)) & \
246 	  GLINT_DYN_CTL_INTERVAL_M) | \
247 	 (((itr_idx) << GLINT_DYN_CTL_ITR_INDX_S) & \
248 	  GLINT_DYN_CTL_ITR_INDX_M) | GLINT_DYN_CTL_INTENA_MSK_M | \
249 	 GLINT_DYN_CTL_WB_ON_ITR_M)
250 
251 /* Legacy or Advanced Mode Queue */
252 #define ICE_TX_ADVANCED	0
253 #define ICE_TX_LEGACY	1
254 
255 /* descriptor ring, associated with a VSI */
256 struct ice_rx_ring {
257 	/* CL1 - 1st cacheline starts here */
258 	struct ice_rx_ring *next;	/* pointer to next ring in q_vector */
259 	void *desc;			/* Descriptor ring memory */
260 	struct device *dev;		/* Used for DMA mapping */
261 	struct net_device *netdev;	/* netdev ring maps to */
262 	struct ice_vsi *vsi;		/* Backreference to associated VSI */
263 	struct ice_q_vector *q_vector;	/* Backreference to associated vector */
264 	u8 __iomem *tail;
265 	union {
266 		struct ice_rx_buf *rx_buf;
267 		struct xdp_buff **xdp_buf;
268 	};
269 	/* CL2 - 2nd cacheline starts here */
270 	struct xdp_rxq_info xdp_rxq;
271 	/* CL3 - 3rd cacheline starts here */
272 	u16 q_index;			/* Queue number of ring */
273 
274 	u16 count;			/* Number of descriptors */
275 	u16 reg_idx;			/* HW register index of the ring */
276 
277 	/* used in interrupt processing */
278 	u16 next_to_use;
279 	u16 next_to_clean;
280 	u16 next_to_alloc;
281 	u16 rx_offset;
282 	u16 rx_buf_len;
283 
284 	/* stats structs */
285 	struct ice_rxq_stats rx_stats;
286 	struct ice_q_stats	stats;
287 	struct u64_stats_sync syncp;
288 
289 	struct rcu_head rcu;		/* to avoid race on free */
290 	/* CL4 - 3rd cacheline starts here */
291 	struct ice_channel *ch;
292 	struct bpf_prog *xdp_prog;
293 	struct ice_tx_ring *xdp_ring;
294 	struct xsk_buff_pool *xsk_pool;
295 	struct sk_buff *skb;
296 	dma_addr_t dma;			/* physical address of ring */
297 #define ICE_RX_FLAGS_RING_BUILD_SKB	BIT(1)
298 	u64 cached_phctime;
299 	u8 dcb_tc;			/* Traffic class of ring */
300 	u8 ptp_rx;
301 	u8 flags;
302 } ____cacheline_internodealigned_in_smp;
303 
304 struct ice_tx_ring {
305 	/* CL1 - 1st cacheline starts here */
306 	struct ice_tx_ring *next;	/* pointer to next ring in q_vector */
307 	void *desc;			/* Descriptor ring memory */
308 	struct device *dev;		/* Used for DMA mapping */
309 	u8 __iomem *tail;
310 	struct ice_tx_buf *tx_buf;
311 	struct ice_q_vector *q_vector;	/* Backreference to associated vector */
312 	struct net_device *netdev;	/* netdev ring maps to */
313 	struct ice_vsi *vsi;		/* Backreference to associated VSI */
314 	/* CL2 - 2nd cacheline starts here */
315 	dma_addr_t dma;			/* physical address of ring */
316 	struct xsk_buff_pool *xsk_pool;
317 	u16 next_to_use;
318 	u16 next_to_clean;
319 	u16 next_rs;
320 	u16 next_dd;
321 	u16 q_handle;			/* Queue handle per TC */
322 	u16 reg_idx;			/* HW register index of the ring */
323 	u16 count;			/* Number of descriptors */
324 	u16 q_index;			/* Queue number of ring */
325 	/* stats structs */
326 	struct ice_txq_stats tx_stats;
327 	/* CL3 - 3rd cacheline starts here */
328 	struct ice_q_stats	stats;
329 	struct u64_stats_sync syncp;
330 	struct rcu_head rcu;		/* to avoid race on free */
331 	DECLARE_BITMAP(xps_state, ICE_TX_NBITS);	/* XPS Config State */
332 	struct ice_channel *ch;
333 	struct ice_ptp_tx *tx_tstamps;
334 	spinlock_t tx_lock;
335 	u32 txq_teid;			/* Added Tx queue TEID */
336 	/* CL4 - 4th cacheline starts here */
337 	u16 xdp_tx_active;
338 #define ICE_TX_FLAGS_RING_XDP		BIT(0)
339 #define ICE_TX_FLAGS_RING_VLAN_L2TAG1	BIT(1)
340 #define ICE_TX_FLAGS_RING_VLAN_L2TAG2	BIT(2)
341 	u8 flags;
342 	u8 dcb_tc;			/* Traffic class of ring */
343 	u8 ptp_tx;
344 } ____cacheline_internodealigned_in_smp;
345 
346 static inline bool ice_ring_uses_build_skb(struct ice_rx_ring *ring)
347 {
348 	return !!(ring->flags & ICE_RX_FLAGS_RING_BUILD_SKB);
349 }
350 
351 static inline void ice_set_ring_build_skb_ena(struct ice_rx_ring *ring)
352 {
353 	ring->flags |= ICE_RX_FLAGS_RING_BUILD_SKB;
354 }
355 
356 static inline void ice_clear_ring_build_skb_ena(struct ice_rx_ring *ring)
357 {
358 	ring->flags &= ~ICE_RX_FLAGS_RING_BUILD_SKB;
359 }
360 
361 static inline bool ice_ring_ch_enabled(struct ice_tx_ring *ring)
362 {
363 	return !!ring->ch;
364 }
365 
366 static inline bool ice_ring_is_xdp(struct ice_tx_ring *ring)
367 {
368 	return !!(ring->flags & ICE_TX_FLAGS_RING_XDP);
369 }
370 
371 enum ice_container_type {
372 	ICE_RX_CONTAINER,
373 	ICE_TX_CONTAINER,
374 };
375 
376 struct ice_ring_container {
377 	/* head of linked-list of rings */
378 	union {
379 		struct ice_rx_ring *rx_ring;
380 		struct ice_tx_ring *tx_ring;
381 	};
382 	struct dim dim;		/* data for net_dim algorithm */
383 	u16 itr_idx;		/* index in the interrupt vector */
384 	/* this matches the maximum number of ITR bits, but in usec
385 	 * values, so it is shifted left one bit (bit zero is ignored)
386 	 */
387 	u16 itr_setting:13;
388 	u16 itr_reserved:2;
389 	u16 itr_mode:1;
390 	enum ice_container_type type;
391 };
392 
393 struct ice_coalesce_stored {
394 	u16 itr_tx;
395 	u16 itr_rx;
396 	u8 intrl;
397 	u8 tx_valid;
398 	u8 rx_valid;
399 };
400 
401 /* iterator for handling rings in ring container */
402 #define ice_for_each_rx_ring(pos, head) \
403 	for (pos = (head).rx_ring; pos; pos = pos->next)
404 
405 #define ice_for_each_tx_ring(pos, head) \
406 	for (pos = (head).tx_ring; pos; pos = pos->next)
407 
408 static inline unsigned int ice_rx_pg_order(struct ice_rx_ring *ring)
409 {
410 #if (PAGE_SIZE < 8192)
411 	if (ring->rx_buf_len > (PAGE_SIZE / 2))
412 		return 1;
413 #endif
414 	return 0;
415 }
416 
417 #define ice_rx_pg_size(_ring) (PAGE_SIZE << ice_rx_pg_order(_ring))
418 
419 union ice_32b_rx_flex_desc;
420 
421 bool ice_alloc_rx_bufs(struct ice_rx_ring *rxr, u16 cleaned_count);
422 netdev_tx_t ice_start_xmit(struct sk_buff *skb, struct net_device *netdev);
423 u16
424 ice_select_queue(struct net_device *dev, struct sk_buff *skb,
425 		 struct net_device *sb_dev);
426 void ice_clean_tx_ring(struct ice_tx_ring *tx_ring);
427 void ice_clean_rx_ring(struct ice_rx_ring *rx_ring);
428 int ice_setup_tx_ring(struct ice_tx_ring *tx_ring);
429 int ice_setup_rx_ring(struct ice_rx_ring *rx_ring);
430 void ice_free_tx_ring(struct ice_tx_ring *tx_ring);
431 void ice_free_rx_ring(struct ice_rx_ring *rx_ring);
432 int ice_napi_poll(struct napi_struct *napi, int budget);
433 int
434 ice_prgm_fdir_fltr(struct ice_vsi *vsi, struct ice_fltr_desc *fdir_desc,
435 		   u8 *raw_packet);
436 int ice_clean_rx_irq(struct ice_rx_ring *rx_ring, int budget);
437 void ice_clean_ctrl_tx_irq(struct ice_tx_ring *tx_ring);
438 #endif /* _ICE_TXRX_H_ */
439