1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_TXRX_H_ 5 #define _ICE_TXRX_H_ 6 7 #include "ice_type.h" 8 9 #define ICE_DFLT_IRQ_WORK 256 10 #define ICE_RXBUF_3072 3072 11 #define ICE_RXBUF_2048 2048 12 #define ICE_RXBUF_1664 1664 13 #define ICE_RXBUF_1536 1536 14 #define ICE_MAX_CHAINED_RX_BUFS 5 15 #define ICE_MAX_BUF_TXD 8 16 #define ICE_MIN_TX_LEN 17 17 #define ICE_MAX_FRAME_LEGACY_RX 8320 18 19 /* The size limit for a transmit buffer in a descriptor is (16K - 1). 20 * In order to align with the read requests we will align the value to 21 * the nearest 4K which represents our maximum read request size. 22 */ 23 #define ICE_MAX_READ_REQ_SIZE 4096 24 #define ICE_MAX_DATA_PER_TXD (16 * 1024 - 1) 25 #define ICE_MAX_DATA_PER_TXD_ALIGNED \ 26 (~(ICE_MAX_READ_REQ_SIZE - 1) & ICE_MAX_DATA_PER_TXD) 27 28 #define ICE_MAX_TXQ_PER_TXQG 128 29 30 /* Attempt to maximize the headroom available for incoming frames. We use a 2K 31 * buffer for MTUs <= 1500 and need 1536/1534 to store the data for the frame. 32 * This leaves us with 512 bytes of room. From that we need to deduct the 33 * space needed for the shared info and the padding needed to IP align the 34 * frame. 35 * 36 * Note: For cache line sizes 256 or larger this value is going to end 37 * up negative. In these cases we should fall back to the legacy 38 * receive path. 39 */ 40 #if (PAGE_SIZE < 8192) 41 #define ICE_2K_TOO_SMALL_WITH_PADDING \ 42 ((unsigned int)(NET_SKB_PAD + ICE_RXBUF_1536) > \ 43 SKB_WITH_OVERHEAD(ICE_RXBUF_2048)) 44 45 /** 46 * ice_compute_pad - compute the padding 47 * @rx_buf_len: buffer length 48 * 49 * Figure out the size of half page based on given buffer length and 50 * then subtract the skb_shared_info followed by subtraction of the 51 * actual buffer length; this in turn results in the actual space that 52 * is left for padding usage 53 */ 54 static inline int ice_compute_pad(int rx_buf_len) 55 { 56 int half_page_size; 57 58 half_page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2); 59 return SKB_WITH_OVERHEAD(half_page_size) - rx_buf_len; 60 } 61 62 /** 63 * ice_skb_pad - determine the padding that we can supply 64 * 65 * Figure out the right Rx buffer size and based on that calculate the 66 * padding 67 */ 68 static inline int ice_skb_pad(void) 69 { 70 int rx_buf_len; 71 72 /* If a 2K buffer cannot handle a standard Ethernet frame then 73 * optimize padding for a 3K buffer instead of a 1.5K buffer. 74 * 75 * For a 3K buffer we need to add enough padding to allow for 76 * tailroom due to NET_IP_ALIGN possibly shifting us out of 77 * cache-line alignment. 78 */ 79 if (ICE_2K_TOO_SMALL_WITH_PADDING) 80 rx_buf_len = ICE_RXBUF_3072 + SKB_DATA_ALIGN(NET_IP_ALIGN); 81 else 82 rx_buf_len = ICE_RXBUF_1536; 83 84 /* if needed make room for NET_IP_ALIGN */ 85 rx_buf_len -= NET_IP_ALIGN; 86 87 return ice_compute_pad(rx_buf_len); 88 } 89 90 #define ICE_SKB_PAD ice_skb_pad() 91 #else 92 #define ICE_2K_TOO_SMALL_WITH_PADDING false 93 #define ICE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 94 #endif 95 96 /* We are assuming that the cache line is always 64 Bytes here for ice. 97 * In order to make sure that is a correct assumption there is a check in probe 98 * to print a warning if the read from GLPCI_CNF2 tells us that the cache line 99 * size is 128 bytes. We do it this way because we do not want to read the 100 * GLPCI_CNF2 register or a variable containing the value on every pass through 101 * the Tx path. 102 */ 103 #define ICE_CACHE_LINE_BYTES 64 104 #define ICE_DESCS_PER_CACHE_LINE (ICE_CACHE_LINE_BYTES / \ 105 sizeof(struct ice_tx_desc)) 106 #define ICE_DESCS_FOR_CTX_DESC 1 107 #define ICE_DESCS_FOR_SKB_DATA_PTR 1 108 /* Tx descriptors needed, worst case */ 109 #define DESC_NEEDED (MAX_SKB_FRAGS + ICE_DESCS_FOR_CTX_DESC + \ 110 ICE_DESCS_PER_CACHE_LINE + ICE_DESCS_FOR_SKB_DATA_PTR) 111 #define ICE_DESC_UNUSED(R) \ 112 (u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 113 (R)->next_to_clean - (R)->next_to_use - 1) 114 115 #define ICE_RING_QUARTER(R) ((R)->count >> 2) 116 117 #define ICE_TX_FLAGS_TSO BIT(0) 118 #define ICE_TX_FLAGS_HW_VLAN BIT(1) 119 #define ICE_TX_FLAGS_SW_VLAN BIT(2) 120 /* ICE_TX_FLAGS_DUMMY_PKT is used to mark dummy packets that should be 121 * freed instead of returned like skb packets. 122 */ 123 #define ICE_TX_FLAGS_DUMMY_PKT BIT(3) 124 #define ICE_TX_FLAGS_TSYN BIT(4) 125 #define ICE_TX_FLAGS_IPV4 BIT(5) 126 #define ICE_TX_FLAGS_IPV6 BIT(6) 127 #define ICE_TX_FLAGS_TUNNEL BIT(7) 128 #define ICE_TX_FLAGS_HW_OUTER_SINGLE_VLAN BIT(8) 129 #define ICE_TX_FLAGS_VLAN_M 0xffff0000 130 #define ICE_TX_FLAGS_VLAN_PR_M 0xe0000000 131 #define ICE_TX_FLAGS_VLAN_PR_S 29 132 #define ICE_TX_FLAGS_VLAN_S 16 133 134 #define ICE_XDP_PASS 0 135 #define ICE_XDP_CONSUMED BIT(0) 136 #define ICE_XDP_TX BIT(1) 137 #define ICE_XDP_REDIR BIT(2) 138 #define ICE_XDP_EXIT BIT(3) 139 140 #define ICE_RX_DMA_ATTR \ 141 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 142 143 #define ICE_ETH_PKT_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2)) 144 145 #define ICE_TXD_LAST_DESC_CMD (ICE_TX_DESC_CMD_EOP | ICE_TX_DESC_CMD_RS) 146 147 struct ice_tx_buf { 148 struct ice_tx_desc *next_to_watch; 149 union { 150 struct sk_buff *skb; 151 void *raw_buf; /* used for XDP */ 152 }; 153 unsigned int bytecount; 154 unsigned short gso_segs; 155 u32 tx_flags; 156 DEFINE_DMA_UNMAP_LEN(len); 157 DEFINE_DMA_UNMAP_ADDR(dma); 158 }; 159 160 struct ice_tx_offload_params { 161 u64 cd_qw1; 162 struct ice_tx_ring *tx_ring; 163 u32 td_cmd; 164 u32 td_offset; 165 u32 td_l2tag1; 166 u32 cd_tunnel_params; 167 u16 cd_l2tag2; 168 u8 header_len; 169 }; 170 171 struct ice_rx_buf { 172 dma_addr_t dma; 173 struct page *page; 174 unsigned int page_offset; 175 u16 pagecnt_bias; 176 }; 177 178 struct ice_q_stats { 179 u64 pkts; 180 u64 bytes; 181 }; 182 183 struct ice_txq_stats { 184 u64 restart_q; 185 u64 tx_busy; 186 u64 tx_linearize; 187 int prev_pkt; /* negative if no pending Tx descriptors */ 188 }; 189 190 struct ice_rxq_stats { 191 u64 non_eop_descs; 192 u64 alloc_page_failed; 193 u64 alloc_buf_failed; 194 }; 195 196 struct ice_ring_stats { 197 struct rcu_head rcu; /* to avoid race on free */ 198 struct ice_q_stats stats; 199 struct u64_stats_sync syncp; 200 union { 201 struct ice_txq_stats tx_stats; 202 struct ice_rxq_stats rx_stats; 203 }; 204 }; 205 206 enum ice_ring_state_t { 207 ICE_TX_XPS_INIT_DONE, 208 ICE_TX_NBITS, 209 }; 210 211 /* this enum matches hardware bits and is meant to be used by DYN_CTLN 212 * registers and QINT registers or more generally anywhere in the manual 213 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any 214 * register but instead is a special value meaning "don't update" ITR0/1/2. 215 */ 216 enum ice_dyn_idx_t { 217 ICE_IDX_ITR0 = 0, 218 ICE_IDX_ITR1 = 1, 219 ICE_IDX_ITR2 = 2, 220 ICE_ITR_NONE = 3 /* ITR_NONE must not be used as an index */ 221 }; 222 223 /* Header split modes defined by DTYPE field of Rx RLAN context */ 224 enum ice_rx_dtype { 225 ICE_RX_DTYPE_NO_SPLIT = 0, 226 ICE_RX_DTYPE_HEADER_SPLIT = 1, 227 ICE_RX_DTYPE_SPLIT_ALWAYS = 2, 228 }; 229 230 /* indices into GLINT_ITR registers */ 231 #define ICE_RX_ITR ICE_IDX_ITR0 232 #define ICE_TX_ITR ICE_IDX_ITR1 233 #define ICE_ITR_8K 124 234 #define ICE_ITR_20K 50 235 #define ICE_ITR_MAX 8160 /* 0x1FE0 */ 236 #define ICE_DFLT_TX_ITR ICE_ITR_20K 237 #define ICE_DFLT_RX_ITR ICE_ITR_20K 238 enum ice_dynamic_itr { 239 ITR_STATIC = 0, 240 ITR_DYNAMIC = 1 241 }; 242 243 #define ITR_IS_DYNAMIC(rc) ((rc)->itr_mode == ITR_DYNAMIC) 244 #define ICE_ITR_GRAN_S 1 /* ITR granularity is always 2us */ 245 #define ICE_ITR_GRAN_US BIT(ICE_ITR_GRAN_S) 246 #define ICE_ITR_MASK 0x1FFE /* ITR register value alignment mask */ 247 #define ITR_REG_ALIGN(setting) ((setting) & ICE_ITR_MASK) 248 249 #define ICE_DFLT_INTRL 0 250 #define ICE_MAX_INTRL 236 251 252 #define ICE_IN_WB_ON_ITR_MODE 255 253 /* Sets WB_ON_ITR and assumes INTENA bit is already cleared, which allows 254 * setting the MSK_M bit to tell hardware to ignore the INTENA_M bit. Also, 255 * set the write-back latency to the usecs passed in. 256 */ 257 #define ICE_GLINT_DYN_CTL_WB_ON_ITR(usecs, itr_idx) \ 258 ((((usecs) << (GLINT_DYN_CTL_INTERVAL_S - ICE_ITR_GRAN_S)) & \ 259 GLINT_DYN_CTL_INTERVAL_M) | \ 260 (((itr_idx) << GLINT_DYN_CTL_ITR_INDX_S) & \ 261 GLINT_DYN_CTL_ITR_INDX_M) | GLINT_DYN_CTL_INTENA_MSK_M | \ 262 GLINT_DYN_CTL_WB_ON_ITR_M) 263 264 /* Legacy or Advanced Mode Queue */ 265 #define ICE_TX_ADVANCED 0 266 #define ICE_TX_LEGACY 1 267 268 /* descriptor ring, associated with a VSI */ 269 struct ice_rx_ring { 270 /* CL1 - 1st cacheline starts here */ 271 struct ice_rx_ring *next; /* pointer to next ring in q_vector */ 272 void *desc; /* Descriptor ring memory */ 273 struct device *dev; /* Used for DMA mapping */ 274 struct net_device *netdev; /* netdev ring maps to */ 275 struct ice_vsi *vsi; /* Backreference to associated VSI */ 276 struct ice_q_vector *q_vector; /* Backreference to associated vector */ 277 u8 __iomem *tail; 278 union { 279 struct ice_rx_buf *rx_buf; 280 struct xdp_buff **xdp_buf; 281 }; 282 /* CL2 - 2nd cacheline starts here */ 283 struct xdp_rxq_info xdp_rxq; 284 /* CL3 - 3rd cacheline starts here */ 285 u16 q_index; /* Queue number of ring */ 286 287 u16 count; /* Number of descriptors */ 288 u16 reg_idx; /* HW register index of the ring */ 289 290 /* used in interrupt processing */ 291 u16 next_to_use; 292 u16 next_to_clean; 293 u16 next_to_alloc; 294 u16 rx_offset; 295 u16 rx_buf_len; 296 297 /* stats structs */ 298 struct ice_ring_stats *ring_stats; 299 300 struct rcu_head rcu; /* to avoid race on free */ 301 /* CL4 - 3rd cacheline starts here */ 302 struct ice_channel *ch; 303 struct bpf_prog *xdp_prog; 304 struct ice_tx_ring *xdp_ring; 305 struct xsk_buff_pool *xsk_pool; 306 struct xdp_buff xdp; 307 struct sk_buff *skb; 308 dma_addr_t dma; /* physical address of ring */ 309 u64 cached_phctime; 310 u8 dcb_tc; /* Traffic class of ring */ 311 u8 ptp_rx; 312 #define ICE_RX_FLAGS_RING_BUILD_SKB BIT(1) 313 #define ICE_RX_FLAGS_CRC_STRIP_DIS BIT(2) 314 u8 flags; 315 } ____cacheline_internodealigned_in_smp; 316 317 struct ice_tx_ring { 318 /* CL1 - 1st cacheline starts here */ 319 struct ice_tx_ring *next; /* pointer to next ring in q_vector */ 320 void *desc; /* Descriptor ring memory */ 321 struct device *dev; /* Used for DMA mapping */ 322 u8 __iomem *tail; 323 struct ice_tx_buf *tx_buf; 324 struct ice_q_vector *q_vector; /* Backreference to associated vector */ 325 struct net_device *netdev; /* netdev ring maps to */ 326 struct ice_vsi *vsi; /* Backreference to associated VSI */ 327 /* CL2 - 2nd cacheline starts here */ 328 dma_addr_t dma; /* physical address of ring */ 329 struct xsk_buff_pool *xsk_pool; 330 u16 next_to_use; 331 u16 next_to_clean; 332 u16 next_rs; 333 u16 next_dd; 334 u16 q_handle; /* Queue handle per TC */ 335 u16 reg_idx; /* HW register index of the ring */ 336 u16 count; /* Number of descriptors */ 337 u16 q_index; /* Queue number of ring */ 338 /* stats structs */ 339 struct ice_ring_stats *ring_stats; 340 /* CL3 - 3rd cacheline starts here */ 341 struct rcu_head rcu; /* to avoid race on free */ 342 DECLARE_BITMAP(xps_state, ICE_TX_NBITS); /* XPS Config State */ 343 struct ice_channel *ch; 344 struct ice_ptp_tx *tx_tstamps; 345 spinlock_t tx_lock; 346 u32 txq_teid; /* Added Tx queue TEID */ 347 /* CL4 - 4th cacheline starts here */ 348 u16 xdp_tx_active; 349 #define ICE_TX_FLAGS_RING_XDP BIT(0) 350 #define ICE_TX_FLAGS_RING_VLAN_L2TAG1 BIT(1) 351 #define ICE_TX_FLAGS_RING_VLAN_L2TAG2 BIT(2) 352 u8 flags; 353 u8 dcb_tc; /* Traffic class of ring */ 354 u8 ptp_tx; 355 } ____cacheline_internodealigned_in_smp; 356 357 static inline bool ice_ring_uses_build_skb(struct ice_rx_ring *ring) 358 { 359 return !!(ring->flags & ICE_RX_FLAGS_RING_BUILD_SKB); 360 } 361 362 static inline void ice_set_ring_build_skb_ena(struct ice_rx_ring *ring) 363 { 364 ring->flags |= ICE_RX_FLAGS_RING_BUILD_SKB; 365 } 366 367 static inline void ice_clear_ring_build_skb_ena(struct ice_rx_ring *ring) 368 { 369 ring->flags &= ~ICE_RX_FLAGS_RING_BUILD_SKB; 370 } 371 372 static inline bool ice_ring_ch_enabled(struct ice_tx_ring *ring) 373 { 374 return !!ring->ch; 375 } 376 377 static inline bool ice_ring_is_xdp(struct ice_tx_ring *ring) 378 { 379 return !!(ring->flags & ICE_TX_FLAGS_RING_XDP); 380 } 381 382 enum ice_container_type { 383 ICE_RX_CONTAINER, 384 ICE_TX_CONTAINER, 385 }; 386 387 struct ice_ring_container { 388 /* head of linked-list of rings */ 389 union { 390 struct ice_rx_ring *rx_ring; 391 struct ice_tx_ring *tx_ring; 392 }; 393 struct dim dim; /* data for net_dim algorithm */ 394 u16 itr_idx; /* index in the interrupt vector */ 395 /* this matches the maximum number of ITR bits, but in usec 396 * values, so it is shifted left one bit (bit zero is ignored) 397 */ 398 union { 399 struct { 400 u16 itr_setting:13; 401 u16 itr_reserved:2; 402 u16 itr_mode:1; 403 }; 404 u16 itr_settings; 405 }; 406 enum ice_container_type type; 407 }; 408 409 struct ice_coalesce_stored { 410 u16 itr_tx; 411 u16 itr_rx; 412 u8 intrl; 413 u8 tx_valid; 414 u8 rx_valid; 415 }; 416 417 /* iterator for handling rings in ring container */ 418 #define ice_for_each_rx_ring(pos, head) \ 419 for (pos = (head).rx_ring; pos; pos = pos->next) 420 421 #define ice_for_each_tx_ring(pos, head) \ 422 for (pos = (head).tx_ring; pos; pos = pos->next) 423 424 static inline unsigned int ice_rx_pg_order(struct ice_rx_ring *ring) 425 { 426 #if (PAGE_SIZE < 8192) 427 if (ring->rx_buf_len > (PAGE_SIZE / 2)) 428 return 1; 429 #endif 430 return 0; 431 } 432 433 #define ice_rx_pg_size(_ring) (PAGE_SIZE << ice_rx_pg_order(_ring)) 434 435 union ice_32b_rx_flex_desc; 436 437 bool ice_alloc_rx_bufs(struct ice_rx_ring *rxr, u16 cleaned_count); 438 netdev_tx_t ice_start_xmit(struct sk_buff *skb, struct net_device *netdev); 439 u16 440 ice_select_queue(struct net_device *dev, struct sk_buff *skb, 441 struct net_device *sb_dev); 442 void ice_clean_tx_ring(struct ice_tx_ring *tx_ring); 443 void ice_clean_rx_ring(struct ice_rx_ring *rx_ring); 444 int ice_setup_tx_ring(struct ice_tx_ring *tx_ring); 445 int ice_setup_rx_ring(struct ice_rx_ring *rx_ring); 446 void ice_free_tx_ring(struct ice_tx_ring *tx_ring); 447 void ice_free_rx_ring(struct ice_rx_ring *rx_ring); 448 int ice_napi_poll(struct napi_struct *napi, int budget); 449 int 450 ice_prgm_fdir_fltr(struct ice_vsi *vsi, struct ice_fltr_desc *fdir_desc, 451 u8 *raw_packet); 452 int ice_clean_rx_irq(struct ice_rx_ring *rx_ring, int budget); 453 void ice_clean_ctrl_tx_irq(struct ice_tx_ring *tx_ring); 454 #endif /* _ICE_TXRX_H_ */ 455