1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_TXRX_H_ 5 #define _ICE_TXRX_H_ 6 7 #include "ice_type.h" 8 9 #define ICE_DFLT_IRQ_WORK 256 10 #define ICE_RXBUF_3072 3072 11 #define ICE_RXBUF_2048 2048 12 #define ICE_RXBUF_1664 1664 13 #define ICE_RXBUF_1536 1536 14 #define ICE_MAX_CHAINED_RX_BUFS 5 15 #define ICE_MAX_BUF_TXD 8 16 #define ICE_MIN_TX_LEN 17 17 #define ICE_MAX_FRAME_LEGACY_RX 8320 18 19 /* The size limit for a transmit buffer in a descriptor is (16K - 1). 20 * In order to align with the read requests we will align the value to 21 * the nearest 4K which represents our maximum read request size. 22 */ 23 #define ICE_MAX_READ_REQ_SIZE 4096 24 #define ICE_MAX_DATA_PER_TXD (16 * 1024 - 1) 25 #define ICE_MAX_DATA_PER_TXD_ALIGNED \ 26 (~(ICE_MAX_READ_REQ_SIZE - 1) & ICE_MAX_DATA_PER_TXD) 27 28 #define ICE_MAX_TXQ_PER_TXQG 128 29 30 /* Attempt to maximize the headroom available for incoming frames. We use a 2K 31 * buffer for MTUs <= 1500 and need 1536/1534 to store the data for the frame. 32 * This leaves us with 512 bytes of room. From that we need to deduct the 33 * space needed for the shared info and the padding needed to IP align the 34 * frame. 35 * 36 * Note: For cache line sizes 256 or larger this value is going to end 37 * up negative. In these cases we should fall back to the legacy 38 * receive path. 39 */ 40 #if (PAGE_SIZE < 8192) 41 #define ICE_2K_TOO_SMALL_WITH_PADDING \ 42 ((unsigned int)(NET_SKB_PAD + ICE_RXBUF_1536) > \ 43 SKB_WITH_OVERHEAD(ICE_RXBUF_2048)) 44 45 /** 46 * ice_compute_pad - compute the padding 47 * @rx_buf_len: buffer length 48 * 49 * Figure out the size of half page based on given buffer length and 50 * then subtract the skb_shared_info followed by subtraction of the 51 * actual buffer length; this in turn results in the actual space that 52 * is left for padding usage 53 */ 54 static inline int ice_compute_pad(int rx_buf_len) 55 { 56 int half_page_size; 57 58 half_page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2); 59 return SKB_WITH_OVERHEAD(half_page_size) - rx_buf_len; 60 } 61 62 /** 63 * ice_skb_pad - determine the padding that we can supply 64 * 65 * Figure out the right Rx buffer size and based on that calculate the 66 * padding 67 */ 68 static inline int ice_skb_pad(void) 69 { 70 int rx_buf_len; 71 72 /* If a 2K buffer cannot handle a standard Ethernet frame then 73 * optimize padding for a 3K buffer instead of a 1.5K buffer. 74 * 75 * For a 3K buffer we need to add enough padding to allow for 76 * tailroom due to NET_IP_ALIGN possibly shifting us out of 77 * cache-line alignment. 78 */ 79 if (ICE_2K_TOO_SMALL_WITH_PADDING) 80 rx_buf_len = ICE_RXBUF_3072 + SKB_DATA_ALIGN(NET_IP_ALIGN); 81 else 82 rx_buf_len = ICE_RXBUF_1536; 83 84 /* if needed make room for NET_IP_ALIGN */ 85 rx_buf_len -= NET_IP_ALIGN; 86 87 return ice_compute_pad(rx_buf_len); 88 } 89 90 #define ICE_SKB_PAD ice_skb_pad() 91 #else 92 #define ICE_2K_TOO_SMALL_WITH_PADDING false 93 #define ICE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) 94 #endif 95 96 /* We are assuming that the cache line is always 64 Bytes here for ice. 97 * In order to make sure that is a correct assumption there is a check in probe 98 * to print a warning if the read from GLPCI_CNF2 tells us that the cache line 99 * size is 128 bytes. We do it this way because we do not want to read the 100 * GLPCI_CNF2 register or a variable containing the value on every pass through 101 * the Tx path. 102 */ 103 #define ICE_CACHE_LINE_BYTES 64 104 #define ICE_DESCS_PER_CACHE_LINE (ICE_CACHE_LINE_BYTES / \ 105 sizeof(struct ice_tx_desc)) 106 #define ICE_DESCS_FOR_CTX_DESC 1 107 #define ICE_DESCS_FOR_SKB_DATA_PTR 1 108 /* Tx descriptors needed, worst case */ 109 #define DESC_NEEDED (MAX_SKB_FRAGS + ICE_DESCS_FOR_CTX_DESC + \ 110 ICE_DESCS_PER_CACHE_LINE + ICE_DESCS_FOR_SKB_DATA_PTR) 111 #define ICE_DESC_UNUSED(R) \ 112 (u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 113 (R)->next_to_clean - (R)->next_to_use - 1) 114 115 #define ICE_RX_DESC_UNUSED(R) \ 116 ((((R)->first_desc > (R)->next_to_use) ? 0 : (R)->count) + \ 117 (R)->first_desc - (R)->next_to_use - 1) 118 119 #define ICE_RING_QUARTER(R) ((R)->count >> 2) 120 121 #define ICE_TX_FLAGS_TSO BIT(0) 122 #define ICE_TX_FLAGS_HW_VLAN BIT(1) 123 #define ICE_TX_FLAGS_SW_VLAN BIT(2) 124 /* ICE_TX_FLAGS_DUMMY_PKT is used to mark dummy packets that should be 125 * freed instead of returned like skb packets. 126 */ 127 #define ICE_TX_FLAGS_DUMMY_PKT BIT(3) 128 #define ICE_TX_FLAGS_TSYN BIT(4) 129 #define ICE_TX_FLAGS_IPV4 BIT(5) 130 #define ICE_TX_FLAGS_IPV6 BIT(6) 131 #define ICE_TX_FLAGS_TUNNEL BIT(7) 132 #define ICE_TX_FLAGS_HW_OUTER_SINGLE_VLAN BIT(8) 133 #define ICE_TX_FLAGS_VLAN_M 0xffff0000 134 #define ICE_TX_FLAGS_VLAN_PR_M 0xe0000000 135 #define ICE_TX_FLAGS_VLAN_PR_S 29 136 #define ICE_TX_FLAGS_VLAN_S 16 137 138 #define ICE_XDP_PASS 0 139 #define ICE_XDP_CONSUMED BIT(0) 140 #define ICE_XDP_TX BIT(1) 141 #define ICE_XDP_REDIR BIT(2) 142 #define ICE_XDP_EXIT BIT(3) 143 #define ICE_SKB_CONSUMED ICE_XDP_CONSUMED 144 145 #define ICE_RX_DMA_ATTR \ 146 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 147 148 #define ICE_ETH_PKT_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2)) 149 150 #define ICE_TXD_LAST_DESC_CMD (ICE_TX_DESC_CMD_EOP | ICE_TX_DESC_CMD_RS) 151 152 struct ice_tx_buf { 153 union { 154 struct ice_tx_desc *next_to_watch; 155 u32 rs_idx; 156 }; 157 union { 158 struct sk_buff *skb; 159 void *raw_buf; /* used for XDP */ 160 }; 161 unsigned int bytecount; 162 union { 163 unsigned int gso_segs; 164 unsigned int nr_frags; /* used for mbuf XDP */ 165 }; 166 u32 tx_flags; 167 DEFINE_DMA_UNMAP_LEN(len); 168 DEFINE_DMA_UNMAP_ADDR(dma); 169 }; 170 171 struct ice_tx_offload_params { 172 u64 cd_qw1; 173 struct ice_tx_ring *tx_ring; 174 u32 td_cmd; 175 u32 td_offset; 176 u32 td_l2tag1; 177 u32 cd_tunnel_params; 178 u16 cd_l2tag2; 179 u8 header_len; 180 }; 181 182 struct ice_rx_buf { 183 dma_addr_t dma; 184 struct page *page; 185 unsigned int page_offset; 186 unsigned int pgcnt; 187 unsigned int act; 188 unsigned int pagecnt_bias; 189 }; 190 191 struct ice_q_stats { 192 u64 pkts; 193 u64 bytes; 194 }; 195 196 struct ice_txq_stats { 197 u64 restart_q; 198 u64 tx_busy; 199 u64 tx_linearize; 200 int prev_pkt; /* negative if no pending Tx descriptors */ 201 }; 202 203 struct ice_rxq_stats { 204 u64 non_eop_descs; 205 u64 alloc_page_failed; 206 u64 alloc_buf_failed; 207 }; 208 209 struct ice_ring_stats { 210 struct rcu_head rcu; /* to avoid race on free */ 211 struct ice_q_stats stats; 212 struct u64_stats_sync syncp; 213 union { 214 struct ice_txq_stats tx_stats; 215 struct ice_rxq_stats rx_stats; 216 }; 217 }; 218 219 enum ice_ring_state_t { 220 ICE_TX_XPS_INIT_DONE, 221 ICE_TX_NBITS, 222 }; 223 224 /* this enum matches hardware bits and is meant to be used by DYN_CTLN 225 * registers and QINT registers or more generally anywhere in the manual 226 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any 227 * register but instead is a special value meaning "don't update" ITR0/1/2. 228 */ 229 enum ice_dyn_idx_t { 230 ICE_IDX_ITR0 = 0, 231 ICE_IDX_ITR1 = 1, 232 ICE_IDX_ITR2 = 2, 233 ICE_ITR_NONE = 3 /* ITR_NONE must not be used as an index */ 234 }; 235 236 /* Header split modes defined by DTYPE field of Rx RLAN context */ 237 enum ice_rx_dtype { 238 ICE_RX_DTYPE_NO_SPLIT = 0, 239 ICE_RX_DTYPE_HEADER_SPLIT = 1, 240 ICE_RX_DTYPE_SPLIT_ALWAYS = 2, 241 }; 242 243 /* indices into GLINT_ITR registers */ 244 #define ICE_RX_ITR ICE_IDX_ITR0 245 #define ICE_TX_ITR ICE_IDX_ITR1 246 #define ICE_ITR_8K 124 247 #define ICE_ITR_20K 50 248 #define ICE_ITR_MAX 8160 /* 0x1FE0 */ 249 #define ICE_DFLT_TX_ITR ICE_ITR_20K 250 #define ICE_DFLT_RX_ITR ICE_ITR_20K 251 enum ice_dynamic_itr { 252 ITR_STATIC = 0, 253 ITR_DYNAMIC = 1 254 }; 255 256 #define ITR_IS_DYNAMIC(rc) ((rc)->itr_mode == ITR_DYNAMIC) 257 #define ICE_ITR_GRAN_S 1 /* ITR granularity is always 2us */ 258 #define ICE_ITR_GRAN_US BIT(ICE_ITR_GRAN_S) 259 #define ICE_ITR_MASK 0x1FFE /* ITR register value alignment mask */ 260 #define ITR_REG_ALIGN(setting) ((setting) & ICE_ITR_MASK) 261 262 #define ICE_DFLT_INTRL 0 263 #define ICE_MAX_INTRL 236 264 265 #define ICE_IN_WB_ON_ITR_MODE 255 266 /* Sets WB_ON_ITR and assumes INTENA bit is already cleared, which allows 267 * setting the MSK_M bit to tell hardware to ignore the INTENA_M bit. Also, 268 * set the write-back latency to the usecs passed in. 269 */ 270 #define ICE_GLINT_DYN_CTL_WB_ON_ITR(usecs, itr_idx) \ 271 ((((usecs) << (GLINT_DYN_CTL_INTERVAL_S - ICE_ITR_GRAN_S)) & \ 272 GLINT_DYN_CTL_INTERVAL_M) | \ 273 (((itr_idx) << GLINT_DYN_CTL_ITR_INDX_S) & \ 274 GLINT_DYN_CTL_ITR_INDX_M) | GLINT_DYN_CTL_INTENA_MSK_M | \ 275 GLINT_DYN_CTL_WB_ON_ITR_M) 276 277 /* Legacy or Advanced Mode Queue */ 278 #define ICE_TX_ADVANCED 0 279 #define ICE_TX_LEGACY 1 280 281 /* descriptor ring, associated with a VSI */ 282 struct ice_rx_ring { 283 /* CL1 - 1st cacheline starts here */ 284 struct ice_rx_ring *next; /* pointer to next ring in q_vector */ 285 void *desc; /* Descriptor ring memory */ 286 struct device *dev; /* Used for DMA mapping */ 287 struct net_device *netdev; /* netdev ring maps to */ 288 struct ice_vsi *vsi; /* Backreference to associated VSI */ 289 struct ice_q_vector *q_vector; /* Backreference to associated vector */ 290 u8 __iomem *tail; 291 u16 q_index; /* Queue number of ring */ 292 293 u16 count; /* Number of descriptors */ 294 u16 reg_idx; /* HW register index of the ring */ 295 u16 next_to_alloc; 296 /* CL2 - 2nd cacheline starts here */ 297 union { 298 struct ice_rx_buf *rx_buf; 299 struct xdp_buff **xdp_buf; 300 }; 301 struct xdp_buff xdp; 302 /* CL3 - 3rd cacheline starts here */ 303 struct bpf_prog *xdp_prog; 304 u16 rx_offset; 305 306 /* used in interrupt processing */ 307 u16 next_to_use; 308 u16 next_to_clean; 309 u16 first_desc; 310 311 /* stats structs */ 312 struct ice_ring_stats *ring_stats; 313 314 struct rcu_head rcu; /* to avoid race on free */ 315 /* CL4 - 4th cacheline starts here */ 316 struct ice_channel *ch; 317 struct ice_tx_ring *xdp_ring; 318 struct xsk_buff_pool *xsk_pool; 319 dma_addr_t dma; /* physical address of ring */ 320 u64 cached_phctime; 321 u16 rx_buf_len; 322 u8 dcb_tc; /* Traffic class of ring */ 323 u8 ptp_rx; 324 #define ICE_RX_FLAGS_RING_BUILD_SKB BIT(1) 325 #define ICE_RX_FLAGS_CRC_STRIP_DIS BIT(2) 326 u8 flags; 327 /* CL5 - 5th cacheline starts here */ 328 struct xdp_rxq_info xdp_rxq; 329 } ____cacheline_internodealigned_in_smp; 330 331 struct ice_tx_ring { 332 /* CL1 - 1st cacheline starts here */ 333 struct ice_tx_ring *next; /* pointer to next ring in q_vector */ 334 void *desc; /* Descriptor ring memory */ 335 struct device *dev; /* Used for DMA mapping */ 336 u8 __iomem *tail; 337 struct ice_tx_buf *tx_buf; 338 struct ice_q_vector *q_vector; /* Backreference to associated vector */ 339 struct net_device *netdev; /* netdev ring maps to */ 340 struct ice_vsi *vsi; /* Backreference to associated VSI */ 341 /* CL2 - 2nd cacheline starts here */ 342 dma_addr_t dma; /* physical address of ring */ 343 struct xsk_buff_pool *xsk_pool; 344 u16 next_to_use; 345 u16 next_to_clean; 346 u16 next_rs; 347 u16 next_dd; 348 u16 q_handle; /* Queue handle per TC */ 349 u16 reg_idx; /* HW register index of the ring */ 350 u16 count; /* Number of descriptors */ 351 u16 q_index; /* Queue number of ring */ 352 u16 xdp_tx_active; 353 /* stats structs */ 354 struct ice_ring_stats *ring_stats; 355 /* CL3 - 3rd cacheline starts here */ 356 struct rcu_head rcu; /* to avoid race on free */ 357 DECLARE_BITMAP(xps_state, ICE_TX_NBITS); /* XPS Config State */ 358 struct ice_channel *ch; 359 struct ice_ptp_tx *tx_tstamps; 360 spinlock_t tx_lock; 361 u32 txq_teid; /* Added Tx queue TEID */ 362 /* CL4 - 4th cacheline starts here */ 363 #define ICE_TX_FLAGS_RING_XDP BIT(0) 364 #define ICE_TX_FLAGS_RING_VLAN_L2TAG1 BIT(1) 365 #define ICE_TX_FLAGS_RING_VLAN_L2TAG2 BIT(2) 366 u8 flags; 367 u8 dcb_tc; /* Traffic class of ring */ 368 u8 ptp_tx; 369 } ____cacheline_internodealigned_in_smp; 370 371 static inline bool ice_ring_uses_build_skb(struct ice_rx_ring *ring) 372 { 373 return !!(ring->flags & ICE_RX_FLAGS_RING_BUILD_SKB); 374 } 375 376 static inline void ice_set_ring_build_skb_ena(struct ice_rx_ring *ring) 377 { 378 ring->flags |= ICE_RX_FLAGS_RING_BUILD_SKB; 379 } 380 381 static inline void ice_clear_ring_build_skb_ena(struct ice_rx_ring *ring) 382 { 383 ring->flags &= ~ICE_RX_FLAGS_RING_BUILD_SKB; 384 } 385 386 static inline bool ice_ring_ch_enabled(struct ice_tx_ring *ring) 387 { 388 return !!ring->ch; 389 } 390 391 static inline bool ice_ring_is_xdp(struct ice_tx_ring *ring) 392 { 393 return !!(ring->flags & ICE_TX_FLAGS_RING_XDP); 394 } 395 396 enum ice_container_type { 397 ICE_RX_CONTAINER, 398 ICE_TX_CONTAINER, 399 }; 400 401 struct ice_ring_container { 402 /* head of linked-list of rings */ 403 union { 404 struct ice_rx_ring *rx_ring; 405 struct ice_tx_ring *tx_ring; 406 }; 407 struct dim dim; /* data for net_dim algorithm */ 408 u16 itr_idx; /* index in the interrupt vector */ 409 /* this matches the maximum number of ITR bits, but in usec 410 * values, so it is shifted left one bit (bit zero is ignored) 411 */ 412 union { 413 struct { 414 u16 itr_setting:13; 415 u16 itr_reserved:2; 416 u16 itr_mode:1; 417 }; 418 u16 itr_settings; 419 }; 420 enum ice_container_type type; 421 }; 422 423 struct ice_coalesce_stored { 424 u16 itr_tx; 425 u16 itr_rx; 426 u8 intrl; 427 u8 tx_valid; 428 u8 rx_valid; 429 }; 430 431 /* iterator for handling rings in ring container */ 432 #define ice_for_each_rx_ring(pos, head) \ 433 for (pos = (head).rx_ring; pos; pos = pos->next) 434 435 #define ice_for_each_tx_ring(pos, head) \ 436 for (pos = (head).tx_ring; pos; pos = pos->next) 437 438 static inline unsigned int ice_rx_pg_order(struct ice_rx_ring *ring) 439 { 440 #if (PAGE_SIZE < 8192) 441 if (ring->rx_buf_len > (PAGE_SIZE / 2)) 442 return 1; 443 #endif 444 return 0; 445 } 446 447 #define ice_rx_pg_size(_ring) (PAGE_SIZE << ice_rx_pg_order(_ring)) 448 449 union ice_32b_rx_flex_desc; 450 451 bool ice_alloc_rx_bufs(struct ice_rx_ring *rxr, unsigned int cleaned_count); 452 netdev_tx_t ice_start_xmit(struct sk_buff *skb, struct net_device *netdev); 453 u16 454 ice_select_queue(struct net_device *dev, struct sk_buff *skb, 455 struct net_device *sb_dev); 456 void ice_clean_tx_ring(struct ice_tx_ring *tx_ring); 457 void ice_clean_rx_ring(struct ice_rx_ring *rx_ring); 458 int ice_setup_tx_ring(struct ice_tx_ring *tx_ring); 459 int ice_setup_rx_ring(struct ice_rx_ring *rx_ring); 460 void ice_free_tx_ring(struct ice_tx_ring *tx_ring); 461 void ice_free_rx_ring(struct ice_rx_ring *rx_ring); 462 int ice_napi_poll(struct napi_struct *napi, int budget); 463 int 464 ice_prgm_fdir_fltr(struct ice_vsi *vsi, struct ice_fltr_desc *fdir_desc, 465 u8 *raw_packet); 466 int ice_clean_rx_irq(struct ice_rx_ring *rx_ring, int budget); 467 void ice_clean_ctrl_tx_irq(struct ice_tx_ring *tx_ring); 468 #endif /* _ICE_TXRX_H_ */ 469