1940b61afSAnirudh Venkataramanan /* SPDX-License-Identifier: GPL-2.0 */ 2940b61afSAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */ 3940b61afSAnirudh Venkataramanan 4940b61afSAnirudh Venkataramanan #ifndef _ICE_TXRX_H_ 5940b61afSAnirudh Venkataramanan #define _ICE_TXRX_H_ 6940b61afSAnirudh Venkataramanan 7940b61afSAnirudh Venkataramanan #define ICE_DFLT_IRQ_WORK 256 8cdedef59SAnirudh Venkataramanan #define ICE_RXBUF_2048 2048 9cdedef59SAnirudh Venkataramanan #define ICE_MAX_CHAINED_RX_BUFS 5 102b245cb2SAnirudh Venkataramanan #define ICE_MAX_BUF_TXD 8 112b245cb2SAnirudh Venkataramanan #define ICE_MIN_TX_LEN 17 122b245cb2SAnirudh Venkataramanan 132b245cb2SAnirudh Venkataramanan /* The size limit for a transmit buffer in a descriptor is (16K - 1). 142b245cb2SAnirudh Venkataramanan * In order to align with the read requests we will align the value to 152b245cb2SAnirudh Venkataramanan * the nearest 4K which represents our maximum read request size. 162b245cb2SAnirudh Venkataramanan */ 172b245cb2SAnirudh Venkataramanan #define ICE_MAX_READ_REQ_SIZE 4096 182b245cb2SAnirudh Venkataramanan #define ICE_MAX_DATA_PER_TXD (16 * 1024 - 1) 192b245cb2SAnirudh Venkataramanan #define ICE_MAX_DATA_PER_TXD_ALIGNED \ 202b245cb2SAnirudh Venkataramanan (~(ICE_MAX_READ_REQ_SIZE - 1) & ICE_MAX_DATA_PER_TXD) 212b245cb2SAnirudh Venkataramanan 222b245cb2SAnirudh Venkataramanan #define ICE_RX_BUF_WRITE 16 /* Must be power of 2 */ 23cdedef59SAnirudh Venkataramanan #define ICE_MAX_TXQ_PER_TXQG 128 24cdedef59SAnirudh Venkataramanan 252b245cb2SAnirudh Venkataramanan /* Tx Descriptors needed, worst case */ 262b245cb2SAnirudh Venkataramanan #define DESC_NEEDED (MAX_SKB_FRAGS + 4) 27cdedef59SAnirudh Venkataramanan #define ICE_DESC_UNUSED(R) \ 28cdedef59SAnirudh Venkataramanan ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 29cdedef59SAnirudh Venkataramanan (R)->next_to_clean - (R)->next_to_use - 1) 30cdedef59SAnirudh Venkataramanan 31d76a60baSAnirudh Venkataramanan #define ICE_TX_FLAGS_TSO BIT(0) 32d76a60baSAnirudh Venkataramanan #define ICE_TX_FLAGS_HW_VLAN BIT(1) 33d76a60baSAnirudh Venkataramanan #define ICE_TX_FLAGS_SW_VLAN BIT(2) 34d76a60baSAnirudh Venkataramanan #define ICE_TX_FLAGS_VLAN_M 0xffff0000 35d76a60baSAnirudh Venkataramanan #define ICE_TX_FLAGS_VLAN_S 16 36d76a60baSAnirudh Venkataramanan 37cdedef59SAnirudh Venkataramanan struct ice_tx_buf { 38cdedef59SAnirudh Venkataramanan struct ice_tx_desc *next_to_watch; 39cdedef59SAnirudh Venkataramanan struct sk_buff *skb; 40cdedef59SAnirudh Venkataramanan unsigned int bytecount; 41cdedef59SAnirudh Venkataramanan unsigned short gso_segs; 42cdedef59SAnirudh Venkataramanan u32 tx_flags; 43cdedef59SAnirudh Venkataramanan DEFINE_DMA_UNMAP_ADDR(dma); 44cdedef59SAnirudh Venkataramanan DEFINE_DMA_UNMAP_LEN(len); 45cdedef59SAnirudh Venkataramanan }; 46cdedef59SAnirudh Venkataramanan 47d76a60baSAnirudh Venkataramanan struct ice_tx_offload_params { 48d76a60baSAnirudh Venkataramanan u8 header_len; 49d76a60baSAnirudh Venkataramanan u32 td_cmd; 50d76a60baSAnirudh Venkataramanan u32 td_offset; 51d76a60baSAnirudh Venkataramanan u32 td_l2tag1; 52d76a60baSAnirudh Venkataramanan u16 cd_l2tag2; 53d76a60baSAnirudh Venkataramanan u32 cd_tunnel_params; 54d76a60baSAnirudh Venkataramanan u64 cd_qw1; 55d76a60baSAnirudh Venkataramanan struct ice_ring *tx_ring; 56d76a60baSAnirudh Venkataramanan }; 57d76a60baSAnirudh Venkataramanan 58cdedef59SAnirudh Venkataramanan struct ice_rx_buf { 59cdedef59SAnirudh Venkataramanan struct sk_buff *skb; 60cdedef59SAnirudh Venkataramanan dma_addr_t dma; 61cdedef59SAnirudh Venkataramanan struct page *page; 62cdedef59SAnirudh Venkataramanan unsigned int page_offset; 63cdedef59SAnirudh Venkataramanan }; 64940b61afSAnirudh Venkataramanan 652b245cb2SAnirudh Venkataramanan struct ice_q_stats { 662b245cb2SAnirudh Venkataramanan u64 pkts; 672b245cb2SAnirudh Venkataramanan u64 bytes; 682b245cb2SAnirudh Venkataramanan }; 692b245cb2SAnirudh Venkataramanan 702b245cb2SAnirudh Venkataramanan struct ice_txq_stats { 712b245cb2SAnirudh Venkataramanan u64 restart_q; 722b245cb2SAnirudh Venkataramanan u64 tx_busy; 732b245cb2SAnirudh Venkataramanan u64 tx_linearize; 742b245cb2SAnirudh Venkataramanan }; 752b245cb2SAnirudh Venkataramanan 762b245cb2SAnirudh Venkataramanan struct ice_rxq_stats { 772b245cb2SAnirudh Venkataramanan u64 non_eop_descs; 782b245cb2SAnirudh Venkataramanan u64 alloc_page_failed; 792b245cb2SAnirudh Venkataramanan u64 alloc_buf_failed; 802b245cb2SAnirudh Venkataramanan u64 page_reuse_count; 812b245cb2SAnirudh Venkataramanan }; 822b245cb2SAnirudh Venkataramanan 83940b61afSAnirudh Venkataramanan /* this enum matches hardware bits and is meant to be used by DYN_CTLN 84940b61afSAnirudh Venkataramanan * registers and QINT registers or more generally anywhere in the manual 85940b61afSAnirudh Venkataramanan * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any 86940b61afSAnirudh Venkataramanan * register but instead is a special value meaning "don't update" ITR0/1/2. 87940b61afSAnirudh Venkataramanan */ 88940b61afSAnirudh Venkataramanan enum ice_dyn_idx_t { 89940b61afSAnirudh Venkataramanan ICE_IDX_ITR0 = 0, 90940b61afSAnirudh Venkataramanan ICE_IDX_ITR1 = 1, 91940b61afSAnirudh Venkataramanan ICE_IDX_ITR2 = 2, 92940b61afSAnirudh Venkataramanan ICE_ITR_NONE = 3 /* ITR_NONE must not be used as an index */ 93940b61afSAnirudh Venkataramanan }; 94940b61afSAnirudh Venkataramanan 95cdedef59SAnirudh Venkataramanan /* Header split modes defined by DTYPE field of Rx RLAN context */ 96cdedef59SAnirudh Venkataramanan enum ice_rx_dtype { 97cdedef59SAnirudh Venkataramanan ICE_RX_DTYPE_NO_SPLIT = 0, 98cdedef59SAnirudh Venkataramanan ICE_RX_DTYPE_HEADER_SPLIT = 1, 99cdedef59SAnirudh Venkataramanan ICE_RX_DTYPE_SPLIT_ALWAYS = 2, 100cdedef59SAnirudh Venkataramanan }; 101cdedef59SAnirudh Venkataramanan 102940b61afSAnirudh Venkataramanan /* indices into GLINT_ITR registers */ 103940b61afSAnirudh Venkataramanan #define ICE_RX_ITR ICE_IDX_ITR0 104cdedef59SAnirudh Venkataramanan #define ICE_TX_ITR ICE_IDX_ITR1 105940b61afSAnirudh Venkataramanan #define ICE_ITR_DYNAMIC 0x8000 /* use top bit as a flag */ 106940b61afSAnirudh Venkataramanan #define ICE_ITR_8K 0x003E 107940b61afSAnirudh Venkataramanan 108940b61afSAnirudh Venkataramanan /* apply ITR HW granularity translation to program the HW registers */ 109940b61afSAnirudh Venkataramanan #define ITR_TO_REG(val, itr_gran) (((val) & ~ICE_ITR_DYNAMIC) >> (itr_gran)) 110940b61afSAnirudh Venkataramanan 111cdedef59SAnirudh Venkataramanan /* Legacy or Advanced Mode Queue */ 112cdedef59SAnirudh Venkataramanan #define ICE_TX_ADVANCED 0 113cdedef59SAnirudh Venkataramanan #define ICE_TX_LEGACY 1 114cdedef59SAnirudh Venkataramanan 1153a858ba3SAnirudh Venkataramanan /* descriptor ring, associated with a VSI */ 1163a858ba3SAnirudh Venkataramanan struct ice_ring { 1173a858ba3SAnirudh Venkataramanan struct ice_ring *next; /* pointer to next ring in q_vector */ 118cdedef59SAnirudh Venkataramanan void *desc; /* Descriptor ring memory */ 1193a858ba3SAnirudh Venkataramanan struct device *dev; /* Used for DMA mapping */ 1203a858ba3SAnirudh Venkataramanan struct net_device *netdev; /* netdev ring maps to */ 1213a858ba3SAnirudh Venkataramanan struct ice_vsi *vsi; /* Backreference to associated VSI */ 1223a858ba3SAnirudh Venkataramanan struct ice_q_vector *q_vector; /* Backreference to associated vector */ 123cdedef59SAnirudh Venkataramanan u8 __iomem *tail; 124cdedef59SAnirudh Venkataramanan union { 125cdedef59SAnirudh Venkataramanan struct ice_tx_buf *tx_buf; 126cdedef59SAnirudh Venkataramanan struct ice_rx_buf *rx_buf; 127cdedef59SAnirudh Venkataramanan }; 1283a858ba3SAnirudh Venkataramanan u16 q_index; /* Queue number of ring */ 129cdedef59SAnirudh Venkataramanan u32 txq_teid; /* Added Tx queue TEID */ 130cdedef59SAnirudh Venkataramanan 131cdedef59SAnirudh Venkataramanan /* high bit set means dynamic, use accessor routines to read/write. 132cdedef59SAnirudh Venkataramanan * hardware supports 2us/1us resolution for the ITR registers. 133cdedef59SAnirudh Venkataramanan * these values always store the USER setting, and must be converted 134cdedef59SAnirudh Venkataramanan * before programming to a register. 135cdedef59SAnirudh Venkataramanan */ 136cdedef59SAnirudh Venkataramanan u16 rx_itr_setting; 137cdedef59SAnirudh Venkataramanan u16 tx_itr_setting; 138cdedef59SAnirudh Venkataramanan 1393a858ba3SAnirudh Venkataramanan u16 count; /* Number of descriptors */ 1403a858ba3SAnirudh Venkataramanan u16 reg_idx; /* HW register index of the ring */ 141cdedef59SAnirudh Venkataramanan 142cdedef59SAnirudh Venkataramanan /* used in interrupt processing */ 143cdedef59SAnirudh Venkataramanan u16 next_to_use; 144cdedef59SAnirudh Venkataramanan u16 next_to_clean; 145cdedef59SAnirudh Venkataramanan 1463a858ba3SAnirudh Venkataramanan bool ring_active; /* is ring online or not */ 1472b245cb2SAnirudh Venkataramanan 1482b245cb2SAnirudh Venkataramanan /* stats structs */ 1492b245cb2SAnirudh Venkataramanan struct ice_q_stats stats; 1502b245cb2SAnirudh Venkataramanan struct u64_stats_sync syncp; 1512b245cb2SAnirudh Venkataramanan union { 1522b245cb2SAnirudh Venkataramanan struct ice_txq_stats tx_stats; 1532b245cb2SAnirudh Venkataramanan struct ice_rxq_stats rx_stats; 1542b245cb2SAnirudh Venkataramanan }; 1552b245cb2SAnirudh Venkataramanan 156cdedef59SAnirudh Venkataramanan unsigned int size; /* length of descriptor ring in bytes */ 157cdedef59SAnirudh Venkataramanan dma_addr_t dma; /* physical address of ring */ 1583a858ba3SAnirudh Venkataramanan struct rcu_head rcu; /* to avoid race on free */ 159cdedef59SAnirudh Venkataramanan u16 next_to_alloc; 1603a858ba3SAnirudh Venkataramanan } ____cacheline_internodealigned_in_smp; 1613a858ba3SAnirudh Venkataramanan 162cdedef59SAnirudh Venkataramanan enum ice_latency_range { 163cdedef59SAnirudh Venkataramanan ICE_LOWEST_LATENCY = 0, 164cdedef59SAnirudh Venkataramanan ICE_LOW_LATENCY = 1, 165cdedef59SAnirudh Venkataramanan ICE_BULK_LATENCY = 2, 166cdedef59SAnirudh Venkataramanan ICE_ULTRA_LATENCY = 3, 167cdedef59SAnirudh Venkataramanan }; 168cdedef59SAnirudh Venkataramanan 1693a858ba3SAnirudh Venkataramanan struct ice_ring_container { 1703a858ba3SAnirudh Venkataramanan /* array of pointers to rings */ 1713a858ba3SAnirudh Venkataramanan struct ice_ring *ring; 1723a858ba3SAnirudh Venkataramanan unsigned int total_bytes; /* total bytes processed this int */ 1733a858ba3SAnirudh Venkataramanan unsigned int total_pkts; /* total packets processed this int */ 174cdedef59SAnirudh Venkataramanan enum ice_latency_range latency_range; 1753a858ba3SAnirudh Venkataramanan u16 itr; 1763a858ba3SAnirudh Venkataramanan }; 1773a858ba3SAnirudh Venkataramanan 1783a858ba3SAnirudh Venkataramanan /* iterator for handling rings in ring container */ 1793a858ba3SAnirudh Venkataramanan #define ice_for_each_ring(pos, head) \ 1803a858ba3SAnirudh Venkataramanan for (pos = (head).ring; pos; pos = pos->next) 1813a858ba3SAnirudh Venkataramanan 182cdedef59SAnirudh Venkataramanan bool ice_alloc_rx_bufs(struct ice_ring *rxr, u16 cleaned_count); 1832b245cb2SAnirudh Venkataramanan netdev_tx_t ice_start_xmit(struct sk_buff *skb, struct net_device *netdev); 184cdedef59SAnirudh Venkataramanan void ice_clean_tx_ring(struct ice_ring *tx_ring); 185cdedef59SAnirudh Venkataramanan void ice_clean_rx_ring(struct ice_ring *rx_ring); 186cdedef59SAnirudh Venkataramanan int ice_setup_tx_ring(struct ice_ring *tx_ring); 187cdedef59SAnirudh Venkataramanan int ice_setup_rx_ring(struct ice_ring *rx_ring); 188cdedef59SAnirudh Venkataramanan void ice_free_tx_ring(struct ice_ring *tx_ring); 189cdedef59SAnirudh Venkataramanan void ice_free_rx_ring(struct ice_ring *rx_ring); 1902b245cb2SAnirudh Venkataramanan int ice_napi_poll(struct napi_struct *napi, int budget); 1912b245cb2SAnirudh Venkataramanan 192940b61afSAnirudh Venkataramanan #endif /* _ICE_TXRX_H_ */ 193