1940b61afSAnirudh Venkataramanan /* SPDX-License-Identifier: GPL-2.0 */ 2940b61afSAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */ 3940b61afSAnirudh Venkataramanan 4940b61afSAnirudh Venkataramanan #ifndef _ICE_TXRX_H_ 5940b61afSAnirudh Venkataramanan #define _ICE_TXRX_H_ 6940b61afSAnirudh Venkataramanan 7940b61afSAnirudh Venkataramanan #define ICE_DFLT_IRQ_WORK 256 8cdedef59SAnirudh Venkataramanan #define ICE_RXBUF_2048 2048 9cdedef59SAnirudh Venkataramanan #define ICE_MAX_CHAINED_RX_BUFS 5 102b245cb2SAnirudh Venkataramanan #define ICE_MAX_BUF_TXD 8 112b245cb2SAnirudh Venkataramanan #define ICE_MIN_TX_LEN 17 122b245cb2SAnirudh Venkataramanan 132b245cb2SAnirudh Venkataramanan /* The size limit for a transmit buffer in a descriptor is (16K - 1). 142b245cb2SAnirudh Venkataramanan * In order to align with the read requests we will align the value to 152b245cb2SAnirudh Venkataramanan * the nearest 4K which represents our maximum read request size. 162b245cb2SAnirudh Venkataramanan */ 172b245cb2SAnirudh Venkataramanan #define ICE_MAX_READ_REQ_SIZE 4096 182b245cb2SAnirudh Venkataramanan #define ICE_MAX_DATA_PER_TXD (16 * 1024 - 1) 192b245cb2SAnirudh Venkataramanan #define ICE_MAX_DATA_PER_TXD_ALIGNED \ 202b245cb2SAnirudh Venkataramanan (~(ICE_MAX_READ_REQ_SIZE - 1) & ICE_MAX_DATA_PER_TXD) 212b245cb2SAnirudh Venkataramanan 222b245cb2SAnirudh Venkataramanan #define ICE_RX_BUF_WRITE 16 /* Must be power of 2 */ 23cdedef59SAnirudh Venkataramanan #define ICE_MAX_TXQ_PER_TXQG 128 24cdedef59SAnirudh Venkataramanan 25c585ea42SBrett Creeley /* We are assuming that the cache line is always 64 Bytes here for ice. 26c585ea42SBrett Creeley * In order to make sure that is a correct assumption there is a check in probe 27c585ea42SBrett Creeley * to print a warning if the read from GLPCI_CNF2 tells us that the cache line 28c585ea42SBrett Creeley * size is 128 bytes. We do it this way because we do not want to read the 29c585ea42SBrett Creeley * GLPCI_CNF2 register or a variable containing the value on every pass through 30c585ea42SBrett Creeley * the Tx path. 31c585ea42SBrett Creeley */ 32c585ea42SBrett Creeley #define ICE_CACHE_LINE_BYTES 64 33c585ea42SBrett Creeley #define ICE_DESCS_PER_CACHE_LINE (ICE_CACHE_LINE_BYTES / \ 34c585ea42SBrett Creeley sizeof(struct ice_tx_desc)) 35c585ea42SBrett Creeley #define ICE_DESCS_FOR_CTX_DESC 1 36c585ea42SBrett Creeley #define ICE_DESCS_FOR_SKB_DATA_PTR 1 37c585ea42SBrett Creeley /* Tx descriptors needed, worst case */ 38c585ea42SBrett Creeley #define DESC_NEEDED (MAX_SKB_FRAGS + ICE_DESCS_FOR_CTX_DESC + \ 39c585ea42SBrett Creeley ICE_DESCS_PER_CACHE_LINE + ICE_DESCS_FOR_SKB_DATA_PTR) 40cdedef59SAnirudh Venkataramanan #define ICE_DESC_UNUSED(R) \ 41cdedef59SAnirudh Venkataramanan ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 42cdedef59SAnirudh Venkataramanan (R)->next_to_clean - (R)->next_to_use - 1) 43cdedef59SAnirudh Venkataramanan 44d76a60baSAnirudh Venkataramanan #define ICE_TX_FLAGS_TSO BIT(0) 45d76a60baSAnirudh Venkataramanan #define ICE_TX_FLAGS_HW_VLAN BIT(1) 46d76a60baSAnirudh Venkataramanan #define ICE_TX_FLAGS_SW_VLAN BIT(2) 47d76a60baSAnirudh Venkataramanan #define ICE_TX_FLAGS_VLAN_M 0xffff0000 48d76a60baSAnirudh Venkataramanan #define ICE_TX_FLAGS_VLAN_S 16 49d76a60baSAnirudh Venkataramanan 50cdedef59SAnirudh Venkataramanan struct ice_tx_buf { 51cdedef59SAnirudh Venkataramanan struct ice_tx_desc *next_to_watch; 52cdedef59SAnirudh Venkataramanan struct sk_buff *skb; 53cdedef59SAnirudh Venkataramanan unsigned int bytecount; 54cdedef59SAnirudh Venkataramanan unsigned short gso_segs; 55cdedef59SAnirudh Venkataramanan u32 tx_flags; 56cdedef59SAnirudh Venkataramanan DEFINE_DMA_UNMAP_ADDR(dma); 57cdedef59SAnirudh Venkataramanan DEFINE_DMA_UNMAP_LEN(len); 58cdedef59SAnirudh Venkataramanan }; 59cdedef59SAnirudh Venkataramanan 60d76a60baSAnirudh Venkataramanan struct ice_tx_offload_params { 61d76a60baSAnirudh Venkataramanan u8 header_len; 62d76a60baSAnirudh Venkataramanan u32 td_cmd; 63d76a60baSAnirudh Venkataramanan u32 td_offset; 64d76a60baSAnirudh Venkataramanan u32 td_l2tag1; 65d76a60baSAnirudh Venkataramanan u16 cd_l2tag2; 66d76a60baSAnirudh Venkataramanan u32 cd_tunnel_params; 67d76a60baSAnirudh Venkataramanan u64 cd_qw1; 68d76a60baSAnirudh Venkataramanan struct ice_ring *tx_ring; 69d76a60baSAnirudh Venkataramanan }; 70d76a60baSAnirudh Venkataramanan 71cdedef59SAnirudh Venkataramanan struct ice_rx_buf { 72cdedef59SAnirudh Venkataramanan struct sk_buff *skb; 73cdedef59SAnirudh Venkataramanan dma_addr_t dma; 74cdedef59SAnirudh Venkataramanan struct page *page; 75cdedef59SAnirudh Venkataramanan unsigned int page_offset; 76cdedef59SAnirudh Venkataramanan }; 77940b61afSAnirudh Venkataramanan 782b245cb2SAnirudh Venkataramanan struct ice_q_stats { 792b245cb2SAnirudh Venkataramanan u64 pkts; 802b245cb2SAnirudh Venkataramanan u64 bytes; 812b245cb2SAnirudh Venkataramanan }; 822b245cb2SAnirudh Venkataramanan 832b245cb2SAnirudh Venkataramanan struct ice_txq_stats { 842b245cb2SAnirudh Venkataramanan u64 restart_q; 852b245cb2SAnirudh Venkataramanan u64 tx_busy; 862b245cb2SAnirudh Venkataramanan u64 tx_linearize; 87b3969fd7SSudheer Mogilappagari int prev_pkt; /* negative if no pending Tx descriptors */ 882b245cb2SAnirudh Venkataramanan }; 892b245cb2SAnirudh Venkataramanan 902b245cb2SAnirudh Venkataramanan struct ice_rxq_stats { 912b245cb2SAnirudh Venkataramanan u64 non_eop_descs; 922b245cb2SAnirudh Venkataramanan u64 alloc_page_failed; 932b245cb2SAnirudh Venkataramanan u64 alloc_buf_failed; 942b245cb2SAnirudh Venkataramanan u64 page_reuse_count; 952b245cb2SAnirudh Venkataramanan }; 962b245cb2SAnirudh Venkataramanan 97940b61afSAnirudh Venkataramanan /* this enum matches hardware bits and is meant to be used by DYN_CTLN 98940b61afSAnirudh Venkataramanan * registers and QINT registers or more generally anywhere in the manual 99940b61afSAnirudh Venkataramanan * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any 100940b61afSAnirudh Venkataramanan * register but instead is a special value meaning "don't update" ITR0/1/2. 101940b61afSAnirudh Venkataramanan */ 102940b61afSAnirudh Venkataramanan enum ice_dyn_idx_t { 103940b61afSAnirudh Venkataramanan ICE_IDX_ITR0 = 0, 104940b61afSAnirudh Venkataramanan ICE_IDX_ITR1 = 1, 105940b61afSAnirudh Venkataramanan ICE_IDX_ITR2 = 2, 106940b61afSAnirudh Venkataramanan ICE_ITR_NONE = 3 /* ITR_NONE must not be used as an index */ 107940b61afSAnirudh Venkataramanan }; 108940b61afSAnirudh Venkataramanan 109cdedef59SAnirudh Venkataramanan /* Header split modes defined by DTYPE field of Rx RLAN context */ 110cdedef59SAnirudh Venkataramanan enum ice_rx_dtype { 111cdedef59SAnirudh Venkataramanan ICE_RX_DTYPE_NO_SPLIT = 0, 112cdedef59SAnirudh Venkataramanan ICE_RX_DTYPE_HEADER_SPLIT = 1, 113cdedef59SAnirudh Venkataramanan ICE_RX_DTYPE_SPLIT_ALWAYS = 2, 114cdedef59SAnirudh Venkataramanan }; 115cdedef59SAnirudh Venkataramanan 116940b61afSAnirudh Venkataramanan /* indices into GLINT_ITR registers */ 117940b61afSAnirudh Venkataramanan #define ICE_RX_ITR ICE_IDX_ITR0 118cdedef59SAnirudh Venkataramanan #define ICE_TX_ITR ICE_IDX_ITR1 11963f545edSBrett Creeley #define ICE_ITR_8K 124 120d2b464a7SBrett Creeley #define ICE_ITR_20K 50 12163f545edSBrett Creeley #define ICE_DFLT_TX_ITR (ICE_ITR_20K | ICE_ITR_DYNAMIC) 12263f545edSBrett Creeley #define ICE_DFLT_RX_ITR (ICE_ITR_20K | ICE_ITR_DYNAMIC) 12363f545edSBrett Creeley #define ICE_ITR_DYNAMIC 0x8000 /* used as flag for itr_setting */ 12463f545edSBrett Creeley #define ITR_TO_REG(setting) ((setting) & ~ICE_ITR_DYNAMIC) 12563f545edSBrett Creeley #define ICE_ITR_GRAN_S 1 /* Assume ITR granularity is 2us */ 12663f545edSBrett Creeley #define ICE_ITR_MASK 0x1FFE /* ITR register value alignment mask */ 12763f545edSBrett Creeley #define ITR_REG_ALIGN(setting) __ALIGN_MASK(setting, ~ICE_ITR_MASK) 128940b61afSAnirudh Venkataramanan 1299e4ab4c2SBrett Creeley #define ICE_DFLT_INTRL 0 130940b61afSAnirudh Venkataramanan 131cdedef59SAnirudh Venkataramanan /* Legacy or Advanced Mode Queue */ 132cdedef59SAnirudh Venkataramanan #define ICE_TX_ADVANCED 0 133cdedef59SAnirudh Venkataramanan #define ICE_TX_LEGACY 1 134cdedef59SAnirudh Venkataramanan 1353a858ba3SAnirudh Venkataramanan /* descriptor ring, associated with a VSI */ 1363a858ba3SAnirudh Venkataramanan struct ice_ring { 1373a858ba3SAnirudh Venkataramanan struct ice_ring *next; /* pointer to next ring in q_vector */ 138cdedef59SAnirudh Venkataramanan void *desc; /* Descriptor ring memory */ 1393a858ba3SAnirudh Venkataramanan struct device *dev; /* Used for DMA mapping */ 1403a858ba3SAnirudh Venkataramanan struct net_device *netdev; /* netdev ring maps to */ 1413a858ba3SAnirudh Venkataramanan struct ice_vsi *vsi; /* Backreference to associated VSI */ 1423a858ba3SAnirudh Venkataramanan struct ice_q_vector *q_vector; /* Backreference to associated vector */ 143cdedef59SAnirudh Venkataramanan u8 __iomem *tail; 144cdedef59SAnirudh Venkataramanan union { 145cdedef59SAnirudh Venkataramanan struct ice_tx_buf *tx_buf; 146cdedef59SAnirudh Venkataramanan struct ice_rx_buf *rx_buf; 147cdedef59SAnirudh Venkataramanan }; 1483a858ba3SAnirudh Venkataramanan u16 q_index; /* Queue number of ring */ 149cdedef59SAnirudh Venkataramanan u32 txq_teid; /* Added Tx queue TEID */ 150cdedef59SAnirudh Venkataramanan 1513a858ba3SAnirudh Venkataramanan u16 count; /* Number of descriptors */ 1523a858ba3SAnirudh Venkataramanan u16 reg_idx; /* HW register index of the ring */ 153cdedef59SAnirudh Venkataramanan 154cdedef59SAnirudh Venkataramanan /* used in interrupt processing */ 155cdedef59SAnirudh Venkataramanan u16 next_to_use; 156cdedef59SAnirudh Venkataramanan u16 next_to_clean; 157cdedef59SAnirudh Venkataramanan 15843f8b224SBruce Allan u8 ring_active; /* is ring online or not */ 1592b245cb2SAnirudh Venkataramanan 1602b245cb2SAnirudh Venkataramanan /* stats structs */ 1612b245cb2SAnirudh Venkataramanan struct ice_q_stats stats; 1622b245cb2SAnirudh Venkataramanan struct u64_stats_sync syncp; 1632b245cb2SAnirudh Venkataramanan union { 1642b245cb2SAnirudh Venkataramanan struct ice_txq_stats tx_stats; 1652b245cb2SAnirudh Venkataramanan struct ice_rxq_stats rx_stats; 1662b245cb2SAnirudh Venkataramanan }; 1672b245cb2SAnirudh Venkataramanan 168cdedef59SAnirudh Venkataramanan unsigned int size; /* length of descriptor ring in bytes */ 169cdedef59SAnirudh Venkataramanan dma_addr_t dma; /* physical address of ring */ 1703a858ba3SAnirudh Venkataramanan struct rcu_head rcu; /* to avoid race on free */ 171cdedef59SAnirudh Venkataramanan u16 next_to_alloc; 1723a858ba3SAnirudh Venkataramanan } ____cacheline_internodealigned_in_smp; 1733a858ba3SAnirudh Venkataramanan 174cdedef59SAnirudh Venkataramanan enum ice_latency_range { 175cdedef59SAnirudh Venkataramanan ICE_LOWEST_LATENCY = 0, 176cdedef59SAnirudh Venkataramanan ICE_LOW_LATENCY = 1, 177cdedef59SAnirudh Venkataramanan ICE_BULK_LATENCY = 2, 178cdedef59SAnirudh Venkataramanan ICE_ULTRA_LATENCY = 3, 179cdedef59SAnirudh Venkataramanan }; 180cdedef59SAnirudh Venkataramanan 1813a858ba3SAnirudh Venkataramanan struct ice_ring_container { 18263f545edSBrett Creeley /* head of linked-list of rings */ 1833a858ba3SAnirudh Venkataramanan struct ice_ring *ring; 18463f545edSBrett Creeley unsigned long next_update; /* jiffies value of next queue update */ 1853a858ba3SAnirudh Venkataramanan unsigned int total_bytes; /* total bytes processed this int */ 1863a858ba3SAnirudh Venkataramanan unsigned int total_pkts; /* total packets processed this int */ 187cdedef59SAnirudh Venkataramanan enum ice_latency_range latency_range; 188d2b464a7SBrett Creeley int itr_idx; /* index in the interrupt vector */ 18963f545edSBrett Creeley u16 target_itr; /* value in usecs divided by the hw->itr_gran */ 19063f545edSBrett Creeley u16 current_itr; /* value in usecs divided by the hw->itr_gran */ 19163f545edSBrett Creeley /* high bit set means dynamic ITR, rest is used to store user 19263f545edSBrett Creeley * readable ITR value in usecs and must be converted before programming 19363f545edSBrett Creeley * to a register. 19463f545edSBrett Creeley */ 19563f545edSBrett Creeley u16 itr_setting; 1963a858ba3SAnirudh Venkataramanan }; 1973a858ba3SAnirudh Venkataramanan 1983a858ba3SAnirudh Venkataramanan /* iterator for handling rings in ring container */ 1993a858ba3SAnirudh Venkataramanan #define ice_for_each_ring(pos, head) \ 2003a858ba3SAnirudh Venkataramanan for (pos = (head).ring; pos; pos = pos->next) 2013a858ba3SAnirudh Venkataramanan 202cdedef59SAnirudh Venkataramanan bool ice_alloc_rx_bufs(struct ice_ring *rxr, u16 cleaned_count); 2032b245cb2SAnirudh Venkataramanan netdev_tx_t ice_start_xmit(struct sk_buff *skb, struct net_device *netdev); 204cdedef59SAnirudh Venkataramanan void ice_clean_tx_ring(struct ice_ring *tx_ring); 205cdedef59SAnirudh Venkataramanan void ice_clean_rx_ring(struct ice_ring *rx_ring); 206cdedef59SAnirudh Venkataramanan int ice_setup_tx_ring(struct ice_ring *tx_ring); 207cdedef59SAnirudh Venkataramanan int ice_setup_rx_ring(struct ice_ring *rx_ring); 208cdedef59SAnirudh Venkataramanan void ice_free_tx_ring(struct ice_ring *tx_ring); 209cdedef59SAnirudh Venkataramanan void ice_free_rx_ring(struct ice_ring *rx_ring); 2102b245cb2SAnirudh Venkataramanan int ice_napi_poll(struct napi_struct *napi, int budget); 2112b245cb2SAnirudh Venkataramanan 212940b61afSAnirudh Venkataramanan #endif /* _ICE_TXRX_H_ */ 213