1940b61afSAnirudh Venkataramanan /* SPDX-License-Identifier: GPL-2.0 */ 2940b61afSAnirudh Venkataramanan /* Copyright (c) 2018, Intel Corporation. */ 3940b61afSAnirudh Venkataramanan 4940b61afSAnirudh Venkataramanan #ifndef _ICE_TXRX_H_ 5940b61afSAnirudh Venkataramanan #define _ICE_TXRX_H_ 6940b61afSAnirudh Venkataramanan 7940b61afSAnirudh Venkataramanan #define ICE_DFLT_IRQ_WORK 256 8cdedef59SAnirudh Venkataramanan #define ICE_RXBUF_2048 2048 9cdedef59SAnirudh Venkataramanan #define ICE_MAX_CHAINED_RX_BUFS 5 102b245cb2SAnirudh Venkataramanan #define ICE_MAX_BUF_TXD 8 112b245cb2SAnirudh Venkataramanan #define ICE_MIN_TX_LEN 17 122b245cb2SAnirudh Venkataramanan 132b245cb2SAnirudh Venkataramanan /* The size limit for a transmit buffer in a descriptor is (16K - 1). 142b245cb2SAnirudh Venkataramanan * In order to align with the read requests we will align the value to 152b245cb2SAnirudh Venkataramanan * the nearest 4K which represents our maximum read request size. 162b245cb2SAnirudh Venkataramanan */ 172b245cb2SAnirudh Venkataramanan #define ICE_MAX_READ_REQ_SIZE 4096 182b245cb2SAnirudh Venkataramanan #define ICE_MAX_DATA_PER_TXD (16 * 1024 - 1) 192b245cb2SAnirudh Venkataramanan #define ICE_MAX_DATA_PER_TXD_ALIGNED \ 202b245cb2SAnirudh Venkataramanan (~(ICE_MAX_READ_REQ_SIZE - 1) & ICE_MAX_DATA_PER_TXD) 212b245cb2SAnirudh Venkataramanan 222b245cb2SAnirudh Venkataramanan #define ICE_RX_BUF_WRITE 16 /* Must be power of 2 */ 23cdedef59SAnirudh Venkataramanan #define ICE_MAX_TXQ_PER_TXQG 128 24cdedef59SAnirudh Venkataramanan 25c585ea42SBrett Creeley /* We are assuming that the cache line is always 64 Bytes here for ice. 26c585ea42SBrett Creeley * In order to make sure that is a correct assumption there is a check in probe 27c585ea42SBrett Creeley * to print a warning if the read from GLPCI_CNF2 tells us that the cache line 28c585ea42SBrett Creeley * size is 128 bytes. We do it this way because we do not want to read the 29c585ea42SBrett Creeley * GLPCI_CNF2 register or a variable containing the value on every pass through 30c585ea42SBrett Creeley * the Tx path. 31c585ea42SBrett Creeley */ 32c585ea42SBrett Creeley #define ICE_CACHE_LINE_BYTES 64 33c585ea42SBrett Creeley #define ICE_DESCS_PER_CACHE_LINE (ICE_CACHE_LINE_BYTES / \ 34c585ea42SBrett Creeley sizeof(struct ice_tx_desc)) 35c585ea42SBrett Creeley #define ICE_DESCS_FOR_CTX_DESC 1 36c585ea42SBrett Creeley #define ICE_DESCS_FOR_SKB_DATA_PTR 1 37c585ea42SBrett Creeley /* Tx descriptors needed, worst case */ 38c585ea42SBrett Creeley #define DESC_NEEDED (MAX_SKB_FRAGS + ICE_DESCS_FOR_CTX_DESC + \ 39c585ea42SBrett Creeley ICE_DESCS_PER_CACHE_LINE + ICE_DESCS_FOR_SKB_DATA_PTR) 40cdedef59SAnirudh Venkataramanan #define ICE_DESC_UNUSED(R) \ 41cdedef59SAnirudh Venkataramanan ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 42cdedef59SAnirudh Venkataramanan (R)->next_to_clean - (R)->next_to_use - 1) 43cdedef59SAnirudh Venkataramanan 44d76a60baSAnirudh Venkataramanan #define ICE_TX_FLAGS_TSO BIT(0) 45d76a60baSAnirudh Venkataramanan #define ICE_TX_FLAGS_HW_VLAN BIT(1) 46d76a60baSAnirudh Venkataramanan #define ICE_TX_FLAGS_SW_VLAN BIT(2) 47d76a60baSAnirudh Venkataramanan #define ICE_TX_FLAGS_VLAN_M 0xffff0000 485f6aa50eSAnirudh Venkataramanan #define ICE_TX_FLAGS_VLAN_PR_M 0xe0000000 495f6aa50eSAnirudh Venkataramanan #define ICE_TX_FLAGS_VLAN_PR_S 29 50d76a60baSAnirudh Venkataramanan #define ICE_TX_FLAGS_VLAN_S 16 51d76a60baSAnirudh Venkataramanan 52a65f71feSMaciej Fijalkowski #define ICE_RX_DMA_ATTR \ 53a65f71feSMaciej Fijalkowski (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) 54a65f71feSMaciej Fijalkowski 55cdedef59SAnirudh Venkataramanan struct ice_tx_buf { 56cdedef59SAnirudh Venkataramanan struct ice_tx_desc *next_to_watch; 57cdedef59SAnirudh Venkataramanan struct sk_buff *skb; 58cdedef59SAnirudh Venkataramanan unsigned int bytecount; 59cdedef59SAnirudh Venkataramanan unsigned short gso_segs; 60cdedef59SAnirudh Venkataramanan u32 tx_flags; 61cdedef59SAnirudh Venkataramanan DEFINE_DMA_UNMAP_LEN(len); 6265124bbfSJesse Brandeburg DEFINE_DMA_UNMAP_ADDR(dma); 63cdedef59SAnirudh Venkataramanan }; 64cdedef59SAnirudh Venkataramanan 65d76a60baSAnirudh Venkataramanan struct ice_tx_offload_params { 6665124bbfSJesse Brandeburg u64 cd_qw1; 6765124bbfSJesse Brandeburg struct ice_ring *tx_ring; 68d76a60baSAnirudh Venkataramanan u32 td_cmd; 69d76a60baSAnirudh Venkataramanan u32 td_offset; 70d76a60baSAnirudh Venkataramanan u32 td_l2tag1; 71d76a60baSAnirudh Venkataramanan u32 cd_tunnel_params; 7265124bbfSJesse Brandeburg u16 cd_l2tag2; 7365124bbfSJesse Brandeburg u8 header_len; 74d76a60baSAnirudh Venkataramanan }; 75d76a60baSAnirudh Venkataramanan 76cdedef59SAnirudh Venkataramanan struct ice_rx_buf { 77cdedef59SAnirudh Venkataramanan struct sk_buff *skb; 78cdedef59SAnirudh Venkataramanan dma_addr_t dma; 79cdedef59SAnirudh Venkataramanan struct page *page; 80cdedef59SAnirudh Venkataramanan unsigned int page_offset; 8103c66a13SMaciej Fijalkowski u16 pagecnt_bias; 82cdedef59SAnirudh Venkataramanan }; 83940b61afSAnirudh Venkataramanan 842b245cb2SAnirudh Venkataramanan struct ice_q_stats { 852b245cb2SAnirudh Venkataramanan u64 pkts; 862b245cb2SAnirudh Venkataramanan u64 bytes; 872b245cb2SAnirudh Venkataramanan }; 882b245cb2SAnirudh Venkataramanan 892b245cb2SAnirudh Venkataramanan struct ice_txq_stats { 902b245cb2SAnirudh Venkataramanan u64 restart_q; 912b245cb2SAnirudh Venkataramanan u64 tx_busy; 922b245cb2SAnirudh Venkataramanan u64 tx_linearize; 93b3969fd7SSudheer Mogilappagari int prev_pkt; /* negative if no pending Tx descriptors */ 942b245cb2SAnirudh Venkataramanan }; 952b245cb2SAnirudh Venkataramanan 962b245cb2SAnirudh Venkataramanan struct ice_rxq_stats { 972b245cb2SAnirudh Venkataramanan u64 non_eop_descs; 982b245cb2SAnirudh Venkataramanan u64 alloc_page_failed; 992b245cb2SAnirudh Venkataramanan u64 alloc_buf_failed; 1002b245cb2SAnirudh Venkataramanan u64 page_reuse_count; 1012b245cb2SAnirudh Venkataramanan }; 1022b245cb2SAnirudh Venkataramanan 103940b61afSAnirudh Venkataramanan /* this enum matches hardware bits and is meant to be used by DYN_CTLN 104940b61afSAnirudh Venkataramanan * registers and QINT registers or more generally anywhere in the manual 105940b61afSAnirudh Venkataramanan * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any 106940b61afSAnirudh Venkataramanan * register but instead is a special value meaning "don't update" ITR0/1/2. 107940b61afSAnirudh Venkataramanan */ 108940b61afSAnirudh Venkataramanan enum ice_dyn_idx_t { 109940b61afSAnirudh Venkataramanan ICE_IDX_ITR0 = 0, 110940b61afSAnirudh Venkataramanan ICE_IDX_ITR1 = 1, 111940b61afSAnirudh Venkataramanan ICE_IDX_ITR2 = 2, 112940b61afSAnirudh Venkataramanan ICE_ITR_NONE = 3 /* ITR_NONE must not be used as an index */ 113940b61afSAnirudh Venkataramanan }; 114940b61afSAnirudh Venkataramanan 115cdedef59SAnirudh Venkataramanan /* Header split modes defined by DTYPE field of Rx RLAN context */ 116cdedef59SAnirudh Venkataramanan enum ice_rx_dtype { 117cdedef59SAnirudh Venkataramanan ICE_RX_DTYPE_NO_SPLIT = 0, 118cdedef59SAnirudh Venkataramanan ICE_RX_DTYPE_HEADER_SPLIT = 1, 119cdedef59SAnirudh Venkataramanan ICE_RX_DTYPE_SPLIT_ALWAYS = 2, 120cdedef59SAnirudh Venkataramanan }; 121cdedef59SAnirudh Venkataramanan 122940b61afSAnirudh Venkataramanan /* indices into GLINT_ITR registers */ 123940b61afSAnirudh Venkataramanan #define ICE_RX_ITR ICE_IDX_ITR0 124cdedef59SAnirudh Venkataramanan #define ICE_TX_ITR ICE_IDX_ITR1 12563f545edSBrett Creeley #define ICE_ITR_8K 124 126d2b464a7SBrett Creeley #define ICE_ITR_20K 50 12767fe64d7SBrett Creeley #define ICE_ITR_MAX 8160 12863f545edSBrett Creeley #define ICE_DFLT_TX_ITR (ICE_ITR_20K | ICE_ITR_DYNAMIC) 12963f545edSBrett Creeley #define ICE_DFLT_RX_ITR (ICE_ITR_20K | ICE_ITR_DYNAMIC) 13063f545edSBrett Creeley #define ICE_ITR_DYNAMIC 0x8000 /* used as flag for itr_setting */ 13167fe64d7SBrett Creeley #define ITR_IS_DYNAMIC(setting) (!!((setting) & ICE_ITR_DYNAMIC)) 13263f545edSBrett Creeley #define ITR_TO_REG(setting) ((setting) & ~ICE_ITR_DYNAMIC) 13392414f32SBrett Creeley #define ICE_ITR_GRAN_S 1 /* ITR granularity is always 2us */ 13470457520SBrett Creeley #define ICE_ITR_GRAN_US BIT(ICE_ITR_GRAN_S) 13563f545edSBrett Creeley #define ICE_ITR_MASK 0x1FFE /* ITR register value alignment mask */ 13663f545edSBrett Creeley #define ITR_REG_ALIGN(setting) __ALIGN_MASK(setting, ~ICE_ITR_MASK) 137940b61afSAnirudh Venkataramanan 13864a59d05SAnirudh Venkataramanan #define ICE_ITR_ADAPTIVE_MIN_INC 0x0002 13964a59d05SAnirudh Venkataramanan #define ICE_ITR_ADAPTIVE_MIN_USECS 0x0002 14064a59d05SAnirudh Venkataramanan #define ICE_ITR_ADAPTIVE_MAX_USECS 0x00FA 14164a59d05SAnirudh Venkataramanan #define ICE_ITR_ADAPTIVE_LATENCY 0x8000 14264a59d05SAnirudh Venkataramanan #define ICE_ITR_ADAPTIVE_BULK 0x0000 14364a59d05SAnirudh Venkataramanan 1449e4ab4c2SBrett Creeley #define ICE_DFLT_INTRL 0 145b9c8bb06SBrett Creeley #define ICE_MAX_INTRL 236 146940b61afSAnirudh Venkataramanan 1472ab28bb0SBrett Creeley #define ICE_WB_ON_ITR_USECS 2 1482ab28bb0SBrett Creeley #define ICE_IN_WB_ON_ITR_MODE 255 1492ab28bb0SBrett Creeley /* Sets WB_ON_ITR and assumes INTENA bit is already cleared, which allows 1502ab28bb0SBrett Creeley * setting the MSK_M bit to tell hardware to ignore the INTENA_M bit. Also, 1512ab28bb0SBrett Creeley * set the write-back latency to the usecs passed in. 1522ab28bb0SBrett Creeley */ 1532ab28bb0SBrett Creeley #define ICE_GLINT_DYN_CTL_WB_ON_ITR(usecs, itr_idx) \ 1542ab28bb0SBrett Creeley ((((usecs) << (GLINT_DYN_CTL_INTERVAL_S - ICE_ITR_GRAN_S)) & \ 1552ab28bb0SBrett Creeley GLINT_DYN_CTL_INTERVAL_M) | \ 1562ab28bb0SBrett Creeley (((itr_idx) << GLINT_DYN_CTL_ITR_INDX_S) & \ 1572ab28bb0SBrett Creeley GLINT_DYN_CTL_ITR_INDX_M) | GLINT_DYN_CTL_INTENA_MSK_M | \ 1582ab28bb0SBrett Creeley GLINT_DYN_CTL_WB_ON_ITR_M) 1592ab28bb0SBrett Creeley 160cdedef59SAnirudh Venkataramanan /* Legacy or Advanced Mode Queue */ 161cdedef59SAnirudh Venkataramanan #define ICE_TX_ADVANCED 0 162cdedef59SAnirudh Venkataramanan #define ICE_TX_LEGACY 1 163cdedef59SAnirudh Venkataramanan 1643a858ba3SAnirudh Venkataramanan /* descriptor ring, associated with a VSI */ 1653a858ba3SAnirudh Venkataramanan struct ice_ring { 16665124bbfSJesse Brandeburg /* CL1 - 1st cacheline starts here */ 1673a858ba3SAnirudh Venkataramanan struct ice_ring *next; /* pointer to next ring in q_vector */ 168cdedef59SAnirudh Venkataramanan void *desc; /* Descriptor ring memory */ 1693a858ba3SAnirudh Venkataramanan struct device *dev; /* Used for DMA mapping */ 1703a858ba3SAnirudh Venkataramanan struct net_device *netdev; /* netdev ring maps to */ 1713a858ba3SAnirudh Venkataramanan struct ice_vsi *vsi; /* Backreference to associated VSI */ 1723a858ba3SAnirudh Venkataramanan struct ice_q_vector *q_vector; /* Backreference to associated vector */ 173cdedef59SAnirudh Venkataramanan u8 __iomem *tail; 174cdedef59SAnirudh Venkataramanan union { 175cdedef59SAnirudh Venkataramanan struct ice_tx_buf *tx_buf; 176cdedef59SAnirudh Venkataramanan struct ice_rx_buf *rx_buf; 177cdedef59SAnirudh Venkataramanan }; 17865124bbfSJesse Brandeburg /* CL2 - 2nd cacheline starts here */ 1793a858ba3SAnirudh Venkataramanan u16 q_index; /* Queue number of ring */ 18065124bbfSJesse Brandeburg u16 q_handle; /* Queue handle per TC */ 18165124bbfSJesse Brandeburg 1820ab54c5fSJesse Brandeburg u8 ring_active:1; /* is ring online or not */ 183cdedef59SAnirudh Venkataramanan 1843a858ba3SAnirudh Venkataramanan u16 count; /* Number of descriptors */ 1853a858ba3SAnirudh Venkataramanan u16 reg_idx; /* HW register index of the ring */ 186cdedef59SAnirudh Venkataramanan 187cdedef59SAnirudh Venkataramanan /* used in interrupt processing */ 188cdedef59SAnirudh Venkataramanan u16 next_to_use; 189cdedef59SAnirudh Venkataramanan u16 next_to_clean; 19065124bbfSJesse Brandeburg u16 next_to_alloc; 1912b245cb2SAnirudh Venkataramanan 1922b245cb2SAnirudh Venkataramanan /* stats structs */ 1932b245cb2SAnirudh Venkataramanan struct ice_q_stats stats; 1942b245cb2SAnirudh Venkataramanan struct u64_stats_sync syncp; 1952b245cb2SAnirudh Venkataramanan union { 1962b245cb2SAnirudh Venkataramanan struct ice_txq_stats tx_stats; 1972b245cb2SAnirudh Venkataramanan struct ice_rxq_stats rx_stats; 1982b245cb2SAnirudh Venkataramanan }; 1992b245cb2SAnirudh Venkataramanan 2003a858ba3SAnirudh Venkataramanan struct rcu_head rcu; /* to avoid race on free */ 20165124bbfSJesse Brandeburg /* CLX - the below items are only accessed infrequently and should be 20265124bbfSJesse Brandeburg * in their own cache line if possible 20365124bbfSJesse Brandeburg */ 20465124bbfSJesse Brandeburg dma_addr_t dma; /* physical address of ring */ 20565124bbfSJesse Brandeburg unsigned int size; /* length of descriptor ring in bytes */ 20665124bbfSJesse Brandeburg u32 txq_teid; /* Added Tx queue TEID */ 20765124bbfSJesse Brandeburg u16 rx_buf_len; 20865124bbfSJesse Brandeburg #ifdef CONFIG_DCB 20965124bbfSJesse Brandeburg u8 dcb_tc; /* Traffic class of ring */ 21065124bbfSJesse Brandeburg #endif /* CONFIG_DCB */ 2113a858ba3SAnirudh Venkataramanan } ____cacheline_internodealigned_in_smp; 2123a858ba3SAnirudh Venkataramanan 2133a858ba3SAnirudh Venkataramanan struct ice_ring_container { 21463f545edSBrett Creeley /* head of linked-list of rings */ 2153a858ba3SAnirudh Venkataramanan struct ice_ring *ring; 21663f545edSBrett Creeley unsigned long next_update; /* jiffies value of next queue update */ 2173a858ba3SAnirudh Venkataramanan unsigned int total_bytes; /* total bytes processed this int */ 2183a858ba3SAnirudh Venkataramanan unsigned int total_pkts; /* total packets processed this int */ 2198244dd2dSBrett Creeley u16 itr_idx; /* index in the interrupt vector */ 22063f545edSBrett Creeley u16 target_itr; /* value in usecs divided by the hw->itr_gran */ 22163f545edSBrett Creeley u16 current_itr; /* value in usecs divided by the hw->itr_gran */ 22263f545edSBrett Creeley /* high bit set means dynamic ITR, rest is used to store user 22363f545edSBrett Creeley * readable ITR value in usecs and must be converted before programming 22463f545edSBrett Creeley * to a register. 22563f545edSBrett Creeley */ 22663f545edSBrett Creeley u16 itr_setting; 2273a858ba3SAnirudh Venkataramanan }; 2283a858ba3SAnirudh Venkataramanan 2293a858ba3SAnirudh Venkataramanan /* iterator for handling rings in ring container */ 2303a858ba3SAnirudh Venkataramanan #define ice_for_each_ring(pos, head) \ 2313a858ba3SAnirudh Venkataramanan for (pos = (head).ring; pos; pos = pos->next) 2323a858ba3SAnirudh Venkataramanan 233cdedef59SAnirudh Venkataramanan bool ice_alloc_rx_bufs(struct ice_ring *rxr, u16 cleaned_count); 2342b245cb2SAnirudh Venkataramanan netdev_tx_t ice_start_xmit(struct sk_buff *skb, struct net_device *netdev); 235cdedef59SAnirudh Venkataramanan void ice_clean_tx_ring(struct ice_ring *tx_ring); 236cdedef59SAnirudh Venkataramanan void ice_clean_rx_ring(struct ice_ring *rx_ring); 237cdedef59SAnirudh Venkataramanan int ice_setup_tx_ring(struct ice_ring *tx_ring); 238cdedef59SAnirudh Venkataramanan int ice_setup_rx_ring(struct ice_ring *rx_ring); 239cdedef59SAnirudh Venkataramanan void ice_free_tx_ring(struct ice_ring *tx_ring); 240cdedef59SAnirudh Venkataramanan void ice_free_rx_ring(struct ice_ring *rx_ring); 2412b245cb2SAnirudh Venkataramanan int ice_napi_poll(struct napi_struct *napi, int budget); 2422b245cb2SAnirudh Venkataramanan 243940b61afSAnirudh Venkataramanan #endif /* _ICE_TXRX_H_ */ 244