1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 /* The driver transmit and receive code */ 5 6 #include <linux/mm.h> 7 #include <linux/netdevice.h> 8 #include <linux/prefetch.h> 9 #include <linux/bpf_trace.h> 10 #include <net/dsfield.h> 11 #include <net/mpls.h> 12 #include <net/xdp.h> 13 #include "ice_txrx_lib.h" 14 #include "ice_lib.h" 15 #include "ice.h" 16 #include "ice_trace.h" 17 #include "ice_dcb_lib.h" 18 #include "ice_xsk.h" 19 #include "ice_eswitch.h" 20 21 #define ICE_RX_HDR_SIZE 256 22 23 #define FDIR_DESC_RXDID 0x40 24 #define ICE_FDIR_CLEAN_DELAY 10 25 26 /** 27 * ice_prgm_fdir_fltr - Program a Flow Director filter 28 * @vsi: VSI to send dummy packet 29 * @fdir_desc: flow director descriptor 30 * @raw_packet: allocated buffer for flow director 31 */ 32 int 33 ice_prgm_fdir_fltr(struct ice_vsi *vsi, struct ice_fltr_desc *fdir_desc, 34 u8 *raw_packet) 35 { 36 struct ice_tx_buf *tx_buf, *first; 37 struct ice_fltr_desc *f_desc; 38 struct ice_tx_desc *tx_desc; 39 struct ice_tx_ring *tx_ring; 40 struct device *dev; 41 dma_addr_t dma; 42 u32 td_cmd; 43 u16 i; 44 45 /* VSI and Tx ring */ 46 if (!vsi) 47 return -ENOENT; 48 tx_ring = vsi->tx_rings[0]; 49 if (!tx_ring || !tx_ring->desc) 50 return -ENOENT; 51 dev = tx_ring->dev; 52 53 /* we are using two descriptors to add/del a filter and we can wait */ 54 for (i = ICE_FDIR_CLEAN_DELAY; ICE_DESC_UNUSED(tx_ring) < 2; i--) { 55 if (!i) 56 return -EAGAIN; 57 msleep_interruptible(1); 58 } 59 60 dma = dma_map_single(dev, raw_packet, ICE_FDIR_MAX_RAW_PKT_SIZE, 61 DMA_TO_DEVICE); 62 63 if (dma_mapping_error(dev, dma)) 64 return -EINVAL; 65 66 /* grab the next descriptor */ 67 i = tx_ring->next_to_use; 68 first = &tx_ring->tx_buf[i]; 69 f_desc = ICE_TX_FDIRDESC(tx_ring, i); 70 memcpy(f_desc, fdir_desc, sizeof(*f_desc)); 71 72 i++; 73 i = (i < tx_ring->count) ? i : 0; 74 tx_desc = ICE_TX_DESC(tx_ring, i); 75 tx_buf = &tx_ring->tx_buf[i]; 76 77 i++; 78 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 79 80 memset(tx_buf, 0, sizeof(*tx_buf)); 81 dma_unmap_len_set(tx_buf, len, ICE_FDIR_MAX_RAW_PKT_SIZE); 82 dma_unmap_addr_set(tx_buf, dma, dma); 83 84 tx_desc->buf_addr = cpu_to_le64(dma); 85 td_cmd = ICE_TXD_LAST_DESC_CMD | ICE_TX_DESC_CMD_DUMMY | 86 ICE_TX_DESC_CMD_RE; 87 88 tx_buf->tx_flags = ICE_TX_FLAGS_DUMMY_PKT; 89 tx_buf->raw_buf = raw_packet; 90 91 tx_desc->cmd_type_offset_bsz = 92 ice_build_ctob(td_cmd, 0, ICE_FDIR_MAX_RAW_PKT_SIZE, 0); 93 94 /* Force memory write to complete before letting h/w know 95 * there are new descriptors to fetch. 96 */ 97 wmb(); 98 99 /* mark the data descriptor to be watched */ 100 first->next_to_watch = tx_desc; 101 102 writel(tx_ring->next_to_use, tx_ring->tail); 103 104 return 0; 105 } 106 107 /** 108 * ice_unmap_and_free_tx_buf - Release a Tx buffer 109 * @ring: the ring that owns the buffer 110 * @tx_buf: the buffer to free 111 */ 112 static void 113 ice_unmap_and_free_tx_buf(struct ice_tx_ring *ring, struct ice_tx_buf *tx_buf) 114 { 115 if (tx_buf->skb) { 116 if (tx_buf->tx_flags & ICE_TX_FLAGS_DUMMY_PKT) 117 devm_kfree(ring->dev, tx_buf->raw_buf); 118 else if (ice_ring_is_xdp(ring)) 119 page_frag_free(tx_buf->raw_buf); 120 else 121 dev_kfree_skb_any(tx_buf->skb); 122 if (dma_unmap_len(tx_buf, len)) 123 dma_unmap_single(ring->dev, 124 dma_unmap_addr(tx_buf, dma), 125 dma_unmap_len(tx_buf, len), 126 DMA_TO_DEVICE); 127 } else if (dma_unmap_len(tx_buf, len)) { 128 dma_unmap_page(ring->dev, 129 dma_unmap_addr(tx_buf, dma), 130 dma_unmap_len(tx_buf, len), 131 DMA_TO_DEVICE); 132 } 133 134 tx_buf->next_to_watch = NULL; 135 tx_buf->skb = NULL; 136 dma_unmap_len_set(tx_buf, len, 0); 137 /* tx_buf must be completely set up in the transmit path */ 138 } 139 140 static struct netdev_queue *txring_txq(const struct ice_tx_ring *ring) 141 { 142 return netdev_get_tx_queue(ring->netdev, ring->q_index); 143 } 144 145 /** 146 * ice_clean_tx_ring - Free any empty Tx buffers 147 * @tx_ring: ring to be cleaned 148 */ 149 void ice_clean_tx_ring(struct ice_tx_ring *tx_ring) 150 { 151 u32 size; 152 u16 i; 153 154 if (ice_ring_is_xdp(tx_ring) && tx_ring->xsk_pool) { 155 ice_xsk_clean_xdp_ring(tx_ring); 156 goto tx_skip_free; 157 } 158 159 /* ring already cleared, nothing to do */ 160 if (!tx_ring->tx_buf) 161 return; 162 163 /* Free all the Tx ring sk_buffs */ 164 for (i = 0; i < tx_ring->count; i++) 165 ice_unmap_and_free_tx_buf(tx_ring, &tx_ring->tx_buf[i]); 166 167 tx_skip_free: 168 memset(tx_ring->tx_buf, 0, sizeof(*tx_ring->tx_buf) * tx_ring->count); 169 170 size = ALIGN(tx_ring->count * sizeof(struct ice_tx_desc), 171 PAGE_SIZE); 172 /* Zero out the descriptor ring */ 173 memset(tx_ring->desc, 0, size); 174 175 tx_ring->next_to_use = 0; 176 tx_ring->next_to_clean = 0; 177 tx_ring->next_dd = ICE_RING_QUARTER(tx_ring) - 1; 178 tx_ring->next_rs = ICE_RING_QUARTER(tx_ring) - 1; 179 180 if (!tx_ring->netdev) 181 return; 182 183 /* cleanup Tx queue statistics */ 184 netdev_tx_reset_queue(txring_txq(tx_ring)); 185 } 186 187 /** 188 * ice_free_tx_ring - Free Tx resources per queue 189 * @tx_ring: Tx descriptor ring for a specific queue 190 * 191 * Free all transmit software resources 192 */ 193 void ice_free_tx_ring(struct ice_tx_ring *tx_ring) 194 { 195 u32 size; 196 197 ice_clean_tx_ring(tx_ring); 198 devm_kfree(tx_ring->dev, tx_ring->tx_buf); 199 tx_ring->tx_buf = NULL; 200 201 if (tx_ring->desc) { 202 size = ALIGN(tx_ring->count * sizeof(struct ice_tx_desc), 203 PAGE_SIZE); 204 dmam_free_coherent(tx_ring->dev, size, 205 tx_ring->desc, tx_ring->dma); 206 tx_ring->desc = NULL; 207 } 208 } 209 210 /** 211 * ice_clean_tx_irq - Reclaim resources after transmit completes 212 * @tx_ring: Tx ring to clean 213 * @napi_budget: Used to determine if we are in netpoll 214 * 215 * Returns true if there's any budget left (e.g. the clean is finished) 216 */ 217 static bool ice_clean_tx_irq(struct ice_tx_ring *tx_ring, int napi_budget) 218 { 219 unsigned int total_bytes = 0, total_pkts = 0; 220 unsigned int budget = ICE_DFLT_IRQ_WORK; 221 struct ice_vsi *vsi = tx_ring->vsi; 222 s16 i = tx_ring->next_to_clean; 223 struct ice_tx_desc *tx_desc; 224 struct ice_tx_buf *tx_buf; 225 226 /* get the bql data ready */ 227 netdev_txq_bql_complete_prefetchw(txring_txq(tx_ring)); 228 229 tx_buf = &tx_ring->tx_buf[i]; 230 tx_desc = ICE_TX_DESC(tx_ring, i); 231 i -= tx_ring->count; 232 233 prefetch(&vsi->state); 234 235 do { 236 struct ice_tx_desc *eop_desc = tx_buf->next_to_watch; 237 238 /* if next_to_watch is not set then there is no work pending */ 239 if (!eop_desc) 240 break; 241 242 /* follow the guidelines of other drivers */ 243 prefetchw(&tx_buf->skb->users); 244 245 smp_rmb(); /* prevent any other reads prior to eop_desc */ 246 247 ice_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf); 248 /* if the descriptor isn't done, no work yet to do */ 249 if (!(eop_desc->cmd_type_offset_bsz & 250 cpu_to_le64(ICE_TX_DESC_DTYPE_DESC_DONE))) 251 break; 252 253 /* clear next_to_watch to prevent false hangs */ 254 tx_buf->next_to_watch = NULL; 255 256 /* update the statistics for this packet */ 257 total_bytes += tx_buf->bytecount; 258 total_pkts += tx_buf->gso_segs; 259 260 /* free the skb */ 261 napi_consume_skb(tx_buf->skb, napi_budget); 262 263 /* unmap skb header data */ 264 dma_unmap_single(tx_ring->dev, 265 dma_unmap_addr(tx_buf, dma), 266 dma_unmap_len(tx_buf, len), 267 DMA_TO_DEVICE); 268 269 /* clear tx_buf data */ 270 tx_buf->skb = NULL; 271 dma_unmap_len_set(tx_buf, len, 0); 272 273 /* unmap remaining buffers */ 274 while (tx_desc != eop_desc) { 275 ice_trace(clean_tx_irq_unmap, tx_ring, tx_desc, tx_buf); 276 tx_buf++; 277 tx_desc++; 278 i++; 279 if (unlikely(!i)) { 280 i -= tx_ring->count; 281 tx_buf = tx_ring->tx_buf; 282 tx_desc = ICE_TX_DESC(tx_ring, 0); 283 } 284 285 /* unmap any remaining paged data */ 286 if (dma_unmap_len(tx_buf, len)) { 287 dma_unmap_page(tx_ring->dev, 288 dma_unmap_addr(tx_buf, dma), 289 dma_unmap_len(tx_buf, len), 290 DMA_TO_DEVICE); 291 dma_unmap_len_set(tx_buf, len, 0); 292 } 293 } 294 ice_trace(clean_tx_irq_unmap_eop, tx_ring, tx_desc, tx_buf); 295 296 /* move us one more past the eop_desc for start of next pkt */ 297 tx_buf++; 298 tx_desc++; 299 i++; 300 if (unlikely(!i)) { 301 i -= tx_ring->count; 302 tx_buf = tx_ring->tx_buf; 303 tx_desc = ICE_TX_DESC(tx_ring, 0); 304 } 305 306 prefetch(tx_desc); 307 308 /* update budget accounting */ 309 budget--; 310 } while (likely(budget)); 311 312 i += tx_ring->count; 313 tx_ring->next_to_clean = i; 314 315 ice_update_tx_ring_stats(tx_ring, total_pkts, total_bytes); 316 netdev_tx_completed_queue(txring_txq(tx_ring), total_pkts, total_bytes); 317 318 #define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2)) 319 if (unlikely(total_pkts && netif_carrier_ok(tx_ring->netdev) && 320 (ICE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { 321 /* Make sure that anybody stopping the queue after this 322 * sees the new next_to_clean. 323 */ 324 smp_mb(); 325 if (netif_tx_queue_stopped(txring_txq(tx_ring)) && 326 !test_bit(ICE_VSI_DOWN, vsi->state)) { 327 netif_tx_wake_queue(txring_txq(tx_ring)); 328 ++tx_ring->tx_stats.restart_q; 329 } 330 } 331 332 return !!budget; 333 } 334 335 /** 336 * ice_setup_tx_ring - Allocate the Tx descriptors 337 * @tx_ring: the Tx ring to set up 338 * 339 * Return 0 on success, negative on error 340 */ 341 int ice_setup_tx_ring(struct ice_tx_ring *tx_ring) 342 { 343 struct device *dev = tx_ring->dev; 344 u32 size; 345 346 if (!dev) 347 return -ENOMEM; 348 349 /* warn if we are about to overwrite the pointer */ 350 WARN_ON(tx_ring->tx_buf); 351 tx_ring->tx_buf = 352 devm_kcalloc(dev, sizeof(*tx_ring->tx_buf), tx_ring->count, 353 GFP_KERNEL); 354 if (!tx_ring->tx_buf) 355 return -ENOMEM; 356 357 /* round up to nearest page */ 358 size = ALIGN(tx_ring->count * sizeof(struct ice_tx_desc), 359 PAGE_SIZE); 360 tx_ring->desc = dmam_alloc_coherent(dev, size, &tx_ring->dma, 361 GFP_KERNEL); 362 if (!tx_ring->desc) { 363 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n", 364 size); 365 goto err; 366 } 367 368 tx_ring->next_to_use = 0; 369 tx_ring->next_to_clean = 0; 370 tx_ring->tx_stats.prev_pkt = -1; 371 return 0; 372 373 err: 374 devm_kfree(dev, tx_ring->tx_buf); 375 tx_ring->tx_buf = NULL; 376 return -ENOMEM; 377 } 378 379 /** 380 * ice_clean_rx_ring - Free Rx buffers 381 * @rx_ring: ring to be cleaned 382 */ 383 void ice_clean_rx_ring(struct ice_rx_ring *rx_ring) 384 { 385 struct device *dev = rx_ring->dev; 386 u32 size; 387 u16 i; 388 389 /* ring already cleared, nothing to do */ 390 if (!rx_ring->rx_buf) 391 return; 392 393 if (rx_ring->skb) { 394 dev_kfree_skb(rx_ring->skb); 395 rx_ring->skb = NULL; 396 } 397 398 if (rx_ring->xsk_pool) { 399 ice_xsk_clean_rx_ring(rx_ring); 400 goto rx_skip_free; 401 } 402 403 /* Free all the Rx ring sk_buffs */ 404 for (i = 0; i < rx_ring->count; i++) { 405 struct ice_rx_buf *rx_buf = &rx_ring->rx_buf[i]; 406 407 if (!rx_buf->page) 408 continue; 409 410 /* Invalidate cache lines that may have been written to by 411 * device so that we avoid corrupting memory. 412 */ 413 dma_sync_single_range_for_cpu(dev, rx_buf->dma, 414 rx_buf->page_offset, 415 rx_ring->rx_buf_len, 416 DMA_FROM_DEVICE); 417 418 /* free resources associated with mapping */ 419 dma_unmap_page_attrs(dev, rx_buf->dma, ice_rx_pg_size(rx_ring), 420 DMA_FROM_DEVICE, ICE_RX_DMA_ATTR); 421 __page_frag_cache_drain(rx_buf->page, rx_buf->pagecnt_bias); 422 423 rx_buf->page = NULL; 424 rx_buf->page_offset = 0; 425 } 426 427 rx_skip_free: 428 if (rx_ring->xsk_pool) 429 memset(rx_ring->xdp_buf, 0, array_size(rx_ring->count, sizeof(*rx_ring->xdp_buf))); 430 else 431 memset(rx_ring->rx_buf, 0, array_size(rx_ring->count, sizeof(*rx_ring->rx_buf))); 432 433 /* Zero out the descriptor ring */ 434 size = ALIGN(rx_ring->count * sizeof(union ice_32byte_rx_desc), 435 PAGE_SIZE); 436 memset(rx_ring->desc, 0, size); 437 438 rx_ring->next_to_alloc = 0; 439 rx_ring->next_to_clean = 0; 440 rx_ring->next_to_use = 0; 441 } 442 443 /** 444 * ice_free_rx_ring - Free Rx resources 445 * @rx_ring: ring to clean the resources from 446 * 447 * Free all receive software resources 448 */ 449 void ice_free_rx_ring(struct ice_rx_ring *rx_ring) 450 { 451 u32 size; 452 453 ice_clean_rx_ring(rx_ring); 454 if (rx_ring->vsi->type == ICE_VSI_PF) 455 if (xdp_rxq_info_is_reg(&rx_ring->xdp_rxq)) 456 xdp_rxq_info_unreg(&rx_ring->xdp_rxq); 457 rx_ring->xdp_prog = NULL; 458 if (rx_ring->xsk_pool) { 459 kfree(rx_ring->xdp_buf); 460 rx_ring->xdp_buf = NULL; 461 } else { 462 kfree(rx_ring->rx_buf); 463 rx_ring->rx_buf = NULL; 464 } 465 466 if (rx_ring->desc) { 467 size = ALIGN(rx_ring->count * sizeof(union ice_32byte_rx_desc), 468 PAGE_SIZE); 469 dmam_free_coherent(rx_ring->dev, size, 470 rx_ring->desc, rx_ring->dma); 471 rx_ring->desc = NULL; 472 } 473 } 474 475 /** 476 * ice_setup_rx_ring - Allocate the Rx descriptors 477 * @rx_ring: the Rx ring to set up 478 * 479 * Return 0 on success, negative on error 480 */ 481 int ice_setup_rx_ring(struct ice_rx_ring *rx_ring) 482 { 483 struct device *dev = rx_ring->dev; 484 u32 size; 485 486 if (!dev) 487 return -ENOMEM; 488 489 /* warn if we are about to overwrite the pointer */ 490 WARN_ON(rx_ring->rx_buf); 491 rx_ring->rx_buf = 492 kcalloc(rx_ring->count, sizeof(*rx_ring->rx_buf), GFP_KERNEL); 493 if (!rx_ring->rx_buf) 494 return -ENOMEM; 495 496 /* round up to nearest page */ 497 size = ALIGN(rx_ring->count * sizeof(union ice_32byte_rx_desc), 498 PAGE_SIZE); 499 rx_ring->desc = dmam_alloc_coherent(dev, size, &rx_ring->dma, 500 GFP_KERNEL); 501 if (!rx_ring->desc) { 502 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n", 503 size); 504 goto err; 505 } 506 507 rx_ring->next_to_use = 0; 508 rx_ring->next_to_clean = 0; 509 510 if (ice_is_xdp_ena_vsi(rx_ring->vsi)) 511 WRITE_ONCE(rx_ring->xdp_prog, rx_ring->vsi->xdp_prog); 512 513 if (rx_ring->vsi->type == ICE_VSI_PF && 514 !xdp_rxq_info_is_reg(&rx_ring->xdp_rxq)) 515 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev, 516 rx_ring->q_index, rx_ring->q_vector->napi.napi_id)) 517 goto err; 518 return 0; 519 520 err: 521 kfree(rx_ring->rx_buf); 522 rx_ring->rx_buf = NULL; 523 return -ENOMEM; 524 } 525 526 static unsigned int 527 ice_rx_frame_truesize(struct ice_rx_ring *rx_ring, unsigned int __maybe_unused size) 528 { 529 unsigned int truesize; 530 531 #if (PAGE_SIZE < 8192) 532 truesize = ice_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */ 533 #else 534 truesize = rx_ring->rx_offset ? 535 SKB_DATA_ALIGN(rx_ring->rx_offset + size) + 536 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) : 537 SKB_DATA_ALIGN(size); 538 #endif 539 return truesize; 540 } 541 542 /** 543 * ice_run_xdp - Executes an XDP program on initialized xdp_buff 544 * @rx_ring: Rx ring 545 * @xdp: xdp_buff used as input to the XDP program 546 * @xdp_prog: XDP program to run 547 * @xdp_ring: ring to be used for XDP_TX action 548 * 549 * Returns any of ICE_XDP_{PASS, CONSUMED, TX, REDIR} 550 */ 551 static int 552 ice_run_xdp(struct ice_rx_ring *rx_ring, struct xdp_buff *xdp, 553 struct bpf_prog *xdp_prog, struct ice_tx_ring *xdp_ring) 554 { 555 int err; 556 u32 act; 557 558 act = bpf_prog_run_xdp(xdp_prog, xdp); 559 switch (act) { 560 case XDP_PASS: 561 return ICE_XDP_PASS; 562 case XDP_TX: 563 if (static_branch_unlikely(&ice_xdp_locking_key)) 564 spin_lock(&xdp_ring->tx_lock); 565 err = ice_xmit_xdp_ring(xdp->data, xdp->data_end - xdp->data, xdp_ring); 566 if (static_branch_unlikely(&ice_xdp_locking_key)) 567 spin_unlock(&xdp_ring->tx_lock); 568 if (err == ICE_XDP_CONSUMED) 569 goto out_failure; 570 return err; 571 case XDP_REDIRECT: 572 err = xdp_do_redirect(rx_ring->netdev, xdp, xdp_prog); 573 if (err) 574 goto out_failure; 575 return ICE_XDP_REDIR; 576 default: 577 bpf_warn_invalid_xdp_action(rx_ring->netdev, xdp_prog, act); 578 fallthrough; 579 case XDP_ABORTED: 580 out_failure: 581 trace_xdp_exception(rx_ring->netdev, xdp_prog, act); 582 fallthrough; 583 case XDP_DROP: 584 return ICE_XDP_CONSUMED; 585 } 586 } 587 588 /** 589 * ice_xdp_xmit - submit packets to XDP ring for transmission 590 * @dev: netdev 591 * @n: number of XDP frames to be transmitted 592 * @frames: XDP frames to be transmitted 593 * @flags: transmit flags 594 * 595 * Returns number of frames successfully sent. Failed frames 596 * will be free'ed by XDP core. 597 * For error cases, a negative errno code is returned and no-frames 598 * are transmitted (caller must handle freeing frames). 599 */ 600 int 601 ice_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames, 602 u32 flags) 603 { 604 struct ice_netdev_priv *np = netdev_priv(dev); 605 unsigned int queue_index = smp_processor_id(); 606 struct ice_vsi *vsi = np->vsi; 607 struct ice_tx_ring *xdp_ring; 608 int nxmit = 0, i; 609 610 if (test_bit(ICE_VSI_DOWN, vsi->state)) 611 return -ENETDOWN; 612 613 if (!ice_is_xdp_ena_vsi(vsi)) 614 return -ENXIO; 615 616 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 617 return -EINVAL; 618 619 if (static_branch_unlikely(&ice_xdp_locking_key)) { 620 queue_index %= vsi->num_xdp_txq; 621 xdp_ring = vsi->xdp_rings[queue_index]; 622 spin_lock(&xdp_ring->tx_lock); 623 } else { 624 /* Generally, should not happen */ 625 if (unlikely(queue_index >= vsi->num_xdp_txq)) 626 return -ENXIO; 627 xdp_ring = vsi->xdp_rings[queue_index]; 628 } 629 630 for (i = 0; i < n; i++) { 631 struct xdp_frame *xdpf = frames[i]; 632 int err; 633 634 err = ice_xmit_xdp_ring(xdpf->data, xdpf->len, xdp_ring); 635 if (err != ICE_XDP_TX) 636 break; 637 nxmit++; 638 } 639 640 if (unlikely(flags & XDP_XMIT_FLUSH)) 641 ice_xdp_ring_update_tail(xdp_ring); 642 643 if (static_branch_unlikely(&ice_xdp_locking_key)) 644 spin_unlock(&xdp_ring->tx_lock); 645 646 return nxmit; 647 } 648 649 /** 650 * ice_alloc_mapped_page - recycle or make a new page 651 * @rx_ring: ring to use 652 * @bi: rx_buf struct to modify 653 * 654 * Returns true if the page was successfully allocated or 655 * reused. 656 */ 657 static bool 658 ice_alloc_mapped_page(struct ice_rx_ring *rx_ring, struct ice_rx_buf *bi) 659 { 660 struct page *page = bi->page; 661 dma_addr_t dma; 662 663 /* since we are recycling buffers we should seldom need to alloc */ 664 if (likely(page)) 665 return true; 666 667 /* alloc new page for storage */ 668 page = dev_alloc_pages(ice_rx_pg_order(rx_ring)); 669 if (unlikely(!page)) { 670 rx_ring->rx_stats.alloc_page_failed++; 671 return false; 672 } 673 674 /* map page for use */ 675 dma = dma_map_page_attrs(rx_ring->dev, page, 0, ice_rx_pg_size(rx_ring), 676 DMA_FROM_DEVICE, ICE_RX_DMA_ATTR); 677 678 /* if mapping failed free memory back to system since 679 * there isn't much point in holding memory we can't use 680 */ 681 if (dma_mapping_error(rx_ring->dev, dma)) { 682 __free_pages(page, ice_rx_pg_order(rx_ring)); 683 rx_ring->rx_stats.alloc_page_failed++; 684 return false; 685 } 686 687 bi->dma = dma; 688 bi->page = page; 689 bi->page_offset = rx_ring->rx_offset; 690 page_ref_add(page, USHRT_MAX - 1); 691 bi->pagecnt_bias = USHRT_MAX; 692 693 return true; 694 } 695 696 /** 697 * ice_alloc_rx_bufs - Replace used receive buffers 698 * @rx_ring: ring to place buffers on 699 * @cleaned_count: number of buffers to replace 700 * 701 * Returns false if all allocations were successful, true if any fail. Returning 702 * true signals to the caller that we didn't replace cleaned_count buffers and 703 * there is more work to do. 704 * 705 * First, try to clean "cleaned_count" Rx buffers. Then refill the cleaned Rx 706 * buffers. Then bump tail at most one time. Grouping like this lets us avoid 707 * multiple tail writes per call. 708 */ 709 bool ice_alloc_rx_bufs(struct ice_rx_ring *rx_ring, u16 cleaned_count) 710 { 711 union ice_32b_rx_flex_desc *rx_desc; 712 u16 ntu = rx_ring->next_to_use; 713 struct ice_rx_buf *bi; 714 715 /* do nothing if no valid netdev defined */ 716 if ((!rx_ring->netdev && rx_ring->vsi->type != ICE_VSI_CTRL) || 717 !cleaned_count) 718 return false; 719 720 /* get the Rx descriptor and buffer based on next_to_use */ 721 rx_desc = ICE_RX_DESC(rx_ring, ntu); 722 bi = &rx_ring->rx_buf[ntu]; 723 724 do { 725 /* if we fail here, we have work remaining */ 726 if (!ice_alloc_mapped_page(rx_ring, bi)) 727 break; 728 729 /* sync the buffer for use by the device */ 730 dma_sync_single_range_for_device(rx_ring->dev, bi->dma, 731 bi->page_offset, 732 rx_ring->rx_buf_len, 733 DMA_FROM_DEVICE); 734 735 /* Refresh the desc even if buffer_addrs didn't change 736 * because each write-back erases this info. 737 */ 738 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 739 740 rx_desc++; 741 bi++; 742 ntu++; 743 if (unlikely(ntu == rx_ring->count)) { 744 rx_desc = ICE_RX_DESC(rx_ring, 0); 745 bi = rx_ring->rx_buf; 746 ntu = 0; 747 } 748 749 /* clear the status bits for the next_to_use descriptor */ 750 rx_desc->wb.status_error0 = 0; 751 752 cleaned_count--; 753 } while (cleaned_count); 754 755 if (rx_ring->next_to_use != ntu) 756 ice_release_rx_desc(rx_ring, ntu); 757 758 return !!cleaned_count; 759 } 760 761 /** 762 * ice_rx_buf_adjust_pg_offset - Prepare Rx buffer for reuse 763 * @rx_buf: Rx buffer to adjust 764 * @size: Size of adjustment 765 * 766 * Update the offset within page so that Rx buf will be ready to be reused. 767 * For systems with PAGE_SIZE < 8192 this function will flip the page offset 768 * so the second half of page assigned to Rx buffer will be used, otherwise 769 * the offset is moved by "size" bytes 770 */ 771 static void 772 ice_rx_buf_adjust_pg_offset(struct ice_rx_buf *rx_buf, unsigned int size) 773 { 774 #if (PAGE_SIZE < 8192) 775 /* flip page offset to other buffer */ 776 rx_buf->page_offset ^= size; 777 #else 778 /* move offset up to the next cache line */ 779 rx_buf->page_offset += size; 780 #endif 781 } 782 783 /** 784 * ice_can_reuse_rx_page - Determine if page can be reused for another Rx 785 * @rx_buf: buffer containing the page 786 * @rx_buf_pgcnt: rx_buf page refcount pre xdp_do_redirect() call 787 * 788 * If page is reusable, we have a green light for calling ice_reuse_rx_page, 789 * which will assign the current buffer to the buffer that next_to_alloc is 790 * pointing to; otherwise, the DMA mapping needs to be destroyed and 791 * page freed 792 */ 793 static bool 794 ice_can_reuse_rx_page(struct ice_rx_buf *rx_buf, int rx_buf_pgcnt) 795 { 796 unsigned int pagecnt_bias = rx_buf->pagecnt_bias; 797 struct page *page = rx_buf->page; 798 799 /* avoid re-using remote and pfmemalloc pages */ 800 if (!dev_page_is_reusable(page)) 801 return false; 802 803 #if (PAGE_SIZE < 8192) 804 /* if we are only owner of page we can reuse it */ 805 if (unlikely((rx_buf_pgcnt - pagecnt_bias) > 1)) 806 return false; 807 #else 808 #define ICE_LAST_OFFSET \ 809 (SKB_WITH_OVERHEAD(PAGE_SIZE) - ICE_RXBUF_2048) 810 if (rx_buf->page_offset > ICE_LAST_OFFSET) 811 return false; 812 #endif /* PAGE_SIZE < 8192) */ 813 814 /* If we have drained the page fragment pool we need to update 815 * the pagecnt_bias and page count so that we fully restock the 816 * number of references the driver holds. 817 */ 818 if (unlikely(pagecnt_bias == 1)) { 819 page_ref_add(page, USHRT_MAX - 1); 820 rx_buf->pagecnt_bias = USHRT_MAX; 821 } 822 823 return true; 824 } 825 826 /** 827 * ice_add_rx_frag - Add contents of Rx buffer to sk_buff as a frag 828 * @rx_ring: Rx descriptor ring to transact packets on 829 * @rx_buf: buffer containing page to add 830 * @skb: sk_buff to place the data into 831 * @size: packet length from rx_desc 832 * 833 * This function will add the data contained in rx_buf->page to the skb. 834 * It will just attach the page as a frag to the skb. 835 * The function will then update the page offset. 836 */ 837 static void 838 ice_add_rx_frag(struct ice_rx_ring *rx_ring, struct ice_rx_buf *rx_buf, 839 struct sk_buff *skb, unsigned int size) 840 { 841 #if (PAGE_SIZE >= 8192) 842 unsigned int truesize = SKB_DATA_ALIGN(size + rx_ring->rx_offset); 843 #else 844 unsigned int truesize = ice_rx_pg_size(rx_ring) / 2; 845 #endif 846 847 if (!size) 848 return; 849 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buf->page, 850 rx_buf->page_offset, size, truesize); 851 852 /* page is being used so we must update the page offset */ 853 ice_rx_buf_adjust_pg_offset(rx_buf, truesize); 854 } 855 856 /** 857 * ice_reuse_rx_page - page flip buffer and store it back on the ring 858 * @rx_ring: Rx descriptor ring to store buffers on 859 * @old_buf: donor buffer to have page reused 860 * 861 * Synchronizes page for reuse by the adapter 862 */ 863 static void 864 ice_reuse_rx_page(struct ice_rx_ring *rx_ring, struct ice_rx_buf *old_buf) 865 { 866 u16 nta = rx_ring->next_to_alloc; 867 struct ice_rx_buf *new_buf; 868 869 new_buf = &rx_ring->rx_buf[nta]; 870 871 /* update, and store next to alloc */ 872 nta++; 873 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 874 875 /* Transfer page from old buffer to new buffer. 876 * Move each member individually to avoid possible store 877 * forwarding stalls and unnecessary copy of skb. 878 */ 879 new_buf->dma = old_buf->dma; 880 new_buf->page = old_buf->page; 881 new_buf->page_offset = old_buf->page_offset; 882 new_buf->pagecnt_bias = old_buf->pagecnt_bias; 883 } 884 885 /** 886 * ice_get_rx_buf - Fetch Rx buffer and synchronize data for use 887 * @rx_ring: Rx descriptor ring to transact packets on 888 * @size: size of buffer to add to skb 889 * @rx_buf_pgcnt: rx_buf page refcount 890 * 891 * This function will pull an Rx buffer from the ring and synchronize it 892 * for use by the CPU. 893 */ 894 static struct ice_rx_buf * 895 ice_get_rx_buf(struct ice_rx_ring *rx_ring, const unsigned int size, 896 int *rx_buf_pgcnt) 897 { 898 struct ice_rx_buf *rx_buf; 899 900 rx_buf = &rx_ring->rx_buf[rx_ring->next_to_clean]; 901 *rx_buf_pgcnt = 902 #if (PAGE_SIZE < 8192) 903 page_count(rx_buf->page); 904 #else 905 0; 906 #endif 907 prefetchw(rx_buf->page); 908 909 if (!size) 910 return rx_buf; 911 /* we are reusing so sync this buffer for CPU use */ 912 dma_sync_single_range_for_cpu(rx_ring->dev, rx_buf->dma, 913 rx_buf->page_offset, size, 914 DMA_FROM_DEVICE); 915 916 /* We have pulled a buffer for use, so decrement pagecnt_bias */ 917 rx_buf->pagecnt_bias--; 918 919 return rx_buf; 920 } 921 922 /** 923 * ice_build_skb - Build skb around an existing buffer 924 * @rx_ring: Rx descriptor ring to transact packets on 925 * @rx_buf: Rx buffer to pull data from 926 * @xdp: xdp_buff pointing to the data 927 * 928 * This function builds an skb around an existing Rx buffer, taking care 929 * to set up the skb correctly and avoid any memcpy overhead. 930 */ 931 static struct sk_buff * 932 ice_build_skb(struct ice_rx_ring *rx_ring, struct ice_rx_buf *rx_buf, 933 struct xdp_buff *xdp) 934 { 935 u8 metasize = xdp->data - xdp->data_meta; 936 #if (PAGE_SIZE < 8192) 937 unsigned int truesize = ice_rx_pg_size(rx_ring) / 2; 938 #else 939 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) + 940 SKB_DATA_ALIGN(xdp->data_end - 941 xdp->data_hard_start); 942 #endif 943 struct sk_buff *skb; 944 945 /* Prefetch first cache line of first page. If xdp->data_meta 946 * is unused, this points exactly as xdp->data, otherwise we 947 * likely have a consumer accessing first few bytes of meta 948 * data, and then actual data. 949 */ 950 net_prefetch(xdp->data_meta); 951 /* build an skb around the page buffer */ 952 skb = napi_build_skb(xdp->data_hard_start, truesize); 953 if (unlikely(!skb)) 954 return NULL; 955 956 /* must to record Rx queue, otherwise OS features such as 957 * symmetric queue won't work 958 */ 959 skb_record_rx_queue(skb, rx_ring->q_index); 960 961 /* update pointers within the skb to store the data */ 962 skb_reserve(skb, xdp->data - xdp->data_hard_start); 963 __skb_put(skb, xdp->data_end - xdp->data); 964 if (metasize) 965 skb_metadata_set(skb, metasize); 966 967 /* buffer is used by skb, update page_offset */ 968 ice_rx_buf_adjust_pg_offset(rx_buf, truesize); 969 970 return skb; 971 } 972 973 /** 974 * ice_construct_skb - Allocate skb and populate it 975 * @rx_ring: Rx descriptor ring to transact packets on 976 * @rx_buf: Rx buffer to pull data from 977 * @xdp: xdp_buff pointing to the data 978 * 979 * This function allocates an skb. It then populates it with the page 980 * data from the current receive descriptor, taking care to set up the 981 * skb correctly. 982 */ 983 static struct sk_buff * 984 ice_construct_skb(struct ice_rx_ring *rx_ring, struct ice_rx_buf *rx_buf, 985 struct xdp_buff *xdp) 986 { 987 unsigned int metasize = xdp->data - xdp->data_meta; 988 unsigned int size = xdp->data_end - xdp->data; 989 unsigned int headlen; 990 struct sk_buff *skb; 991 992 /* prefetch first cache line of first page */ 993 net_prefetch(xdp->data_meta); 994 995 /* allocate a skb to store the frags */ 996 skb = __napi_alloc_skb(&rx_ring->q_vector->napi, 997 ICE_RX_HDR_SIZE + metasize, 998 GFP_ATOMIC | __GFP_NOWARN); 999 if (unlikely(!skb)) 1000 return NULL; 1001 1002 skb_record_rx_queue(skb, rx_ring->q_index); 1003 /* Determine available headroom for copy */ 1004 headlen = size; 1005 if (headlen > ICE_RX_HDR_SIZE) 1006 headlen = eth_get_headlen(skb->dev, xdp->data, ICE_RX_HDR_SIZE); 1007 1008 /* align pull length to size of long to optimize memcpy performance */ 1009 memcpy(__skb_put(skb, headlen + metasize), xdp->data_meta, 1010 ALIGN(headlen + metasize, sizeof(long))); 1011 1012 if (metasize) { 1013 skb_metadata_set(skb, metasize); 1014 __skb_pull(skb, metasize); 1015 } 1016 1017 /* if we exhaust the linear part then add what is left as a frag */ 1018 size -= headlen; 1019 if (size) { 1020 #if (PAGE_SIZE >= 8192) 1021 unsigned int truesize = SKB_DATA_ALIGN(size); 1022 #else 1023 unsigned int truesize = ice_rx_pg_size(rx_ring) / 2; 1024 #endif 1025 skb_add_rx_frag(skb, 0, rx_buf->page, 1026 rx_buf->page_offset + headlen, size, truesize); 1027 /* buffer is used by skb, update page_offset */ 1028 ice_rx_buf_adjust_pg_offset(rx_buf, truesize); 1029 } else { 1030 /* buffer is unused, reset bias back to rx_buf; data was copied 1031 * onto skb's linear part so there's no need for adjusting 1032 * page offset and we can reuse this buffer as-is 1033 */ 1034 rx_buf->pagecnt_bias++; 1035 } 1036 1037 return skb; 1038 } 1039 1040 /** 1041 * ice_put_rx_buf - Clean up used buffer and either recycle or free 1042 * @rx_ring: Rx descriptor ring to transact packets on 1043 * @rx_buf: Rx buffer to pull data from 1044 * @rx_buf_pgcnt: Rx buffer page count pre xdp_do_redirect() 1045 * 1046 * This function will update next_to_clean and then clean up the contents 1047 * of the rx_buf. It will either recycle the buffer or unmap it and free 1048 * the associated resources. 1049 */ 1050 static void 1051 ice_put_rx_buf(struct ice_rx_ring *rx_ring, struct ice_rx_buf *rx_buf, 1052 int rx_buf_pgcnt) 1053 { 1054 u16 ntc = rx_ring->next_to_clean + 1; 1055 1056 /* fetch, update, and store next to clean */ 1057 ntc = (ntc < rx_ring->count) ? ntc : 0; 1058 rx_ring->next_to_clean = ntc; 1059 1060 if (!rx_buf) 1061 return; 1062 1063 if (ice_can_reuse_rx_page(rx_buf, rx_buf_pgcnt)) { 1064 /* hand second half of page back to the ring */ 1065 ice_reuse_rx_page(rx_ring, rx_buf); 1066 } else { 1067 /* we are not reusing the buffer so unmap it */ 1068 dma_unmap_page_attrs(rx_ring->dev, rx_buf->dma, 1069 ice_rx_pg_size(rx_ring), DMA_FROM_DEVICE, 1070 ICE_RX_DMA_ATTR); 1071 __page_frag_cache_drain(rx_buf->page, rx_buf->pagecnt_bias); 1072 } 1073 1074 /* clear contents of buffer_info */ 1075 rx_buf->page = NULL; 1076 } 1077 1078 /** 1079 * ice_is_non_eop - process handling of non-EOP buffers 1080 * @rx_ring: Rx ring being processed 1081 * @rx_desc: Rx descriptor for current buffer 1082 * 1083 * If the buffer is an EOP buffer, this function exits returning false, 1084 * otherwise return true indicating that this is in fact a non-EOP buffer. 1085 */ 1086 static bool 1087 ice_is_non_eop(struct ice_rx_ring *rx_ring, union ice_32b_rx_flex_desc *rx_desc) 1088 { 1089 /* if we are the last buffer then there is nothing else to do */ 1090 #define ICE_RXD_EOF BIT(ICE_RX_FLEX_DESC_STATUS0_EOF_S) 1091 if (likely(ice_test_staterr(rx_desc->wb.status_error0, ICE_RXD_EOF))) 1092 return false; 1093 1094 rx_ring->rx_stats.non_eop_descs++; 1095 1096 return true; 1097 } 1098 1099 /** 1100 * ice_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf 1101 * @rx_ring: Rx descriptor ring to transact packets on 1102 * @budget: Total limit on number of packets to process 1103 * 1104 * This function provides a "bounce buffer" approach to Rx interrupt 1105 * processing. The advantage to this is that on systems that have 1106 * expensive overhead for IOMMU access this provides a means of avoiding 1107 * it by maintaining the mapping of the page to the system. 1108 * 1109 * Returns amount of work completed 1110 */ 1111 int ice_clean_rx_irq(struct ice_rx_ring *rx_ring, int budget) 1112 { 1113 unsigned int total_rx_bytes = 0, total_rx_pkts = 0, frame_sz = 0; 1114 u16 cleaned_count = ICE_DESC_UNUSED(rx_ring); 1115 unsigned int offset = rx_ring->rx_offset; 1116 struct ice_tx_ring *xdp_ring = NULL; 1117 unsigned int xdp_res, xdp_xmit = 0; 1118 struct sk_buff *skb = rx_ring->skb; 1119 struct bpf_prog *xdp_prog = NULL; 1120 struct xdp_buff xdp; 1121 bool failure; 1122 1123 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */ 1124 #if (PAGE_SIZE < 8192) 1125 frame_sz = ice_rx_frame_truesize(rx_ring, 0); 1126 #endif 1127 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq); 1128 1129 xdp_prog = READ_ONCE(rx_ring->xdp_prog); 1130 if (xdp_prog) 1131 xdp_ring = rx_ring->xdp_ring; 1132 1133 /* start the loop to process Rx packets bounded by 'budget' */ 1134 while (likely(total_rx_pkts < (unsigned int)budget)) { 1135 union ice_32b_rx_flex_desc *rx_desc; 1136 struct ice_rx_buf *rx_buf; 1137 unsigned char *hard_start; 1138 unsigned int size; 1139 u16 stat_err_bits; 1140 int rx_buf_pgcnt; 1141 u16 vlan_tag = 0; 1142 u16 rx_ptype; 1143 1144 /* get the Rx desc from Rx ring based on 'next_to_clean' */ 1145 rx_desc = ICE_RX_DESC(rx_ring, rx_ring->next_to_clean); 1146 1147 /* status_error_len will always be zero for unused descriptors 1148 * because it's cleared in cleanup, and overlaps with hdr_addr 1149 * which is always zero because packet split isn't used, if the 1150 * hardware wrote DD then it will be non-zero 1151 */ 1152 stat_err_bits = BIT(ICE_RX_FLEX_DESC_STATUS0_DD_S); 1153 if (!ice_test_staterr(rx_desc->wb.status_error0, stat_err_bits)) 1154 break; 1155 1156 /* This memory barrier is needed to keep us from reading 1157 * any other fields out of the rx_desc until we know the 1158 * DD bit is set. 1159 */ 1160 dma_rmb(); 1161 1162 ice_trace(clean_rx_irq, rx_ring, rx_desc); 1163 if (rx_desc->wb.rxdid == FDIR_DESC_RXDID || !rx_ring->netdev) { 1164 struct ice_vsi *ctrl_vsi = rx_ring->vsi; 1165 1166 if (rx_desc->wb.rxdid == FDIR_DESC_RXDID && 1167 ctrl_vsi->vf) 1168 ice_vc_fdir_irq_handler(ctrl_vsi, rx_desc); 1169 ice_put_rx_buf(rx_ring, NULL, 0); 1170 cleaned_count++; 1171 continue; 1172 } 1173 1174 size = le16_to_cpu(rx_desc->wb.pkt_len) & 1175 ICE_RX_FLX_DESC_PKT_LEN_M; 1176 1177 /* retrieve a buffer from the ring */ 1178 rx_buf = ice_get_rx_buf(rx_ring, size, &rx_buf_pgcnt); 1179 1180 if (!size) { 1181 xdp.data = NULL; 1182 xdp.data_end = NULL; 1183 xdp.data_hard_start = NULL; 1184 xdp.data_meta = NULL; 1185 goto construct_skb; 1186 } 1187 1188 hard_start = page_address(rx_buf->page) + rx_buf->page_offset - 1189 offset; 1190 xdp_prepare_buff(&xdp, hard_start, offset, size, true); 1191 #if (PAGE_SIZE > 4096) 1192 /* At larger PAGE_SIZE, frame_sz depend on len size */ 1193 xdp.frame_sz = ice_rx_frame_truesize(rx_ring, size); 1194 #endif 1195 1196 if (!xdp_prog) 1197 goto construct_skb; 1198 1199 xdp_res = ice_run_xdp(rx_ring, &xdp, xdp_prog, xdp_ring); 1200 if (!xdp_res) 1201 goto construct_skb; 1202 if (xdp_res & (ICE_XDP_TX | ICE_XDP_REDIR)) { 1203 xdp_xmit |= xdp_res; 1204 ice_rx_buf_adjust_pg_offset(rx_buf, xdp.frame_sz); 1205 } else { 1206 rx_buf->pagecnt_bias++; 1207 } 1208 total_rx_bytes += size; 1209 total_rx_pkts++; 1210 1211 cleaned_count++; 1212 ice_put_rx_buf(rx_ring, rx_buf, rx_buf_pgcnt); 1213 continue; 1214 construct_skb: 1215 if (skb) { 1216 ice_add_rx_frag(rx_ring, rx_buf, skb, size); 1217 } else if (likely(xdp.data)) { 1218 if (ice_ring_uses_build_skb(rx_ring)) 1219 skb = ice_build_skb(rx_ring, rx_buf, &xdp); 1220 else 1221 skb = ice_construct_skb(rx_ring, rx_buf, &xdp); 1222 } 1223 /* exit if we failed to retrieve a buffer */ 1224 if (!skb) { 1225 rx_ring->rx_stats.alloc_buf_failed++; 1226 if (rx_buf) 1227 rx_buf->pagecnt_bias++; 1228 break; 1229 } 1230 1231 ice_put_rx_buf(rx_ring, rx_buf, rx_buf_pgcnt); 1232 cleaned_count++; 1233 1234 /* skip if it is NOP desc */ 1235 if (ice_is_non_eop(rx_ring, rx_desc)) 1236 continue; 1237 1238 stat_err_bits = BIT(ICE_RX_FLEX_DESC_STATUS0_RXE_S); 1239 if (unlikely(ice_test_staterr(rx_desc->wb.status_error0, 1240 stat_err_bits))) { 1241 dev_kfree_skb_any(skb); 1242 continue; 1243 } 1244 1245 vlan_tag = ice_get_vlan_tag_from_rx_desc(rx_desc); 1246 1247 /* pad the skb if needed, to make a valid ethernet frame */ 1248 if (eth_skb_pad(skb)) { 1249 skb = NULL; 1250 continue; 1251 } 1252 1253 /* probably a little skewed due to removing CRC */ 1254 total_rx_bytes += skb->len; 1255 1256 /* populate checksum, VLAN, and protocol */ 1257 rx_ptype = le16_to_cpu(rx_desc->wb.ptype_flex_flags0) & 1258 ICE_RX_FLEX_DESC_PTYPE_M; 1259 1260 ice_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype); 1261 1262 ice_trace(clean_rx_irq_indicate, rx_ring, rx_desc, skb); 1263 /* send completed skb up the stack */ 1264 ice_receive_skb(rx_ring, skb, vlan_tag); 1265 skb = NULL; 1266 1267 /* update budget accounting */ 1268 total_rx_pkts++; 1269 } 1270 1271 /* return up to cleaned_count buffers to hardware */ 1272 failure = ice_alloc_rx_bufs(rx_ring, cleaned_count); 1273 1274 if (xdp_prog) 1275 ice_finalize_xdp_rx(xdp_ring, xdp_xmit); 1276 rx_ring->skb = skb; 1277 1278 ice_update_rx_ring_stats(rx_ring, total_rx_pkts, total_rx_bytes); 1279 1280 /* guarantee a trip back through this routine if there was a failure */ 1281 return failure ? budget : (int)total_rx_pkts; 1282 } 1283 1284 static void __ice_update_sample(struct ice_q_vector *q_vector, 1285 struct ice_ring_container *rc, 1286 struct dim_sample *sample, 1287 bool is_tx) 1288 { 1289 u64 packets = 0, bytes = 0; 1290 1291 if (is_tx) { 1292 struct ice_tx_ring *tx_ring; 1293 1294 ice_for_each_tx_ring(tx_ring, *rc) { 1295 packets += tx_ring->stats.pkts; 1296 bytes += tx_ring->stats.bytes; 1297 } 1298 } else { 1299 struct ice_rx_ring *rx_ring; 1300 1301 ice_for_each_rx_ring(rx_ring, *rc) { 1302 packets += rx_ring->stats.pkts; 1303 bytes += rx_ring->stats.bytes; 1304 } 1305 } 1306 1307 dim_update_sample(q_vector->total_events, packets, bytes, sample); 1308 sample->comp_ctr = 0; 1309 1310 /* if dim settings get stale, like when not updated for 1 1311 * second or longer, force it to start again. This addresses the 1312 * frequent case of an idle queue being switched to by the 1313 * scheduler. The 1,000 here means 1,000 milliseconds. 1314 */ 1315 if (ktime_ms_delta(sample->time, rc->dim.start_sample.time) >= 1000) 1316 rc->dim.state = DIM_START_MEASURE; 1317 } 1318 1319 /** 1320 * ice_net_dim - Update net DIM algorithm 1321 * @q_vector: the vector associated with the interrupt 1322 * 1323 * Create a DIM sample and notify net_dim() so that it can possibly decide 1324 * a new ITR value based on incoming packets, bytes, and interrupts. 1325 * 1326 * This function is a no-op if the ring is not configured to dynamic ITR. 1327 */ 1328 static void ice_net_dim(struct ice_q_vector *q_vector) 1329 { 1330 struct ice_ring_container *tx = &q_vector->tx; 1331 struct ice_ring_container *rx = &q_vector->rx; 1332 1333 if (ITR_IS_DYNAMIC(tx)) { 1334 struct dim_sample dim_sample; 1335 1336 __ice_update_sample(q_vector, tx, &dim_sample, true); 1337 net_dim(&tx->dim, dim_sample); 1338 } 1339 1340 if (ITR_IS_DYNAMIC(rx)) { 1341 struct dim_sample dim_sample; 1342 1343 __ice_update_sample(q_vector, rx, &dim_sample, false); 1344 net_dim(&rx->dim, dim_sample); 1345 } 1346 } 1347 1348 /** 1349 * ice_buildreg_itr - build value for writing to the GLINT_DYN_CTL register 1350 * @itr_idx: interrupt throttling index 1351 * @itr: interrupt throttling value in usecs 1352 */ 1353 static u32 ice_buildreg_itr(u16 itr_idx, u16 itr) 1354 { 1355 /* The ITR value is reported in microseconds, and the register value is 1356 * recorded in 2 microsecond units. For this reason we only need to 1357 * shift by the GLINT_DYN_CTL_INTERVAL_S - ICE_ITR_GRAN_S to apply this 1358 * granularity as a shift instead of division. The mask makes sure the 1359 * ITR value is never odd so we don't accidentally write into the field 1360 * prior to the ITR field. 1361 */ 1362 itr &= ICE_ITR_MASK; 1363 1364 return GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M | 1365 (itr_idx << GLINT_DYN_CTL_ITR_INDX_S) | 1366 (itr << (GLINT_DYN_CTL_INTERVAL_S - ICE_ITR_GRAN_S)); 1367 } 1368 1369 /** 1370 * ice_enable_interrupt - re-enable MSI-X interrupt 1371 * @q_vector: the vector associated with the interrupt to enable 1372 * 1373 * If the VSI is down, the interrupt will not be re-enabled. Also, 1374 * when enabling the interrupt always reset the wb_on_itr to false 1375 * and trigger a software interrupt to clean out internal state. 1376 */ 1377 static void ice_enable_interrupt(struct ice_q_vector *q_vector) 1378 { 1379 struct ice_vsi *vsi = q_vector->vsi; 1380 bool wb_en = q_vector->wb_on_itr; 1381 u32 itr_val; 1382 1383 if (test_bit(ICE_DOWN, vsi->state)) 1384 return; 1385 1386 /* trigger an ITR delayed software interrupt when exiting busy poll, to 1387 * make sure to catch any pending cleanups that might have been missed 1388 * due to interrupt state transition. If busy poll or poll isn't 1389 * enabled, then don't update ITR, and just enable the interrupt. 1390 */ 1391 if (!wb_en) { 1392 itr_val = ice_buildreg_itr(ICE_ITR_NONE, 0); 1393 } else { 1394 q_vector->wb_on_itr = false; 1395 1396 /* do two things here with a single write. Set up the third ITR 1397 * index to be used for software interrupt moderation, and then 1398 * trigger a software interrupt with a rate limit of 20K on 1399 * software interrupts, this will help avoid high interrupt 1400 * loads due to frequently polling and exiting polling. 1401 */ 1402 itr_val = ice_buildreg_itr(ICE_IDX_ITR2, ICE_ITR_20K); 1403 itr_val |= GLINT_DYN_CTL_SWINT_TRIG_M | 1404 ICE_IDX_ITR2 << GLINT_DYN_CTL_SW_ITR_INDX_S | 1405 GLINT_DYN_CTL_SW_ITR_INDX_ENA_M; 1406 } 1407 wr32(&vsi->back->hw, GLINT_DYN_CTL(q_vector->reg_idx), itr_val); 1408 } 1409 1410 /** 1411 * ice_set_wb_on_itr - set WB_ON_ITR for this q_vector 1412 * @q_vector: q_vector to set WB_ON_ITR on 1413 * 1414 * We need to tell hardware to write-back completed descriptors even when 1415 * interrupts are disabled. Descriptors will be written back on cache line 1416 * boundaries without WB_ON_ITR enabled, but if we don't enable WB_ON_ITR 1417 * descriptors may not be written back if they don't fill a cache line until 1418 * the next interrupt. 1419 * 1420 * This sets the write-back frequency to whatever was set previously for the 1421 * ITR indices. Also, set the INTENA_MSK bit to make sure hardware knows we 1422 * aren't meddling with the INTENA_M bit. 1423 */ 1424 static void ice_set_wb_on_itr(struct ice_q_vector *q_vector) 1425 { 1426 struct ice_vsi *vsi = q_vector->vsi; 1427 1428 /* already in wb_on_itr mode no need to change it */ 1429 if (q_vector->wb_on_itr) 1430 return; 1431 1432 /* use previously set ITR values for all of the ITR indices by 1433 * specifying ICE_ITR_NONE, which will vary in adaptive (AIM) mode and 1434 * be static in non-adaptive mode (user configured) 1435 */ 1436 wr32(&vsi->back->hw, GLINT_DYN_CTL(q_vector->reg_idx), 1437 ((ICE_ITR_NONE << GLINT_DYN_CTL_ITR_INDX_S) & 1438 GLINT_DYN_CTL_ITR_INDX_M) | GLINT_DYN_CTL_INTENA_MSK_M | 1439 GLINT_DYN_CTL_WB_ON_ITR_M); 1440 1441 q_vector->wb_on_itr = true; 1442 } 1443 1444 /** 1445 * ice_napi_poll - NAPI polling Rx/Tx cleanup routine 1446 * @napi: napi struct with our devices info in it 1447 * @budget: amount of work driver is allowed to do this pass, in packets 1448 * 1449 * This function will clean all queues associated with a q_vector. 1450 * 1451 * Returns the amount of work done 1452 */ 1453 int ice_napi_poll(struct napi_struct *napi, int budget) 1454 { 1455 struct ice_q_vector *q_vector = 1456 container_of(napi, struct ice_q_vector, napi); 1457 struct ice_tx_ring *tx_ring; 1458 struct ice_rx_ring *rx_ring; 1459 bool clean_complete = true; 1460 int budget_per_ring; 1461 int work_done = 0; 1462 1463 /* Since the actual Tx work is minimal, we can give the Tx a larger 1464 * budget and be more aggressive about cleaning up the Tx descriptors. 1465 */ 1466 ice_for_each_tx_ring(tx_ring, q_vector->tx) { 1467 bool wd; 1468 1469 if (tx_ring->xsk_pool) 1470 wd = ice_xmit_zc(tx_ring); 1471 else if (ice_ring_is_xdp(tx_ring)) 1472 wd = true; 1473 else 1474 wd = ice_clean_tx_irq(tx_ring, budget); 1475 1476 if (!wd) 1477 clean_complete = false; 1478 } 1479 1480 /* Handle case where we are called by netpoll with a budget of 0 */ 1481 if (unlikely(budget <= 0)) 1482 return budget; 1483 1484 /* normally we have 1 Rx ring per q_vector */ 1485 if (unlikely(q_vector->num_ring_rx > 1)) 1486 /* We attempt to distribute budget to each Rx queue fairly, but 1487 * don't allow the budget to go below 1 because that would exit 1488 * polling early. 1489 */ 1490 budget_per_ring = max_t(int, budget / q_vector->num_ring_rx, 1); 1491 else 1492 /* Max of 1 Rx ring in this q_vector so give it the budget */ 1493 budget_per_ring = budget; 1494 1495 ice_for_each_rx_ring(rx_ring, q_vector->rx) { 1496 int cleaned; 1497 1498 /* A dedicated path for zero-copy allows making a single 1499 * comparison in the irq context instead of many inside the 1500 * ice_clean_rx_irq function and makes the codebase cleaner. 1501 */ 1502 cleaned = rx_ring->xsk_pool ? 1503 ice_clean_rx_irq_zc(rx_ring, budget_per_ring) : 1504 ice_clean_rx_irq(rx_ring, budget_per_ring); 1505 work_done += cleaned; 1506 /* if we clean as many as budgeted, we must not be done */ 1507 if (cleaned >= budget_per_ring) 1508 clean_complete = false; 1509 } 1510 1511 /* If work not completed, return budget and polling will return */ 1512 if (!clean_complete) { 1513 /* Set the writeback on ITR so partial completions of 1514 * cache-lines will still continue even if we're polling. 1515 */ 1516 ice_set_wb_on_itr(q_vector); 1517 return budget; 1518 } 1519 1520 /* Exit the polling mode, but don't re-enable interrupts if stack might 1521 * poll us due to busy-polling 1522 */ 1523 if (napi_complete_done(napi, work_done)) { 1524 ice_net_dim(q_vector); 1525 ice_enable_interrupt(q_vector); 1526 } else { 1527 ice_set_wb_on_itr(q_vector); 1528 } 1529 1530 return min_t(int, work_done, budget - 1); 1531 } 1532 1533 /** 1534 * __ice_maybe_stop_tx - 2nd level check for Tx stop conditions 1535 * @tx_ring: the ring to be checked 1536 * @size: the size buffer we want to assure is available 1537 * 1538 * Returns -EBUSY if a stop is needed, else 0 1539 */ 1540 static int __ice_maybe_stop_tx(struct ice_tx_ring *tx_ring, unsigned int size) 1541 { 1542 netif_tx_stop_queue(txring_txq(tx_ring)); 1543 /* Memory barrier before checking head and tail */ 1544 smp_mb(); 1545 1546 /* Check again in a case another CPU has just made room available. */ 1547 if (likely(ICE_DESC_UNUSED(tx_ring) < size)) 1548 return -EBUSY; 1549 1550 /* A reprieve! - use start_queue because it doesn't call schedule */ 1551 netif_tx_start_queue(txring_txq(tx_ring)); 1552 ++tx_ring->tx_stats.restart_q; 1553 return 0; 1554 } 1555 1556 /** 1557 * ice_maybe_stop_tx - 1st level check for Tx stop conditions 1558 * @tx_ring: the ring to be checked 1559 * @size: the size buffer we want to assure is available 1560 * 1561 * Returns 0 if stop is not needed 1562 */ 1563 static int ice_maybe_stop_tx(struct ice_tx_ring *tx_ring, unsigned int size) 1564 { 1565 if (likely(ICE_DESC_UNUSED(tx_ring) >= size)) 1566 return 0; 1567 1568 return __ice_maybe_stop_tx(tx_ring, size); 1569 } 1570 1571 /** 1572 * ice_tx_map - Build the Tx descriptor 1573 * @tx_ring: ring to send buffer on 1574 * @first: first buffer info buffer to use 1575 * @off: pointer to struct that holds offload parameters 1576 * 1577 * This function loops over the skb data pointed to by *first 1578 * and gets a physical address for each memory location and programs 1579 * it and the length into the transmit descriptor. 1580 */ 1581 static void 1582 ice_tx_map(struct ice_tx_ring *tx_ring, struct ice_tx_buf *first, 1583 struct ice_tx_offload_params *off) 1584 { 1585 u64 td_offset, td_tag, td_cmd; 1586 u16 i = tx_ring->next_to_use; 1587 unsigned int data_len, size; 1588 struct ice_tx_desc *tx_desc; 1589 struct ice_tx_buf *tx_buf; 1590 struct sk_buff *skb; 1591 skb_frag_t *frag; 1592 dma_addr_t dma; 1593 bool kick; 1594 1595 td_tag = off->td_l2tag1; 1596 td_cmd = off->td_cmd; 1597 td_offset = off->td_offset; 1598 skb = first->skb; 1599 1600 data_len = skb->data_len; 1601 size = skb_headlen(skb); 1602 1603 tx_desc = ICE_TX_DESC(tx_ring, i); 1604 1605 if (first->tx_flags & ICE_TX_FLAGS_HW_VLAN) { 1606 td_cmd |= (u64)ICE_TX_DESC_CMD_IL2TAG1; 1607 td_tag = (first->tx_flags & ICE_TX_FLAGS_VLAN_M) >> 1608 ICE_TX_FLAGS_VLAN_S; 1609 } 1610 1611 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 1612 1613 tx_buf = first; 1614 1615 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 1616 unsigned int max_data = ICE_MAX_DATA_PER_TXD_ALIGNED; 1617 1618 if (dma_mapping_error(tx_ring->dev, dma)) 1619 goto dma_error; 1620 1621 /* record length, and DMA address */ 1622 dma_unmap_len_set(tx_buf, len, size); 1623 dma_unmap_addr_set(tx_buf, dma, dma); 1624 1625 /* align size to end of page */ 1626 max_data += -dma & (ICE_MAX_READ_REQ_SIZE - 1); 1627 tx_desc->buf_addr = cpu_to_le64(dma); 1628 1629 /* account for data chunks larger than the hardware 1630 * can handle 1631 */ 1632 while (unlikely(size > ICE_MAX_DATA_PER_TXD)) { 1633 tx_desc->cmd_type_offset_bsz = 1634 ice_build_ctob(td_cmd, td_offset, max_data, 1635 td_tag); 1636 1637 tx_desc++; 1638 i++; 1639 1640 if (i == tx_ring->count) { 1641 tx_desc = ICE_TX_DESC(tx_ring, 0); 1642 i = 0; 1643 } 1644 1645 dma += max_data; 1646 size -= max_data; 1647 1648 max_data = ICE_MAX_DATA_PER_TXD_ALIGNED; 1649 tx_desc->buf_addr = cpu_to_le64(dma); 1650 } 1651 1652 if (likely(!data_len)) 1653 break; 1654 1655 tx_desc->cmd_type_offset_bsz = ice_build_ctob(td_cmd, td_offset, 1656 size, td_tag); 1657 1658 tx_desc++; 1659 i++; 1660 1661 if (i == tx_ring->count) { 1662 tx_desc = ICE_TX_DESC(tx_ring, 0); 1663 i = 0; 1664 } 1665 1666 size = skb_frag_size(frag); 1667 data_len -= size; 1668 1669 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, 1670 DMA_TO_DEVICE); 1671 1672 tx_buf = &tx_ring->tx_buf[i]; 1673 } 1674 1675 /* record SW timestamp if HW timestamp is not available */ 1676 skb_tx_timestamp(first->skb); 1677 1678 i++; 1679 if (i == tx_ring->count) 1680 i = 0; 1681 1682 /* write last descriptor with RS and EOP bits */ 1683 td_cmd |= (u64)ICE_TXD_LAST_DESC_CMD; 1684 tx_desc->cmd_type_offset_bsz = 1685 ice_build_ctob(td_cmd, td_offset, size, td_tag); 1686 1687 /* Force memory writes to complete before letting h/w know there 1688 * are new descriptors to fetch. 1689 * 1690 * We also use this memory barrier to make certain all of the 1691 * status bits have been updated before next_to_watch is written. 1692 */ 1693 wmb(); 1694 1695 /* set next_to_watch value indicating a packet is present */ 1696 first->next_to_watch = tx_desc; 1697 1698 tx_ring->next_to_use = i; 1699 1700 ice_maybe_stop_tx(tx_ring, DESC_NEEDED); 1701 1702 /* notify HW of packet */ 1703 kick = __netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount, 1704 netdev_xmit_more()); 1705 if (kick) 1706 /* notify HW of packet */ 1707 writel(i, tx_ring->tail); 1708 1709 return; 1710 1711 dma_error: 1712 /* clear DMA mappings for failed tx_buf map */ 1713 for (;;) { 1714 tx_buf = &tx_ring->tx_buf[i]; 1715 ice_unmap_and_free_tx_buf(tx_ring, tx_buf); 1716 if (tx_buf == first) 1717 break; 1718 if (i == 0) 1719 i = tx_ring->count; 1720 i--; 1721 } 1722 1723 tx_ring->next_to_use = i; 1724 } 1725 1726 /** 1727 * ice_tx_csum - Enable Tx checksum offloads 1728 * @first: pointer to the first descriptor 1729 * @off: pointer to struct that holds offload parameters 1730 * 1731 * Returns 0 or error (negative) if checksum offload can't happen, 1 otherwise. 1732 */ 1733 static 1734 int ice_tx_csum(struct ice_tx_buf *first, struct ice_tx_offload_params *off) 1735 { 1736 u32 l4_len = 0, l3_len = 0, l2_len = 0; 1737 struct sk_buff *skb = first->skb; 1738 union { 1739 struct iphdr *v4; 1740 struct ipv6hdr *v6; 1741 unsigned char *hdr; 1742 } ip; 1743 union { 1744 struct tcphdr *tcp; 1745 unsigned char *hdr; 1746 } l4; 1747 __be16 frag_off, protocol; 1748 unsigned char *exthdr; 1749 u32 offset, cmd = 0; 1750 u8 l4_proto = 0; 1751 1752 if (skb->ip_summed != CHECKSUM_PARTIAL) 1753 return 0; 1754 1755 protocol = vlan_get_protocol(skb); 1756 1757 if (eth_p_mpls(protocol)) { 1758 ip.hdr = skb_inner_network_header(skb); 1759 l4.hdr = skb_checksum_start(skb); 1760 } else { 1761 ip.hdr = skb_network_header(skb); 1762 l4.hdr = skb_transport_header(skb); 1763 } 1764 1765 /* compute outer L2 header size */ 1766 l2_len = ip.hdr - skb->data; 1767 offset = (l2_len / 2) << ICE_TX_DESC_LEN_MACLEN_S; 1768 1769 /* set the tx_flags to indicate the IP protocol type. this is 1770 * required so that checksum header computation below is accurate. 1771 */ 1772 if (ip.v4->version == 4) 1773 first->tx_flags |= ICE_TX_FLAGS_IPV4; 1774 else if (ip.v6->version == 6) 1775 first->tx_flags |= ICE_TX_FLAGS_IPV6; 1776 1777 if (skb->encapsulation) { 1778 bool gso_ena = false; 1779 u32 tunnel = 0; 1780 1781 /* define outer network header type */ 1782 if (first->tx_flags & ICE_TX_FLAGS_IPV4) { 1783 tunnel |= (first->tx_flags & ICE_TX_FLAGS_TSO) ? 1784 ICE_TX_CTX_EIPT_IPV4 : 1785 ICE_TX_CTX_EIPT_IPV4_NO_CSUM; 1786 l4_proto = ip.v4->protocol; 1787 } else if (first->tx_flags & ICE_TX_FLAGS_IPV6) { 1788 int ret; 1789 1790 tunnel |= ICE_TX_CTX_EIPT_IPV6; 1791 exthdr = ip.hdr + sizeof(*ip.v6); 1792 l4_proto = ip.v6->nexthdr; 1793 ret = ipv6_skip_exthdr(skb, exthdr - skb->data, 1794 &l4_proto, &frag_off); 1795 if (ret < 0) 1796 return -1; 1797 } 1798 1799 /* define outer transport */ 1800 switch (l4_proto) { 1801 case IPPROTO_UDP: 1802 tunnel |= ICE_TXD_CTX_UDP_TUNNELING; 1803 first->tx_flags |= ICE_TX_FLAGS_TUNNEL; 1804 break; 1805 case IPPROTO_GRE: 1806 tunnel |= ICE_TXD_CTX_GRE_TUNNELING; 1807 first->tx_flags |= ICE_TX_FLAGS_TUNNEL; 1808 break; 1809 case IPPROTO_IPIP: 1810 case IPPROTO_IPV6: 1811 first->tx_flags |= ICE_TX_FLAGS_TUNNEL; 1812 l4.hdr = skb_inner_network_header(skb); 1813 break; 1814 default: 1815 if (first->tx_flags & ICE_TX_FLAGS_TSO) 1816 return -1; 1817 1818 skb_checksum_help(skb); 1819 return 0; 1820 } 1821 1822 /* compute outer L3 header size */ 1823 tunnel |= ((l4.hdr - ip.hdr) / 4) << 1824 ICE_TXD_CTX_QW0_EIPLEN_S; 1825 1826 /* switch IP header pointer from outer to inner header */ 1827 ip.hdr = skb_inner_network_header(skb); 1828 1829 /* compute tunnel header size */ 1830 tunnel |= ((ip.hdr - l4.hdr) / 2) << 1831 ICE_TXD_CTX_QW0_NATLEN_S; 1832 1833 gso_ena = skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL; 1834 /* indicate if we need to offload outer UDP header */ 1835 if ((first->tx_flags & ICE_TX_FLAGS_TSO) && !gso_ena && 1836 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) 1837 tunnel |= ICE_TXD_CTX_QW0_L4T_CS_M; 1838 1839 /* record tunnel offload values */ 1840 off->cd_tunnel_params |= tunnel; 1841 1842 /* set DTYP=1 to indicate that it's an Tx context descriptor 1843 * in IPsec tunnel mode with Tx offloads in Quad word 1 1844 */ 1845 off->cd_qw1 |= (u64)ICE_TX_DESC_DTYPE_CTX; 1846 1847 /* switch L4 header pointer from outer to inner */ 1848 l4.hdr = skb_inner_transport_header(skb); 1849 l4_proto = 0; 1850 1851 /* reset type as we transition from outer to inner headers */ 1852 first->tx_flags &= ~(ICE_TX_FLAGS_IPV4 | ICE_TX_FLAGS_IPV6); 1853 if (ip.v4->version == 4) 1854 first->tx_flags |= ICE_TX_FLAGS_IPV4; 1855 if (ip.v6->version == 6) 1856 first->tx_flags |= ICE_TX_FLAGS_IPV6; 1857 } 1858 1859 /* Enable IP checksum offloads */ 1860 if (first->tx_flags & ICE_TX_FLAGS_IPV4) { 1861 l4_proto = ip.v4->protocol; 1862 /* the stack computes the IP header already, the only time we 1863 * need the hardware to recompute it is in the case of TSO. 1864 */ 1865 if (first->tx_flags & ICE_TX_FLAGS_TSO) 1866 cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM; 1867 else 1868 cmd |= ICE_TX_DESC_CMD_IIPT_IPV4; 1869 1870 } else if (first->tx_flags & ICE_TX_FLAGS_IPV6) { 1871 cmd |= ICE_TX_DESC_CMD_IIPT_IPV6; 1872 exthdr = ip.hdr + sizeof(*ip.v6); 1873 l4_proto = ip.v6->nexthdr; 1874 if (l4.hdr != exthdr) 1875 ipv6_skip_exthdr(skb, exthdr - skb->data, &l4_proto, 1876 &frag_off); 1877 } else { 1878 return -1; 1879 } 1880 1881 /* compute inner L3 header size */ 1882 l3_len = l4.hdr - ip.hdr; 1883 offset |= (l3_len / 4) << ICE_TX_DESC_LEN_IPLEN_S; 1884 1885 /* Enable L4 checksum offloads */ 1886 switch (l4_proto) { 1887 case IPPROTO_TCP: 1888 /* enable checksum offloads */ 1889 cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP; 1890 l4_len = l4.tcp->doff; 1891 offset |= l4_len << ICE_TX_DESC_LEN_L4_LEN_S; 1892 break; 1893 case IPPROTO_UDP: 1894 /* enable UDP checksum offload */ 1895 cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP; 1896 l4_len = (sizeof(struct udphdr) >> 2); 1897 offset |= l4_len << ICE_TX_DESC_LEN_L4_LEN_S; 1898 break; 1899 case IPPROTO_SCTP: 1900 /* enable SCTP checksum offload */ 1901 cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP; 1902 l4_len = sizeof(struct sctphdr) >> 2; 1903 offset |= l4_len << ICE_TX_DESC_LEN_L4_LEN_S; 1904 break; 1905 1906 default: 1907 if (first->tx_flags & ICE_TX_FLAGS_TSO) 1908 return -1; 1909 skb_checksum_help(skb); 1910 return 0; 1911 } 1912 1913 off->td_cmd |= cmd; 1914 off->td_offset |= offset; 1915 return 1; 1916 } 1917 1918 /** 1919 * ice_tx_prepare_vlan_flags - prepare generic Tx VLAN tagging flags for HW 1920 * @tx_ring: ring to send buffer on 1921 * @first: pointer to struct ice_tx_buf 1922 * 1923 * Checks the skb and set up correspondingly several generic transmit flags 1924 * related to VLAN tagging for the HW, such as VLAN, DCB, etc. 1925 */ 1926 static void 1927 ice_tx_prepare_vlan_flags(struct ice_tx_ring *tx_ring, struct ice_tx_buf *first) 1928 { 1929 struct sk_buff *skb = first->skb; 1930 1931 /* nothing left to do, software offloaded VLAN */ 1932 if (!skb_vlan_tag_present(skb) && eth_type_vlan(skb->protocol)) 1933 return; 1934 1935 /* the VLAN ethertype/tpid is determined by VSI configuration and netdev 1936 * feature flags, which the driver only allows either 802.1Q or 802.1ad 1937 * VLAN offloads exclusively so we only care about the VLAN ID here 1938 */ 1939 if (skb_vlan_tag_present(skb)) { 1940 first->tx_flags |= skb_vlan_tag_get(skb) << ICE_TX_FLAGS_VLAN_S; 1941 if (tx_ring->flags & ICE_TX_FLAGS_RING_VLAN_L2TAG2) 1942 first->tx_flags |= ICE_TX_FLAGS_HW_OUTER_SINGLE_VLAN; 1943 else 1944 first->tx_flags |= ICE_TX_FLAGS_HW_VLAN; 1945 } 1946 1947 ice_tx_prepare_vlan_flags_dcb(tx_ring, first); 1948 } 1949 1950 /** 1951 * ice_tso - computes mss and TSO length to prepare for TSO 1952 * @first: pointer to struct ice_tx_buf 1953 * @off: pointer to struct that holds offload parameters 1954 * 1955 * Returns 0 or error (negative) if TSO can't happen, 1 otherwise. 1956 */ 1957 static 1958 int ice_tso(struct ice_tx_buf *first, struct ice_tx_offload_params *off) 1959 { 1960 struct sk_buff *skb = first->skb; 1961 union { 1962 struct iphdr *v4; 1963 struct ipv6hdr *v6; 1964 unsigned char *hdr; 1965 } ip; 1966 union { 1967 struct tcphdr *tcp; 1968 struct udphdr *udp; 1969 unsigned char *hdr; 1970 } l4; 1971 u64 cd_mss, cd_tso_len; 1972 __be16 protocol; 1973 u32 paylen; 1974 u8 l4_start; 1975 int err; 1976 1977 if (skb->ip_summed != CHECKSUM_PARTIAL) 1978 return 0; 1979 1980 if (!skb_is_gso(skb)) 1981 return 0; 1982 1983 err = skb_cow_head(skb, 0); 1984 if (err < 0) 1985 return err; 1986 1987 /* cppcheck-suppress unreadVariable */ 1988 protocol = vlan_get_protocol(skb); 1989 1990 if (eth_p_mpls(protocol)) 1991 ip.hdr = skb_inner_network_header(skb); 1992 else 1993 ip.hdr = skb_network_header(skb); 1994 l4.hdr = skb_checksum_start(skb); 1995 1996 /* initialize outer IP header fields */ 1997 if (ip.v4->version == 4) { 1998 ip.v4->tot_len = 0; 1999 ip.v4->check = 0; 2000 } else { 2001 ip.v6->payload_len = 0; 2002 } 2003 2004 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | 2005 SKB_GSO_GRE_CSUM | 2006 SKB_GSO_IPXIP4 | 2007 SKB_GSO_IPXIP6 | 2008 SKB_GSO_UDP_TUNNEL | 2009 SKB_GSO_UDP_TUNNEL_CSUM)) { 2010 if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && 2011 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) { 2012 l4.udp->len = 0; 2013 2014 /* determine offset of outer transport header */ 2015 l4_start = (u8)(l4.hdr - skb->data); 2016 2017 /* remove payload length from outer checksum */ 2018 paylen = skb->len - l4_start; 2019 csum_replace_by_diff(&l4.udp->check, 2020 (__force __wsum)htonl(paylen)); 2021 } 2022 2023 /* reset pointers to inner headers */ 2024 2025 /* cppcheck-suppress unreadVariable */ 2026 ip.hdr = skb_inner_network_header(skb); 2027 l4.hdr = skb_inner_transport_header(skb); 2028 2029 /* initialize inner IP header fields */ 2030 if (ip.v4->version == 4) { 2031 ip.v4->tot_len = 0; 2032 ip.v4->check = 0; 2033 } else { 2034 ip.v6->payload_len = 0; 2035 } 2036 } 2037 2038 /* determine offset of transport header */ 2039 l4_start = (u8)(l4.hdr - skb->data); 2040 2041 /* remove payload length from checksum */ 2042 paylen = skb->len - l4_start; 2043 2044 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 2045 csum_replace_by_diff(&l4.udp->check, 2046 (__force __wsum)htonl(paylen)); 2047 /* compute length of UDP segmentation header */ 2048 off->header_len = (u8)sizeof(l4.udp) + l4_start; 2049 } else { 2050 csum_replace_by_diff(&l4.tcp->check, 2051 (__force __wsum)htonl(paylen)); 2052 /* compute length of TCP segmentation header */ 2053 off->header_len = (u8)((l4.tcp->doff * 4) + l4_start); 2054 } 2055 2056 /* update gso_segs and bytecount */ 2057 first->gso_segs = skb_shinfo(skb)->gso_segs; 2058 first->bytecount += (first->gso_segs - 1) * off->header_len; 2059 2060 cd_tso_len = skb->len - off->header_len; 2061 cd_mss = skb_shinfo(skb)->gso_size; 2062 2063 /* record cdesc_qw1 with TSO parameters */ 2064 off->cd_qw1 |= (u64)(ICE_TX_DESC_DTYPE_CTX | 2065 (ICE_TX_CTX_DESC_TSO << ICE_TXD_CTX_QW1_CMD_S) | 2066 (cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) | 2067 (cd_mss << ICE_TXD_CTX_QW1_MSS_S)); 2068 first->tx_flags |= ICE_TX_FLAGS_TSO; 2069 return 1; 2070 } 2071 2072 /** 2073 * ice_txd_use_count - estimate the number of descriptors needed for Tx 2074 * @size: transmit request size in bytes 2075 * 2076 * Due to hardware alignment restrictions (4K alignment), we need to 2077 * assume that we can have no more than 12K of data per descriptor, even 2078 * though each descriptor can take up to 16K - 1 bytes of aligned memory. 2079 * Thus, we need to divide by 12K. But division is slow! Instead, 2080 * we decompose the operation into shifts and one relatively cheap 2081 * multiply operation. 2082 * 2083 * To divide by 12K, we first divide by 4K, then divide by 3: 2084 * To divide by 4K, shift right by 12 bits 2085 * To divide by 3, multiply by 85, then divide by 256 2086 * (Divide by 256 is done by shifting right by 8 bits) 2087 * Finally, we add one to round up. Because 256 isn't an exact multiple of 2088 * 3, we'll underestimate near each multiple of 12K. This is actually more 2089 * accurate as we have 4K - 1 of wiggle room that we can fit into the last 2090 * segment. For our purposes this is accurate out to 1M which is orders of 2091 * magnitude greater than our largest possible GSO size. 2092 * 2093 * This would then be implemented as: 2094 * return (((size >> 12) * 85) >> 8) + ICE_DESCS_FOR_SKB_DATA_PTR; 2095 * 2096 * Since multiplication and division are commutative, we can reorder 2097 * operations into: 2098 * return ((size * 85) >> 20) + ICE_DESCS_FOR_SKB_DATA_PTR; 2099 */ 2100 static unsigned int ice_txd_use_count(unsigned int size) 2101 { 2102 return ((size * 85) >> 20) + ICE_DESCS_FOR_SKB_DATA_PTR; 2103 } 2104 2105 /** 2106 * ice_xmit_desc_count - calculate number of Tx descriptors needed 2107 * @skb: send buffer 2108 * 2109 * Returns number of data descriptors needed for this skb. 2110 */ 2111 static unsigned int ice_xmit_desc_count(struct sk_buff *skb) 2112 { 2113 const skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; 2114 unsigned int nr_frags = skb_shinfo(skb)->nr_frags; 2115 unsigned int count = 0, size = skb_headlen(skb); 2116 2117 for (;;) { 2118 count += ice_txd_use_count(size); 2119 2120 if (!nr_frags--) 2121 break; 2122 2123 size = skb_frag_size(frag++); 2124 } 2125 2126 return count; 2127 } 2128 2129 /** 2130 * __ice_chk_linearize - Check if there are more than 8 buffers per packet 2131 * @skb: send buffer 2132 * 2133 * Note: This HW can't DMA more than 8 buffers to build a packet on the wire 2134 * and so we need to figure out the cases where we need to linearize the skb. 2135 * 2136 * For TSO we need to count the TSO header and segment payload separately. 2137 * As such we need to check cases where we have 7 fragments or more as we 2138 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for 2139 * the segment payload in the first descriptor, and another 7 for the 2140 * fragments. 2141 */ 2142 static bool __ice_chk_linearize(struct sk_buff *skb) 2143 { 2144 const skb_frag_t *frag, *stale; 2145 int nr_frags, sum; 2146 2147 /* no need to check if number of frags is less than 7 */ 2148 nr_frags = skb_shinfo(skb)->nr_frags; 2149 if (nr_frags < (ICE_MAX_BUF_TXD - 1)) 2150 return false; 2151 2152 /* We need to walk through the list and validate that each group 2153 * of 6 fragments totals at least gso_size. 2154 */ 2155 nr_frags -= ICE_MAX_BUF_TXD - 2; 2156 frag = &skb_shinfo(skb)->frags[0]; 2157 2158 /* Initialize size to the negative value of gso_size minus 1. We 2159 * use this as the worst case scenario in which the frag ahead 2160 * of us only provides one byte which is why we are limited to 6 2161 * descriptors for a single transmit as the header and previous 2162 * fragment are already consuming 2 descriptors. 2163 */ 2164 sum = 1 - skb_shinfo(skb)->gso_size; 2165 2166 /* Add size of frags 0 through 4 to create our initial sum */ 2167 sum += skb_frag_size(frag++); 2168 sum += skb_frag_size(frag++); 2169 sum += skb_frag_size(frag++); 2170 sum += skb_frag_size(frag++); 2171 sum += skb_frag_size(frag++); 2172 2173 /* Walk through fragments adding latest fragment, testing it, and 2174 * then removing stale fragments from the sum. 2175 */ 2176 for (stale = &skb_shinfo(skb)->frags[0];; stale++) { 2177 int stale_size = skb_frag_size(stale); 2178 2179 sum += skb_frag_size(frag++); 2180 2181 /* The stale fragment may present us with a smaller 2182 * descriptor than the actual fragment size. To account 2183 * for that we need to remove all the data on the front and 2184 * figure out what the remainder would be in the last 2185 * descriptor associated with the fragment. 2186 */ 2187 if (stale_size > ICE_MAX_DATA_PER_TXD) { 2188 int align_pad = -(skb_frag_off(stale)) & 2189 (ICE_MAX_READ_REQ_SIZE - 1); 2190 2191 sum -= align_pad; 2192 stale_size -= align_pad; 2193 2194 do { 2195 sum -= ICE_MAX_DATA_PER_TXD_ALIGNED; 2196 stale_size -= ICE_MAX_DATA_PER_TXD_ALIGNED; 2197 } while (stale_size > ICE_MAX_DATA_PER_TXD); 2198 } 2199 2200 /* if sum is negative we failed to make sufficient progress */ 2201 if (sum < 0) 2202 return true; 2203 2204 if (!nr_frags--) 2205 break; 2206 2207 sum -= stale_size; 2208 } 2209 2210 return false; 2211 } 2212 2213 /** 2214 * ice_chk_linearize - Check if there are more than 8 fragments per packet 2215 * @skb: send buffer 2216 * @count: number of buffers used 2217 * 2218 * Note: Our HW can't scatter-gather more than 8 fragments to build 2219 * a packet on the wire and so we need to figure out the cases where we 2220 * need to linearize the skb. 2221 */ 2222 static bool ice_chk_linearize(struct sk_buff *skb, unsigned int count) 2223 { 2224 /* Both TSO and single send will work if count is less than 8 */ 2225 if (likely(count < ICE_MAX_BUF_TXD)) 2226 return false; 2227 2228 if (skb_is_gso(skb)) 2229 return __ice_chk_linearize(skb); 2230 2231 /* we can support up to 8 data buffers for a single send */ 2232 return count != ICE_MAX_BUF_TXD; 2233 } 2234 2235 /** 2236 * ice_tstamp - set up context descriptor for hardware timestamp 2237 * @tx_ring: pointer to the Tx ring to send buffer on 2238 * @skb: pointer to the SKB we're sending 2239 * @first: Tx buffer 2240 * @off: Tx offload parameters 2241 */ 2242 static void 2243 ice_tstamp(struct ice_tx_ring *tx_ring, struct sk_buff *skb, 2244 struct ice_tx_buf *first, struct ice_tx_offload_params *off) 2245 { 2246 s8 idx; 2247 2248 /* only timestamp the outbound packet if the user has requested it */ 2249 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))) 2250 return; 2251 2252 if (!tx_ring->ptp_tx) 2253 return; 2254 2255 /* Tx timestamps cannot be sampled when doing TSO */ 2256 if (first->tx_flags & ICE_TX_FLAGS_TSO) 2257 return; 2258 2259 /* Grab an open timestamp slot */ 2260 idx = ice_ptp_request_ts(tx_ring->tx_tstamps, skb); 2261 if (idx < 0) { 2262 tx_ring->vsi->back->ptp.tx_hwtstamp_skipped++; 2263 return; 2264 } 2265 2266 off->cd_qw1 |= (u64)(ICE_TX_DESC_DTYPE_CTX | 2267 (ICE_TX_CTX_DESC_TSYN << ICE_TXD_CTX_QW1_CMD_S) | 2268 ((u64)idx << ICE_TXD_CTX_QW1_TSO_LEN_S)); 2269 first->tx_flags |= ICE_TX_FLAGS_TSYN; 2270 } 2271 2272 /** 2273 * ice_xmit_frame_ring - Sends buffer on Tx ring 2274 * @skb: send buffer 2275 * @tx_ring: ring to send buffer on 2276 * 2277 * Returns NETDEV_TX_OK if sent, else an error code 2278 */ 2279 static netdev_tx_t 2280 ice_xmit_frame_ring(struct sk_buff *skb, struct ice_tx_ring *tx_ring) 2281 { 2282 struct ice_tx_offload_params offload = { 0 }; 2283 struct ice_vsi *vsi = tx_ring->vsi; 2284 struct ice_tx_buf *first; 2285 struct ethhdr *eth; 2286 unsigned int count; 2287 int tso, csum; 2288 2289 ice_trace(xmit_frame_ring, tx_ring, skb); 2290 2291 count = ice_xmit_desc_count(skb); 2292 if (ice_chk_linearize(skb, count)) { 2293 if (__skb_linearize(skb)) 2294 goto out_drop; 2295 count = ice_txd_use_count(skb->len); 2296 tx_ring->tx_stats.tx_linearize++; 2297 } 2298 2299 /* need: 1 descriptor per page * PAGE_SIZE/ICE_MAX_DATA_PER_TXD, 2300 * + 1 desc for skb_head_len/ICE_MAX_DATA_PER_TXD, 2301 * + 4 desc gap to avoid the cache line where head is, 2302 * + 1 desc for context descriptor, 2303 * otherwise try next time 2304 */ 2305 if (ice_maybe_stop_tx(tx_ring, count + ICE_DESCS_PER_CACHE_LINE + 2306 ICE_DESCS_FOR_CTX_DESC)) { 2307 tx_ring->tx_stats.tx_busy++; 2308 return NETDEV_TX_BUSY; 2309 } 2310 2311 /* prefetch for bql data which is infrequently used */ 2312 netdev_txq_bql_enqueue_prefetchw(txring_txq(tx_ring)); 2313 2314 offload.tx_ring = tx_ring; 2315 2316 /* record the location of the first descriptor for this packet */ 2317 first = &tx_ring->tx_buf[tx_ring->next_to_use]; 2318 first->skb = skb; 2319 first->bytecount = max_t(unsigned int, skb->len, ETH_ZLEN); 2320 first->gso_segs = 1; 2321 first->tx_flags = 0; 2322 2323 /* prepare the VLAN tagging flags for Tx */ 2324 ice_tx_prepare_vlan_flags(tx_ring, first); 2325 if (first->tx_flags & ICE_TX_FLAGS_HW_OUTER_SINGLE_VLAN) { 2326 offload.cd_qw1 |= (u64)(ICE_TX_DESC_DTYPE_CTX | 2327 (ICE_TX_CTX_DESC_IL2TAG2 << 2328 ICE_TXD_CTX_QW1_CMD_S)); 2329 offload.cd_l2tag2 = (first->tx_flags & ICE_TX_FLAGS_VLAN_M) >> 2330 ICE_TX_FLAGS_VLAN_S; 2331 } 2332 2333 /* set up TSO offload */ 2334 tso = ice_tso(first, &offload); 2335 if (tso < 0) 2336 goto out_drop; 2337 2338 /* always set up Tx checksum offload */ 2339 csum = ice_tx_csum(first, &offload); 2340 if (csum < 0) 2341 goto out_drop; 2342 2343 /* allow CONTROL frames egress from main VSI if FW LLDP disabled */ 2344 eth = (struct ethhdr *)skb_mac_header(skb); 2345 if (unlikely((skb->priority == TC_PRIO_CONTROL || 2346 eth->h_proto == htons(ETH_P_LLDP)) && 2347 vsi->type == ICE_VSI_PF && 2348 vsi->port_info->qos_cfg.is_sw_lldp)) 2349 offload.cd_qw1 |= (u64)(ICE_TX_DESC_DTYPE_CTX | 2350 ICE_TX_CTX_DESC_SWTCH_UPLINK << 2351 ICE_TXD_CTX_QW1_CMD_S); 2352 2353 ice_tstamp(tx_ring, skb, first, &offload); 2354 if (ice_is_switchdev_running(vsi->back)) 2355 ice_eswitch_set_target_vsi(skb, &offload); 2356 2357 if (offload.cd_qw1 & ICE_TX_DESC_DTYPE_CTX) { 2358 struct ice_tx_ctx_desc *cdesc; 2359 u16 i = tx_ring->next_to_use; 2360 2361 /* grab the next descriptor */ 2362 cdesc = ICE_TX_CTX_DESC(tx_ring, i); 2363 i++; 2364 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 2365 2366 /* setup context descriptor */ 2367 cdesc->tunneling_params = cpu_to_le32(offload.cd_tunnel_params); 2368 cdesc->l2tag2 = cpu_to_le16(offload.cd_l2tag2); 2369 cdesc->rsvd = cpu_to_le16(0); 2370 cdesc->qw1 = cpu_to_le64(offload.cd_qw1); 2371 } 2372 2373 ice_tx_map(tx_ring, first, &offload); 2374 return NETDEV_TX_OK; 2375 2376 out_drop: 2377 ice_trace(xmit_frame_ring_drop, tx_ring, skb); 2378 dev_kfree_skb_any(skb); 2379 return NETDEV_TX_OK; 2380 } 2381 2382 /** 2383 * ice_start_xmit - Selects the correct VSI and Tx queue to send buffer 2384 * @skb: send buffer 2385 * @netdev: network interface device structure 2386 * 2387 * Returns NETDEV_TX_OK if sent, else an error code 2388 */ 2389 netdev_tx_t ice_start_xmit(struct sk_buff *skb, struct net_device *netdev) 2390 { 2391 struct ice_netdev_priv *np = netdev_priv(netdev); 2392 struct ice_vsi *vsi = np->vsi; 2393 struct ice_tx_ring *tx_ring; 2394 2395 tx_ring = vsi->tx_rings[skb->queue_mapping]; 2396 2397 /* hardware can't handle really short frames, hardware padding works 2398 * beyond this point 2399 */ 2400 if (skb_put_padto(skb, ICE_MIN_TX_LEN)) 2401 return NETDEV_TX_OK; 2402 2403 return ice_xmit_frame_ring(skb, tx_ring); 2404 } 2405 2406 /** 2407 * ice_get_dscp_up - return the UP/TC value for a SKB 2408 * @dcbcfg: DCB config that contains DSCP to UP/TC mapping 2409 * @skb: SKB to query for info to determine UP/TC 2410 * 2411 * This function is to only be called when the PF is in L3 DSCP PFC mode 2412 */ 2413 static u8 ice_get_dscp_up(struct ice_dcbx_cfg *dcbcfg, struct sk_buff *skb) 2414 { 2415 u8 dscp = 0; 2416 2417 if (skb->protocol == htons(ETH_P_IP)) 2418 dscp = ipv4_get_dsfield(ip_hdr(skb)) >> 2; 2419 else if (skb->protocol == htons(ETH_P_IPV6)) 2420 dscp = ipv6_get_dsfield(ipv6_hdr(skb)) >> 2; 2421 2422 return dcbcfg->dscp_map[dscp]; 2423 } 2424 2425 u16 2426 ice_select_queue(struct net_device *netdev, struct sk_buff *skb, 2427 struct net_device *sb_dev) 2428 { 2429 struct ice_pf *pf = ice_netdev_to_pf(netdev); 2430 struct ice_dcbx_cfg *dcbcfg; 2431 2432 dcbcfg = &pf->hw.port_info->qos_cfg.local_dcbx_cfg; 2433 if (dcbcfg->pfc_mode == ICE_QOS_MODE_DSCP) 2434 skb->priority = ice_get_dscp_up(dcbcfg, skb); 2435 2436 return netdev_pick_tx(netdev, skb, sb_dev); 2437 } 2438 2439 /** 2440 * ice_clean_ctrl_tx_irq - interrupt handler for flow director Tx queue 2441 * @tx_ring: tx_ring to clean 2442 */ 2443 void ice_clean_ctrl_tx_irq(struct ice_tx_ring *tx_ring) 2444 { 2445 struct ice_vsi *vsi = tx_ring->vsi; 2446 s16 i = tx_ring->next_to_clean; 2447 int budget = ICE_DFLT_IRQ_WORK; 2448 struct ice_tx_desc *tx_desc; 2449 struct ice_tx_buf *tx_buf; 2450 2451 tx_buf = &tx_ring->tx_buf[i]; 2452 tx_desc = ICE_TX_DESC(tx_ring, i); 2453 i -= tx_ring->count; 2454 2455 do { 2456 struct ice_tx_desc *eop_desc = tx_buf->next_to_watch; 2457 2458 /* if next_to_watch is not set then there is no pending work */ 2459 if (!eop_desc) 2460 break; 2461 2462 /* prevent any other reads prior to eop_desc */ 2463 smp_rmb(); 2464 2465 /* if the descriptor isn't done, no work to do */ 2466 if (!(eop_desc->cmd_type_offset_bsz & 2467 cpu_to_le64(ICE_TX_DESC_DTYPE_DESC_DONE))) 2468 break; 2469 2470 /* clear next_to_watch to prevent false hangs */ 2471 tx_buf->next_to_watch = NULL; 2472 tx_desc->buf_addr = 0; 2473 tx_desc->cmd_type_offset_bsz = 0; 2474 2475 /* move past filter desc */ 2476 tx_buf++; 2477 tx_desc++; 2478 i++; 2479 if (unlikely(!i)) { 2480 i -= tx_ring->count; 2481 tx_buf = tx_ring->tx_buf; 2482 tx_desc = ICE_TX_DESC(tx_ring, 0); 2483 } 2484 2485 /* unmap the data header */ 2486 if (dma_unmap_len(tx_buf, len)) 2487 dma_unmap_single(tx_ring->dev, 2488 dma_unmap_addr(tx_buf, dma), 2489 dma_unmap_len(tx_buf, len), 2490 DMA_TO_DEVICE); 2491 if (tx_buf->tx_flags & ICE_TX_FLAGS_DUMMY_PKT) 2492 devm_kfree(tx_ring->dev, tx_buf->raw_buf); 2493 2494 /* clear next_to_watch to prevent false hangs */ 2495 tx_buf->raw_buf = NULL; 2496 tx_buf->tx_flags = 0; 2497 tx_buf->next_to_watch = NULL; 2498 dma_unmap_len_set(tx_buf, len, 0); 2499 tx_desc->buf_addr = 0; 2500 tx_desc->cmd_type_offset_bsz = 0; 2501 2502 /* move past eop_desc for start of next FD desc */ 2503 tx_buf++; 2504 tx_desc++; 2505 i++; 2506 if (unlikely(!i)) { 2507 i -= tx_ring->count; 2508 tx_buf = tx_ring->tx_buf; 2509 tx_desc = ICE_TX_DESC(tx_ring, 0); 2510 } 2511 2512 budget--; 2513 } while (likely(budget)); 2514 2515 i += tx_ring->count; 2516 tx_ring->next_to_clean = i; 2517 2518 /* re-enable interrupt if needed */ 2519 ice_irq_dynamic_ena(&vsi->back->hw, vsi, vsi->q_vectors[0]); 2520 } 2521