10d08a441SKiran Patil /* SPDX-License-Identifier: GPL-2.0 */ 20d08a441SKiran Patil /* Copyright (C) 2019-2021, Intel Corporation. */ 30d08a441SKiran Patil 40d08a441SKiran Patil #ifndef _ICE_TC_LIB_H_ 50d08a441SKiran Patil #define _ICE_TC_LIB_H_ 60d08a441SKiran Patil 70d08a441SKiran Patil #define ICE_TC_FLWR_FIELD_DST_MAC BIT(0) 80d08a441SKiran Patil #define ICE_TC_FLWR_FIELD_SRC_MAC BIT(1) 90d08a441SKiran Patil #define ICE_TC_FLWR_FIELD_VLAN BIT(2) 100d08a441SKiran Patil #define ICE_TC_FLWR_FIELD_DEST_IPV4 BIT(3) 110d08a441SKiran Patil #define ICE_TC_FLWR_FIELD_SRC_IPV4 BIT(4) 120d08a441SKiran Patil #define ICE_TC_FLWR_FIELD_DEST_IPV6 BIT(5) 130d08a441SKiran Patil #define ICE_TC_FLWR_FIELD_SRC_IPV6 BIT(6) 140d08a441SKiran Patil #define ICE_TC_FLWR_FIELD_DEST_L4_PORT BIT(7) 150d08a441SKiran Patil #define ICE_TC_FLWR_FIELD_SRC_L4_PORT BIT(8) 160d08a441SKiran Patil #define ICE_TC_FLWR_FIELD_TENANT_ID BIT(9) 170d08a441SKiran Patil #define ICE_TC_FLWR_FIELD_ENC_DEST_IPV4 BIT(10) 180d08a441SKiran Patil #define ICE_TC_FLWR_FIELD_ENC_SRC_IPV4 BIT(11) 190d08a441SKiran Patil #define ICE_TC_FLWR_FIELD_ENC_DEST_IPV6 BIT(12) 200d08a441SKiran Patil #define ICE_TC_FLWR_FIELD_ENC_SRC_IPV6 BIT(13) 210d08a441SKiran Patil #define ICE_TC_FLWR_FIELD_ENC_DEST_L4_PORT BIT(14) 220d08a441SKiran Patil #define ICE_TC_FLWR_FIELD_ENC_SRC_L4_PORT BIT(15) 230d08a441SKiran Patil #define ICE_TC_FLWR_FIELD_ENC_DST_MAC BIT(16) 240d08a441SKiran Patil #define ICE_TC_FLWR_FIELD_ETH_TYPE_ID BIT(17) 259a225f81SMarcin Szycik #define ICE_TC_FLWR_FIELD_ENC_OPTS BIT(18) 2606bca7c2SMartyna Szapar-Mudlaw #define ICE_TC_FLWR_FIELD_CVLAN BIT(19) 27cd8efeeeSMarcin Szycik #define ICE_TC_FLWR_FIELD_PPPOE_SESSID BIT(20) 28cd8efeeeSMarcin Szycik #define ICE_TC_FLWR_FIELD_PPP_PROTO BIT(21) 294c99bc96SMarcin Szycik #define ICE_TC_FLWR_FIELD_IP_TOS BIT(22) 304c99bc96SMarcin Szycik #define ICE_TC_FLWR_FIELD_IP_TTL BIT(23) 314c99bc96SMarcin Szycik #define ICE_TC_FLWR_FIELD_ENC_IP_TOS BIT(24) 324c99bc96SMarcin Szycik #define ICE_TC_FLWR_FIELD_ENC_IP_TTL BIT(25) 33cd634549SMarcin Szycik #define ICE_TC_FLWR_FIELD_L2TPV3_SESSID BIT(26) 3434800178SMartyna Szapar-Mudlaw #define ICE_TC_FLWR_FIELD_VLAN_PRIO BIT(27) 3534800178SMartyna Szapar-Mudlaw #define ICE_TC_FLWR_FIELD_CVLAN_PRIO BIT(28) 360d08a441SKiran Patil 379e300987SMichal Swiatkowski #define ICE_TC_FLOWER_MASK_32 0xFFFFFFFF 389e300987SMichal Swiatkowski 394c99bc96SMarcin Szycik #define ICE_IPV6_HDR_TC_MASK 0xFF00000 404c99bc96SMarcin Szycik 41195bb48fSMichal Swiatkowski struct ice_indr_block_priv { 42195bb48fSMichal Swiatkowski struct net_device *netdev; 43195bb48fSMichal Swiatkowski struct ice_netdev_priv *np; 44195bb48fSMichal Swiatkowski struct list_head list; 45195bb48fSMichal Swiatkowski }; 46195bb48fSMichal Swiatkowski 470d08a441SKiran Patil struct ice_tc_flower_action { 48*143b86f3SAmritha Nambiar /* forward action specific params */ 49*143b86f3SAmritha Nambiar union { 50*143b86f3SAmritha Nambiar struct { 51*143b86f3SAmritha Nambiar u32 tc_class; /* forward to hw_tc */ 52*143b86f3SAmritha Nambiar u32 rsvd; 53*143b86f3SAmritha Nambiar } tc; 54*143b86f3SAmritha Nambiar struct { 55*143b86f3SAmritha Nambiar u16 queue; /* forward to queue */ 56*143b86f3SAmritha Nambiar /* To add filter in HW, absolute queue number in global 57*143b86f3SAmritha Nambiar * space of queues (between 0...N) is needed 58*143b86f3SAmritha Nambiar */ 59*143b86f3SAmritha Nambiar u16 hw_queue; 60*143b86f3SAmritha Nambiar } q; 61*143b86f3SAmritha Nambiar } fwd; 620d08a441SKiran Patil enum ice_sw_fwd_act_type fltr_act; 630d08a441SKiran Patil }; 640d08a441SKiran Patil 650d08a441SKiran Patil struct ice_tc_vlan_hdr { 660d08a441SKiran Patil __be16 vlan_id; /* Only last 12 bits valid */ 6734800178SMartyna Szapar-Mudlaw __be16 vlan_prio; /* Only last 3 bits valid (valid values: 0..7) */ 68ea71b967SMartyna Szapar-Mudlaw __be16 vlan_tpid; 690d08a441SKiran Patil }; 700d08a441SKiran Patil 71cd8efeeeSMarcin Szycik struct ice_tc_pppoe_hdr { 72cd8efeeeSMarcin Szycik __be16 session_id; 73cd8efeeeSMarcin Szycik __be16 ppp_proto; 74cd8efeeeSMarcin Szycik }; 75cd8efeeeSMarcin Szycik 760d08a441SKiran Patil struct ice_tc_l2_hdr { 770d08a441SKiran Patil u8 dst_mac[ETH_ALEN]; 780d08a441SKiran Patil u8 src_mac[ETH_ALEN]; 790d08a441SKiran Patil __be16 n_proto; /* Ethernet Protocol */ 800d08a441SKiran Patil }; 810d08a441SKiran Patil 820d08a441SKiran Patil struct ice_tc_l3_hdr { 830d08a441SKiran Patil u8 ip_proto; /* IPPROTO value */ 840d08a441SKiran Patil union { 850d08a441SKiran Patil struct { 860d08a441SKiran Patil struct in_addr dst_ip; 870d08a441SKiran Patil struct in_addr src_ip; 880d08a441SKiran Patil } v4; 890d08a441SKiran Patil struct { 900d08a441SKiran Patil struct in6_addr dst_ip6; 910d08a441SKiran Patil struct in6_addr src_ip6; 920d08a441SKiran Patil } v6; 930d08a441SKiran Patil } ip; 940d08a441SKiran Patil #define dst_ipv6 ip.v6.dst_ip6.s6_addr32 950d08a441SKiran Patil #define dst_ipv6_addr ip.v6.dst_ip6.s6_addr 960d08a441SKiran Patil #define src_ipv6 ip.v6.src_ip6.s6_addr32 970d08a441SKiran Patil #define src_ipv6_addr ip.v6.src_ip6.s6_addr 980d08a441SKiran Patil #define dst_ipv4 ip.v4.dst_ip.s_addr 990d08a441SKiran Patil #define src_ipv4 ip.v4.src_ip.s_addr 1000d08a441SKiran Patil 1010d08a441SKiran Patil u8 tos; 1020d08a441SKiran Patil u8 ttl; 1030d08a441SKiran Patil }; 1040d08a441SKiran Patil 105cd634549SMarcin Szycik struct ice_tc_l2tpv3_hdr { 106cd634549SMarcin Szycik __be32 session_id; 107cd634549SMarcin Szycik }; 108cd634549SMarcin Szycik 1090d08a441SKiran Patil struct ice_tc_l4_hdr { 1100d08a441SKiran Patil __be16 dst_port; 1110d08a441SKiran Patil __be16 src_port; 1120d08a441SKiran Patil }; 1130d08a441SKiran Patil 1140d08a441SKiran Patil struct ice_tc_flower_lyr_2_4_hdrs { 1150d08a441SKiran Patil /* L2 layer fields with their mask */ 1160d08a441SKiran Patil struct ice_tc_l2_hdr l2_key; 1170d08a441SKiran Patil struct ice_tc_l2_hdr l2_mask; 1180d08a441SKiran Patil struct ice_tc_vlan_hdr vlan_hdr; 11906bca7c2SMartyna Szapar-Mudlaw struct ice_tc_vlan_hdr cvlan_hdr; 120cd8efeeeSMarcin Szycik struct ice_tc_pppoe_hdr pppoe_hdr; 121cd634549SMarcin Szycik struct ice_tc_l2tpv3_hdr l2tpv3_hdr; 1220d08a441SKiran Patil /* L3 (IPv4[6]) layer fields with their mask */ 1230d08a441SKiran Patil struct ice_tc_l3_hdr l3_key; 1240d08a441SKiran Patil struct ice_tc_l3_hdr l3_mask; 1250d08a441SKiran Patil 1260d08a441SKiran Patil /* L4 layer fields with their mask */ 1270d08a441SKiran Patil struct ice_tc_l4_hdr l4_key; 1280d08a441SKiran Patil struct ice_tc_l4_hdr l4_mask; 1290d08a441SKiran Patil }; 1300d08a441SKiran Patil 1310d08a441SKiran Patil enum ice_eswitch_fltr_direction { 1320d08a441SKiran Patil ICE_ESWITCH_FLTR_INGRESS, 1330d08a441SKiran Patil ICE_ESWITCH_FLTR_EGRESS, 1340d08a441SKiran Patil }; 1350d08a441SKiran Patil 1360d08a441SKiran Patil struct ice_tc_flower_fltr { 1370d08a441SKiran Patil struct hlist_node tc_flower_node; 1380d08a441SKiran Patil 1390d08a441SKiran Patil /* cookie becomes filter_rule_id if rule is added successfully */ 1400d08a441SKiran Patil unsigned long cookie; 1410d08a441SKiran Patil 1420d08a441SKiran Patil /* add_adv_rule returns information like recipe ID, rule_id. Store 1430d08a441SKiran Patil * those values since they are needed to remove advanced rule 1440d08a441SKiran Patil */ 1450d08a441SKiran Patil u16 rid; 1460d08a441SKiran Patil u16 rule_id; 147*143b86f3SAmritha Nambiar /* VSI handle of the destination VSI (it could be main PF VSI, CHNL_VSI, 148*143b86f3SAmritha Nambiar * VF VSI) 1490d08a441SKiran Patil */ 150*143b86f3SAmritha Nambiar u16 dest_vsi_handle; 151*143b86f3SAmritha Nambiar /* ptr to destination VSI */ 1520d08a441SKiran Patil struct ice_vsi *dest_vsi; 1530d08a441SKiran Patil /* direction of fltr for eswitch use case */ 1540d08a441SKiran Patil enum ice_eswitch_fltr_direction direction; 1550d08a441SKiran Patil 1560d08a441SKiran Patil /* Parsed TC flower configuration params */ 1570d08a441SKiran Patil struct ice_tc_flower_lyr_2_4_hdrs outer_headers; 1580d08a441SKiran Patil struct ice_tc_flower_lyr_2_4_hdrs inner_headers; 1590d08a441SKiran Patil struct ice_vsi *src_vsi; 1600d08a441SKiran Patil __be32 tenant_id; 1619a225f81SMarcin Szycik struct gtp_pdu_session_info gtp_pdu_info_keys; 1629a225f81SMarcin Szycik struct gtp_pdu_session_info gtp_pdu_info_masks; 1630d08a441SKiran Patil u32 flags; 1649e300987SMichal Swiatkowski u8 tunnel_type; 1650d08a441SKiran Patil struct ice_tc_flower_action action; 1660d08a441SKiran Patil 1670d08a441SKiran Patil /* cache ptr which is used wherever needed to communicate netlink 1680d08a441SKiran Patil * messages 1690d08a441SKiran Patil */ 1700d08a441SKiran Patil struct netlink_ext_ack *extack; 1710d08a441SKiran Patil }; 1720d08a441SKiran Patil 1739fea7498SKiran Patil /** 1749fea7498SKiran Patil * ice_is_chnl_fltr - is this a valid channel filter 1759fea7498SKiran Patil * @f: Pointer to tc-flower filter 1769fea7498SKiran Patil * 1779fea7498SKiran Patil * Criteria to determine of given filter is valid channel filter 178*143b86f3SAmritha Nambiar * or not is based on its destination. 179*143b86f3SAmritha Nambiar * For forward to VSI action, if destination is valid hw_tc (aka tc_class) 180*143b86f3SAmritha Nambiar * and in supported range of TCs for ADQ, then return true. 181*143b86f3SAmritha Nambiar * For forward to queue, as long as dest_vsi is valid and it is of type 182*143b86f3SAmritha Nambiar * VSI_CHNL (PF ADQ VSI is of type VSI_CHNL), return true. 183*143b86f3SAmritha Nambiar * NOTE: For forward to queue, correct dest_vsi is still set in tc_fltr based 184*143b86f3SAmritha Nambiar * on destination queue specified. 1859fea7498SKiran Patil */ 1869fea7498SKiran Patil static inline bool ice_is_chnl_fltr(struct ice_tc_flower_fltr *f) 1879fea7498SKiran Patil { 188*143b86f3SAmritha Nambiar if (f->action.fltr_act == ICE_FWD_TO_VSI) 189*143b86f3SAmritha Nambiar return f->action.fwd.tc.tc_class >= ICE_CHNL_START_TC && 190*143b86f3SAmritha Nambiar f->action.fwd.tc.tc_class < ICE_CHNL_MAX_TC; 191*143b86f3SAmritha Nambiar else if (f->action.fltr_act == ICE_FWD_TO_Q) 192*143b86f3SAmritha Nambiar return f->dest_vsi && f->dest_vsi->type == ICE_VSI_CHNL; 193*143b86f3SAmritha Nambiar 194*143b86f3SAmritha Nambiar return false; 1959fea7498SKiran Patil } 1969fea7498SKiran Patil 1979fea7498SKiran Patil /** 1989fea7498SKiran Patil * ice_chnl_dmac_fltr_cnt - DMAC based CHNL filter count 1999fea7498SKiran Patil * @pf: Pointer to PF 2009fea7498SKiran Patil */ 2019fea7498SKiran Patil static inline int ice_chnl_dmac_fltr_cnt(struct ice_pf *pf) 2029fea7498SKiran Patil { 2039fea7498SKiran Patil return pf->num_dmac_chnl_fltrs; 2049fea7498SKiran Patil } 2059fea7498SKiran Patil 2060d08a441SKiran Patil int 2070d08a441SKiran Patil ice_add_cls_flower(struct net_device *netdev, struct ice_vsi *vsi, 2080d08a441SKiran Patil struct flow_cls_offload *cls_flower); 2090d08a441SKiran Patil int 2100d08a441SKiran Patil ice_del_cls_flower(struct ice_vsi *vsi, struct flow_cls_offload *cls_flower); 2117fde6d8bSMichal Swiatkowski void ice_replay_tc_fltrs(struct ice_pf *pf); 2129e300987SMichal Swiatkowski bool ice_is_tunnel_supported(struct net_device *dev); 2130d08a441SKiran Patil 2140d08a441SKiran Patil #endif /* _ICE_TC_LIB_H_ */ 215