1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_SCHED_H_ 5 #define _ICE_SCHED_H_ 6 7 #include "ice_common.h" 8 9 #define ICE_QGRP_LAYER_OFFSET 2 10 #define ICE_VSI_LAYER_OFFSET 4 11 #define ICE_AGG_LAYER_OFFSET 6 12 #define ICE_SCHED_INVAL_LAYER_NUM 0xFF 13 /* Burst size is a 12 bits register that is configured while creating the RL 14 * profile(s). MSB is a granularity bit and tells the granularity type 15 * 0 - LSB bits are in 64 bytes granularity 16 * 1 - LSB bits are in 1K bytes granularity 17 */ 18 #define ICE_64_BYTE_GRANULARITY 0 19 #define ICE_KBYTE_GRANULARITY BIT(11) 20 #define ICE_MIN_BURST_SIZE_ALLOWED 64 /* In Bytes */ 21 #define ICE_MAX_BURST_SIZE_ALLOWED \ 22 ((BIT(11) - 1) * 1024) /* In Bytes */ 23 #define ICE_MAX_BURST_SIZE_64_BYTE_GRANULARITY \ 24 ((BIT(11) - 1) * 64) /* In Bytes */ 25 #define ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY ICE_MAX_BURST_SIZE_ALLOWED 26 27 #define ICE_RL_PROF_ACCURACY_BYTES 128 28 #define ICE_RL_PROF_MULTIPLIER 10000 29 #define ICE_RL_PROF_TS_MULTIPLIER 32 30 #define ICE_RL_PROF_FRACTION 512 31 32 #define ICE_PSM_CLK_367MHZ_IN_HZ 367647059 33 #define ICE_PSM_CLK_416MHZ_IN_HZ 416666667 34 #define ICE_PSM_CLK_446MHZ_IN_HZ 446428571 35 #define ICE_PSM_CLK_390MHZ_IN_HZ 390625000 36 37 /* BW rate limit profile parameters list entry along 38 * with bandwidth maintained per layer in port info 39 */ 40 struct ice_aqc_rl_profile_info { 41 struct ice_aqc_rl_profile_elem profile; 42 struct list_head list_entry; 43 u32 bw; /* requested */ 44 u16 prof_id_ref; /* profile ID to node association ref count */ 45 }; 46 47 struct ice_sched_agg_vsi_info { 48 struct list_head list_entry; 49 DECLARE_BITMAP(tc_bitmap, ICE_MAX_TRAFFIC_CLASS); 50 u16 vsi_handle; 51 /* save aggregator VSI TC bitmap */ 52 DECLARE_BITMAP(replay_tc_bitmap, ICE_MAX_TRAFFIC_CLASS); 53 }; 54 55 struct ice_sched_agg_info { 56 struct list_head agg_vsi_list; 57 struct list_head list_entry; 58 DECLARE_BITMAP(tc_bitmap, ICE_MAX_TRAFFIC_CLASS); 59 u32 agg_id; 60 enum ice_agg_type agg_type; 61 /* bw_t_info saves aggregator BW information */ 62 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS]; 63 /* save aggregator TC bitmap */ 64 DECLARE_BITMAP(replay_tc_bitmap, ICE_MAX_TRAFFIC_CLASS); 65 }; 66 67 /* FW AQ command calls */ 68 int 69 ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req, 70 struct ice_aqc_txsched_elem_data *buf, u16 buf_size, 71 u16 *elems_ret, struct ice_sq_cd *cd); 72 int ice_sched_init_port(struct ice_port_info *pi); 73 int ice_sched_query_res_alloc(struct ice_hw *hw); 74 void ice_sched_get_psm_clk_freq(struct ice_hw *hw); 75 76 void ice_sched_clear_port(struct ice_port_info *pi); 77 void ice_sched_cleanup_all(struct ice_hw *hw); 78 void ice_sched_clear_agg(struct ice_hw *hw); 79 80 struct ice_sched_node * 81 ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid); 82 int 83 ice_sched_add_node(struct ice_port_info *pi, u8 layer, 84 struct ice_aqc_txsched_elem_data *info); 85 void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node); 86 struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc); 87 struct ice_sched_node * 88 ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 89 u8 owner); 90 int 91 ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 maxqs, 92 u8 owner, bool enable); 93 int ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle); 94 int ice_rm_vsi_rdma_cfg(struct ice_port_info *pi, u16 vsi_handle); 95 96 /* Tx scheduler rate limiter functions */ 97 int 98 ice_cfg_agg(struct ice_port_info *pi, u32 agg_id, 99 enum ice_agg_type agg_type, u8 tc_bitmap); 100 int 101 ice_move_vsi_to_agg(struct ice_port_info *pi, u32 agg_id, u16 vsi_handle, 102 u8 tc_bitmap); 103 int 104 ice_cfg_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 105 u16 q_handle, enum ice_rl_type rl_type, u32 bw); 106 int 107 ice_cfg_q_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 108 u16 q_handle, enum ice_rl_type rl_type); 109 int 110 ice_cfg_vsi_bw_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 111 enum ice_rl_type rl_type, u32 bw); 112 int 113 ice_cfg_vsi_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc, 114 enum ice_rl_type rl_type); 115 int 116 ice_sched_set_node_bw_lmt_per_tc(struct ice_port_info *pi, u32 id, 117 enum ice_agg_type agg_type, u8 tc, 118 enum ice_rl_type rl_type, u32 bw); 119 int ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes); 120 void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw); 121 void ice_sched_replay_agg(struct ice_hw *hw); 122 int ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle); 123 int ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx); 124 #endif /* _ICE_SCHED_H_ */ 125