1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
3 
4 #ifndef _ICE_SCHED_H_
5 #define _ICE_SCHED_H_
6 
7 #include "ice_common.h"
8 
9 #define ICE_QGRP_LAYER_OFFSET	2
10 #define ICE_VSI_LAYER_OFFSET	4
11 #define ICE_SCHED_INVAL_LAYER_NUM	0xFF
12 /* Burst size is a 12 bits register that is configured while creating the RL
13  * profile(s). MSB is a granularity bit and tells the granularity type
14  * 0 - LSB bits are in 64 bytes granularity
15  * 1 - LSB bits are in 1K bytes granularity
16  */
17 #define ICE_64_BYTE_GRANULARITY			0
18 #define ICE_KBYTE_GRANULARITY			BIT(11)
19 #define ICE_MIN_BURST_SIZE_ALLOWED		64 /* In Bytes */
20 #define ICE_MAX_BURST_SIZE_ALLOWED \
21 	((BIT(11) - 1) * 1024) /* In Bytes */
22 #define ICE_MAX_BURST_SIZE_64_BYTE_GRANULARITY \
23 	((BIT(11) - 1) * 64) /* In Bytes */
24 #define ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY	ICE_MAX_BURST_SIZE_ALLOWED
25 
26 #define ICE_RL_PROF_FREQUENCY 446000000
27 #define ICE_RL_PROF_ACCURACY_BYTES 128
28 #define ICE_RL_PROF_MULTIPLIER 10000
29 #define ICE_RL_PROF_TS_MULTIPLIER 32
30 #define ICE_RL_PROF_FRACTION 512
31 
32 /* BW rate limit profile parameters list entry along
33  * with bandwidth maintained per layer in port info
34  */
35 struct ice_aqc_rl_profile_info {
36 	struct ice_aqc_rl_profile_elem profile;
37 	struct list_head list_entry;
38 	u32 bw;			/* requested */
39 	u16 prof_id_ref;	/* profile ID to node association ref count */
40 };
41 
42 struct ice_sched_agg_vsi_info {
43 	struct list_head list_entry;
44 	DECLARE_BITMAP(tc_bitmap, ICE_MAX_TRAFFIC_CLASS);
45 	u16 vsi_handle;
46 };
47 
48 struct ice_sched_agg_info {
49 	struct list_head agg_vsi_list;
50 	struct list_head list_entry;
51 	DECLARE_BITMAP(tc_bitmap, ICE_MAX_TRAFFIC_CLASS);
52 	u32 agg_id;
53 	enum ice_agg_type agg_type;
54 };
55 
56 /* FW AQ command calls */
57 enum ice_status
58 ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req,
59 			 struct ice_aqc_get_elem *buf, u16 buf_size,
60 			 u16 *elems_ret, struct ice_sq_cd *cd);
61 enum ice_status ice_sched_init_port(struct ice_port_info *pi);
62 enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw);
63 void ice_sched_clear_port(struct ice_port_info *pi);
64 void ice_sched_cleanup_all(struct ice_hw *hw);
65 void ice_sched_clear_agg(struct ice_hw *hw);
66 
67 struct ice_sched_node *
68 ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid);
69 enum ice_status
70 ice_sched_add_node(struct ice_port_info *pi, u8 layer,
71 		   struct ice_aqc_txsched_elem_data *info);
72 void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node);
73 struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc);
74 struct ice_sched_node *
75 ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
76 			   u8 owner);
77 enum ice_status
78 ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 maxqs,
79 		  u8 owner, bool enable);
80 enum ice_status ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle);
81 enum ice_status
82 ice_cfg_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
83 		 u16 q_handle, enum ice_rl_type rl_type, u32 bw);
84 enum ice_status
85 ice_cfg_q_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
86 		      u16 q_handle, enum ice_rl_type rl_type);
87 enum ice_status ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes);
88 enum ice_status
89 ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx);
90 #endif /* _ICE_SCHED_H_ */
91