1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2021, Intel Corporation. */ 3 4 #ifndef _ICE_PTP_HW_H_ 5 #define _ICE_PTP_HW_H_ 6 7 enum ice_ptp_tmr_cmd { 8 INIT_TIME, 9 INIT_INCVAL, 10 ADJ_TIME, 11 ADJ_TIME_AT_TIME, 12 READ_TIME 13 }; 14 15 /* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for 16 * the E810 devices. Based off of a PLL with an 812.5 MHz frequency. 17 */ 18 #define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL 19 20 /* Device agnostic functions */ 21 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw); 22 bool ice_ptp_lock(struct ice_hw *hw); 23 void ice_ptp_unlock(struct ice_hw *hw); 24 int ice_ptp_init_time(struct ice_hw *hw, u64 time); 25 int ice_ptp_write_incval(struct ice_hw *hw, u64 incval); 26 int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval); 27 int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj); 28 int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp); 29 int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx); 30 31 /* E810 family functions */ 32 int ice_ptp_init_phy_e810(struct ice_hw *hw); 33 int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data); 34 int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data); 35 bool ice_is_pca9575_present(struct ice_hw *hw); 36 37 #define PFTSYN_SEM_BYTES 4 38 39 /* PHY timer commands */ 40 #define SEL_CPK_SRC 8 41 42 /* Time Sync command Definitions */ 43 #define GLTSYN_CMD_INIT_TIME BIT(0) 44 #define GLTSYN_CMD_INIT_INCVAL BIT(1) 45 #define GLTSYN_CMD_ADJ_TIME BIT(2) 46 #define GLTSYN_CMD_ADJ_INIT_TIME (BIT(2) | BIT(3)) 47 #define GLTSYN_CMD_READ_TIME BIT(7) 48 49 #define TS_CMD_MASK_E810 0xFF 50 #define SYNC_EXEC_CMD 0x3 51 52 /* E810 timesync enable register */ 53 #define ETH_GLTSYN_ENA(_i) (0x03000348 + ((_i) * 4)) 54 55 /* E810 shadow init time registers */ 56 #define ETH_GLTSYN_SHTIME_0(i) (0x03000368 + ((i) * 32)) 57 #define ETH_GLTSYN_SHTIME_L(i) (0x0300036C + ((i) * 32)) 58 59 /* E810 shadow time adjust registers */ 60 #define ETH_GLTSYN_SHADJ_L(_i) (0x03000378 + ((_i) * 32)) 61 #define ETH_GLTSYN_SHADJ_H(_i) (0x0300037C + ((_i) * 32)) 62 63 /* E810 timer command register */ 64 #define ETH_GLTSYN_CMD 0x03000344 65 66 /* Source timer incval macros */ 67 #define INCVAL_HIGH_M 0xFF 68 69 /* Timestamp block macros */ 70 #define TS_LOW_M 0xFFFFFFFF 71 #define TS_HIGH_S 32 72 73 #define BYTES_PER_IDX_ADDR_L_U 8 74 75 /* External PHY timestamp address */ 76 #define TS_EXT(a, port, idx) ((a) + (0x1000 * (port)) + \ 77 ((idx) * BYTES_PER_IDX_ADDR_L_U)) 78 79 #define LOW_TX_MEMORY_BANK_START 0x03090000 80 #define HIGH_TX_MEMORY_BANK_START 0x03090004 81 82 /* E810T SMA controller pin control */ 83 #define ICE_SMA1_DIR_EN_E810T BIT(4) 84 #define ICE_SMA1_TX_EN_E810T BIT(5) 85 #define ICE_SMA2_UFL2_RX_DIS_E810T BIT(3) 86 #define ICE_SMA2_DIR_EN_E810T BIT(6) 87 #define ICE_SMA2_TX_EN_E810T BIT(7) 88 89 #define ICE_SMA1_MASK_E810T (ICE_SMA1_DIR_EN_E810T | \ 90 ICE_SMA1_TX_EN_E810T) 91 #define ICE_SMA2_MASK_E810T (ICE_SMA2_UFL2_RX_DIS_E810T | \ 92 ICE_SMA2_DIR_EN_E810T | \ 93 ICE_SMA2_TX_EN_E810T) 94 #define ICE_ALL_SMA_MASK_E810T (ICE_SMA1_MASK_E810T | \ 95 ICE_SMA2_MASK_E810T) 96 97 #define ICE_SMA_MIN_BIT_E810T 3 98 #define ICE_SMA_MAX_BIT_E810T 7 99 #define ICE_PCA9575_P1_OFFSET 8 100 101 #endif /* _ICE_PTP_HW_H_ */ 102