103cb4473SJacob Keller /* SPDX-License-Identifier: GPL-2.0 */ 203cb4473SJacob Keller /* Copyright (C) 2021, Intel Corporation. */ 303cb4473SJacob Keller 403cb4473SJacob Keller #ifndef _ICE_PTP_HW_H_ 503cb4473SJacob Keller #define _ICE_PTP_HW_H_ 603cb4473SJacob Keller 703cb4473SJacob Keller enum ice_ptp_tmr_cmd { 803cb4473SJacob Keller INIT_TIME, 903cb4473SJacob Keller INIT_INCVAL, 1003cb4473SJacob Keller ADJ_TIME, 1103cb4473SJacob Keller ADJ_TIME_AT_TIME, 1203cb4473SJacob Keller READ_TIME 1303cb4473SJacob Keller }; 1403cb4473SJacob Keller 153a749623SJacob Keller enum ice_ptp_serdes { 163a749623SJacob Keller ICE_PTP_SERDES_1G, 173a749623SJacob Keller ICE_PTP_SERDES_10G, 183a749623SJacob Keller ICE_PTP_SERDES_25G, 193a749623SJacob Keller ICE_PTP_SERDES_40G, 203a749623SJacob Keller ICE_PTP_SERDES_50G, 213a749623SJacob Keller ICE_PTP_SERDES_100G 223a749623SJacob Keller }; 233a749623SJacob Keller 243a749623SJacob Keller enum ice_ptp_link_spd { 253a749623SJacob Keller ICE_PTP_LNK_SPD_1G, 263a749623SJacob Keller ICE_PTP_LNK_SPD_10G, 273a749623SJacob Keller ICE_PTP_LNK_SPD_25G, 283a749623SJacob Keller ICE_PTP_LNK_SPD_25G_RS, 293a749623SJacob Keller ICE_PTP_LNK_SPD_40G, 303a749623SJacob Keller ICE_PTP_LNK_SPD_50G, 313a749623SJacob Keller ICE_PTP_LNK_SPD_50G_RS, 323a749623SJacob Keller ICE_PTP_LNK_SPD_100G_RS, 333a749623SJacob Keller NUM_ICE_PTP_LNK_SPD /* Must be last */ 343a749623SJacob Keller }; 353a749623SJacob Keller 363a749623SJacob Keller enum ice_ptp_fec_mode { 373a749623SJacob Keller ICE_PTP_FEC_MODE_NONE, 383a749623SJacob Keller ICE_PTP_FEC_MODE_CLAUSE74, 393a749623SJacob Keller ICE_PTP_FEC_MODE_RS_FEC 403a749623SJacob Keller }; 413a749623SJacob Keller 423a749623SJacob Keller /** 433a749623SJacob Keller * struct ice_time_ref_info_e822 443a749623SJacob Keller * @pll_freq: Frequency of PLL that drives timer ticks in Hz 453a749623SJacob Keller * @nominal_incval: increment to generate nanoseconds in GLTSYN_TIME_L 463a749623SJacob Keller * @pps_delay: propagation delay of the PPS output signal 473a749623SJacob Keller * 483a749623SJacob Keller * Characteristic information for the various TIME_REF sources possible in the 493a749623SJacob Keller * E822 devices 503a749623SJacob Keller */ 513a749623SJacob Keller struct ice_time_ref_info_e822 { 523a749623SJacob Keller u64 pll_freq; 533a749623SJacob Keller u64 nominal_incval; 543a749623SJacob Keller u8 pps_delay; 553a749623SJacob Keller }; 563a749623SJacob Keller 573a749623SJacob Keller /** 583a749623SJacob Keller * struct ice_vernier_info_e822 593a749623SJacob Keller * @tx_par_clk: Frequency used to calculate P_REG_PAR_TX_TUS 603a749623SJacob Keller * @rx_par_clk: Frequency used to calculate P_REG_PAR_RX_TUS 613a749623SJacob Keller * @tx_pcs_clk: Frequency used to calculate P_REG_PCS_TX_TUS 623a749623SJacob Keller * @rx_pcs_clk: Frequency used to calculate P_REG_PCS_RX_TUS 633a749623SJacob Keller * @tx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_TX_TUS 643a749623SJacob Keller * @rx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_RX_TUS 653a749623SJacob Keller * @tx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_TX_TUS 663a749623SJacob Keller * @rx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_RX_TUS 673a749623SJacob Keller * @tx_fixed_delay: Fixed Tx latency measured in 1/100th nanoseconds 683a749623SJacob Keller * @pmd_adj_divisor: Divisor used to calculate PDM alignment adjustment 693a749623SJacob Keller * @rx_fixed_delay: Fixed Rx latency measured in 1/100th nanoseconds 703a749623SJacob Keller * 713a749623SJacob Keller * Table of constants used during as part of the Vernier calibration of the Tx 723a749623SJacob Keller * and Rx timestamps. This includes frequency values used to compute TUs per 733a749623SJacob Keller * PAR/PCS clock cycle, and static delay values measured during hardware 743a749623SJacob Keller * design. 753a749623SJacob Keller * 763a749623SJacob Keller * Note that some values are not used for all link speeds, and the 773a749623SJacob Keller * P_REG_DESK_PAR* registers may represent different clock markers at 783a749623SJacob Keller * different link speeds, either the deskew marker for multi-lane link speeds 793a749623SJacob Keller * or the Reed Solomon gearbox marker for RS-FEC. 803a749623SJacob Keller */ 813a749623SJacob Keller struct ice_vernier_info_e822 { 823a749623SJacob Keller u32 tx_par_clk; 833a749623SJacob Keller u32 rx_par_clk; 843a749623SJacob Keller u32 tx_pcs_clk; 853a749623SJacob Keller u32 rx_pcs_clk; 863a749623SJacob Keller u32 tx_desk_rsgb_par; 873a749623SJacob Keller u32 rx_desk_rsgb_par; 883a749623SJacob Keller u32 tx_desk_rsgb_pcs; 893a749623SJacob Keller u32 rx_desk_rsgb_pcs; 903a749623SJacob Keller u32 tx_fixed_delay; 913a749623SJacob Keller u32 pmd_adj_divisor; 923a749623SJacob Keller u32 rx_fixed_delay; 933a749623SJacob Keller }; 943a749623SJacob Keller 95b111ab5aSJacob Keller /** 96b111ab5aSJacob Keller * struct ice_cgu_pll_params_e822 97b111ab5aSJacob Keller * @refclk_pre_div: Reference clock pre-divisor 98b111ab5aSJacob Keller * @feedback_div: Feedback divisor 99b111ab5aSJacob Keller * @frac_n_div: Fractional divisor 100b111ab5aSJacob Keller * @post_pll_div: Post PLL divisor 101b111ab5aSJacob Keller * 102b111ab5aSJacob Keller * Clock Generation Unit parameters used to program the PLL based on the 103b111ab5aSJacob Keller * selected TIME_REF frequency. 104b111ab5aSJacob Keller */ 105b111ab5aSJacob Keller struct ice_cgu_pll_params_e822 { 106b111ab5aSJacob Keller u32 refclk_pre_div; 107b111ab5aSJacob Keller u32 feedback_div; 108b111ab5aSJacob Keller u32 frac_n_div; 109b111ab5aSJacob Keller u32 post_pll_div; 110b111ab5aSJacob Keller }; 111b111ab5aSJacob Keller 112b111ab5aSJacob Keller extern const struct 113b111ab5aSJacob Keller ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ]; 114b111ab5aSJacob Keller 1153a749623SJacob Keller /* Table of constants related to possible TIME_REF sources */ 1163a749623SJacob Keller extern const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ]; 1173a749623SJacob Keller 1183a749623SJacob Keller /* Table of constants for Vernier calibration on E822 */ 1193a749623SJacob Keller extern const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD]; 1203a749623SJacob Keller 12103cb4473SJacob Keller /* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for 12203cb4473SJacob Keller * the E810 devices. Based off of a PLL with an 812.5 MHz frequency. 12303cb4473SJacob Keller */ 12403cb4473SJacob Keller #define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL 12503cb4473SJacob Keller 12603cb4473SJacob Keller /* Device agnostic functions */ 12703cb4473SJacob Keller u8 ice_get_ptp_src_clock_index(struct ice_hw *hw); 12803cb4473SJacob Keller bool ice_ptp_lock(struct ice_hw *hw); 12903cb4473SJacob Keller void ice_ptp_unlock(struct ice_hw *hw); 13003cb4473SJacob Keller int ice_ptp_init_time(struct ice_hw *hw, u64 time); 13103cb4473SJacob Keller int ice_ptp_write_incval(struct ice_hw *hw, u64 incval); 13203cb4473SJacob Keller int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval); 13303cb4473SJacob Keller int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj); 13403cb4473SJacob Keller int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp); 13503cb4473SJacob Keller int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx); 136b2ee7256SJacob Keller int ice_ptp_init_phc(struct ice_hw *hw); 13703cb4473SJacob Keller 1383a749623SJacob Keller /* E822 family functions */ 1393a749623SJacob Keller int ice_read_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 *val); 1403a749623SJacob Keller int ice_write_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 val); 1413a749623SJacob Keller int ice_read_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 *val); 1423a749623SJacob Keller int ice_write_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 val); 1433a749623SJacob Keller int ice_ptp_prep_port_adj_e822(struct ice_hw *hw, u8 port, s64 time); 1443a749623SJacob Keller 1453a749623SJacob Keller /** 1463a749623SJacob Keller * ice_e822_time_ref - Get the current TIME_REF from capabilities 1473a749623SJacob Keller * @hw: pointer to the HW structure 1483a749623SJacob Keller * 1493a749623SJacob Keller * Returns the current TIME_REF from the capabilities structure. 1503a749623SJacob Keller */ 1513a749623SJacob Keller static inline enum ice_time_ref_freq ice_e822_time_ref(struct ice_hw *hw) 1523a749623SJacob Keller { 1533a749623SJacob Keller return hw->func_caps.ts_func_info.time_ref; 1543a749623SJacob Keller } 1553a749623SJacob Keller 1563a749623SJacob Keller /** 1573a749623SJacob Keller * ice_set_e822_time_ref - Set new TIME_REF 1583a749623SJacob Keller * @hw: pointer to the HW structure 1593a749623SJacob Keller * @time_ref: new TIME_REF to set 1603a749623SJacob Keller * 1613a749623SJacob Keller * Update the TIME_REF in the capabilities structure in response to some 1623a749623SJacob Keller * change, such as an update to the CGU registers. 1633a749623SJacob Keller */ 1643a749623SJacob Keller static inline void 1653a749623SJacob Keller ice_set_e822_time_ref(struct ice_hw *hw, enum ice_time_ref_freq time_ref) 1663a749623SJacob Keller { 1673a749623SJacob Keller hw->func_caps.ts_func_info.time_ref = time_ref; 1683a749623SJacob Keller } 1693a749623SJacob Keller 1703a749623SJacob Keller static inline u64 ice_e822_pll_freq(enum ice_time_ref_freq time_ref) 1713a749623SJacob Keller { 1723a749623SJacob Keller return e822_time_ref[time_ref].pll_freq; 1733a749623SJacob Keller } 1743a749623SJacob Keller 1753a749623SJacob Keller static inline u64 ice_e822_nominal_incval(enum ice_time_ref_freq time_ref) 1763a749623SJacob Keller { 1773a749623SJacob Keller return e822_time_ref[time_ref].nominal_incval; 1783a749623SJacob Keller } 1793a749623SJacob Keller 1803a749623SJacob Keller static inline u64 ice_e822_pps_delay(enum ice_time_ref_freq time_ref) 1813a749623SJacob Keller { 1823a749623SJacob Keller return e822_time_ref[time_ref].pps_delay; 1833a749623SJacob Keller } 1843a749623SJacob Keller 1853a749623SJacob Keller /* E822 Vernier calibration functions */ 1863a749623SJacob Keller int ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset); 187*0357d5caSMilena Olech int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port); 188*0357d5caSMilena Olech int ice_phy_calc_vernier_e822(struct ice_hw *hw, u8 port); 1893a749623SJacob Keller 19003cb4473SJacob Keller /* E810 family functions */ 19103cb4473SJacob Keller int ice_ptp_init_phy_e810(struct ice_hw *hw); 192885fe693SMaciej Machnikowski int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data); 193885fe693SMaciej Machnikowski int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data); 19443113ff7SKarol Kolacinski int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data); 195885fe693SMaciej Machnikowski bool ice_is_pca9575_present(struct ice_hw *hw); 19603cb4473SJacob Keller 19703cb4473SJacob Keller #define PFTSYN_SEM_BYTES 4 19803cb4473SJacob Keller 1993a749623SJacob Keller #define ICE_PTP_CLOCK_INDEX_0 0x00 2003a749623SJacob Keller #define ICE_PTP_CLOCK_INDEX_1 0x01 2013a749623SJacob Keller 20203cb4473SJacob Keller /* PHY timer commands */ 20303cb4473SJacob Keller #define SEL_CPK_SRC 8 2043a749623SJacob Keller #define SEL_PHY_SRC 3 20503cb4473SJacob Keller 20603cb4473SJacob Keller /* Time Sync command Definitions */ 20703cb4473SJacob Keller #define GLTSYN_CMD_INIT_TIME BIT(0) 20803cb4473SJacob Keller #define GLTSYN_CMD_INIT_INCVAL BIT(1) 2093a749623SJacob Keller #define GLTSYN_CMD_INIT_TIME_INCVAL (BIT(0) | BIT(1)) 21003cb4473SJacob Keller #define GLTSYN_CMD_ADJ_TIME BIT(2) 21103cb4473SJacob Keller #define GLTSYN_CMD_ADJ_INIT_TIME (BIT(2) | BIT(3)) 21203cb4473SJacob Keller #define GLTSYN_CMD_READ_TIME BIT(7) 21303cb4473SJacob Keller 2143a749623SJacob Keller /* PHY port Time Sync command definitions */ 2153a749623SJacob Keller #define PHY_CMD_INIT_TIME BIT(0) 2163a749623SJacob Keller #define PHY_CMD_INIT_INCVAL BIT(1) 2173a749623SJacob Keller #define PHY_CMD_ADJ_TIME (BIT(0) | BIT(1)) 2183a749623SJacob Keller #define PHY_CMD_ADJ_TIME_AT_TIME (BIT(0) | BIT(2)) 2193a749623SJacob Keller #define PHY_CMD_READ_TIME (BIT(0) | BIT(1) | BIT(2)) 2203a749623SJacob Keller 22103cb4473SJacob Keller #define TS_CMD_MASK_E810 0xFF 2223a749623SJacob Keller #define TS_CMD_MASK 0xF 22303cb4473SJacob Keller #define SYNC_EXEC_CMD 0x3 22403cb4473SJacob Keller 2253a749623SJacob Keller /* Macros to derive port low and high addresses on both quads */ 2263a749623SJacob Keller #define P_Q0_L(a, p) ((((a) + (0x2000 * (p)))) & 0xFFFF) 2273a749623SJacob Keller #define P_Q0_H(a, p) ((((a) + (0x2000 * (p)))) >> 16) 2283a749623SJacob Keller #define P_Q1_L(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) & 0xFFFF) 2293a749623SJacob Keller #define P_Q1_H(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) >> 16) 2303a749623SJacob Keller 2313a749623SJacob Keller /* PHY QUAD register base addresses */ 2323a749623SJacob Keller #define Q_0_BASE 0x94000 2333a749623SJacob Keller #define Q_1_BASE 0x114000 2343a749623SJacob Keller 2353a749623SJacob Keller /* Timestamp memory reset registers */ 2363a749623SJacob Keller #define Q_REG_TS_CTRL 0x618 2373a749623SJacob Keller #define Q_REG_TS_CTRL_S 0 2383a749623SJacob Keller #define Q_REG_TS_CTRL_M BIT(0) 2393a749623SJacob Keller 2403a749623SJacob Keller /* Timestamp availability status registers */ 2413a749623SJacob Keller #define Q_REG_TX_MEMORY_STATUS_L 0xCF0 2423a749623SJacob Keller #define Q_REG_TX_MEMORY_STATUS_U 0xCF4 2433a749623SJacob Keller 2443a749623SJacob Keller /* Tx FIFO status registers */ 2453a749623SJacob Keller #define Q_REG_FIFO23_STATUS 0xCF8 2463a749623SJacob Keller #define Q_REG_FIFO01_STATUS 0xCFC 2473a749623SJacob Keller #define Q_REG_FIFO02_S 0 2483a749623SJacob Keller #define Q_REG_FIFO02_M ICE_M(0x3FF, 0) 2493a749623SJacob Keller #define Q_REG_FIFO13_S 10 2503a749623SJacob Keller #define Q_REG_FIFO13_M ICE_M(0x3FF, 10) 2513a749623SJacob Keller 2523a749623SJacob Keller /* Interrupt control Config registers */ 2533a749623SJacob Keller #define Q_REG_TX_MEM_GBL_CFG 0xC08 2543a749623SJacob Keller #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S 0 2553a749623SJacob Keller #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M BIT(0) 2563a749623SJacob Keller #define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_S 1 2573a749623SJacob Keller #define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M ICE_M(0xFF, 1) 2583a749623SJacob Keller #define Q_REG_TX_MEM_GBL_CFG_INTR_THR_S 9 2593a749623SJacob Keller #define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M ICE_M(0x3F, 9) 2603a749623SJacob Keller #define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_S 15 2613a749623SJacob Keller #define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M BIT(15) 2623a749623SJacob Keller 2633a749623SJacob Keller /* Tx Timestamp data registers */ 2643a749623SJacob Keller #define Q_REG_TX_MEMORY_BANK_START 0xA00 2653a749623SJacob Keller 2663a749623SJacob Keller /* PHY port register base addresses */ 2673a749623SJacob Keller #define P_0_BASE 0x80000 2683a749623SJacob Keller #define P_4_BASE 0x106000 2693a749623SJacob Keller 2703a749623SJacob Keller /* Timestamp init registers */ 2713a749623SJacob Keller #define P_REG_RX_TIMER_INC_PRE_L 0x46C 2723a749623SJacob Keller #define P_REG_RX_TIMER_INC_PRE_U 0x470 2733a749623SJacob Keller #define P_REG_TX_TIMER_INC_PRE_L 0x44C 2743a749623SJacob Keller #define P_REG_TX_TIMER_INC_PRE_U 0x450 2753a749623SJacob Keller 2763a749623SJacob Keller /* Timestamp match and adjust target registers */ 2773a749623SJacob Keller #define P_REG_RX_TIMER_CNT_ADJ_L 0x474 2783a749623SJacob Keller #define P_REG_RX_TIMER_CNT_ADJ_U 0x478 2793a749623SJacob Keller #define P_REG_TX_TIMER_CNT_ADJ_L 0x454 2803a749623SJacob Keller #define P_REG_TX_TIMER_CNT_ADJ_U 0x458 2813a749623SJacob Keller 2823a749623SJacob Keller /* Timestamp capture registers */ 2833a749623SJacob Keller #define P_REG_RX_CAPTURE_L 0x4D8 2843a749623SJacob Keller #define P_REG_RX_CAPTURE_U 0x4DC 2853a749623SJacob Keller #define P_REG_TX_CAPTURE_L 0x4B4 2863a749623SJacob Keller #define P_REG_TX_CAPTURE_U 0x4B8 2873a749623SJacob Keller 2883a749623SJacob Keller /* Timestamp PHY incval registers */ 2893a749623SJacob Keller #define P_REG_TIMETUS_L 0x410 2903a749623SJacob Keller #define P_REG_TIMETUS_U 0x414 2913a749623SJacob Keller 2923a749623SJacob Keller #define P_REG_40B_LOW_M 0xFF 2933a749623SJacob Keller #define P_REG_40B_HIGH_S 8 2943a749623SJacob Keller 2953a749623SJacob Keller /* PHY window length registers */ 2963a749623SJacob Keller #define P_REG_WL 0x40C 2973a749623SJacob Keller 2983a749623SJacob Keller #define PTP_VERNIER_WL 0x111ed 2993a749623SJacob Keller 3003a749623SJacob Keller /* PHY start registers */ 3013a749623SJacob Keller #define P_REG_PS 0x408 3023a749623SJacob Keller #define P_REG_PS_START_S 0 3033a749623SJacob Keller #define P_REG_PS_START_M BIT(0) 3043a749623SJacob Keller #define P_REG_PS_BYPASS_MODE_S 1 3053a749623SJacob Keller #define P_REG_PS_BYPASS_MODE_M BIT(1) 3063a749623SJacob Keller #define P_REG_PS_ENA_CLK_S 2 3073a749623SJacob Keller #define P_REG_PS_ENA_CLK_M BIT(2) 3083a749623SJacob Keller #define P_REG_PS_LOAD_OFFSET_S 3 3093a749623SJacob Keller #define P_REG_PS_LOAD_OFFSET_M BIT(3) 3103a749623SJacob Keller #define P_REG_PS_SFT_RESET_S 11 3113a749623SJacob Keller #define P_REG_PS_SFT_RESET_M BIT(11) 3123a749623SJacob Keller 3133a749623SJacob Keller /* PHY offset valid registers */ 3143a749623SJacob Keller #define P_REG_TX_OV_STATUS 0x4D4 3153a749623SJacob Keller #define P_REG_TX_OV_STATUS_OV_S 0 3163a749623SJacob Keller #define P_REG_TX_OV_STATUS_OV_M BIT(0) 3173a749623SJacob Keller #define P_REG_RX_OV_STATUS 0x4F8 3183a749623SJacob Keller #define P_REG_RX_OV_STATUS_OV_S 0 3193a749623SJacob Keller #define P_REG_RX_OV_STATUS_OV_M BIT(0) 3203a749623SJacob Keller 3213a749623SJacob Keller /* PHY offset ready registers */ 3223a749623SJacob Keller #define P_REG_TX_OR 0x45C 3233a749623SJacob Keller #define P_REG_RX_OR 0x47C 3243a749623SJacob Keller 3253a749623SJacob Keller /* PHY total offset registers */ 3263a749623SJacob Keller #define P_REG_TOTAL_RX_OFFSET_L 0x460 3273a749623SJacob Keller #define P_REG_TOTAL_RX_OFFSET_U 0x464 3283a749623SJacob Keller #define P_REG_TOTAL_TX_OFFSET_L 0x440 3293a749623SJacob Keller #define P_REG_TOTAL_TX_OFFSET_U 0x444 3303a749623SJacob Keller 3313a749623SJacob Keller /* Timestamp PAR/PCS registers */ 3323a749623SJacob Keller #define P_REG_UIX66_10G_40G_L 0x480 3333a749623SJacob Keller #define P_REG_UIX66_10G_40G_U 0x484 3343a749623SJacob Keller #define P_REG_UIX66_25G_100G_L 0x488 3353a749623SJacob Keller #define P_REG_UIX66_25G_100G_U 0x48C 3363a749623SJacob Keller #define P_REG_DESK_PAR_RX_TUS_L 0x490 3373a749623SJacob Keller #define P_REG_DESK_PAR_RX_TUS_U 0x494 3383a749623SJacob Keller #define P_REG_DESK_PAR_TX_TUS_L 0x498 3393a749623SJacob Keller #define P_REG_DESK_PAR_TX_TUS_U 0x49C 3403a749623SJacob Keller #define P_REG_DESK_PCS_RX_TUS_L 0x4A0 3413a749623SJacob Keller #define P_REG_DESK_PCS_RX_TUS_U 0x4A4 3423a749623SJacob Keller #define P_REG_DESK_PCS_TX_TUS_L 0x4A8 3433a749623SJacob Keller #define P_REG_DESK_PCS_TX_TUS_U 0x4AC 3443a749623SJacob Keller #define P_REG_PAR_RX_TUS_L 0x420 3453a749623SJacob Keller #define P_REG_PAR_RX_TUS_U 0x424 3463a749623SJacob Keller #define P_REG_PAR_TX_TUS_L 0x428 3473a749623SJacob Keller #define P_REG_PAR_TX_TUS_U 0x42C 3483a749623SJacob Keller #define P_REG_PCS_RX_TUS_L 0x430 3493a749623SJacob Keller #define P_REG_PCS_RX_TUS_U 0x434 3503a749623SJacob Keller #define P_REG_PCS_TX_TUS_L 0x438 3513a749623SJacob Keller #define P_REG_PCS_TX_TUS_U 0x43C 3523a749623SJacob Keller #define P_REG_PAR_RX_TIME_L 0x4F0 3533a749623SJacob Keller #define P_REG_PAR_RX_TIME_U 0x4F4 3543a749623SJacob Keller #define P_REG_PAR_TX_TIME_L 0x4CC 3553a749623SJacob Keller #define P_REG_PAR_TX_TIME_U 0x4D0 3563a749623SJacob Keller #define P_REG_PAR_PCS_RX_OFFSET_L 0x4E8 3573a749623SJacob Keller #define P_REG_PAR_PCS_RX_OFFSET_U 0x4EC 3583a749623SJacob Keller #define P_REG_PAR_PCS_TX_OFFSET_L 0x4C4 3593a749623SJacob Keller #define P_REG_PAR_PCS_TX_OFFSET_U 0x4C8 3603a749623SJacob Keller #define P_REG_LINK_SPEED 0x4FC 3613a749623SJacob Keller #define P_REG_LINK_SPEED_SERDES_S 0 3623a749623SJacob Keller #define P_REG_LINK_SPEED_SERDES_M ICE_M(0x7, 0) 3633a749623SJacob Keller #define P_REG_LINK_SPEED_FEC_MODE_S 3 3643a749623SJacob Keller #define P_REG_LINK_SPEED_FEC_MODE_M ICE_M(0x3, 3) 3653a749623SJacob Keller #define P_REG_LINK_SPEED_FEC_MODE(reg) \ 3663a749623SJacob Keller (((reg) & P_REG_LINK_SPEED_FEC_MODE_M) >> \ 3673a749623SJacob Keller P_REG_LINK_SPEED_FEC_MODE_S) 3683a749623SJacob Keller 3693a749623SJacob Keller /* PHY timestamp related registers */ 3703a749623SJacob Keller #define P_REG_PMD_ALIGNMENT 0x0FC 3713a749623SJacob Keller #define P_REG_RX_80_TO_160_CNT 0x6FC 3723a749623SJacob Keller #define P_REG_RX_80_TO_160_CNT_RXCYC_S 0 3733a749623SJacob Keller #define P_REG_RX_80_TO_160_CNT_RXCYC_M BIT(0) 3743a749623SJacob Keller #define P_REG_RX_40_TO_160_CNT 0x8FC 3753a749623SJacob Keller #define P_REG_RX_40_TO_160_CNT_RXCYC_S 0 3763a749623SJacob Keller #define P_REG_RX_40_TO_160_CNT_RXCYC_M ICE_M(0x3, 0) 3773a749623SJacob Keller 3783a749623SJacob Keller /* Rx FIFO status registers */ 3793a749623SJacob Keller #define P_REG_RX_OV_FS 0x4F8 3803a749623SJacob Keller #define P_REG_RX_OV_FS_FIFO_STATUS_S 2 3813a749623SJacob Keller #define P_REG_RX_OV_FS_FIFO_STATUS_M ICE_M(0x3FF, 2) 3823a749623SJacob Keller 3833a749623SJacob Keller /* Timestamp command registers */ 3843a749623SJacob Keller #define P_REG_TX_TMR_CMD 0x448 3853a749623SJacob Keller #define P_REG_RX_TMR_CMD 0x468 3863a749623SJacob Keller 38703cb4473SJacob Keller /* E810 timesync enable register */ 38803cb4473SJacob Keller #define ETH_GLTSYN_ENA(_i) (0x03000348 + ((_i) * 4)) 38903cb4473SJacob Keller 39003cb4473SJacob Keller /* E810 shadow init time registers */ 39103cb4473SJacob Keller #define ETH_GLTSYN_SHTIME_0(i) (0x03000368 + ((i) * 32)) 39203cb4473SJacob Keller #define ETH_GLTSYN_SHTIME_L(i) (0x0300036C + ((i) * 32)) 39303cb4473SJacob Keller 39403cb4473SJacob Keller /* E810 shadow time adjust registers */ 39503cb4473SJacob Keller #define ETH_GLTSYN_SHADJ_L(_i) (0x03000378 + ((_i) * 32)) 39603cb4473SJacob Keller #define ETH_GLTSYN_SHADJ_H(_i) (0x0300037C + ((_i) * 32)) 39703cb4473SJacob Keller 39803cb4473SJacob Keller /* E810 timer command register */ 39903cb4473SJacob Keller #define ETH_GLTSYN_CMD 0x03000344 40003cb4473SJacob Keller 40103cb4473SJacob Keller /* Source timer incval macros */ 40203cb4473SJacob Keller #define INCVAL_HIGH_M 0xFF 40303cb4473SJacob Keller 40403cb4473SJacob Keller /* Timestamp block macros */ 4051229b339SKarol Kolacinski #define TS_VALID BIT(0) 40603cb4473SJacob Keller #define TS_LOW_M 0xFFFFFFFF 4073a749623SJacob Keller #define TS_HIGH_M 0xFF 40803cb4473SJacob Keller #define TS_HIGH_S 32 40903cb4473SJacob Keller 4103a749623SJacob Keller #define TS_PHY_LOW_M 0xFF 4113a749623SJacob Keller #define TS_PHY_HIGH_M 0xFFFFFFFF 4123a749623SJacob Keller #define TS_PHY_HIGH_S 8 4133a749623SJacob Keller 41403cb4473SJacob Keller #define BYTES_PER_IDX_ADDR_L_U 8 4153a749623SJacob Keller #define BYTES_PER_IDX_ADDR_L 4 4163a749623SJacob Keller 4171229b339SKarol Kolacinski /* Tx timestamp low latency read definitions */ 4181229b339SKarol Kolacinski #define TS_LL_READ_RETRIES 200 4191229b339SKarol Kolacinski #define TS_LL_READ_TS_HIGH GENMASK(23, 16) 4201229b339SKarol Kolacinski #define TS_LL_READ_TS_IDX GENMASK(29, 24) 4211229b339SKarol Kolacinski #define TS_LL_READ_TS BIT(31) 4221229b339SKarol Kolacinski 4233a749623SJacob Keller /* Internal PHY timestamp address */ 4243a749623SJacob Keller #define TS_L(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U)) 4253a749623SJacob Keller #define TS_H(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U + \ 4263a749623SJacob Keller BYTES_PER_IDX_ADDR_L)) 42703cb4473SJacob Keller 42803cb4473SJacob Keller /* External PHY timestamp address */ 42903cb4473SJacob Keller #define TS_EXT(a, port, idx) ((a) + (0x1000 * (port)) + \ 43003cb4473SJacob Keller ((idx) * BYTES_PER_IDX_ADDR_L_U)) 43103cb4473SJacob Keller 43203cb4473SJacob Keller #define LOW_TX_MEMORY_BANK_START 0x03090000 43303cb4473SJacob Keller #define HIGH_TX_MEMORY_BANK_START 0x03090004 43403cb4473SJacob Keller 435885fe693SMaciej Machnikowski /* E810T SMA controller pin control */ 436885fe693SMaciej Machnikowski #define ICE_SMA1_DIR_EN_E810T BIT(4) 437885fe693SMaciej Machnikowski #define ICE_SMA1_TX_EN_E810T BIT(5) 438885fe693SMaciej Machnikowski #define ICE_SMA2_UFL2_RX_DIS_E810T BIT(3) 439885fe693SMaciej Machnikowski #define ICE_SMA2_DIR_EN_E810T BIT(6) 440885fe693SMaciej Machnikowski #define ICE_SMA2_TX_EN_E810T BIT(7) 441885fe693SMaciej Machnikowski 442885fe693SMaciej Machnikowski #define ICE_SMA1_MASK_E810T (ICE_SMA1_DIR_EN_E810T | \ 443885fe693SMaciej Machnikowski ICE_SMA1_TX_EN_E810T) 444885fe693SMaciej Machnikowski #define ICE_SMA2_MASK_E810T (ICE_SMA2_UFL2_RX_DIS_E810T | \ 445885fe693SMaciej Machnikowski ICE_SMA2_DIR_EN_E810T | \ 446885fe693SMaciej Machnikowski ICE_SMA2_TX_EN_E810T) 447885fe693SMaciej Machnikowski #define ICE_ALL_SMA_MASK_E810T (ICE_SMA1_MASK_E810T | \ 448885fe693SMaciej Machnikowski ICE_SMA2_MASK_E810T) 449885fe693SMaciej Machnikowski 450885fe693SMaciej Machnikowski #define ICE_SMA_MIN_BIT_E810T 3 451885fe693SMaciej Machnikowski #define ICE_SMA_MAX_BIT_E810T 7 452885fe693SMaciej Machnikowski #define ICE_PCA9575_P1_OFFSET 8 453885fe693SMaciej Machnikowski 45443113ff7SKarol Kolacinski /* E810T PCA9575 IO controller registers */ 45543113ff7SKarol Kolacinski #define ICE_PCA9575_P0_IN 0x0 45643113ff7SKarol Kolacinski 45743113ff7SKarol Kolacinski /* E810T PCA9575 IO controller pin control */ 45843113ff7SKarol Kolacinski #define ICE_E810T_P0_GNSS_PRSNT_N BIT(4) 45943113ff7SKarol Kolacinski 46003cb4473SJacob Keller #endif /* _ICE_PTP_HW_H_ */ 461