1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (C) 2021, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_ptp_hw.h" 6 #include "ice_ptp_consts.h" 7 #include "ice_cgu_regs.h" 8 9 /* Low level functions for interacting with and managing the device clock used 10 * for the Precision Time Protocol. 11 * 12 * The ice hardware represents the current time using three registers: 13 * 14 * GLTSYN_TIME_H GLTSYN_TIME_L GLTSYN_TIME_R 15 * +---------------+ +---------------+ +---------------+ 16 * | 32 bits | | 32 bits | | 32 bits | 17 * +---------------+ +---------------+ +---------------+ 18 * 19 * The registers are incremented every clock tick using a 40bit increment 20 * value defined over two registers: 21 * 22 * GLTSYN_INCVAL_H GLTSYN_INCVAL_L 23 * +---------------+ +---------------+ 24 * | 8 bit s | | 32 bits | 25 * +---------------+ +---------------+ 26 * 27 * The increment value is added to the GLSTYN_TIME_R and GLSTYN_TIME_L 28 * registers every clock source tick. Depending on the specific device 29 * configuration, the clock source frequency could be one of a number of 30 * values. 31 * 32 * For E810 devices, the increment frequency is 812.5 MHz 33 * 34 * For E822 devices the clock can be derived from different sources, and the 35 * increment has an effective frequency of one of the following: 36 * - 823.4375 MHz 37 * - 783.36 MHz 38 * - 796.875 MHz 39 * - 816 MHz 40 * - 830.078125 MHz 41 * - 783.36 MHz 42 * 43 * The hardware captures timestamps in the PHY for incoming packets, and for 44 * outgoing packets on request. To support this, the PHY maintains a timer 45 * that matches the lower 64 bits of the global source timer. 46 * 47 * In order to ensure that the PHY timers and the source timer are equivalent, 48 * shadow registers are used to prepare the desired initial values. A special 49 * sync command is issued to trigger copying from the shadow registers into 50 * the appropriate source and PHY registers simultaneously. 51 * 52 * The driver supports devices which have different PHYs with subtly different 53 * mechanisms to program and control the timers. We divide the devices into 54 * families named after the first major device, E810 and similar devices, and 55 * E822 and similar devices. 56 * 57 * - E822 based devices have additional support for fine grained Vernier 58 * calibration which requires significant setup 59 * - The layout of timestamp data in the PHY register blocks is different 60 * - The way timer synchronization commands are issued is different. 61 * 62 * To support this, very low level functions have an e810 or e822 suffix 63 * indicating what type of device they work on. Higher level abstractions for 64 * tasks that can be done on both devices do not have the suffix and will 65 * correctly look up the appropriate low level function when running. 66 * 67 * Functions which only make sense on a single device family may not have 68 * a suitable generic implementation 69 */ 70 71 /** 72 * ice_get_ptp_src_clock_index - determine source clock index 73 * @hw: pointer to HW struct 74 * 75 * Determine the source clock index currently in use, based on device 76 * capabilities reported during initialization. 77 */ 78 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw) 79 { 80 return hw->func_caps.ts_func_info.tmr_index_assoc; 81 } 82 83 /** 84 * ice_ptp_read_src_incval - Read source timer increment value 85 * @hw: pointer to HW struct 86 * 87 * Read the increment value of the source timer and return it. 88 */ 89 static u64 ice_ptp_read_src_incval(struct ice_hw *hw) 90 { 91 u32 lo, hi; 92 u8 tmr_idx; 93 94 tmr_idx = ice_get_ptp_src_clock_index(hw); 95 96 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 97 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 98 99 return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo; 100 } 101 102 /** 103 * ice_ptp_src_cmd - Prepare source timer for a timer command 104 * @hw: pointer to HW structure 105 * @cmd: Timer command 106 * 107 * Prepare the source timer for an upcoming timer sync command. 108 */ 109 static void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 110 { 111 u32 cmd_val; 112 u8 tmr_idx; 113 114 tmr_idx = ice_get_ptp_src_clock_index(hw); 115 cmd_val = tmr_idx << SEL_CPK_SRC; 116 117 switch (cmd) { 118 case INIT_TIME: 119 cmd_val |= GLTSYN_CMD_INIT_TIME; 120 break; 121 case INIT_INCVAL: 122 cmd_val |= GLTSYN_CMD_INIT_INCVAL; 123 break; 124 case ADJ_TIME: 125 cmd_val |= GLTSYN_CMD_ADJ_TIME; 126 break; 127 case ADJ_TIME_AT_TIME: 128 cmd_val |= GLTSYN_CMD_ADJ_INIT_TIME; 129 break; 130 case READ_TIME: 131 cmd_val |= GLTSYN_CMD_READ_TIME; 132 break; 133 } 134 135 wr32(hw, GLTSYN_CMD, cmd_val); 136 } 137 138 /** 139 * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands 140 * @hw: pointer to HW struct 141 * 142 * Write the SYNC_EXEC_CMD bit to the GLTSYN_CMD_SYNC register, and flush the 143 * write immediately. This triggers the hardware to begin executing all of the 144 * source and PHY timer commands synchronously. 145 */ 146 static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw) 147 { 148 wr32(hw, GLTSYN_CMD_SYNC, SYNC_EXEC_CMD); 149 ice_flush(hw); 150 } 151 152 /* E822 family functions 153 * 154 * The following functions operate on the E822 family of devices. 155 */ 156 157 /** 158 * ice_fill_phy_msg_e822 - Fill message data for a PHY register access 159 * @msg: the PHY message buffer to fill in 160 * @port: the port to access 161 * @offset: the register offset 162 */ 163 static void 164 ice_fill_phy_msg_e822(struct ice_sbq_msg_input *msg, u8 port, u16 offset) 165 { 166 int phy_port, phy, quadtype; 167 168 phy_port = port % ICE_PORTS_PER_PHY; 169 phy = port / ICE_PORTS_PER_PHY; 170 quadtype = (port / ICE_PORTS_PER_QUAD) % ICE_NUM_QUAD_TYPE; 171 172 if (quadtype == 0) { 173 msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port); 174 msg->msg_addr_high = P_Q0_H(P_0_BASE + offset, phy_port); 175 } else { 176 msg->msg_addr_low = P_Q1_L(P_4_BASE + offset, phy_port); 177 msg->msg_addr_high = P_Q1_H(P_4_BASE + offset, phy_port); 178 } 179 180 if (phy == 0) 181 msg->dest_dev = rmn_0; 182 else if (phy == 1) 183 msg->dest_dev = rmn_1; 184 else 185 msg->dest_dev = rmn_2; 186 } 187 188 /** 189 * ice_is_64b_phy_reg_e822 - Check if this is a 64bit PHY register 190 * @low_addr: the low address to check 191 * @high_addr: on return, contains the high address of the 64bit register 192 * 193 * Checks if the provided low address is one of the known 64bit PHY values 194 * represented as two 32bit registers. If it is, return the appropriate high 195 * register offset to use. 196 */ 197 static bool ice_is_64b_phy_reg_e822(u16 low_addr, u16 *high_addr) 198 { 199 switch (low_addr) { 200 case P_REG_PAR_PCS_TX_OFFSET_L: 201 *high_addr = P_REG_PAR_PCS_TX_OFFSET_U; 202 return true; 203 case P_REG_PAR_PCS_RX_OFFSET_L: 204 *high_addr = P_REG_PAR_PCS_RX_OFFSET_U; 205 return true; 206 case P_REG_PAR_TX_TIME_L: 207 *high_addr = P_REG_PAR_TX_TIME_U; 208 return true; 209 case P_REG_PAR_RX_TIME_L: 210 *high_addr = P_REG_PAR_RX_TIME_U; 211 return true; 212 case P_REG_TOTAL_TX_OFFSET_L: 213 *high_addr = P_REG_TOTAL_TX_OFFSET_U; 214 return true; 215 case P_REG_TOTAL_RX_OFFSET_L: 216 *high_addr = P_REG_TOTAL_RX_OFFSET_U; 217 return true; 218 case P_REG_UIX66_10G_40G_L: 219 *high_addr = P_REG_UIX66_10G_40G_U; 220 return true; 221 case P_REG_UIX66_25G_100G_L: 222 *high_addr = P_REG_UIX66_25G_100G_U; 223 return true; 224 case P_REG_TX_CAPTURE_L: 225 *high_addr = P_REG_TX_CAPTURE_U; 226 return true; 227 case P_REG_RX_CAPTURE_L: 228 *high_addr = P_REG_RX_CAPTURE_U; 229 return true; 230 case P_REG_TX_TIMER_INC_PRE_L: 231 *high_addr = P_REG_TX_TIMER_INC_PRE_U; 232 return true; 233 case P_REG_RX_TIMER_INC_PRE_L: 234 *high_addr = P_REG_RX_TIMER_INC_PRE_U; 235 return true; 236 default: 237 return false; 238 } 239 } 240 241 /** 242 * ice_is_40b_phy_reg_e822 - Check if this is a 40bit PHY register 243 * @low_addr: the low address to check 244 * @high_addr: on return, contains the high address of the 40bit value 245 * 246 * Checks if the provided low address is one of the known 40bit PHY values 247 * split into two registers with the lower 8 bits in the low register and the 248 * upper 32 bits in the high register. If it is, return the appropriate high 249 * register offset to use. 250 */ 251 static bool ice_is_40b_phy_reg_e822(u16 low_addr, u16 *high_addr) 252 { 253 switch (low_addr) { 254 case P_REG_TIMETUS_L: 255 *high_addr = P_REG_TIMETUS_U; 256 return true; 257 case P_REG_PAR_RX_TUS_L: 258 *high_addr = P_REG_PAR_RX_TUS_U; 259 return true; 260 case P_REG_PAR_TX_TUS_L: 261 *high_addr = P_REG_PAR_TX_TUS_U; 262 return true; 263 case P_REG_PCS_RX_TUS_L: 264 *high_addr = P_REG_PCS_RX_TUS_U; 265 return true; 266 case P_REG_PCS_TX_TUS_L: 267 *high_addr = P_REG_PCS_TX_TUS_U; 268 return true; 269 case P_REG_DESK_PAR_RX_TUS_L: 270 *high_addr = P_REG_DESK_PAR_RX_TUS_U; 271 return true; 272 case P_REG_DESK_PAR_TX_TUS_L: 273 *high_addr = P_REG_DESK_PAR_TX_TUS_U; 274 return true; 275 case P_REG_DESK_PCS_RX_TUS_L: 276 *high_addr = P_REG_DESK_PCS_RX_TUS_U; 277 return true; 278 case P_REG_DESK_PCS_TX_TUS_L: 279 *high_addr = P_REG_DESK_PCS_TX_TUS_U; 280 return true; 281 default: 282 return false; 283 } 284 } 285 286 /** 287 * ice_read_phy_reg_e822 - Read a PHY register 288 * @hw: pointer to the HW struct 289 * @port: PHY port to read from 290 * @offset: PHY register offset to read 291 * @val: on return, the contents read from the PHY 292 * 293 * Read a PHY register for the given port over the device sideband queue. 294 */ 295 int 296 ice_read_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 *val) 297 { 298 struct ice_sbq_msg_input msg = {0}; 299 int err; 300 301 ice_fill_phy_msg_e822(&msg, port, offset); 302 msg.opcode = ice_sbq_msg_rd; 303 304 err = ice_sbq_rw_reg(hw, &msg); 305 if (err) { 306 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 307 err); 308 return err; 309 } 310 311 *val = msg.data; 312 313 return 0; 314 } 315 316 /** 317 * ice_read_64b_phy_reg_e822 - Read a 64bit value from PHY registers 318 * @hw: pointer to the HW struct 319 * @port: PHY port to read from 320 * @low_addr: offset of the lower register to read from 321 * @val: on return, the contents of the 64bit value from the PHY registers 322 * 323 * Reads the two registers associated with a 64bit value and returns it in the 324 * val pointer. The offset always specifies the lower register offset to use. 325 * The high offset is looked up. This function only operates on registers 326 * known to be two parts of a 64bit value. 327 */ 328 static int 329 ice_read_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val) 330 { 331 u32 low, high; 332 u16 high_addr; 333 int err; 334 335 /* Only operate on registers known to be split into two 32bit 336 * registers. 337 */ 338 if (!ice_is_64b_phy_reg_e822(low_addr, &high_addr)) { 339 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n", 340 low_addr); 341 return -EINVAL; 342 } 343 344 err = ice_read_phy_reg_e822(hw, port, low_addr, &low); 345 if (err) { 346 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, err %d", 347 low_addr, err); 348 return err; 349 } 350 351 err = ice_read_phy_reg_e822(hw, port, high_addr, &high); 352 if (err) { 353 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, err %d", 354 high_addr, err); 355 return err; 356 } 357 358 *val = (u64)high << 32 | low; 359 360 return 0; 361 } 362 363 /** 364 * ice_write_phy_reg_e822 - Write a PHY register 365 * @hw: pointer to the HW struct 366 * @port: PHY port to write to 367 * @offset: PHY register offset to write 368 * @val: The value to write to the register 369 * 370 * Write a PHY register for the given port over the device sideband queue. 371 */ 372 int 373 ice_write_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 val) 374 { 375 struct ice_sbq_msg_input msg = {0}; 376 int err; 377 378 ice_fill_phy_msg_e822(&msg, port, offset); 379 msg.opcode = ice_sbq_msg_wr; 380 msg.data = val; 381 382 err = ice_sbq_rw_reg(hw, &msg); 383 if (err) { 384 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 385 err); 386 return err; 387 } 388 389 return 0; 390 } 391 392 /** 393 * ice_write_40b_phy_reg_e822 - Write a 40b value to the PHY 394 * @hw: pointer to the HW struct 395 * @port: port to write to 396 * @low_addr: offset of the low register 397 * @val: 40b value to write 398 * 399 * Write the provided 40b value to the two associated registers by splitting 400 * it up into two chunks, the lower 8 bits and the upper 32 bits. 401 */ 402 static int 403 ice_write_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) 404 { 405 u32 low, high; 406 u16 high_addr; 407 int err; 408 409 /* Only operate on registers known to be split into a lower 8 bit 410 * register and an upper 32 bit register. 411 */ 412 if (!ice_is_40b_phy_reg_e822(low_addr, &high_addr)) { 413 ice_debug(hw, ICE_DBG_PTP, "Invalid 40b register addr 0x%08x\n", 414 low_addr); 415 return -EINVAL; 416 } 417 418 low = (u32)(val & P_REG_40B_LOW_M); 419 high = (u32)(val >> P_REG_40B_HIGH_S); 420 421 err = ice_write_phy_reg_e822(hw, port, low_addr, low); 422 if (err) { 423 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 424 low_addr, err); 425 return err; 426 } 427 428 err = ice_write_phy_reg_e822(hw, port, high_addr, high); 429 if (err) { 430 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 431 high_addr, err); 432 return err; 433 } 434 435 return 0; 436 } 437 438 /** 439 * ice_write_64b_phy_reg_e822 - Write a 64bit value to PHY registers 440 * @hw: pointer to the HW struct 441 * @port: PHY port to read from 442 * @low_addr: offset of the lower register to read from 443 * @val: the contents of the 64bit value to write to PHY 444 * 445 * Write the 64bit value to the two associated 32bit PHY registers. The offset 446 * is always specified as the lower register, and the high address is looked 447 * up. This function only operates on registers known to be two parts of 448 * a 64bit value. 449 */ 450 static int 451 ice_write_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) 452 { 453 u32 low, high; 454 u16 high_addr; 455 int err; 456 457 /* Only operate on registers known to be split into two 32bit 458 * registers. 459 */ 460 if (!ice_is_64b_phy_reg_e822(low_addr, &high_addr)) { 461 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n", 462 low_addr); 463 return -EINVAL; 464 } 465 466 low = lower_32_bits(val); 467 high = upper_32_bits(val); 468 469 err = ice_write_phy_reg_e822(hw, port, low_addr, low); 470 if (err) { 471 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 472 low_addr, err); 473 return err; 474 } 475 476 err = ice_write_phy_reg_e822(hw, port, high_addr, high); 477 if (err) { 478 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 479 high_addr, err); 480 return err; 481 } 482 483 return 0; 484 } 485 486 /** 487 * ice_fill_quad_msg_e822 - Fill message data for quad register access 488 * @msg: the PHY message buffer to fill in 489 * @quad: the quad to access 490 * @offset: the register offset 491 * 492 * Fill a message buffer for accessing a register in a quad shared between 493 * multiple PHYs. 494 */ 495 static void 496 ice_fill_quad_msg_e822(struct ice_sbq_msg_input *msg, u8 quad, u16 offset) 497 { 498 u32 addr; 499 500 msg->dest_dev = rmn_0; 501 502 if ((quad % ICE_NUM_QUAD_TYPE) == 0) 503 addr = Q_0_BASE + offset; 504 else 505 addr = Q_1_BASE + offset; 506 507 msg->msg_addr_low = lower_16_bits(addr); 508 msg->msg_addr_high = upper_16_bits(addr); 509 } 510 511 /** 512 * ice_read_quad_reg_e822 - Read a PHY quad register 513 * @hw: pointer to the HW struct 514 * @quad: quad to read from 515 * @offset: quad register offset to read 516 * @val: on return, the contents read from the quad 517 * 518 * Read a quad register over the device sideband queue. Quad registers are 519 * shared between multiple PHYs. 520 */ 521 int 522 ice_read_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 *val) 523 { 524 struct ice_sbq_msg_input msg = {0}; 525 int err; 526 527 if (quad >= ICE_MAX_QUAD) 528 return -EINVAL; 529 530 ice_fill_quad_msg_e822(&msg, quad, offset); 531 msg.opcode = ice_sbq_msg_rd; 532 533 err = ice_sbq_rw_reg(hw, &msg); 534 if (err) { 535 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 536 err); 537 return err; 538 } 539 540 *val = msg.data; 541 542 return 0; 543 } 544 545 /** 546 * ice_write_quad_reg_e822 - Write a PHY quad register 547 * @hw: pointer to the HW struct 548 * @quad: quad to write to 549 * @offset: quad register offset to write 550 * @val: The value to write to the register 551 * 552 * Write a quad register over the device sideband queue. Quad registers are 553 * shared between multiple PHYs. 554 */ 555 int 556 ice_write_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 val) 557 { 558 struct ice_sbq_msg_input msg = {0}; 559 int err; 560 561 if (quad >= ICE_MAX_QUAD) 562 return -EINVAL; 563 564 ice_fill_quad_msg_e822(&msg, quad, offset); 565 msg.opcode = ice_sbq_msg_wr; 566 msg.data = val; 567 568 err = ice_sbq_rw_reg(hw, &msg); 569 if (err) { 570 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 571 err); 572 return err; 573 } 574 575 return 0; 576 } 577 578 /** 579 * ice_read_phy_tstamp_e822 - Read a PHY timestamp out of the quad block 580 * @hw: pointer to the HW struct 581 * @quad: the quad to read from 582 * @idx: the timestamp index to read 583 * @tstamp: on return, the 40bit timestamp value 584 * 585 * Read a 40bit timestamp value out of the two associated registers in the 586 * quad memory block that is shared between the internal PHYs of the E822 587 * family of devices. 588 */ 589 static int 590 ice_read_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp) 591 { 592 u16 lo_addr, hi_addr; 593 u32 lo, hi; 594 int err; 595 596 lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx); 597 hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx); 598 599 err = ice_read_quad_reg_e822(hw, quad, lo_addr, &lo); 600 if (err) { 601 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 602 err); 603 return err; 604 } 605 606 err = ice_read_quad_reg_e822(hw, quad, hi_addr, &hi); 607 if (err) { 608 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 609 err); 610 return err; 611 } 612 613 /* For E822 based internal PHYs, the timestamp is reported with the 614 * lower 8 bits in the low register, and the upper 32 bits in the high 615 * register. 616 */ 617 *tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M); 618 619 return 0; 620 } 621 622 /** 623 * ice_clear_phy_tstamp_e822 - Clear a timestamp from the quad block 624 * @hw: pointer to the HW struct 625 * @quad: the quad to read from 626 * @idx: the timestamp index to reset 627 * 628 * Clear a timestamp, resetting its valid bit, from the PHY quad block that is 629 * shared between the internal PHYs on the E822 devices. 630 */ 631 static int 632 ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx) 633 { 634 u16 lo_addr, hi_addr; 635 int err; 636 637 lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx); 638 hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx); 639 640 err = ice_write_quad_reg_e822(hw, quad, lo_addr, 0); 641 if (err) { 642 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, err %d\n", 643 err); 644 return err; 645 } 646 647 err = ice_write_quad_reg_e822(hw, quad, hi_addr, 0); 648 if (err) { 649 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, err %d\n", 650 err); 651 return err; 652 } 653 654 return 0; 655 } 656 657 /** 658 * ice_read_cgu_reg_e822 - Read a CGU register 659 * @hw: pointer to the HW struct 660 * @addr: Register address to read 661 * @val: storage for register value read 662 * 663 * Read the contents of a register of the Clock Generation Unit. Only 664 * applicable to E822 devices. 665 */ 666 static int 667 ice_read_cgu_reg_e822(struct ice_hw *hw, u32 addr, u32 *val) 668 { 669 struct ice_sbq_msg_input cgu_msg; 670 int err; 671 672 cgu_msg.opcode = ice_sbq_msg_rd; 673 cgu_msg.dest_dev = cgu; 674 cgu_msg.msg_addr_low = addr; 675 cgu_msg.msg_addr_high = 0x0; 676 677 err = ice_sbq_rw_reg(hw, &cgu_msg); 678 if (err) { 679 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n", 680 addr, err); 681 return err; 682 } 683 684 *val = cgu_msg.data; 685 686 return err; 687 } 688 689 /** 690 * ice_write_cgu_reg_e822 - Write a CGU register 691 * @hw: pointer to the HW struct 692 * @addr: Register address to write 693 * @val: value to write into the register 694 * 695 * Write the specified value to a register of the Clock Generation Unit. Only 696 * applicable to E822 devices. 697 */ 698 static int 699 ice_write_cgu_reg_e822(struct ice_hw *hw, u32 addr, u32 val) 700 { 701 struct ice_sbq_msg_input cgu_msg; 702 int err; 703 704 cgu_msg.opcode = ice_sbq_msg_wr; 705 cgu_msg.dest_dev = cgu; 706 cgu_msg.msg_addr_low = addr; 707 cgu_msg.msg_addr_high = 0x0; 708 cgu_msg.data = val; 709 710 err = ice_sbq_rw_reg(hw, &cgu_msg); 711 if (err) { 712 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n", 713 addr, err); 714 return err; 715 } 716 717 return err; 718 } 719 720 /** 721 * ice_clk_freq_str - Convert time_ref_freq to string 722 * @clk_freq: Clock frequency 723 * 724 * Convert the specified TIME_REF clock frequency to a string. 725 */ 726 static const char *ice_clk_freq_str(u8 clk_freq) 727 { 728 switch ((enum ice_time_ref_freq)clk_freq) { 729 case ICE_TIME_REF_FREQ_25_000: 730 return "25 MHz"; 731 case ICE_TIME_REF_FREQ_122_880: 732 return "122.88 MHz"; 733 case ICE_TIME_REF_FREQ_125_000: 734 return "125 MHz"; 735 case ICE_TIME_REF_FREQ_153_600: 736 return "153.6 MHz"; 737 case ICE_TIME_REF_FREQ_156_250: 738 return "156.25 MHz"; 739 case ICE_TIME_REF_FREQ_245_760: 740 return "245.76 MHz"; 741 default: 742 return "Unknown"; 743 } 744 } 745 746 /** 747 * ice_clk_src_str - Convert time_ref_src to string 748 * @clk_src: Clock source 749 * 750 * Convert the specified clock source to its string name. 751 */ 752 static const char *ice_clk_src_str(u8 clk_src) 753 { 754 switch ((enum ice_clk_src)clk_src) { 755 case ICE_CLK_SRC_TCX0: 756 return "TCX0"; 757 case ICE_CLK_SRC_TIME_REF: 758 return "TIME_REF"; 759 default: 760 return "Unknown"; 761 } 762 } 763 764 /** 765 * ice_cfg_cgu_pll_e822 - Configure the Clock Generation Unit 766 * @hw: pointer to the HW struct 767 * @clk_freq: Clock frequency to program 768 * @clk_src: Clock source to select (TIME_REF, or TCX0) 769 * 770 * Configure the Clock Generation Unit with the desired clock frequency and 771 * time reference, enabling the PLL which drives the PTP hardware clock. 772 */ 773 static int 774 ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq, 775 enum ice_clk_src clk_src) 776 { 777 union tspll_ro_bwm_lf bwm_lf; 778 union nac_cgu_dword19 dw19; 779 union nac_cgu_dword22 dw22; 780 union nac_cgu_dword24 dw24; 781 union nac_cgu_dword9 dw9; 782 int err; 783 784 if (clk_freq >= NUM_ICE_TIME_REF_FREQ) { 785 dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n", 786 clk_freq); 787 return -EINVAL; 788 } 789 790 if (clk_src >= NUM_ICE_CLK_SRC) { 791 dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n", 792 clk_src); 793 return -EINVAL; 794 } 795 796 if (clk_src == ICE_CLK_SRC_TCX0 && 797 clk_freq != ICE_TIME_REF_FREQ_25_000) { 798 dev_warn(ice_hw_to_dev(hw), 799 "TCX0 only supports 25 MHz frequency\n"); 800 return -EINVAL; 801 } 802 803 err = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD9, &dw9.val); 804 if (err) 805 return err; 806 807 err = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD24, &dw24.val); 808 if (err) 809 return err; 810 811 err = ice_read_cgu_reg_e822(hw, TSPLL_RO_BWM_LF, &bwm_lf.val); 812 if (err) 813 return err; 814 815 /* Log the current clock configuration */ 816 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 817 dw24.field.ts_pll_enable ? "enabled" : "disabled", 818 ice_clk_src_str(dw24.field.time_ref_sel), 819 ice_clk_freq_str(dw9.field.time_ref_freq_sel), 820 bwm_lf.field.plllock_true_lock_cri ? "locked" : "unlocked"); 821 822 /* Disable the PLL before changing the clock source or frequency */ 823 if (dw24.field.ts_pll_enable) { 824 dw24.field.ts_pll_enable = 0; 825 826 err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val); 827 if (err) 828 return err; 829 } 830 831 /* Set the frequency */ 832 dw9.field.time_ref_freq_sel = clk_freq; 833 err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD9, dw9.val); 834 if (err) 835 return err; 836 837 /* Configure the TS PLL feedback divisor */ 838 err = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD19, &dw19.val); 839 if (err) 840 return err; 841 842 dw19.field.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div; 843 dw19.field.tspll_ndivratio = 1; 844 845 err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD19, dw19.val); 846 if (err) 847 return err; 848 849 /* Configure the TS PLL post divisor */ 850 err = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD22, &dw22.val); 851 if (err) 852 return err; 853 854 dw22.field.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div; 855 dw22.field.time1588clk_sel_div2 = 0; 856 857 err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD22, dw22.val); 858 if (err) 859 return err; 860 861 /* Configure the TS PLL pre divisor and clock source */ 862 err = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD24, &dw24.val); 863 if (err) 864 return err; 865 866 dw24.field.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div; 867 dw24.field.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div; 868 dw24.field.time_ref_sel = clk_src; 869 870 err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val); 871 if (err) 872 return err; 873 874 /* Finally, enable the PLL */ 875 dw24.field.ts_pll_enable = 1; 876 877 err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val); 878 if (err) 879 return err; 880 881 /* Wait to verify if the PLL locks */ 882 usleep_range(1000, 5000); 883 884 err = ice_read_cgu_reg_e822(hw, TSPLL_RO_BWM_LF, &bwm_lf.val); 885 if (err) 886 return err; 887 888 if (!bwm_lf.field.plllock_true_lock_cri) { 889 dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n"); 890 return -EBUSY; 891 } 892 893 /* Log the current clock configuration */ 894 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 895 dw24.field.ts_pll_enable ? "enabled" : "disabled", 896 ice_clk_src_str(dw24.field.time_ref_sel), 897 ice_clk_freq_str(dw9.field.time_ref_freq_sel), 898 bwm_lf.field.plllock_true_lock_cri ? "locked" : "unlocked"); 899 900 return 0; 901 } 902 903 /** 904 * ice_init_cgu_e822 - Initialize CGU with settings from firmware 905 * @hw: pointer to the HW structure 906 * 907 * Initialize the Clock Generation Unit of the E822 device. 908 */ 909 static int ice_init_cgu_e822(struct ice_hw *hw) 910 { 911 struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info; 912 union tspll_cntr_bist_settings cntr_bist; 913 int err; 914 915 err = ice_read_cgu_reg_e822(hw, TSPLL_CNTR_BIST_SETTINGS, 916 &cntr_bist.val); 917 if (err) 918 return err; 919 920 /* Disable sticky lock detection so lock err reported is accurate */ 921 cntr_bist.field.i_plllock_sel_0 = 0; 922 cntr_bist.field.i_plllock_sel_1 = 0; 923 924 err = ice_write_cgu_reg_e822(hw, TSPLL_CNTR_BIST_SETTINGS, 925 cntr_bist.val); 926 if (err) 927 return err; 928 929 /* Configure the CGU PLL using the parameters from the function 930 * capabilities. 931 */ 932 err = ice_cfg_cgu_pll_e822(hw, ts_info->time_ref, 933 (enum ice_clk_src)ts_info->clk_src); 934 if (err) 935 return err; 936 937 return 0; 938 } 939 940 /** 941 * ice_ptp_set_vernier_wl - Set the window length for vernier calibration 942 * @hw: pointer to the HW struct 943 * 944 * Set the window length used for the vernier port calibration process. 945 */ 946 static int ice_ptp_set_vernier_wl(struct ice_hw *hw) 947 { 948 u8 port; 949 950 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { 951 int err; 952 953 err = ice_write_phy_reg_e822(hw, port, P_REG_WL, 954 PTP_VERNIER_WL); 955 if (err) { 956 ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, err %d\n", 957 port, err); 958 return err; 959 } 960 } 961 962 return 0; 963 } 964 965 /** 966 * ice_ptp_init_phc_e822 - Perform E822 specific PHC initialization 967 * @hw: pointer to HW struct 968 * 969 * Perform PHC initialization steps specific to E822 devices. 970 */ 971 static int ice_ptp_init_phc_e822(struct ice_hw *hw) 972 { 973 int err; 974 u32 regval; 975 976 /* Enable reading switch and PHY registers over the sideband queue */ 977 #define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1) 978 #define PF_SB_REM_DEV_CTL_PHY0 BIT(2) 979 regval = rd32(hw, PF_SB_REM_DEV_CTL); 980 regval |= (PF_SB_REM_DEV_CTL_SWITCH_READ | 981 PF_SB_REM_DEV_CTL_PHY0); 982 wr32(hw, PF_SB_REM_DEV_CTL, regval); 983 984 /* Initialize the Clock Generation Unit */ 985 err = ice_init_cgu_e822(hw); 986 if (err) 987 return err; 988 989 /* Set window length for all the ports */ 990 return ice_ptp_set_vernier_wl(hw); 991 } 992 993 /** 994 * ice_ptp_prep_phy_time_e822 - Prepare PHY port with initial time 995 * @hw: pointer to the HW struct 996 * @time: Time to initialize the PHY port clocks to 997 * 998 * Program the PHY port registers with a new initial time value. The port 999 * clock will be initialized once the driver issues an INIT_TIME sync 1000 * command. The time value is the upper 32 bits of the PHY timer, usually in 1001 * units of nominal nanoseconds. 1002 */ 1003 static int 1004 ice_ptp_prep_phy_time_e822(struct ice_hw *hw, u32 time) 1005 { 1006 u64 phy_time; 1007 u8 port; 1008 int err; 1009 1010 /* The time represents the upper 32 bits of the PHY timer, so we need 1011 * to shift to account for this when programming. 1012 */ 1013 phy_time = (u64)time << 32; 1014 1015 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { 1016 /* Tx case */ 1017 err = ice_write_64b_phy_reg_e822(hw, port, 1018 P_REG_TX_TIMER_INC_PRE_L, 1019 phy_time); 1020 if (err) 1021 goto exit_err; 1022 1023 /* Rx case */ 1024 err = ice_write_64b_phy_reg_e822(hw, port, 1025 P_REG_RX_TIMER_INC_PRE_L, 1026 phy_time); 1027 if (err) 1028 goto exit_err; 1029 } 1030 1031 return 0; 1032 1033 exit_err: 1034 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n", 1035 port, err); 1036 1037 return err; 1038 } 1039 1040 /** 1041 * ice_ptp_prep_port_adj_e822 - Prepare a single port for time adjust 1042 * @hw: pointer to HW struct 1043 * @port: Port number to be programmed 1044 * @time: time in cycles to adjust the port Tx and Rx clocks 1045 * 1046 * Program the port for an atomic adjustment by writing the Tx and Rx timer 1047 * registers. The atomic adjustment won't be completed until the driver issues 1048 * an ADJ_TIME command. 1049 * 1050 * Note that time is not in units of nanoseconds. It is in clock time 1051 * including the lower sub-nanosecond portion of the port timer. 1052 * 1053 * Negative adjustments are supported using 2s complement arithmetic. 1054 */ 1055 int 1056 ice_ptp_prep_port_adj_e822(struct ice_hw *hw, u8 port, s64 time) 1057 { 1058 u32 l_time, u_time; 1059 int err; 1060 1061 l_time = lower_32_bits(time); 1062 u_time = upper_32_bits(time); 1063 1064 /* Tx case */ 1065 err = ice_write_phy_reg_e822(hw, port, P_REG_TX_TIMER_INC_PRE_L, 1066 l_time); 1067 if (err) 1068 goto exit_err; 1069 1070 err = ice_write_phy_reg_e822(hw, port, P_REG_TX_TIMER_INC_PRE_U, 1071 u_time); 1072 if (err) 1073 goto exit_err; 1074 1075 /* Rx case */ 1076 err = ice_write_phy_reg_e822(hw, port, P_REG_RX_TIMER_INC_PRE_L, 1077 l_time); 1078 if (err) 1079 goto exit_err; 1080 1081 err = ice_write_phy_reg_e822(hw, port, P_REG_RX_TIMER_INC_PRE_U, 1082 u_time); 1083 if (err) 1084 goto exit_err; 1085 1086 return 0; 1087 1088 exit_err: 1089 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n", 1090 port, err); 1091 return err; 1092 } 1093 1094 /** 1095 * ice_ptp_prep_phy_adj_e822 - Prep PHY ports for a time adjustment 1096 * @hw: pointer to HW struct 1097 * @adj: adjustment in nanoseconds 1098 * 1099 * Prepare the PHY ports for an atomic time adjustment by programming the PHY 1100 * Tx and Rx port registers. The actual adjustment is completed by issuing an 1101 * ADJ_TIME or ADJ_TIME_AT_TIME sync command. 1102 */ 1103 static int 1104 ice_ptp_prep_phy_adj_e822(struct ice_hw *hw, s32 adj) 1105 { 1106 s64 cycles; 1107 u8 port; 1108 1109 /* The port clock supports adjustment of the sub-nanosecond portion of 1110 * the clock. We shift the provided adjustment in nanoseconds to 1111 * calculate the appropriate adjustment to program into the PHY ports. 1112 */ 1113 if (adj > 0) 1114 cycles = (s64)adj << 32; 1115 else 1116 cycles = -(((s64)-adj) << 32); 1117 1118 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { 1119 int err; 1120 1121 err = ice_ptp_prep_port_adj_e822(hw, port, cycles); 1122 if (err) 1123 return err; 1124 } 1125 1126 return 0; 1127 } 1128 1129 /** 1130 * ice_ptp_prep_phy_incval_e822 - Prepare PHY ports for time adjustment 1131 * @hw: pointer to HW struct 1132 * @incval: new increment value to prepare 1133 * 1134 * Prepare each of the PHY ports for a new increment value by programming the 1135 * port's TIMETUS registers. The new increment value will be updated after 1136 * issuing an INIT_INCVAL command. 1137 */ 1138 static int 1139 ice_ptp_prep_phy_incval_e822(struct ice_hw *hw, u64 incval) 1140 { 1141 int err; 1142 u8 port; 1143 1144 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { 1145 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L, 1146 incval); 1147 if (err) 1148 goto exit_err; 1149 } 1150 1151 return 0; 1152 1153 exit_err: 1154 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n", 1155 port, err); 1156 1157 return err; 1158 } 1159 1160 /** 1161 * ice_ptp_read_port_capture - Read a port's local time capture 1162 * @hw: pointer to HW struct 1163 * @port: Port number to read 1164 * @tx_ts: on return, the Tx port time capture 1165 * @rx_ts: on return, the Rx port time capture 1166 * 1167 * Read the port's Tx and Rx local time capture values. 1168 * 1169 * Note this has no equivalent for the E810 devices. 1170 */ 1171 static int 1172 ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts) 1173 { 1174 int err; 1175 1176 /* Tx case */ 1177 err = ice_read_64b_phy_reg_e822(hw, port, P_REG_TX_CAPTURE_L, tx_ts); 1178 if (err) { 1179 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n", 1180 err); 1181 return err; 1182 } 1183 1184 ice_debug(hw, ICE_DBG_PTP, "tx_init = 0x%016llx\n", 1185 (unsigned long long)*tx_ts); 1186 1187 /* Rx case */ 1188 err = ice_read_64b_phy_reg_e822(hw, port, P_REG_RX_CAPTURE_L, rx_ts); 1189 if (err) { 1190 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n", 1191 err); 1192 return err; 1193 } 1194 1195 ice_debug(hw, ICE_DBG_PTP, "rx_init = 0x%016llx\n", 1196 (unsigned long long)*rx_ts); 1197 1198 return 0; 1199 } 1200 1201 /** 1202 * ice_ptp_one_port_cmd - Prepare a single PHY port for a timer command 1203 * @hw: pointer to HW struct 1204 * @port: Port to which cmd has to be sent 1205 * @cmd: Command to be sent to the port 1206 * 1207 * Prepare the requested port for an upcoming timer sync command. 1208 * 1209 * Note there is no equivalent of this operation on E810, as that device 1210 * always handles all external PHYs internally. 1211 */ 1212 static int 1213 ice_ptp_one_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd) 1214 { 1215 u32 cmd_val, val; 1216 u8 tmr_idx; 1217 int err; 1218 1219 tmr_idx = ice_get_ptp_src_clock_index(hw); 1220 cmd_val = tmr_idx << SEL_PHY_SRC; 1221 switch (cmd) { 1222 case INIT_TIME: 1223 cmd_val |= PHY_CMD_INIT_TIME; 1224 break; 1225 case INIT_INCVAL: 1226 cmd_val |= PHY_CMD_INIT_INCVAL; 1227 break; 1228 case ADJ_TIME: 1229 cmd_val |= PHY_CMD_ADJ_TIME; 1230 break; 1231 case READ_TIME: 1232 cmd_val |= PHY_CMD_READ_TIME; 1233 break; 1234 case ADJ_TIME_AT_TIME: 1235 cmd_val |= PHY_CMD_ADJ_TIME_AT_TIME; 1236 break; 1237 } 1238 1239 /* Tx case */ 1240 /* Read, modify, write */ 1241 err = ice_read_phy_reg_e822(hw, port, P_REG_TX_TMR_CMD, &val); 1242 if (err) { 1243 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_TMR_CMD, err %d\n", 1244 err); 1245 return err; 1246 } 1247 1248 /* Modify necessary bits only and perform write */ 1249 val &= ~TS_CMD_MASK; 1250 val |= cmd_val; 1251 1252 err = ice_write_phy_reg_e822(hw, port, P_REG_TX_TMR_CMD, val); 1253 if (err) { 1254 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n", 1255 err); 1256 return err; 1257 } 1258 1259 /* Rx case */ 1260 /* Read, modify, write */ 1261 err = ice_read_phy_reg_e822(hw, port, P_REG_RX_TMR_CMD, &val); 1262 if (err) { 1263 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_TMR_CMD, err %d\n", 1264 err); 1265 return err; 1266 } 1267 1268 /* Modify necessary bits only and perform write */ 1269 val &= ~TS_CMD_MASK; 1270 val |= cmd_val; 1271 1272 err = ice_write_phy_reg_e822(hw, port, P_REG_RX_TMR_CMD, val); 1273 if (err) { 1274 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n", 1275 err); 1276 return err; 1277 } 1278 1279 return 0; 1280 } 1281 1282 /** 1283 * ice_ptp_port_cmd_e822 - Prepare all ports for a timer command 1284 * @hw: pointer to the HW struct 1285 * @cmd: timer command to prepare 1286 * 1287 * Prepare all ports connected to this device for an upcoming timer sync 1288 * command. 1289 */ 1290 static int 1291 ice_ptp_port_cmd_e822(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 1292 { 1293 u8 port; 1294 1295 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { 1296 int err; 1297 1298 err = ice_ptp_one_port_cmd(hw, port, cmd); 1299 if (err) 1300 return err; 1301 } 1302 1303 return 0; 1304 } 1305 1306 /* E822 Vernier calibration functions 1307 * 1308 * The following functions are used as part of the vernier calibration of 1309 * a port. This calibration increases the precision of the timestamps on the 1310 * port. 1311 */ 1312 1313 /** 1314 * ice_phy_get_speed_and_fec_e822 - Get link speed and FEC based on serdes mode 1315 * @hw: pointer to HW struct 1316 * @port: the port to read from 1317 * @link_out: if non-NULL, holds link speed on success 1318 * @fec_out: if non-NULL, holds FEC algorithm on success 1319 * 1320 * Read the serdes data for the PHY port and extract the link speed and FEC 1321 * algorithm. 1322 */ 1323 static int 1324 ice_phy_get_speed_and_fec_e822(struct ice_hw *hw, u8 port, 1325 enum ice_ptp_link_spd *link_out, 1326 enum ice_ptp_fec_mode *fec_out) 1327 { 1328 enum ice_ptp_link_spd link; 1329 enum ice_ptp_fec_mode fec; 1330 u32 serdes; 1331 int err; 1332 1333 err = ice_read_phy_reg_e822(hw, port, P_REG_LINK_SPEED, &serdes); 1334 if (err) { 1335 ice_debug(hw, ICE_DBG_PTP, "Failed to read serdes info\n"); 1336 return err; 1337 } 1338 1339 /* Determine the FEC algorithm */ 1340 fec = (enum ice_ptp_fec_mode)P_REG_LINK_SPEED_FEC_MODE(serdes); 1341 1342 serdes &= P_REG_LINK_SPEED_SERDES_M; 1343 1344 /* Determine the link speed */ 1345 if (fec == ICE_PTP_FEC_MODE_RS_FEC) { 1346 switch (serdes) { 1347 case ICE_PTP_SERDES_25G: 1348 link = ICE_PTP_LNK_SPD_25G_RS; 1349 break; 1350 case ICE_PTP_SERDES_50G: 1351 link = ICE_PTP_LNK_SPD_50G_RS; 1352 break; 1353 case ICE_PTP_SERDES_100G: 1354 link = ICE_PTP_LNK_SPD_100G_RS; 1355 break; 1356 default: 1357 return -EIO; 1358 } 1359 } else { 1360 switch (serdes) { 1361 case ICE_PTP_SERDES_1G: 1362 link = ICE_PTP_LNK_SPD_1G; 1363 break; 1364 case ICE_PTP_SERDES_10G: 1365 link = ICE_PTP_LNK_SPD_10G; 1366 break; 1367 case ICE_PTP_SERDES_25G: 1368 link = ICE_PTP_LNK_SPD_25G; 1369 break; 1370 case ICE_PTP_SERDES_40G: 1371 link = ICE_PTP_LNK_SPD_40G; 1372 break; 1373 case ICE_PTP_SERDES_50G: 1374 link = ICE_PTP_LNK_SPD_50G; 1375 break; 1376 default: 1377 return -EIO; 1378 } 1379 } 1380 1381 if (link_out) 1382 *link_out = link; 1383 if (fec_out) 1384 *fec_out = fec; 1385 1386 return 0; 1387 } 1388 1389 /** 1390 * ice_phy_cfg_lane_e822 - Configure PHY quad for single/multi-lane timestamp 1391 * @hw: pointer to HW struct 1392 * @port: to configure the quad for 1393 */ 1394 static void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port) 1395 { 1396 enum ice_ptp_link_spd link_spd; 1397 int err; 1398 u32 val; 1399 u8 quad; 1400 1401 err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, NULL); 1402 if (err) { 1403 ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, err %d\n", 1404 err); 1405 return; 1406 } 1407 1408 quad = port / ICE_PORTS_PER_QUAD; 1409 1410 err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val); 1411 if (err) { 1412 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, err %d\n", 1413 err); 1414 return; 1415 } 1416 1417 if (link_spd >= ICE_PTP_LNK_SPD_40G) 1418 val &= ~Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M; 1419 else 1420 val |= Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M; 1421 1422 err = ice_write_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG, val); 1423 if (err) { 1424 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, err %d\n", 1425 err); 1426 return; 1427 } 1428 } 1429 1430 /** 1431 * ice_phy_cfg_uix_e822 - Configure Serdes UI to TU conversion for E822 1432 * @hw: pointer to the HW structure 1433 * @port: the port to configure 1434 * 1435 * Program the conversion ration of Serdes clock "unit intervals" (UIs) to PHC 1436 * hardware clock time units (TUs). That is, determine the number of TUs per 1437 * serdes unit interval, and program the UIX registers with this conversion. 1438 * 1439 * This conversion is used as part of the calibration process when determining 1440 * the additional error of a timestamp vs the real time of transmission or 1441 * receipt of the packet. 1442 * 1443 * Hardware uses the number of TUs per 66 UIs, written to the UIX registers 1444 * for the two main serdes clock rates, 10G/40G and 25G/100G serdes clocks. 1445 * 1446 * To calculate the conversion ratio, we use the following facts: 1447 * 1448 * a) the clock frequency in Hz (cycles per second) 1449 * b) the number of TUs per cycle (the increment value of the clock) 1450 * c) 1 second per 1 billion nanoseconds 1451 * d) the duration of 66 UIs in nanoseconds 1452 * 1453 * Given these facts, we can use the following table to work out what ratios 1454 * to multiply in order to get the number of TUs per 66 UIs: 1455 * 1456 * cycles | 1 second | incval (TUs) | nanoseconds 1457 * -------+--------------+--------------+------------- 1458 * second | 1 billion ns | cycle | 66 UIs 1459 * 1460 * To perform the multiplication using integers without too much loss of 1461 * precision, we can take use the following equation: 1462 * 1463 * (freq * incval * 6600 LINE_UI ) / ( 100 * 1 billion) 1464 * 1465 * We scale up to using 6600 UI instead of 66 in order to avoid fractional 1466 * nanosecond UIs (66 UI at 10G/40G is 6.4 ns) 1467 * 1468 * The increment value has a maximum expected range of about 34 bits, while 1469 * the frequency value is about 29 bits. Multiplying these values shouldn't 1470 * overflow the 64 bits. However, we must then further multiply them again by 1471 * the Serdes unit interval duration. To avoid overflow here, we split the 1472 * overall divide by 1e11 into a divide by 256 (shift down by 8 bits) and 1473 * a divide by 390,625,000. This does lose some precision, but avoids 1474 * miscalculation due to arithmetic overflow. 1475 */ 1476 static int ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port) 1477 { 1478 u64 cur_freq, clk_incval, tu_per_sec, uix; 1479 int err; 1480 1481 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw)); 1482 clk_incval = ice_ptp_read_src_incval(hw); 1483 1484 /* Calculate TUs per second divided by 256 */ 1485 tu_per_sec = (cur_freq * clk_incval) >> 8; 1486 1487 #define LINE_UI_10G_40G 640 /* 6600 UIs is 640 nanoseconds at 10Gb/40Gb */ 1488 #define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */ 1489 1490 /* Program the 10Gb/40Gb conversion ratio */ 1491 uix = div_u64(tu_per_sec * LINE_UI_10G_40G, 390625000); 1492 1493 err = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_10G_40G_L, 1494 uix); 1495 if (err) { 1496 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, err %d\n", 1497 err); 1498 return err; 1499 } 1500 1501 /* Program the 25Gb/100Gb conversion ratio */ 1502 uix = div_u64(tu_per_sec * LINE_UI_25G_100G, 390625000); 1503 1504 err = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_25G_100G_L, 1505 uix); 1506 if (err) { 1507 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, err %d\n", 1508 err); 1509 return err; 1510 } 1511 1512 return 0; 1513 } 1514 1515 /** 1516 * ice_phy_cfg_parpcs_e822 - Configure TUs per PAR/PCS clock cycle 1517 * @hw: pointer to the HW struct 1518 * @port: port to configure 1519 * 1520 * Configure the number of TUs for the PAR and PCS clocks used as part of the 1521 * timestamp calibration process. This depends on the link speed, as the PHY 1522 * uses different markers depending on the speed. 1523 * 1524 * 1Gb/10Gb/25Gb: 1525 * - Tx/Rx PAR/PCS markers 1526 * 1527 * 25Gb RS: 1528 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers 1529 * 1530 * 40Gb/50Gb: 1531 * - Tx/Rx PAR/PCS markers 1532 * - Rx Deskew PAR/PCS markers 1533 * 1534 * 50G RS and 100GB RS: 1535 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers 1536 * - Rx Deskew PAR/PCS markers 1537 * - Tx PAR/PCS markers 1538 * 1539 * To calculate the conversion, we use the PHC clock frequency (cycles per 1540 * second), the increment value (TUs per cycle), and the related PHY clock 1541 * frequency to calculate the TUs per unit of the PHY link clock. The 1542 * following table shows how the units convert: 1543 * 1544 * cycles | TUs | second 1545 * -------+-------+-------- 1546 * second | cycle | cycles 1547 * 1548 * For each conversion register, look up the appropriate frequency from the 1549 * e822 PAR/PCS table and calculate the TUs per unit of that clock. Program 1550 * this to the appropriate register, preparing hardware to perform timestamp 1551 * calibration to calculate the total Tx or Rx offset to adjust the timestamp 1552 * in order to calibrate for the internal PHY delays. 1553 * 1554 * Note that the increment value ranges up to ~34 bits, and the clock 1555 * frequency is ~29 bits, so multiplying them together should fit within the 1556 * 64 bit arithmetic. 1557 */ 1558 static int ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port) 1559 { 1560 u64 cur_freq, clk_incval, tu_per_sec, phy_tus; 1561 enum ice_ptp_link_spd link_spd; 1562 enum ice_ptp_fec_mode fec_mode; 1563 int err; 1564 1565 err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode); 1566 if (err) 1567 return err; 1568 1569 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw)); 1570 clk_incval = ice_ptp_read_src_incval(hw); 1571 1572 /* Calculate TUs per cycle of the PHC clock */ 1573 tu_per_sec = cur_freq * clk_incval; 1574 1575 /* For each PHY conversion register, look up the appropriate link 1576 * speed frequency and determine the TUs per that clock's cycle time. 1577 * Split this into a high and low value and then program the 1578 * appropriate register. If that link speed does not use the 1579 * associated register, write zeros to clear it instead. 1580 */ 1581 1582 /* P_REG_PAR_TX_TUS */ 1583 if (e822_vernier[link_spd].tx_par_clk) 1584 phy_tus = div_u64(tu_per_sec, 1585 e822_vernier[link_spd].tx_par_clk); 1586 else 1587 phy_tus = 0; 1588 1589 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PAR_TX_TUS_L, 1590 phy_tus); 1591 if (err) 1592 return err; 1593 1594 /* P_REG_PAR_RX_TUS */ 1595 if (e822_vernier[link_spd].rx_par_clk) 1596 phy_tus = div_u64(tu_per_sec, 1597 e822_vernier[link_spd].rx_par_clk); 1598 else 1599 phy_tus = 0; 1600 1601 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PAR_RX_TUS_L, 1602 phy_tus); 1603 if (err) 1604 return err; 1605 1606 /* P_REG_PCS_TX_TUS */ 1607 if (e822_vernier[link_spd].tx_pcs_clk) 1608 phy_tus = div_u64(tu_per_sec, 1609 e822_vernier[link_spd].tx_pcs_clk); 1610 else 1611 phy_tus = 0; 1612 1613 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PCS_TX_TUS_L, 1614 phy_tus); 1615 if (err) 1616 return err; 1617 1618 /* P_REG_PCS_RX_TUS */ 1619 if (e822_vernier[link_spd].rx_pcs_clk) 1620 phy_tus = div_u64(tu_per_sec, 1621 e822_vernier[link_spd].rx_pcs_clk); 1622 else 1623 phy_tus = 0; 1624 1625 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PCS_RX_TUS_L, 1626 phy_tus); 1627 if (err) 1628 return err; 1629 1630 /* P_REG_DESK_PAR_TX_TUS */ 1631 if (e822_vernier[link_spd].tx_desk_rsgb_par) 1632 phy_tus = div_u64(tu_per_sec, 1633 e822_vernier[link_spd].tx_desk_rsgb_par); 1634 else 1635 phy_tus = 0; 1636 1637 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PAR_TX_TUS_L, 1638 phy_tus); 1639 if (err) 1640 return err; 1641 1642 /* P_REG_DESK_PAR_RX_TUS */ 1643 if (e822_vernier[link_spd].rx_desk_rsgb_par) 1644 phy_tus = div_u64(tu_per_sec, 1645 e822_vernier[link_spd].rx_desk_rsgb_par); 1646 else 1647 phy_tus = 0; 1648 1649 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PAR_RX_TUS_L, 1650 phy_tus); 1651 if (err) 1652 return err; 1653 1654 /* P_REG_DESK_PCS_TX_TUS */ 1655 if (e822_vernier[link_spd].tx_desk_rsgb_pcs) 1656 phy_tus = div_u64(tu_per_sec, 1657 e822_vernier[link_spd].tx_desk_rsgb_pcs); 1658 else 1659 phy_tus = 0; 1660 1661 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PCS_TX_TUS_L, 1662 phy_tus); 1663 if (err) 1664 return err; 1665 1666 /* P_REG_DESK_PCS_RX_TUS */ 1667 if (e822_vernier[link_spd].rx_desk_rsgb_pcs) 1668 phy_tus = div_u64(tu_per_sec, 1669 e822_vernier[link_spd].rx_desk_rsgb_pcs); 1670 else 1671 phy_tus = 0; 1672 1673 return ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PCS_RX_TUS_L, 1674 phy_tus); 1675 } 1676 1677 /** 1678 * ice_calc_fixed_tx_offset_e822 - Calculated Fixed Tx offset for a port 1679 * @hw: pointer to the HW struct 1680 * @link_spd: the Link speed to calculate for 1681 * 1682 * Calculate the fixed offset due to known static latency data. 1683 */ 1684 static u64 1685 ice_calc_fixed_tx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) 1686 { 1687 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset; 1688 1689 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw)); 1690 clk_incval = ice_ptp_read_src_incval(hw); 1691 1692 /* Calculate TUs per second */ 1693 tu_per_sec = cur_freq * clk_incval; 1694 1695 /* Calculate number of TUs to add for the fixed Tx latency. Since the 1696 * latency measurement is in 1/100th of a nanosecond, we need to 1697 * multiply by tu_per_sec and then divide by 1e11. This calculation 1698 * overflows 64 bit integer arithmetic, so break it up into two 1699 * divisions by 1e4 first then by 1e7. 1700 */ 1701 fixed_offset = div_u64(tu_per_sec, 10000); 1702 fixed_offset *= e822_vernier[link_spd].tx_fixed_delay; 1703 fixed_offset = div_u64(fixed_offset, 10000000); 1704 1705 return fixed_offset; 1706 } 1707 1708 /** 1709 * ice_phy_cfg_fixed_tx_offset_e822 - Configure Tx offset for bypass mode 1710 * @hw: pointer to the HW struct 1711 * @port: the PHY port to configure 1712 * 1713 * Calculate and program the fixed Tx offset, and indicate that the offset is 1714 * ready. This can be used when operating in bypass mode. 1715 */ 1716 static int 1717 ice_phy_cfg_fixed_tx_offset_e822(struct ice_hw *hw, u8 port) 1718 { 1719 enum ice_ptp_link_spd link_spd; 1720 enum ice_ptp_fec_mode fec_mode; 1721 u64 total_offset; 1722 int err; 1723 1724 err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode); 1725 if (err) 1726 return err; 1727 1728 total_offset = ice_calc_fixed_tx_offset_e822(hw, link_spd); 1729 1730 /* Program the fixed Tx offset into the P_REG_TOTAL_TX_OFFSET_L 1731 * register, then indicate that the Tx offset is ready. After this, 1732 * timestamps will be enabled. 1733 * 1734 * Note that this skips including the more precise offsets generated 1735 * by the Vernier calibration. 1736 */ 1737 err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L, 1738 total_offset); 1739 if (err) 1740 return err; 1741 1742 err = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1); 1743 if (err) 1744 return err; 1745 1746 return 0; 1747 } 1748 1749 /** 1750 * ice_calc_fixed_rx_offset_e822 - Calculated the fixed Rx offset for a port 1751 * @hw: pointer to HW struct 1752 * @link_spd: The Link speed to calculate for 1753 * 1754 * Determine the fixed Rx latency for a given link speed. 1755 */ 1756 static u64 1757 ice_calc_fixed_rx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) 1758 { 1759 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset; 1760 1761 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw)); 1762 clk_incval = ice_ptp_read_src_incval(hw); 1763 1764 /* Calculate TUs per second */ 1765 tu_per_sec = cur_freq * clk_incval; 1766 1767 /* Calculate number of TUs to add for the fixed Rx latency. Since the 1768 * latency measurement is in 1/100th of a nanosecond, we need to 1769 * multiply by tu_per_sec and then divide by 1e11. This calculation 1770 * overflows 64 bit integer arithmetic, so break it up into two 1771 * divisions by 1e4 first then by 1e7. 1772 */ 1773 fixed_offset = div_u64(tu_per_sec, 10000); 1774 fixed_offset *= e822_vernier[link_spd].rx_fixed_delay; 1775 fixed_offset = div_u64(fixed_offset, 10000000); 1776 1777 return fixed_offset; 1778 } 1779 1780 /** 1781 * ice_phy_cfg_fixed_rx_offset_e822 - Configure fixed Rx offset for bypass mode 1782 * @hw: pointer to the HW struct 1783 * @port: the PHY port to configure 1784 * 1785 * Calculate and program the fixed Rx offset, and indicate that the offset is 1786 * ready. This can be used when operating in bypass mode. 1787 */ 1788 static int 1789 ice_phy_cfg_fixed_rx_offset_e822(struct ice_hw *hw, u8 port) 1790 { 1791 enum ice_ptp_link_spd link_spd; 1792 enum ice_ptp_fec_mode fec_mode; 1793 u64 total_offset; 1794 int err; 1795 1796 err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode); 1797 if (err) 1798 return err; 1799 1800 total_offset = ice_calc_fixed_rx_offset_e822(hw, link_spd); 1801 1802 /* Program the fixed Rx offset into the P_REG_TOTAL_RX_OFFSET_L 1803 * register, then indicate that the Rx offset is ready. After this, 1804 * timestamps will be enabled. 1805 * 1806 * Note that this skips including the more precise offsets generated 1807 * by Vernier calibration. 1808 */ 1809 err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L, 1810 total_offset); 1811 if (err) 1812 return err; 1813 1814 err = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1); 1815 if (err) 1816 return err; 1817 1818 return 0; 1819 } 1820 1821 /** 1822 * ice_read_phy_and_phc_time_e822 - Simultaneously capture PHC and PHY time 1823 * @hw: pointer to the HW struct 1824 * @port: the PHY port to read 1825 * @phy_time: on return, the 64bit PHY timer value 1826 * @phc_time: on return, the lower 64bits of PHC time 1827 * 1828 * Issue a READ_TIME timer command to simultaneously capture the PHY and PHC 1829 * timer values. 1830 */ 1831 static int 1832 ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8 port, u64 *phy_time, 1833 u64 *phc_time) 1834 { 1835 u64 tx_time, rx_time; 1836 u32 zo, lo; 1837 u8 tmr_idx; 1838 int err; 1839 1840 tmr_idx = ice_get_ptp_src_clock_index(hw); 1841 1842 /* Prepare the PHC timer for a READ_TIME capture command */ 1843 ice_ptp_src_cmd(hw, READ_TIME); 1844 1845 /* Prepare the PHY timer for a READ_TIME capture command */ 1846 err = ice_ptp_one_port_cmd(hw, port, READ_TIME); 1847 if (err) 1848 return err; 1849 1850 /* Issue the sync to start the READ_TIME capture */ 1851 ice_ptp_exec_tmr_cmd(hw); 1852 1853 /* Read the captured PHC time from the shadow time registers */ 1854 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx)); 1855 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx)); 1856 *phc_time = (u64)lo << 32 | zo; 1857 1858 /* Read the captured PHY time from the PHY shadow registers */ 1859 err = ice_ptp_read_port_capture(hw, port, &tx_time, &rx_time); 1860 if (err) 1861 return err; 1862 1863 /* If the PHY Tx and Rx timers don't match, log a warning message. 1864 * Note that this should not happen in normal circumstances since the 1865 * driver always programs them together. 1866 */ 1867 if (tx_time != rx_time) 1868 dev_warn(ice_hw_to_dev(hw), 1869 "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n", 1870 port, (unsigned long long)tx_time, 1871 (unsigned long long)rx_time); 1872 1873 *phy_time = tx_time; 1874 1875 return 0; 1876 } 1877 1878 /** 1879 * ice_sync_phy_timer_e822 - Synchronize the PHY timer with PHC timer 1880 * @hw: pointer to the HW struct 1881 * @port: the PHY port to synchronize 1882 * 1883 * Perform an adjustment to ensure that the PHY and PHC timers are in sync. 1884 * This is done by issuing a READ_TIME command which triggers a simultaneous 1885 * read of the PHY timer and PHC timer. Then we use the difference to 1886 * calculate an appropriate 2s complement addition to add to the PHY timer in 1887 * order to ensure it reads the same value as the primary PHC timer. 1888 */ 1889 static int ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port) 1890 { 1891 u64 phc_time, phy_time, difference; 1892 int err; 1893 1894 if (!ice_ptp_lock(hw)) { 1895 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n"); 1896 return -EBUSY; 1897 } 1898 1899 err = ice_read_phy_and_phc_time_e822(hw, port, &phy_time, &phc_time); 1900 if (err) 1901 goto err_unlock; 1902 1903 /* Calculate the amount required to add to the port time in order for 1904 * it to match the PHC time. 1905 * 1906 * Note that the port adjustment is done using 2s complement 1907 * arithmetic. This is convenient since it means that we can simply 1908 * calculate the difference between the PHC time and the port time, 1909 * and it will be interpreted correctly. 1910 */ 1911 difference = phc_time - phy_time; 1912 1913 err = ice_ptp_prep_port_adj_e822(hw, port, (s64)difference); 1914 if (err) 1915 goto err_unlock; 1916 1917 err = ice_ptp_one_port_cmd(hw, port, ADJ_TIME); 1918 if (err) 1919 goto err_unlock; 1920 1921 /* Issue the sync to activate the time adjustment */ 1922 ice_ptp_exec_tmr_cmd(hw); 1923 1924 /* Re-capture the timer values to flush the command registers and 1925 * verify that the time was properly adjusted. 1926 */ 1927 err = ice_read_phy_and_phc_time_e822(hw, port, &phy_time, &phc_time); 1928 if (err) 1929 goto err_unlock; 1930 1931 dev_info(ice_hw_to_dev(hw), 1932 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n", 1933 port, (unsigned long long)phy_time, 1934 (unsigned long long)phc_time); 1935 1936 ice_ptp_unlock(hw); 1937 1938 return 0; 1939 1940 err_unlock: 1941 ice_ptp_unlock(hw); 1942 return err; 1943 } 1944 1945 /** 1946 * ice_stop_phy_timer_e822 - Stop the PHY clock timer 1947 * @hw: pointer to the HW struct 1948 * @port: the PHY port to stop 1949 * @soft_reset: if true, hold the SOFT_RESET bit of P_REG_PS 1950 * 1951 * Stop the clock of a PHY port. This must be done as part of the flow to 1952 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 1953 * initialized or when link speed changes. 1954 */ 1955 int 1956 ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset) 1957 { 1958 int err; 1959 u32 val; 1960 1961 err = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 0); 1962 if (err) 1963 return err; 1964 1965 err = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 0); 1966 if (err) 1967 return err; 1968 1969 err = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val); 1970 if (err) 1971 return err; 1972 1973 val &= ~P_REG_PS_START_M; 1974 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 1975 if (err) 1976 return err; 1977 1978 val &= ~P_REG_PS_ENA_CLK_M; 1979 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 1980 if (err) 1981 return err; 1982 1983 if (soft_reset) { 1984 val |= P_REG_PS_SFT_RESET_M; 1985 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 1986 if (err) 1987 return err; 1988 } 1989 1990 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port); 1991 1992 return 0; 1993 } 1994 1995 /** 1996 * ice_start_phy_timer_e822 - Start the PHY clock timer 1997 * @hw: pointer to the HW struct 1998 * @port: the PHY port to start 1999 * @bypass: if true, start the PHY in bypass mode 2000 * 2001 * Start the clock of a PHY port. This must be done as part of the flow to 2002 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 2003 * initialized or when link speed changes. 2004 * 2005 * Bypass mode enables timestamps immediately without waiting for Vernier 2006 * calibration to complete. Hardware will still continue taking Vernier 2007 * measurements on Tx or Rx of packets, but they will not be applied to 2008 * timestamps. Use ice_phy_exit_bypass_e822 to exit bypass mode once hardware 2009 * has completed offset calculation. 2010 */ 2011 int 2012 ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass) 2013 { 2014 u32 lo, hi, val; 2015 u64 incval; 2016 u8 tmr_idx; 2017 int err; 2018 2019 tmr_idx = ice_get_ptp_src_clock_index(hw); 2020 2021 err = ice_stop_phy_timer_e822(hw, port, false); 2022 if (err) 2023 return err; 2024 2025 ice_phy_cfg_lane_e822(hw, port); 2026 2027 err = ice_phy_cfg_uix_e822(hw, port); 2028 if (err) 2029 return err; 2030 2031 err = ice_phy_cfg_parpcs_e822(hw, port); 2032 if (err) 2033 return err; 2034 2035 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 2036 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 2037 incval = (u64)hi << 32 | lo; 2038 2039 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L, incval); 2040 if (err) 2041 return err; 2042 2043 err = ice_ptp_one_port_cmd(hw, port, INIT_INCVAL); 2044 if (err) 2045 return err; 2046 2047 ice_ptp_exec_tmr_cmd(hw); 2048 2049 err = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val); 2050 if (err) 2051 return err; 2052 2053 val |= P_REG_PS_SFT_RESET_M; 2054 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 2055 if (err) 2056 return err; 2057 2058 val |= P_REG_PS_START_M; 2059 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 2060 if (err) 2061 return err; 2062 2063 val &= ~P_REG_PS_SFT_RESET_M; 2064 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 2065 if (err) 2066 return err; 2067 2068 err = ice_ptp_one_port_cmd(hw, port, INIT_INCVAL); 2069 if (err) 2070 return err; 2071 2072 ice_ptp_exec_tmr_cmd(hw); 2073 2074 val |= P_REG_PS_ENA_CLK_M; 2075 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 2076 if (err) 2077 return err; 2078 2079 val |= P_REG_PS_LOAD_OFFSET_M; 2080 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 2081 if (err) 2082 return err; 2083 2084 ice_ptp_exec_tmr_cmd(hw); 2085 2086 err = ice_sync_phy_timer_e822(hw, port); 2087 if (err) 2088 return err; 2089 2090 if (bypass) { 2091 val |= P_REG_PS_BYPASS_MODE_M; 2092 /* Enter BYPASS mode, enabling timestamps immediately. */ 2093 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 2094 if (err) 2095 return err; 2096 2097 /* Program the fixed Tx offset */ 2098 err = ice_phy_cfg_fixed_tx_offset_e822(hw, port); 2099 if (err) 2100 return err; 2101 2102 /* Program the fixed Rx offset */ 2103 err = ice_phy_cfg_fixed_rx_offset_e822(hw, port); 2104 if (err) 2105 return err; 2106 } 2107 2108 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port); 2109 2110 return 0; 2111 } 2112 2113 /* E810 functions 2114 * 2115 * The following functions operate on the E810 series devices which use 2116 * a separate external PHY. 2117 */ 2118 2119 /** 2120 * ice_read_phy_reg_e810 - Read register from external PHY on E810 2121 * @hw: pointer to the HW struct 2122 * @addr: the address to read from 2123 * @val: On return, the value read from the PHY 2124 * 2125 * Read a register from the external PHY on the E810 device. 2126 */ 2127 static int ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val) 2128 { 2129 struct ice_sbq_msg_input msg = {0}; 2130 int err; 2131 2132 msg.msg_addr_low = lower_16_bits(addr); 2133 msg.msg_addr_high = upper_16_bits(addr); 2134 msg.opcode = ice_sbq_msg_rd; 2135 msg.dest_dev = rmn_0; 2136 2137 err = ice_sbq_rw_reg(hw, &msg); 2138 if (err) { 2139 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2140 err); 2141 return err; 2142 } 2143 2144 *val = msg.data; 2145 2146 return 0; 2147 } 2148 2149 /** 2150 * ice_write_phy_reg_e810 - Write register on external PHY on E810 2151 * @hw: pointer to the HW struct 2152 * @addr: the address to writem to 2153 * @val: the value to write to the PHY 2154 * 2155 * Write a value to a register of the external PHY on the E810 device. 2156 */ 2157 static int ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val) 2158 { 2159 struct ice_sbq_msg_input msg = {0}; 2160 int err; 2161 2162 msg.msg_addr_low = lower_16_bits(addr); 2163 msg.msg_addr_high = upper_16_bits(addr); 2164 msg.opcode = ice_sbq_msg_wr; 2165 msg.dest_dev = rmn_0; 2166 msg.data = val; 2167 2168 err = ice_sbq_rw_reg(hw, &msg); 2169 if (err) { 2170 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2171 err); 2172 return err; 2173 } 2174 2175 return 0; 2176 } 2177 2178 /** 2179 * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY 2180 * @hw: pointer to the HW struct 2181 * @lport: the lport to read from 2182 * @idx: the timestamp index to read 2183 * @tstamp: on return, the 40bit timestamp value 2184 * 2185 * Read a 40bit timestamp value out of the timestamp block of the external PHY 2186 * on the E810 device. 2187 */ 2188 static int 2189 ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) 2190 { 2191 u32 lo_addr, hi_addr, lo, hi; 2192 int err; 2193 2194 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); 2195 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); 2196 2197 err = ice_read_phy_reg_e810(hw, lo_addr, &lo); 2198 if (err) { 2199 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 2200 err); 2201 return err; 2202 } 2203 2204 err = ice_read_phy_reg_e810(hw, hi_addr, &hi); 2205 if (err) { 2206 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 2207 err); 2208 return err; 2209 } 2210 2211 /* For E810 devices, the timestamp is reported with the lower 32 bits 2212 * in the low register, and the upper 8 bits in the high register. 2213 */ 2214 *tstamp = ((u64)hi) << TS_HIGH_S | ((u64)lo & TS_LOW_M); 2215 2216 return 0; 2217 } 2218 2219 /** 2220 * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY 2221 * @hw: pointer to the HW struct 2222 * @lport: the lport to read from 2223 * @idx: the timestamp index to reset 2224 * 2225 * Clear a timestamp, resetting its valid bit, from the timestamp block of the 2226 * external PHY on the E810 device. 2227 */ 2228 static int ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx) 2229 { 2230 u32 lo_addr, hi_addr; 2231 int err; 2232 2233 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); 2234 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); 2235 2236 err = ice_write_phy_reg_e810(hw, lo_addr, 0); 2237 if (err) { 2238 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, err %d\n", 2239 err); 2240 return err; 2241 } 2242 2243 err = ice_write_phy_reg_e810(hw, hi_addr, 0); 2244 if (err) { 2245 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, err %d\n", 2246 err); 2247 return err; 2248 } 2249 2250 return 0; 2251 } 2252 2253 /** 2254 * ice_ptp_init_phy_e810 - Enable PTP function on the external PHY 2255 * @hw: pointer to HW struct 2256 * 2257 * Enable the timesync PTP functionality for the external PHY connected to 2258 * this function. 2259 */ 2260 int ice_ptp_init_phy_e810(struct ice_hw *hw) 2261 { 2262 u8 tmr_idx; 2263 int err; 2264 2265 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 2266 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx), 2267 GLTSYN_ENA_TSYN_ENA_M); 2268 if (err) 2269 ice_debug(hw, ICE_DBG_PTP, "PTP failed in ena_phy_time_syn %d\n", 2270 err); 2271 2272 return err; 2273 } 2274 2275 /** 2276 * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization 2277 * @hw: pointer to HW struct 2278 * 2279 * Perform E810-specific PTP hardware clock initialization steps. 2280 */ 2281 static int ice_ptp_init_phc_e810(struct ice_hw *hw) 2282 { 2283 /* Ensure synchronization delay is zero */ 2284 wr32(hw, GLTSYN_SYNC_DLAY, 0); 2285 2286 /* Initialize the PHY */ 2287 return ice_ptp_init_phy_e810(hw); 2288 } 2289 2290 /** 2291 * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time 2292 * @hw: Board private structure 2293 * @time: Time to initialize the PHY port clock to 2294 * 2295 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the 2296 * initial clock time. The time will not actually be programmed until the 2297 * driver issues an INIT_TIME command. 2298 * 2299 * The time value is the upper 32 bits of the PHY timer, usually in units of 2300 * nominal nanoseconds. 2301 */ 2302 static int ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time) 2303 { 2304 u8 tmr_idx; 2305 int err; 2306 2307 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 2308 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0); 2309 if (err) { 2310 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, err %d\n", 2311 err); 2312 return err; 2313 } 2314 2315 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx), time); 2316 if (err) { 2317 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, err %d\n", 2318 err); 2319 return err; 2320 } 2321 2322 return 0; 2323 } 2324 2325 /** 2326 * ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment 2327 * @hw: pointer to HW struct 2328 * @adj: adjustment value to program 2329 * 2330 * Prepare the PHY port for an atomic adjustment by programming the PHY 2331 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual adjustment 2332 * is completed by issuing an ADJ_TIME sync command. 2333 * 2334 * The adjustment value only contains the portion used for the upper 32bits of 2335 * the PHY timer, usually in units of nominal nanoseconds. Negative 2336 * adjustments are supported using 2s complement arithmetic. 2337 */ 2338 static int ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj) 2339 { 2340 u8 tmr_idx; 2341 int err; 2342 2343 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 2344 2345 /* Adjustments are represented as signed 2's complement values in 2346 * nanoseconds. Sub-nanosecond adjustment is not supported. 2347 */ 2348 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), 0); 2349 if (err) { 2350 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, err %d\n", 2351 err); 2352 return err; 2353 } 2354 2355 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), adj); 2356 if (err) { 2357 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, err %d\n", 2358 err); 2359 return err; 2360 } 2361 2362 return 0; 2363 } 2364 2365 /** 2366 * ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change 2367 * @hw: pointer to HW struct 2368 * @incval: The new 40bit increment value to prepare 2369 * 2370 * Prepare the PHY port for a new increment value by programming the PHY 2371 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual change is 2372 * completed by issuing an INIT_INCVAL command. 2373 */ 2374 static int ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval) 2375 { 2376 u32 high, low; 2377 u8 tmr_idx; 2378 int err; 2379 2380 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 2381 low = lower_32_bits(incval); 2382 high = upper_32_bits(incval); 2383 2384 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), low); 2385 if (err) { 2386 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, err %d\n", 2387 err); 2388 return err; 2389 } 2390 2391 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), high); 2392 if (err) { 2393 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, err %d\n", 2394 err); 2395 return err; 2396 } 2397 2398 return 0; 2399 } 2400 2401 /** 2402 * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command 2403 * @hw: pointer to HW struct 2404 * @cmd: Command to be sent to the port 2405 * 2406 * Prepare the external PHYs connected to this device for a timer sync 2407 * command. 2408 */ 2409 static int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 2410 { 2411 u32 cmd_val, val; 2412 int err; 2413 2414 switch (cmd) { 2415 case INIT_TIME: 2416 cmd_val = GLTSYN_CMD_INIT_TIME; 2417 break; 2418 case INIT_INCVAL: 2419 cmd_val = GLTSYN_CMD_INIT_INCVAL; 2420 break; 2421 case ADJ_TIME: 2422 cmd_val = GLTSYN_CMD_ADJ_TIME; 2423 break; 2424 case READ_TIME: 2425 cmd_val = GLTSYN_CMD_READ_TIME; 2426 break; 2427 case ADJ_TIME_AT_TIME: 2428 cmd_val = GLTSYN_CMD_ADJ_INIT_TIME; 2429 break; 2430 } 2431 2432 /* Read, modify, write */ 2433 err = ice_read_phy_reg_e810(hw, ETH_GLTSYN_CMD, &val); 2434 if (err) { 2435 ice_debug(hw, ICE_DBG_PTP, "Failed to read GLTSYN_CMD, err %d\n", err); 2436 return err; 2437 } 2438 2439 /* Modify necessary bits only and perform write */ 2440 val &= ~TS_CMD_MASK_E810; 2441 val |= cmd_val; 2442 2443 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_CMD, val); 2444 if (err) { 2445 ice_debug(hw, ICE_DBG_PTP, "Failed to write back GLTSYN_CMD, err %d\n", err); 2446 return err; 2447 } 2448 2449 return 0; 2450 } 2451 2452 /* Device agnostic functions 2453 * 2454 * The following functions implement shared behavior common to both E822 and 2455 * E810 devices, possibly calling a device specific implementation where 2456 * necessary. 2457 */ 2458 2459 /** 2460 * ice_ptp_lock - Acquire PTP global semaphore register lock 2461 * @hw: pointer to the HW struct 2462 * 2463 * Acquire the global PTP hardware semaphore lock. Returns true if the lock 2464 * was acquired, false otherwise. 2465 * 2466 * The PFTSYN_SEM register sets the busy bit on read, returning the previous 2467 * value. If software sees the busy bit cleared, this means that this function 2468 * acquired the lock (and the busy bit is now set). If software sees the busy 2469 * bit set, it means that another function acquired the lock. 2470 * 2471 * Software must clear the busy bit with a write to release the lock for other 2472 * functions when done. 2473 */ 2474 bool ice_ptp_lock(struct ice_hw *hw) 2475 { 2476 u32 hw_lock; 2477 int i; 2478 2479 #define MAX_TRIES 5 2480 2481 for (i = 0; i < MAX_TRIES; i++) { 2482 hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id)); 2483 hw_lock = hw_lock & PFTSYN_SEM_BUSY_M; 2484 if (!hw_lock) 2485 break; 2486 2487 /* Somebody is holding the lock */ 2488 usleep_range(10000, 20000); 2489 } 2490 2491 return !hw_lock; 2492 } 2493 2494 /** 2495 * ice_ptp_unlock - Release PTP global semaphore register lock 2496 * @hw: pointer to the HW struct 2497 * 2498 * Release the global PTP hardware semaphore lock. This is done by writing to 2499 * the PFTSYN_SEM register. 2500 */ 2501 void ice_ptp_unlock(struct ice_hw *hw) 2502 { 2503 wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0); 2504 } 2505 2506 /** 2507 * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command 2508 * @hw: pointer to HW struct 2509 * @cmd: the command to issue 2510 * 2511 * Prepare the source timer and PHY timers and then trigger the requested 2512 * command. This causes the shadow registers previously written in preparation 2513 * for the command to be synchronously applied to both the source and PHY 2514 * timers. 2515 */ 2516 static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 2517 { 2518 int err; 2519 2520 /* First, prepare the source timer */ 2521 ice_ptp_src_cmd(hw, cmd); 2522 2523 /* Next, prepare the ports */ 2524 if (ice_is_e810(hw)) 2525 err = ice_ptp_port_cmd_e810(hw, cmd); 2526 else 2527 err = ice_ptp_port_cmd_e822(hw, cmd); 2528 if (err) { 2529 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, err %d\n", 2530 cmd, err); 2531 return err; 2532 } 2533 2534 /* Write the sync command register to drive both source and PHY timer 2535 * commands synchronously 2536 */ 2537 ice_ptp_exec_tmr_cmd(hw); 2538 2539 return 0; 2540 } 2541 2542 /** 2543 * ice_ptp_init_time - Initialize device time to provided value 2544 * @hw: pointer to HW struct 2545 * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H) 2546 * 2547 * Initialize the device to the specified time provided. This requires a three 2548 * step process: 2549 * 2550 * 1) write the new init time to the source timer shadow registers 2551 * 2) write the new init time to the PHY timer shadow registers 2552 * 3) issue an init_time timer command to synchronously switch both the source 2553 * and port timers to the new init time value at the next clock cycle. 2554 */ 2555 int ice_ptp_init_time(struct ice_hw *hw, u64 time) 2556 { 2557 u8 tmr_idx; 2558 int err; 2559 2560 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 2561 2562 /* Source timers */ 2563 wr32(hw, GLTSYN_SHTIME_L(tmr_idx), lower_32_bits(time)); 2564 wr32(hw, GLTSYN_SHTIME_H(tmr_idx), upper_32_bits(time)); 2565 wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0); 2566 2567 /* PHY timers */ 2568 /* Fill Rx and Tx ports and send msg to PHY */ 2569 if (ice_is_e810(hw)) 2570 err = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF); 2571 else 2572 err = ice_ptp_prep_phy_time_e822(hw, time & 0xFFFFFFFF); 2573 if (err) 2574 return err; 2575 2576 return ice_ptp_tmr_cmd(hw, INIT_TIME); 2577 } 2578 2579 /** 2580 * ice_ptp_write_incval - Program PHC with new increment value 2581 * @hw: pointer to HW struct 2582 * @incval: Source timer increment value per clock cycle 2583 * 2584 * Program the PHC with a new increment value. This requires a three-step 2585 * process: 2586 * 2587 * 1) Write the increment value to the source timer shadow registers 2588 * 2) Write the increment value to the PHY timer shadow registers 2589 * 3) Issue an INIT_INCVAL timer command to synchronously switch both the 2590 * source and port timers to the new increment value at the next clock 2591 * cycle. 2592 */ 2593 int ice_ptp_write_incval(struct ice_hw *hw, u64 incval) 2594 { 2595 u8 tmr_idx; 2596 int err; 2597 2598 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 2599 2600 /* Shadow Adjust */ 2601 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), lower_32_bits(incval)); 2602 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), upper_32_bits(incval)); 2603 2604 if (ice_is_e810(hw)) 2605 err = ice_ptp_prep_phy_incval_e810(hw, incval); 2606 else 2607 err = ice_ptp_prep_phy_incval_e822(hw, incval); 2608 if (err) 2609 return err; 2610 2611 return ice_ptp_tmr_cmd(hw, INIT_INCVAL); 2612 } 2613 2614 /** 2615 * ice_ptp_write_incval_locked - Program new incval while holding semaphore 2616 * @hw: pointer to HW struct 2617 * @incval: Source timer increment value per clock cycle 2618 * 2619 * Program a new PHC incval while holding the PTP semaphore. 2620 */ 2621 int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval) 2622 { 2623 int err; 2624 2625 if (!ice_ptp_lock(hw)) 2626 return -EBUSY; 2627 2628 err = ice_ptp_write_incval(hw, incval); 2629 2630 ice_ptp_unlock(hw); 2631 2632 return err; 2633 } 2634 2635 /** 2636 * ice_ptp_adj_clock - Adjust PHC clock time atomically 2637 * @hw: pointer to HW struct 2638 * @adj: Adjustment in nanoseconds 2639 * 2640 * Perform an atomic adjustment of the PHC time by the specified number of 2641 * nanoseconds. This requires a three-step process: 2642 * 2643 * 1) Write the adjustment to the source timer shadow registers 2644 * 2) Write the adjustment to the PHY timer shadow registers 2645 * 3) Issue an ADJ_TIME timer command to synchronously apply the adjustment to 2646 * both the source and port timers at the next clock cycle. 2647 */ 2648 int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj) 2649 { 2650 u8 tmr_idx; 2651 int err; 2652 2653 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 2654 2655 /* Write the desired clock adjustment into the GLTSYN_SHADJ register. 2656 * For an ADJ_TIME command, this set of registers represents the value 2657 * to add to the clock time. It supports subtraction by interpreting 2658 * the value as a 2's complement integer. 2659 */ 2660 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0); 2661 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj); 2662 2663 if (ice_is_e810(hw)) 2664 err = ice_ptp_prep_phy_adj_e810(hw, adj); 2665 else 2666 err = ice_ptp_prep_phy_adj_e822(hw, adj); 2667 if (err) 2668 return err; 2669 2670 return ice_ptp_tmr_cmd(hw, ADJ_TIME); 2671 } 2672 2673 /** 2674 * ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block 2675 * @hw: pointer to the HW struct 2676 * @block: the block to read from 2677 * @idx: the timestamp index to read 2678 * @tstamp: on return, the 40bit timestamp value 2679 * 2680 * Read a 40bit timestamp value out of the timestamp block. For E822 devices, 2681 * the block is the quad to read from. For E810 devices, the block is the 2682 * logical port to read from. 2683 */ 2684 int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp) 2685 { 2686 if (ice_is_e810(hw)) 2687 return ice_read_phy_tstamp_e810(hw, block, idx, tstamp); 2688 else 2689 return ice_read_phy_tstamp_e822(hw, block, idx, tstamp); 2690 } 2691 2692 /** 2693 * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block 2694 * @hw: pointer to the HW struct 2695 * @block: the block to read from 2696 * @idx: the timestamp index to reset 2697 * 2698 * Clear a timestamp, resetting its valid bit, from the timestamp block. For 2699 * E822 devices, the block is the quad to clear from. For E810 devices, the 2700 * block is the logical port to clear from. 2701 */ 2702 int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx) 2703 { 2704 if (ice_is_e810(hw)) 2705 return ice_clear_phy_tstamp_e810(hw, block, idx); 2706 else 2707 return ice_clear_phy_tstamp_e822(hw, block, idx); 2708 } 2709 2710 /* E810T SMA functions 2711 * 2712 * The following functions operate specifically on E810T hardware and are used 2713 * to access the extended GPIOs available. 2714 */ 2715 2716 /** 2717 * ice_get_pca9575_handle 2718 * @hw: pointer to the hw struct 2719 * @pca9575_handle: GPIO controller's handle 2720 * 2721 * Find and return the GPIO controller's handle in the netlist. 2722 * When found - the value will be cached in the hw structure and following calls 2723 * will return cached value 2724 */ 2725 static int 2726 ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) 2727 { 2728 struct ice_aqc_get_link_topo *cmd; 2729 struct ice_aq_desc desc; 2730 int status; 2731 u8 idx; 2732 2733 /* If handle was read previously return cached value */ 2734 if (hw->io_expander_handle) { 2735 *pca9575_handle = hw->io_expander_handle; 2736 return 0; 2737 } 2738 2739 /* If handle was not detected read it from the netlist */ 2740 cmd = &desc.params.get_link_topo; 2741 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 2742 2743 /* Set node type to GPIO controller */ 2744 cmd->addr.topo_params.node_type_ctx = 2745 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & 2746 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL); 2747 2748 #define SW_PCA9575_SFP_TOPO_IDX 2 2749 #define SW_PCA9575_QSFP_TOPO_IDX 1 2750 2751 /* Check if the SW IO expander controlling SMA exists in the netlist. */ 2752 if (hw->device_id == ICE_DEV_ID_E810C_SFP) 2753 idx = SW_PCA9575_SFP_TOPO_IDX; 2754 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP) 2755 idx = SW_PCA9575_QSFP_TOPO_IDX; 2756 else 2757 return -EOPNOTSUPP; 2758 2759 cmd->addr.topo_params.index = idx; 2760 2761 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2762 if (status) 2763 return -EOPNOTSUPP; 2764 2765 /* Verify if we found the right IO expander type */ 2766 if (desc.params.get_link_topo.node_part_num != 2767 ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575) 2768 return -EOPNOTSUPP; 2769 2770 /* If present save the handle and return it */ 2771 hw->io_expander_handle = 2772 le16_to_cpu(desc.params.get_link_topo.addr.handle); 2773 *pca9575_handle = hw->io_expander_handle; 2774 2775 return 0; 2776 } 2777 2778 /** 2779 * ice_read_sma_ctrl_e810t 2780 * @hw: pointer to the hw struct 2781 * @data: pointer to data to be read from the GPIO controller 2782 * 2783 * Read the SMA controller state. It is connected to pins 3-7 of Port 1 of the 2784 * PCA9575 expander, so only bits 3-7 in data are valid. 2785 */ 2786 int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data) 2787 { 2788 int status; 2789 u16 handle; 2790 u8 i; 2791 2792 status = ice_get_pca9575_handle(hw, &handle); 2793 if (status) 2794 return status; 2795 2796 *data = 0; 2797 2798 for (i = ICE_SMA_MIN_BIT_E810T; i <= ICE_SMA_MAX_BIT_E810T; i++) { 2799 bool pin; 2800 2801 status = ice_aq_get_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, 2802 &pin, NULL); 2803 if (status) 2804 break; 2805 *data |= (u8)(!pin) << i; 2806 } 2807 2808 return status; 2809 } 2810 2811 /** 2812 * ice_write_sma_ctrl_e810t 2813 * @hw: pointer to the hw struct 2814 * @data: data to be written to the GPIO controller 2815 * 2816 * Write the data to the SMA controller. It is connected to pins 3-7 of Port 1 2817 * of the PCA9575 expander, so only bits 3-7 in data are valid. 2818 */ 2819 int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data) 2820 { 2821 int status; 2822 u16 handle; 2823 u8 i; 2824 2825 status = ice_get_pca9575_handle(hw, &handle); 2826 if (status) 2827 return status; 2828 2829 for (i = ICE_SMA_MIN_BIT_E810T; i <= ICE_SMA_MAX_BIT_E810T; i++) { 2830 bool pin; 2831 2832 pin = !(data & (1 << i)); 2833 status = ice_aq_set_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, 2834 pin, NULL); 2835 if (status) 2836 break; 2837 } 2838 2839 return status; 2840 } 2841 2842 /** 2843 * ice_is_pca9575_present 2844 * @hw: pointer to the hw struct 2845 * 2846 * Check if the SW IO expander is present in the netlist 2847 */ 2848 bool ice_is_pca9575_present(struct ice_hw *hw) 2849 { 2850 u16 handle = 0; 2851 int status; 2852 2853 if (!ice_is_e810t(hw)) 2854 return false; 2855 2856 status = ice_get_pca9575_handle(hw, &handle); 2857 2858 return !status && handle; 2859 } 2860 2861 /** 2862 * ice_ptp_init_phc - Initialize PTP hardware clock 2863 * @hw: pointer to the HW struct 2864 * 2865 * Perform the steps required to initialize the PTP hardware clock. 2866 */ 2867 int ice_ptp_init_phc(struct ice_hw *hw) 2868 { 2869 u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned; 2870 2871 /* Enable source clocks */ 2872 wr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M); 2873 2874 /* Clear event err indications for auxiliary pins */ 2875 (void)rd32(hw, GLTSYN_STAT(src_idx)); 2876 2877 if (ice_is_e810(hw)) 2878 return ice_ptp_init_phc_e810(hw); 2879 else 2880 return ice_ptp_init_phc_e822(hw); 2881 } 2882