1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (C) 2021, Intel Corporation. */ 3 4 #include <linux/delay.h> 5 #include "ice_common.h" 6 #include "ice_ptp_hw.h" 7 #include "ice_ptp_consts.h" 8 #include "ice_cgu_regs.h" 9 10 /* Low level functions for interacting with and managing the device clock used 11 * for the Precision Time Protocol. 12 * 13 * The ice hardware represents the current time using three registers: 14 * 15 * GLTSYN_TIME_H GLTSYN_TIME_L GLTSYN_TIME_R 16 * +---------------+ +---------------+ +---------------+ 17 * | 32 bits | | 32 bits | | 32 bits | 18 * +---------------+ +---------------+ +---------------+ 19 * 20 * The registers are incremented every clock tick using a 40bit increment 21 * value defined over two registers: 22 * 23 * GLTSYN_INCVAL_H GLTSYN_INCVAL_L 24 * +---------------+ +---------------+ 25 * | 8 bit s | | 32 bits | 26 * +---------------+ +---------------+ 27 * 28 * The increment value is added to the GLSTYN_TIME_R and GLSTYN_TIME_L 29 * registers every clock source tick. Depending on the specific device 30 * configuration, the clock source frequency could be one of a number of 31 * values. 32 * 33 * For E810 devices, the increment frequency is 812.5 MHz 34 * 35 * For E822 devices the clock can be derived from different sources, and the 36 * increment has an effective frequency of one of the following: 37 * - 823.4375 MHz 38 * - 783.36 MHz 39 * - 796.875 MHz 40 * - 816 MHz 41 * - 830.078125 MHz 42 * - 783.36 MHz 43 * 44 * The hardware captures timestamps in the PHY for incoming packets, and for 45 * outgoing packets on request. To support this, the PHY maintains a timer 46 * that matches the lower 64 bits of the global source timer. 47 * 48 * In order to ensure that the PHY timers and the source timer are equivalent, 49 * shadow registers are used to prepare the desired initial values. A special 50 * sync command is issued to trigger copying from the shadow registers into 51 * the appropriate source and PHY registers simultaneously. 52 * 53 * The driver supports devices which have different PHYs with subtly different 54 * mechanisms to program and control the timers. We divide the devices into 55 * families named after the first major device, E810 and similar devices, and 56 * E822 and similar devices. 57 * 58 * - E822 based devices have additional support for fine grained Vernier 59 * calibration which requires significant setup 60 * - The layout of timestamp data in the PHY register blocks is different 61 * - The way timer synchronization commands are issued is different. 62 * 63 * To support this, very low level functions have an e810 or e822 suffix 64 * indicating what type of device they work on. Higher level abstractions for 65 * tasks that can be done on both devices do not have the suffix and will 66 * correctly look up the appropriate low level function when running. 67 * 68 * Functions which only make sense on a single device family may not have 69 * a suitable generic implementation 70 */ 71 72 /** 73 * ice_get_ptp_src_clock_index - determine source clock index 74 * @hw: pointer to HW struct 75 * 76 * Determine the source clock index currently in use, based on device 77 * capabilities reported during initialization. 78 */ 79 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw) 80 { 81 return hw->func_caps.ts_func_info.tmr_index_assoc; 82 } 83 84 /** 85 * ice_ptp_read_src_incval - Read source timer increment value 86 * @hw: pointer to HW struct 87 * 88 * Read the increment value of the source timer and return it. 89 */ 90 static u64 ice_ptp_read_src_incval(struct ice_hw *hw) 91 { 92 u32 lo, hi; 93 u8 tmr_idx; 94 95 tmr_idx = ice_get_ptp_src_clock_index(hw); 96 97 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 98 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 99 100 return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo; 101 } 102 103 /** 104 * ice_ptp_src_cmd - Prepare source timer for a timer command 105 * @hw: pointer to HW structure 106 * @cmd: Timer command 107 * 108 * Prepare the source timer for an upcoming timer sync command. 109 */ 110 static void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 111 { 112 u32 cmd_val; 113 u8 tmr_idx; 114 115 tmr_idx = ice_get_ptp_src_clock_index(hw); 116 cmd_val = tmr_idx << SEL_CPK_SRC; 117 118 switch (cmd) { 119 case INIT_TIME: 120 cmd_val |= GLTSYN_CMD_INIT_TIME; 121 break; 122 case INIT_INCVAL: 123 cmd_val |= GLTSYN_CMD_INIT_INCVAL; 124 break; 125 case ADJ_TIME: 126 cmd_val |= GLTSYN_CMD_ADJ_TIME; 127 break; 128 case ADJ_TIME_AT_TIME: 129 cmd_val |= GLTSYN_CMD_ADJ_INIT_TIME; 130 break; 131 case READ_TIME: 132 cmd_val |= GLTSYN_CMD_READ_TIME; 133 break; 134 } 135 136 wr32(hw, GLTSYN_CMD, cmd_val); 137 } 138 139 /** 140 * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands 141 * @hw: pointer to HW struct 142 * 143 * Write the SYNC_EXEC_CMD bit to the GLTSYN_CMD_SYNC register, and flush the 144 * write immediately. This triggers the hardware to begin executing all of the 145 * source and PHY timer commands synchronously. 146 */ 147 static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw) 148 { 149 wr32(hw, GLTSYN_CMD_SYNC, SYNC_EXEC_CMD); 150 ice_flush(hw); 151 } 152 153 /* E822 family functions 154 * 155 * The following functions operate on the E822 family of devices. 156 */ 157 158 /** 159 * ice_fill_phy_msg_e822 - Fill message data for a PHY register access 160 * @msg: the PHY message buffer to fill in 161 * @port: the port to access 162 * @offset: the register offset 163 */ 164 static void 165 ice_fill_phy_msg_e822(struct ice_sbq_msg_input *msg, u8 port, u16 offset) 166 { 167 int phy_port, phy, quadtype; 168 169 phy_port = port % ICE_PORTS_PER_PHY; 170 phy = port / ICE_PORTS_PER_PHY; 171 quadtype = (port / ICE_PORTS_PER_QUAD) % ICE_NUM_QUAD_TYPE; 172 173 if (quadtype == 0) { 174 msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port); 175 msg->msg_addr_high = P_Q0_H(P_0_BASE + offset, phy_port); 176 } else { 177 msg->msg_addr_low = P_Q1_L(P_4_BASE + offset, phy_port); 178 msg->msg_addr_high = P_Q1_H(P_4_BASE + offset, phy_port); 179 } 180 181 if (phy == 0) 182 msg->dest_dev = rmn_0; 183 else if (phy == 1) 184 msg->dest_dev = rmn_1; 185 else 186 msg->dest_dev = rmn_2; 187 } 188 189 /** 190 * ice_is_64b_phy_reg_e822 - Check if this is a 64bit PHY register 191 * @low_addr: the low address to check 192 * @high_addr: on return, contains the high address of the 64bit register 193 * 194 * Checks if the provided low address is one of the known 64bit PHY values 195 * represented as two 32bit registers. If it is, return the appropriate high 196 * register offset to use. 197 */ 198 static bool ice_is_64b_phy_reg_e822(u16 low_addr, u16 *high_addr) 199 { 200 switch (low_addr) { 201 case P_REG_PAR_PCS_TX_OFFSET_L: 202 *high_addr = P_REG_PAR_PCS_TX_OFFSET_U; 203 return true; 204 case P_REG_PAR_PCS_RX_OFFSET_L: 205 *high_addr = P_REG_PAR_PCS_RX_OFFSET_U; 206 return true; 207 case P_REG_PAR_TX_TIME_L: 208 *high_addr = P_REG_PAR_TX_TIME_U; 209 return true; 210 case P_REG_PAR_RX_TIME_L: 211 *high_addr = P_REG_PAR_RX_TIME_U; 212 return true; 213 case P_REG_TOTAL_TX_OFFSET_L: 214 *high_addr = P_REG_TOTAL_TX_OFFSET_U; 215 return true; 216 case P_REG_TOTAL_RX_OFFSET_L: 217 *high_addr = P_REG_TOTAL_RX_OFFSET_U; 218 return true; 219 case P_REG_UIX66_10G_40G_L: 220 *high_addr = P_REG_UIX66_10G_40G_U; 221 return true; 222 case P_REG_UIX66_25G_100G_L: 223 *high_addr = P_REG_UIX66_25G_100G_U; 224 return true; 225 case P_REG_TX_CAPTURE_L: 226 *high_addr = P_REG_TX_CAPTURE_U; 227 return true; 228 case P_REG_RX_CAPTURE_L: 229 *high_addr = P_REG_RX_CAPTURE_U; 230 return true; 231 case P_REG_TX_TIMER_INC_PRE_L: 232 *high_addr = P_REG_TX_TIMER_INC_PRE_U; 233 return true; 234 case P_REG_RX_TIMER_INC_PRE_L: 235 *high_addr = P_REG_RX_TIMER_INC_PRE_U; 236 return true; 237 default: 238 return false; 239 } 240 } 241 242 /** 243 * ice_is_40b_phy_reg_e822 - Check if this is a 40bit PHY register 244 * @low_addr: the low address to check 245 * @high_addr: on return, contains the high address of the 40bit value 246 * 247 * Checks if the provided low address is one of the known 40bit PHY values 248 * split into two registers with the lower 8 bits in the low register and the 249 * upper 32 bits in the high register. If it is, return the appropriate high 250 * register offset to use. 251 */ 252 static bool ice_is_40b_phy_reg_e822(u16 low_addr, u16 *high_addr) 253 { 254 switch (low_addr) { 255 case P_REG_TIMETUS_L: 256 *high_addr = P_REG_TIMETUS_U; 257 return true; 258 case P_REG_PAR_RX_TUS_L: 259 *high_addr = P_REG_PAR_RX_TUS_U; 260 return true; 261 case P_REG_PAR_TX_TUS_L: 262 *high_addr = P_REG_PAR_TX_TUS_U; 263 return true; 264 case P_REG_PCS_RX_TUS_L: 265 *high_addr = P_REG_PCS_RX_TUS_U; 266 return true; 267 case P_REG_PCS_TX_TUS_L: 268 *high_addr = P_REG_PCS_TX_TUS_U; 269 return true; 270 case P_REG_DESK_PAR_RX_TUS_L: 271 *high_addr = P_REG_DESK_PAR_RX_TUS_U; 272 return true; 273 case P_REG_DESK_PAR_TX_TUS_L: 274 *high_addr = P_REG_DESK_PAR_TX_TUS_U; 275 return true; 276 case P_REG_DESK_PCS_RX_TUS_L: 277 *high_addr = P_REG_DESK_PCS_RX_TUS_U; 278 return true; 279 case P_REG_DESK_PCS_TX_TUS_L: 280 *high_addr = P_REG_DESK_PCS_TX_TUS_U; 281 return true; 282 default: 283 return false; 284 } 285 } 286 287 /** 288 * ice_read_phy_reg_e822 - Read a PHY register 289 * @hw: pointer to the HW struct 290 * @port: PHY port to read from 291 * @offset: PHY register offset to read 292 * @val: on return, the contents read from the PHY 293 * 294 * Read a PHY register for the given port over the device sideband queue. 295 */ 296 static int 297 ice_read_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 *val) 298 { 299 struct ice_sbq_msg_input msg = {0}; 300 int err; 301 302 ice_fill_phy_msg_e822(&msg, port, offset); 303 msg.opcode = ice_sbq_msg_rd; 304 305 err = ice_sbq_rw_reg(hw, &msg); 306 if (err) { 307 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 308 err); 309 return err; 310 } 311 312 *val = msg.data; 313 314 return 0; 315 } 316 317 /** 318 * ice_read_64b_phy_reg_e822 - Read a 64bit value from PHY registers 319 * @hw: pointer to the HW struct 320 * @port: PHY port to read from 321 * @low_addr: offset of the lower register to read from 322 * @val: on return, the contents of the 64bit value from the PHY registers 323 * 324 * Reads the two registers associated with a 64bit value and returns it in the 325 * val pointer. The offset always specifies the lower register offset to use. 326 * The high offset is looked up. This function only operates on registers 327 * known to be two parts of a 64bit value. 328 */ 329 static int 330 ice_read_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val) 331 { 332 u32 low, high; 333 u16 high_addr; 334 int err; 335 336 /* Only operate on registers known to be split into two 32bit 337 * registers. 338 */ 339 if (!ice_is_64b_phy_reg_e822(low_addr, &high_addr)) { 340 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n", 341 low_addr); 342 return -EINVAL; 343 } 344 345 err = ice_read_phy_reg_e822(hw, port, low_addr, &low); 346 if (err) { 347 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, err %d", 348 low_addr, err); 349 return err; 350 } 351 352 err = ice_read_phy_reg_e822(hw, port, high_addr, &high); 353 if (err) { 354 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, err %d", 355 high_addr, err); 356 return err; 357 } 358 359 *val = (u64)high << 32 | low; 360 361 return 0; 362 } 363 364 /** 365 * ice_write_phy_reg_e822 - Write a PHY register 366 * @hw: pointer to the HW struct 367 * @port: PHY port to write to 368 * @offset: PHY register offset to write 369 * @val: The value to write to the register 370 * 371 * Write a PHY register for the given port over the device sideband queue. 372 */ 373 static int 374 ice_write_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 val) 375 { 376 struct ice_sbq_msg_input msg = {0}; 377 int err; 378 379 ice_fill_phy_msg_e822(&msg, port, offset); 380 msg.opcode = ice_sbq_msg_wr; 381 msg.data = val; 382 383 err = ice_sbq_rw_reg(hw, &msg); 384 if (err) { 385 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 386 err); 387 return err; 388 } 389 390 return 0; 391 } 392 393 /** 394 * ice_write_40b_phy_reg_e822 - Write a 40b value to the PHY 395 * @hw: pointer to the HW struct 396 * @port: port to write to 397 * @low_addr: offset of the low register 398 * @val: 40b value to write 399 * 400 * Write the provided 40b value to the two associated registers by splitting 401 * it up into two chunks, the lower 8 bits and the upper 32 bits. 402 */ 403 static int 404 ice_write_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) 405 { 406 u32 low, high; 407 u16 high_addr; 408 int err; 409 410 /* Only operate on registers known to be split into a lower 8 bit 411 * register and an upper 32 bit register. 412 */ 413 if (!ice_is_40b_phy_reg_e822(low_addr, &high_addr)) { 414 ice_debug(hw, ICE_DBG_PTP, "Invalid 40b register addr 0x%08x\n", 415 low_addr); 416 return -EINVAL; 417 } 418 419 low = (u32)(val & P_REG_40B_LOW_M); 420 high = (u32)(val >> P_REG_40B_HIGH_S); 421 422 err = ice_write_phy_reg_e822(hw, port, low_addr, low); 423 if (err) { 424 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 425 low_addr, err); 426 return err; 427 } 428 429 err = ice_write_phy_reg_e822(hw, port, high_addr, high); 430 if (err) { 431 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 432 high_addr, err); 433 return err; 434 } 435 436 return 0; 437 } 438 439 /** 440 * ice_write_64b_phy_reg_e822 - Write a 64bit value to PHY registers 441 * @hw: pointer to the HW struct 442 * @port: PHY port to read from 443 * @low_addr: offset of the lower register to read from 444 * @val: the contents of the 64bit value to write to PHY 445 * 446 * Write the 64bit value to the two associated 32bit PHY registers. The offset 447 * is always specified as the lower register, and the high address is looked 448 * up. This function only operates on registers known to be two parts of 449 * a 64bit value. 450 */ 451 static int 452 ice_write_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) 453 { 454 u32 low, high; 455 u16 high_addr; 456 int err; 457 458 /* Only operate on registers known to be split into two 32bit 459 * registers. 460 */ 461 if (!ice_is_64b_phy_reg_e822(low_addr, &high_addr)) { 462 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n", 463 low_addr); 464 return -EINVAL; 465 } 466 467 low = lower_32_bits(val); 468 high = upper_32_bits(val); 469 470 err = ice_write_phy_reg_e822(hw, port, low_addr, low); 471 if (err) { 472 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 473 low_addr, err); 474 return err; 475 } 476 477 err = ice_write_phy_reg_e822(hw, port, high_addr, high); 478 if (err) { 479 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 480 high_addr, err); 481 return err; 482 } 483 484 return 0; 485 } 486 487 /** 488 * ice_fill_quad_msg_e822 - Fill message data for quad register access 489 * @msg: the PHY message buffer to fill in 490 * @quad: the quad to access 491 * @offset: the register offset 492 * 493 * Fill a message buffer for accessing a register in a quad shared between 494 * multiple PHYs. 495 */ 496 static void 497 ice_fill_quad_msg_e822(struct ice_sbq_msg_input *msg, u8 quad, u16 offset) 498 { 499 u32 addr; 500 501 msg->dest_dev = rmn_0; 502 503 if ((quad % ICE_NUM_QUAD_TYPE) == 0) 504 addr = Q_0_BASE + offset; 505 else 506 addr = Q_1_BASE + offset; 507 508 msg->msg_addr_low = lower_16_bits(addr); 509 msg->msg_addr_high = upper_16_bits(addr); 510 } 511 512 /** 513 * ice_read_quad_reg_e822 - Read a PHY quad register 514 * @hw: pointer to the HW struct 515 * @quad: quad to read from 516 * @offset: quad register offset to read 517 * @val: on return, the contents read from the quad 518 * 519 * Read a quad register over the device sideband queue. Quad registers are 520 * shared between multiple PHYs. 521 */ 522 int 523 ice_read_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 *val) 524 { 525 struct ice_sbq_msg_input msg = {0}; 526 int err; 527 528 if (quad >= ICE_MAX_QUAD) 529 return -EINVAL; 530 531 ice_fill_quad_msg_e822(&msg, quad, offset); 532 msg.opcode = ice_sbq_msg_rd; 533 534 err = ice_sbq_rw_reg(hw, &msg); 535 if (err) { 536 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 537 err); 538 return err; 539 } 540 541 *val = msg.data; 542 543 return 0; 544 } 545 546 /** 547 * ice_write_quad_reg_e822 - Write a PHY quad register 548 * @hw: pointer to the HW struct 549 * @quad: quad to write to 550 * @offset: quad register offset to write 551 * @val: The value to write to the register 552 * 553 * Write a quad register over the device sideband queue. Quad registers are 554 * shared between multiple PHYs. 555 */ 556 int 557 ice_write_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 val) 558 { 559 struct ice_sbq_msg_input msg = {0}; 560 int err; 561 562 if (quad >= ICE_MAX_QUAD) 563 return -EINVAL; 564 565 ice_fill_quad_msg_e822(&msg, quad, offset); 566 msg.opcode = ice_sbq_msg_wr; 567 msg.data = val; 568 569 err = ice_sbq_rw_reg(hw, &msg); 570 if (err) { 571 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 572 err); 573 return err; 574 } 575 576 return 0; 577 } 578 579 /** 580 * ice_read_phy_tstamp_e822 - Read a PHY timestamp out of the quad block 581 * @hw: pointer to the HW struct 582 * @quad: the quad to read from 583 * @idx: the timestamp index to read 584 * @tstamp: on return, the 40bit timestamp value 585 * 586 * Read a 40bit timestamp value out of the two associated registers in the 587 * quad memory block that is shared between the internal PHYs of the E822 588 * family of devices. 589 */ 590 static int 591 ice_read_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp) 592 { 593 u16 lo_addr, hi_addr; 594 u32 lo, hi; 595 int err; 596 597 lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx); 598 hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx); 599 600 err = ice_read_quad_reg_e822(hw, quad, lo_addr, &lo); 601 if (err) { 602 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 603 err); 604 return err; 605 } 606 607 err = ice_read_quad_reg_e822(hw, quad, hi_addr, &hi); 608 if (err) { 609 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 610 err); 611 return err; 612 } 613 614 /* For E822 based internal PHYs, the timestamp is reported with the 615 * lower 8 bits in the low register, and the upper 32 bits in the high 616 * register. 617 */ 618 *tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M); 619 620 return 0; 621 } 622 623 /** 624 * ice_clear_phy_tstamp_e822 - Clear a timestamp from the quad block 625 * @hw: pointer to the HW struct 626 * @quad: the quad to read from 627 * @idx: the timestamp index to reset 628 * 629 * Clear a timestamp, resetting its valid bit, from the PHY quad block that is 630 * shared between the internal PHYs on the E822 devices. 631 */ 632 static int 633 ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx) 634 { 635 u16 lo_addr, hi_addr; 636 int err; 637 638 lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx); 639 hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx); 640 641 err = ice_write_quad_reg_e822(hw, quad, lo_addr, 0); 642 if (err) { 643 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, err %d\n", 644 err); 645 return err; 646 } 647 648 err = ice_write_quad_reg_e822(hw, quad, hi_addr, 0); 649 if (err) { 650 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, err %d\n", 651 err); 652 return err; 653 } 654 655 return 0; 656 } 657 658 /** 659 * ice_ptp_reset_ts_memory_quad_e822 - Clear all timestamps from the quad block 660 * @hw: pointer to the HW struct 661 * @quad: the quad to read from 662 * 663 * Clear all timestamps from the PHY quad block that is shared between the 664 * internal PHYs on the E822 devices. 665 */ 666 void ice_ptp_reset_ts_memory_quad_e822(struct ice_hw *hw, u8 quad) 667 { 668 ice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M); 669 ice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M); 670 } 671 672 /** 673 * ice_ptp_reset_ts_memory_e822 - Clear all timestamps from all quad blocks 674 * @hw: pointer to the HW struct 675 */ 676 static void ice_ptp_reset_ts_memory_e822(struct ice_hw *hw) 677 { 678 unsigned int quad; 679 680 for (quad = 0; quad < ICE_MAX_QUAD; quad++) 681 ice_ptp_reset_ts_memory_quad_e822(hw, quad); 682 } 683 684 /** 685 * ice_read_cgu_reg_e822 - Read a CGU register 686 * @hw: pointer to the HW struct 687 * @addr: Register address to read 688 * @val: storage for register value read 689 * 690 * Read the contents of a register of the Clock Generation Unit. Only 691 * applicable to E822 devices. 692 */ 693 static int 694 ice_read_cgu_reg_e822(struct ice_hw *hw, u32 addr, u32 *val) 695 { 696 struct ice_sbq_msg_input cgu_msg; 697 int err; 698 699 cgu_msg.opcode = ice_sbq_msg_rd; 700 cgu_msg.dest_dev = cgu; 701 cgu_msg.msg_addr_low = addr; 702 cgu_msg.msg_addr_high = 0x0; 703 704 err = ice_sbq_rw_reg(hw, &cgu_msg); 705 if (err) { 706 ice_debug(hw, ICE_DBG_PTP, "Failed to read CGU register 0x%04x, err %d\n", 707 addr, err); 708 return err; 709 } 710 711 *val = cgu_msg.data; 712 713 return err; 714 } 715 716 /** 717 * ice_write_cgu_reg_e822 - Write a CGU register 718 * @hw: pointer to the HW struct 719 * @addr: Register address to write 720 * @val: value to write into the register 721 * 722 * Write the specified value to a register of the Clock Generation Unit. Only 723 * applicable to E822 devices. 724 */ 725 static int 726 ice_write_cgu_reg_e822(struct ice_hw *hw, u32 addr, u32 val) 727 { 728 struct ice_sbq_msg_input cgu_msg; 729 int err; 730 731 cgu_msg.opcode = ice_sbq_msg_wr; 732 cgu_msg.dest_dev = cgu; 733 cgu_msg.msg_addr_low = addr; 734 cgu_msg.msg_addr_high = 0x0; 735 cgu_msg.data = val; 736 737 err = ice_sbq_rw_reg(hw, &cgu_msg); 738 if (err) { 739 ice_debug(hw, ICE_DBG_PTP, "Failed to write CGU register 0x%04x, err %d\n", 740 addr, err); 741 return err; 742 } 743 744 return err; 745 } 746 747 /** 748 * ice_clk_freq_str - Convert time_ref_freq to string 749 * @clk_freq: Clock frequency 750 * 751 * Convert the specified TIME_REF clock frequency to a string. 752 */ 753 static const char *ice_clk_freq_str(u8 clk_freq) 754 { 755 switch ((enum ice_time_ref_freq)clk_freq) { 756 case ICE_TIME_REF_FREQ_25_000: 757 return "25 MHz"; 758 case ICE_TIME_REF_FREQ_122_880: 759 return "122.88 MHz"; 760 case ICE_TIME_REF_FREQ_125_000: 761 return "125 MHz"; 762 case ICE_TIME_REF_FREQ_153_600: 763 return "153.6 MHz"; 764 case ICE_TIME_REF_FREQ_156_250: 765 return "156.25 MHz"; 766 case ICE_TIME_REF_FREQ_245_760: 767 return "245.76 MHz"; 768 default: 769 return "Unknown"; 770 } 771 } 772 773 /** 774 * ice_clk_src_str - Convert time_ref_src to string 775 * @clk_src: Clock source 776 * 777 * Convert the specified clock source to its string name. 778 */ 779 static const char *ice_clk_src_str(u8 clk_src) 780 { 781 switch ((enum ice_clk_src)clk_src) { 782 case ICE_CLK_SRC_TCX0: 783 return "TCX0"; 784 case ICE_CLK_SRC_TIME_REF: 785 return "TIME_REF"; 786 default: 787 return "Unknown"; 788 } 789 } 790 791 /** 792 * ice_cfg_cgu_pll_e822 - Configure the Clock Generation Unit 793 * @hw: pointer to the HW struct 794 * @clk_freq: Clock frequency to program 795 * @clk_src: Clock source to select (TIME_REF, or TCX0) 796 * 797 * Configure the Clock Generation Unit with the desired clock frequency and 798 * time reference, enabling the PLL which drives the PTP hardware clock. 799 */ 800 static int 801 ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq, 802 enum ice_clk_src clk_src) 803 { 804 union tspll_ro_bwm_lf bwm_lf; 805 union nac_cgu_dword19 dw19; 806 union nac_cgu_dword22 dw22; 807 union nac_cgu_dword24 dw24; 808 union nac_cgu_dword9 dw9; 809 int err; 810 811 if (clk_freq >= NUM_ICE_TIME_REF_FREQ) { 812 dev_warn(ice_hw_to_dev(hw), "Invalid TIME_REF frequency %u\n", 813 clk_freq); 814 return -EINVAL; 815 } 816 817 if (clk_src >= NUM_ICE_CLK_SRC) { 818 dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n", 819 clk_src); 820 return -EINVAL; 821 } 822 823 if (clk_src == ICE_CLK_SRC_TCX0 && 824 clk_freq != ICE_TIME_REF_FREQ_25_000) { 825 dev_warn(ice_hw_to_dev(hw), 826 "TCX0 only supports 25 MHz frequency\n"); 827 return -EINVAL; 828 } 829 830 err = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD9, &dw9.val); 831 if (err) 832 return err; 833 834 err = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD24, &dw24.val); 835 if (err) 836 return err; 837 838 err = ice_read_cgu_reg_e822(hw, TSPLL_RO_BWM_LF, &bwm_lf.val); 839 if (err) 840 return err; 841 842 /* Log the current clock configuration */ 843 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 844 dw24.field.ts_pll_enable ? "enabled" : "disabled", 845 ice_clk_src_str(dw24.field.time_ref_sel), 846 ice_clk_freq_str(dw9.field.time_ref_freq_sel), 847 bwm_lf.field.plllock_true_lock_cri ? "locked" : "unlocked"); 848 849 /* Disable the PLL before changing the clock source or frequency */ 850 if (dw24.field.ts_pll_enable) { 851 dw24.field.ts_pll_enable = 0; 852 853 err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val); 854 if (err) 855 return err; 856 } 857 858 /* Set the frequency */ 859 dw9.field.time_ref_freq_sel = clk_freq; 860 err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD9, dw9.val); 861 if (err) 862 return err; 863 864 /* Configure the TS PLL feedback divisor */ 865 err = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD19, &dw19.val); 866 if (err) 867 return err; 868 869 dw19.field.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div; 870 dw19.field.tspll_ndivratio = 1; 871 872 err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD19, dw19.val); 873 if (err) 874 return err; 875 876 /* Configure the TS PLL post divisor */ 877 err = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD22, &dw22.val); 878 if (err) 879 return err; 880 881 dw22.field.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div; 882 dw22.field.time1588clk_sel_div2 = 0; 883 884 err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD22, dw22.val); 885 if (err) 886 return err; 887 888 /* Configure the TS PLL pre divisor and clock source */ 889 err = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD24, &dw24.val); 890 if (err) 891 return err; 892 893 dw24.field.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div; 894 dw24.field.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div; 895 dw24.field.time_ref_sel = clk_src; 896 897 err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val); 898 if (err) 899 return err; 900 901 /* Finally, enable the PLL */ 902 dw24.field.ts_pll_enable = 1; 903 904 err = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val); 905 if (err) 906 return err; 907 908 /* Wait to verify if the PLL locks */ 909 usleep_range(1000, 5000); 910 911 err = ice_read_cgu_reg_e822(hw, TSPLL_RO_BWM_LF, &bwm_lf.val); 912 if (err) 913 return err; 914 915 if (!bwm_lf.field.plllock_true_lock_cri) { 916 dev_warn(ice_hw_to_dev(hw), "CGU PLL failed to lock\n"); 917 return -EBUSY; 918 } 919 920 /* Log the current clock configuration */ 921 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", 922 dw24.field.ts_pll_enable ? "enabled" : "disabled", 923 ice_clk_src_str(dw24.field.time_ref_sel), 924 ice_clk_freq_str(dw9.field.time_ref_freq_sel), 925 bwm_lf.field.plllock_true_lock_cri ? "locked" : "unlocked"); 926 927 return 0; 928 } 929 930 /** 931 * ice_init_cgu_e822 - Initialize CGU with settings from firmware 932 * @hw: pointer to the HW structure 933 * 934 * Initialize the Clock Generation Unit of the E822 device. 935 */ 936 static int ice_init_cgu_e822(struct ice_hw *hw) 937 { 938 struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info; 939 union tspll_cntr_bist_settings cntr_bist; 940 int err; 941 942 err = ice_read_cgu_reg_e822(hw, TSPLL_CNTR_BIST_SETTINGS, 943 &cntr_bist.val); 944 if (err) 945 return err; 946 947 /* Disable sticky lock detection so lock err reported is accurate */ 948 cntr_bist.field.i_plllock_sel_0 = 0; 949 cntr_bist.field.i_plllock_sel_1 = 0; 950 951 err = ice_write_cgu_reg_e822(hw, TSPLL_CNTR_BIST_SETTINGS, 952 cntr_bist.val); 953 if (err) 954 return err; 955 956 /* Configure the CGU PLL using the parameters from the function 957 * capabilities. 958 */ 959 err = ice_cfg_cgu_pll_e822(hw, ts_info->time_ref, 960 (enum ice_clk_src)ts_info->clk_src); 961 if (err) 962 return err; 963 964 return 0; 965 } 966 967 /** 968 * ice_ptp_set_vernier_wl - Set the window length for vernier calibration 969 * @hw: pointer to the HW struct 970 * 971 * Set the window length used for the vernier port calibration process. 972 */ 973 static int ice_ptp_set_vernier_wl(struct ice_hw *hw) 974 { 975 u8 port; 976 977 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { 978 int err; 979 980 err = ice_write_phy_reg_e822(hw, port, P_REG_WL, 981 PTP_VERNIER_WL); 982 if (err) { 983 ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, err %d\n", 984 port, err); 985 return err; 986 } 987 } 988 989 return 0; 990 } 991 992 /** 993 * ice_ptp_init_phc_e822 - Perform E822 specific PHC initialization 994 * @hw: pointer to HW struct 995 * 996 * Perform PHC initialization steps specific to E822 devices. 997 */ 998 static int ice_ptp_init_phc_e822(struct ice_hw *hw) 999 { 1000 int err; 1001 u32 regval; 1002 1003 /* Enable reading switch and PHY registers over the sideband queue */ 1004 #define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1) 1005 #define PF_SB_REM_DEV_CTL_PHY0 BIT(2) 1006 regval = rd32(hw, PF_SB_REM_DEV_CTL); 1007 regval |= (PF_SB_REM_DEV_CTL_SWITCH_READ | 1008 PF_SB_REM_DEV_CTL_PHY0); 1009 wr32(hw, PF_SB_REM_DEV_CTL, regval); 1010 1011 /* Initialize the Clock Generation Unit */ 1012 err = ice_init_cgu_e822(hw); 1013 if (err) 1014 return err; 1015 1016 /* Set window length for all the ports */ 1017 return ice_ptp_set_vernier_wl(hw); 1018 } 1019 1020 /** 1021 * ice_ptp_prep_phy_time_e822 - Prepare PHY port with initial time 1022 * @hw: pointer to the HW struct 1023 * @time: Time to initialize the PHY port clocks to 1024 * 1025 * Program the PHY port registers with a new initial time value. The port 1026 * clock will be initialized once the driver issues an INIT_TIME sync 1027 * command. The time value is the upper 32 bits of the PHY timer, usually in 1028 * units of nominal nanoseconds. 1029 */ 1030 static int 1031 ice_ptp_prep_phy_time_e822(struct ice_hw *hw, u32 time) 1032 { 1033 u64 phy_time; 1034 u8 port; 1035 int err; 1036 1037 /* The time represents the upper 32 bits of the PHY timer, so we need 1038 * to shift to account for this when programming. 1039 */ 1040 phy_time = (u64)time << 32; 1041 1042 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { 1043 /* Tx case */ 1044 err = ice_write_64b_phy_reg_e822(hw, port, 1045 P_REG_TX_TIMER_INC_PRE_L, 1046 phy_time); 1047 if (err) 1048 goto exit_err; 1049 1050 /* Rx case */ 1051 err = ice_write_64b_phy_reg_e822(hw, port, 1052 P_REG_RX_TIMER_INC_PRE_L, 1053 phy_time); 1054 if (err) 1055 goto exit_err; 1056 } 1057 1058 return 0; 1059 1060 exit_err: 1061 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n", 1062 port, err); 1063 1064 return err; 1065 } 1066 1067 /** 1068 * ice_ptp_prep_port_adj_e822 - Prepare a single port for time adjust 1069 * @hw: pointer to HW struct 1070 * @port: Port number to be programmed 1071 * @time: time in cycles to adjust the port Tx and Rx clocks 1072 * 1073 * Program the port for an atomic adjustment by writing the Tx and Rx timer 1074 * registers. The atomic adjustment won't be completed until the driver issues 1075 * an ADJ_TIME command. 1076 * 1077 * Note that time is not in units of nanoseconds. It is in clock time 1078 * including the lower sub-nanosecond portion of the port timer. 1079 * 1080 * Negative adjustments are supported using 2s complement arithmetic. 1081 */ 1082 static int 1083 ice_ptp_prep_port_adj_e822(struct ice_hw *hw, u8 port, s64 time) 1084 { 1085 u32 l_time, u_time; 1086 int err; 1087 1088 l_time = lower_32_bits(time); 1089 u_time = upper_32_bits(time); 1090 1091 /* Tx case */ 1092 err = ice_write_phy_reg_e822(hw, port, P_REG_TX_TIMER_INC_PRE_L, 1093 l_time); 1094 if (err) 1095 goto exit_err; 1096 1097 err = ice_write_phy_reg_e822(hw, port, P_REG_TX_TIMER_INC_PRE_U, 1098 u_time); 1099 if (err) 1100 goto exit_err; 1101 1102 /* Rx case */ 1103 err = ice_write_phy_reg_e822(hw, port, P_REG_RX_TIMER_INC_PRE_L, 1104 l_time); 1105 if (err) 1106 goto exit_err; 1107 1108 err = ice_write_phy_reg_e822(hw, port, P_REG_RX_TIMER_INC_PRE_U, 1109 u_time); 1110 if (err) 1111 goto exit_err; 1112 1113 return 0; 1114 1115 exit_err: 1116 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n", 1117 port, err); 1118 return err; 1119 } 1120 1121 /** 1122 * ice_ptp_prep_phy_adj_e822 - Prep PHY ports for a time adjustment 1123 * @hw: pointer to HW struct 1124 * @adj: adjustment in nanoseconds 1125 * 1126 * Prepare the PHY ports for an atomic time adjustment by programming the PHY 1127 * Tx and Rx port registers. The actual adjustment is completed by issuing an 1128 * ADJ_TIME or ADJ_TIME_AT_TIME sync command. 1129 */ 1130 static int 1131 ice_ptp_prep_phy_adj_e822(struct ice_hw *hw, s32 adj) 1132 { 1133 s64 cycles; 1134 u8 port; 1135 1136 /* The port clock supports adjustment of the sub-nanosecond portion of 1137 * the clock. We shift the provided adjustment in nanoseconds to 1138 * calculate the appropriate adjustment to program into the PHY ports. 1139 */ 1140 if (adj > 0) 1141 cycles = (s64)adj << 32; 1142 else 1143 cycles = -(((s64)-adj) << 32); 1144 1145 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { 1146 int err; 1147 1148 err = ice_ptp_prep_port_adj_e822(hw, port, cycles); 1149 if (err) 1150 return err; 1151 } 1152 1153 return 0; 1154 } 1155 1156 /** 1157 * ice_ptp_prep_phy_incval_e822 - Prepare PHY ports for time adjustment 1158 * @hw: pointer to HW struct 1159 * @incval: new increment value to prepare 1160 * 1161 * Prepare each of the PHY ports for a new increment value by programming the 1162 * port's TIMETUS registers. The new increment value will be updated after 1163 * issuing an INIT_INCVAL command. 1164 */ 1165 static int 1166 ice_ptp_prep_phy_incval_e822(struct ice_hw *hw, u64 incval) 1167 { 1168 int err; 1169 u8 port; 1170 1171 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { 1172 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L, 1173 incval); 1174 if (err) 1175 goto exit_err; 1176 } 1177 1178 return 0; 1179 1180 exit_err: 1181 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n", 1182 port, err); 1183 1184 return err; 1185 } 1186 1187 /** 1188 * ice_ptp_read_port_capture - Read a port's local time capture 1189 * @hw: pointer to HW struct 1190 * @port: Port number to read 1191 * @tx_ts: on return, the Tx port time capture 1192 * @rx_ts: on return, the Rx port time capture 1193 * 1194 * Read the port's Tx and Rx local time capture values. 1195 * 1196 * Note this has no equivalent for the E810 devices. 1197 */ 1198 static int 1199 ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts) 1200 { 1201 int err; 1202 1203 /* Tx case */ 1204 err = ice_read_64b_phy_reg_e822(hw, port, P_REG_TX_CAPTURE_L, tx_ts); 1205 if (err) { 1206 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n", 1207 err); 1208 return err; 1209 } 1210 1211 ice_debug(hw, ICE_DBG_PTP, "tx_init = 0x%016llx\n", 1212 (unsigned long long)*tx_ts); 1213 1214 /* Rx case */ 1215 err = ice_read_64b_phy_reg_e822(hw, port, P_REG_RX_CAPTURE_L, rx_ts); 1216 if (err) { 1217 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n", 1218 err); 1219 return err; 1220 } 1221 1222 ice_debug(hw, ICE_DBG_PTP, "rx_init = 0x%016llx\n", 1223 (unsigned long long)*rx_ts); 1224 1225 return 0; 1226 } 1227 1228 /** 1229 * ice_ptp_one_port_cmd - Prepare a single PHY port for a timer command 1230 * @hw: pointer to HW struct 1231 * @port: Port to which cmd has to be sent 1232 * @cmd: Command to be sent to the port 1233 * 1234 * Prepare the requested port for an upcoming timer sync command. 1235 * 1236 * Note there is no equivalent of this operation on E810, as that device 1237 * always handles all external PHYs internally. 1238 */ 1239 static int 1240 ice_ptp_one_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd) 1241 { 1242 u32 cmd_val, val; 1243 u8 tmr_idx; 1244 int err; 1245 1246 tmr_idx = ice_get_ptp_src_clock_index(hw); 1247 cmd_val = tmr_idx << SEL_PHY_SRC; 1248 switch (cmd) { 1249 case INIT_TIME: 1250 cmd_val |= PHY_CMD_INIT_TIME; 1251 break; 1252 case INIT_INCVAL: 1253 cmd_val |= PHY_CMD_INIT_INCVAL; 1254 break; 1255 case ADJ_TIME: 1256 cmd_val |= PHY_CMD_ADJ_TIME; 1257 break; 1258 case READ_TIME: 1259 cmd_val |= PHY_CMD_READ_TIME; 1260 break; 1261 case ADJ_TIME_AT_TIME: 1262 cmd_val |= PHY_CMD_ADJ_TIME_AT_TIME; 1263 break; 1264 } 1265 1266 /* Tx case */ 1267 /* Read, modify, write */ 1268 err = ice_read_phy_reg_e822(hw, port, P_REG_TX_TMR_CMD, &val); 1269 if (err) { 1270 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_TMR_CMD, err %d\n", 1271 err); 1272 return err; 1273 } 1274 1275 /* Modify necessary bits only and perform write */ 1276 val &= ~TS_CMD_MASK; 1277 val |= cmd_val; 1278 1279 err = ice_write_phy_reg_e822(hw, port, P_REG_TX_TMR_CMD, val); 1280 if (err) { 1281 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n", 1282 err); 1283 return err; 1284 } 1285 1286 /* Rx case */ 1287 /* Read, modify, write */ 1288 err = ice_read_phy_reg_e822(hw, port, P_REG_RX_TMR_CMD, &val); 1289 if (err) { 1290 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_TMR_CMD, err %d\n", 1291 err); 1292 return err; 1293 } 1294 1295 /* Modify necessary bits only and perform write */ 1296 val &= ~TS_CMD_MASK; 1297 val |= cmd_val; 1298 1299 err = ice_write_phy_reg_e822(hw, port, P_REG_RX_TMR_CMD, val); 1300 if (err) { 1301 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n", 1302 err); 1303 return err; 1304 } 1305 1306 return 0; 1307 } 1308 1309 /** 1310 * ice_ptp_port_cmd_e822 - Prepare all ports for a timer command 1311 * @hw: pointer to the HW struct 1312 * @cmd: timer command to prepare 1313 * 1314 * Prepare all ports connected to this device for an upcoming timer sync 1315 * command. 1316 */ 1317 static int 1318 ice_ptp_port_cmd_e822(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 1319 { 1320 u8 port; 1321 1322 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { 1323 int err; 1324 1325 err = ice_ptp_one_port_cmd(hw, port, cmd); 1326 if (err) 1327 return err; 1328 } 1329 1330 return 0; 1331 } 1332 1333 /* E822 Vernier calibration functions 1334 * 1335 * The following functions are used as part of the vernier calibration of 1336 * a port. This calibration increases the precision of the timestamps on the 1337 * port. 1338 */ 1339 1340 /** 1341 * ice_phy_get_speed_and_fec_e822 - Get link speed and FEC based on serdes mode 1342 * @hw: pointer to HW struct 1343 * @port: the port to read from 1344 * @link_out: if non-NULL, holds link speed on success 1345 * @fec_out: if non-NULL, holds FEC algorithm on success 1346 * 1347 * Read the serdes data for the PHY port and extract the link speed and FEC 1348 * algorithm. 1349 */ 1350 static int 1351 ice_phy_get_speed_and_fec_e822(struct ice_hw *hw, u8 port, 1352 enum ice_ptp_link_spd *link_out, 1353 enum ice_ptp_fec_mode *fec_out) 1354 { 1355 enum ice_ptp_link_spd link; 1356 enum ice_ptp_fec_mode fec; 1357 u32 serdes; 1358 int err; 1359 1360 err = ice_read_phy_reg_e822(hw, port, P_REG_LINK_SPEED, &serdes); 1361 if (err) { 1362 ice_debug(hw, ICE_DBG_PTP, "Failed to read serdes info\n"); 1363 return err; 1364 } 1365 1366 /* Determine the FEC algorithm */ 1367 fec = (enum ice_ptp_fec_mode)P_REG_LINK_SPEED_FEC_MODE(serdes); 1368 1369 serdes &= P_REG_LINK_SPEED_SERDES_M; 1370 1371 /* Determine the link speed */ 1372 if (fec == ICE_PTP_FEC_MODE_RS_FEC) { 1373 switch (serdes) { 1374 case ICE_PTP_SERDES_25G: 1375 link = ICE_PTP_LNK_SPD_25G_RS; 1376 break; 1377 case ICE_PTP_SERDES_50G: 1378 link = ICE_PTP_LNK_SPD_50G_RS; 1379 break; 1380 case ICE_PTP_SERDES_100G: 1381 link = ICE_PTP_LNK_SPD_100G_RS; 1382 break; 1383 default: 1384 return -EIO; 1385 } 1386 } else { 1387 switch (serdes) { 1388 case ICE_PTP_SERDES_1G: 1389 link = ICE_PTP_LNK_SPD_1G; 1390 break; 1391 case ICE_PTP_SERDES_10G: 1392 link = ICE_PTP_LNK_SPD_10G; 1393 break; 1394 case ICE_PTP_SERDES_25G: 1395 link = ICE_PTP_LNK_SPD_25G; 1396 break; 1397 case ICE_PTP_SERDES_40G: 1398 link = ICE_PTP_LNK_SPD_40G; 1399 break; 1400 case ICE_PTP_SERDES_50G: 1401 link = ICE_PTP_LNK_SPD_50G; 1402 break; 1403 default: 1404 return -EIO; 1405 } 1406 } 1407 1408 if (link_out) 1409 *link_out = link; 1410 if (fec_out) 1411 *fec_out = fec; 1412 1413 return 0; 1414 } 1415 1416 /** 1417 * ice_phy_cfg_lane_e822 - Configure PHY quad for single/multi-lane timestamp 1418 * @hw: pointer to HW struct 1419 * @port: to configure the quad for 1420 */ 1421 static void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port) 1422 { 1423 enum ice_ptp_link_spd link_spd; 1424 int err; 1425 u32 val; 1426 u8 quad; 1427 1428 err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, NULL); 1429 if (err) { 1430 ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, err %d\n", 1431 err); 1432 return; 1433 } 1434 1435 quad = port / ICE_PORTS_PER_QUAD; 1436 1437 err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val); 1438 if (err) { 1439 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, err %d\n", 1440 err); 1441 return; 1442 } 1443 1444 if (link_spd >= ICE_PTP_LNK_SPD_40G) 1445 val &= ~Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M; 1446 else 1447 val |= Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M; 1448 1449 err = ice_write_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG, val); 1450 if (err) { 1451 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, err %d\n", 1452 err); 1453 return; 1454 } 1455 } 1456 1457 /** 1458 * ice_phy_cfg_uix_e822 - Configure Serdes UI to TU conversion for E822 1459 * @hw: pointer to the HW structure 1460 * @port: the port to configure 1461 * 1462 * Program the conversion ration of Serdes clock "unit intervals" (UIs) to PHC 1463 * hardware clock time units (TUs). That is, determine the number of TUs per 1464 * serdes unit interval, and program the UIX registers with this conversion. 1465 * 1466 * This conversion is used as part of the calibration process when determining 1467 * the additional error of a timestamp vs the real time of transmission or 1468 * receipt of the packet. 1469 * 1470 * Hardware uses the number of TUs per 66 UIs, written to the UIX registers 1471 * for the two main serdes clock rates, 10G/40G and 25G/100G serdes clocks. 1472 * 1473 * To calculate the conversion ratio, we use the following facts: 1474 * 1475 * a) the clock frequency in Hz (cycles per second) 1476 * b) the number of TUs per cycle (the increment value of the clock) 1477 * c) 1 second per 1 billion nanoseconds 1478 * d) the duration of 66 UIs in nanoseconds 1479 * 1480 * Given these facts, we can use the following table to work out what ratios 1481 * to multiply in order to get the number of TUs per 66 UIs: 1482 * 1483 * cycles | 1 second | incval (TUs) | nanoseconds 1484 * -------+--------------+--------------+------------- 1485 * second | 1 billion ns | cycle | 66 UIs 1486 * 1487 * To perform the multiplication using integers without too much loss of 1488 * precision, we can take use the following equation: 1489 * 1490 * (freq * incval * 6600 LINE_UI ) / ( 100 * 1 billion) 1491 * 1492 * We scale up to using 6600 UI instead of 66 in order to avoid fractional 1493 * nanosecond UIs (66 UI at 10G/40G is 6.4 ns) 1494 * 1495 * The increment value has a maximum expected range of about 34 bits, while 1496 * the frequency value is about 29 bits. Multiplying these values shouldn't 1497 * overflow the 64 bits. However, we must then further multiply them again by 1498 * the Serdes unit interval duration. To avoid overflow here, we split the 1499 * overall divide by 1e11 into a divide by 256 (shift down by 8 bits) and 1500 * a divide by 390,625,000. This does lose some precision, but avoids 1501 * miscalculation due to arithmetic overflow. 1502 */ 1503 static int ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port) 1504 { 1505 u64 cur_freq, clk_incval, tu_per_sec, uix; 1506 int err; 1507 1508 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw)); 1509 clk_incval = ice_ptp_read_src_incval(hw); 1510 1511 /* Calculate TUs per second divided by 256 */ 1512 tu_per_sec = (cur_freq * clk_incval) >> 8; 1513 1514 #define LINE_UI_10G_40G 640 /* 6600 UIs is 640 nanoseconds at 10Gb/40Gb */ 1515 #define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */ 1516 1517 /* Program the 10Gb/40Gb conversion ratio */ 1518 uix = div_u64(tu_per_sec * LINE_UI_10G_40G, 390625000); 1519 1520 err = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_10G_40G_L, 1521 uix); 1522 if (err) { 1523 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, err %d\n", 1524 err); 1525 return err; 1526 } 1527 1528 /* Program the 25Gb/100Gb conversion ratio */ 1529 uix = div_u64(tu_per_sec * LINE_UI_25G_100G, 390625000); 1530 1531 err = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_25G_100G_L, 1532 uix); 1533 if (err) { 1534 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, err %d\n", 1535 err); 1536 return err; 1537 } 1538 1539 return 0; 1540 } 1541 1542 /** 1543 * ice_phy_cfg_parpcs_e822 - Configure TUs per PAR/PCS clock cycle 1544 * @hw: pointer to the HW struct 1545 * @port: port to configure 1546 * 1547 * Configure the number of TUs for the PAR and PCS clocks used as part of the 1548 * timestamp calibration process. This depends on the link speed, as the PHY 1549 * uses different markers depending on the speed. 1550 * 1551 * 1Gb/10Gb/25Gb: 1552 * - Tx/Rx PAR/PCS markers 1553 * 1554 * 25Gb RS: 1555 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers 1556 * 1557 * 40Gb/50Gb: 1558 * - Tx/Rx PAR/PCS markers 1559 * - Rx Deskew PAR/PCS markers 1560 * 1561 * 50G RS and 100GB RS: 1562 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers 1563 * - Rx Deskew PAR/PCS markers 1564 * - Tx PAR/PCS markers 1565 * 1566 * To calculate the conversion, we use the PHC clock frequency (cycles per 1567 * second), the increment value (TUs per cycle), and the related PHY clock 1568 * frequency to calculate the TUs per unit of the PHY link clock. The 1569 * following table shows how the units convert: 1570 * 1571 * cycles | TUs | second 1572 * -------+-------+-------- 1573 * second | cycle | cycles 1574 * 1575 * For each conversion register, look up the appropriate frequency from the 1576 * e822 PAR/PCS table and calculate the TUs per unit of that clock. Program 1577 * this to the appropriate register, preparing hardware to perform timestamp 1578 * calibration to calculate the total Tx or Rx offset to adjust the timestamp 1579 * in order to calibrate for the internal PHY delays. 1580 * 1581 * Note that the increment value ranges up to ~34 bits, and the clock 1582 * frequency is ~29 bits, so multiplying them together should fit within the 1583 * 64 bit arithmetic. 1584 */ 1585 static int ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port) 1586 { 1587 u64 cur_freq, clk_incval, tu_per_sec, phy_tus; 1588 enum ice_ptp_link_spd link_spd; 1589 enum ice_ptp_fec_mode fec_mode; 1590 int err; 1591 1592 err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode); 1593 if (err) 1594 return err; 1595 1596 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw)); 1597 clk_incval = ice_ptp_read_src_incval(hw); 1598 1599 /* Calculate TUs per cycle of the PHC clock */ 1600 tu_per_sec = cur_freq * clk_incval; 1601 1602 /* For each PHY conversion register, look up the appropriate link 1603 * speed frequency and determine the TUs per that clock's cycle time. 1604 * Split this into a high and low value and then program the 1605 * appropriate register. If that link speed does not use the 1606 * associated register, write zeros to clear it instead. 1607 */ 1608 1609 /* P_REG_PAR_TX_TUS */ 1610 if (e822_vernier[link_spd].tx_par_clk) 1611 phy_tus = div_u64(tu_per_sec, 1612 e822_vernier[link_spd].tx_par_clk); 1613 else 1614 phy_tus = 0; 1615 1616 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PAR_TX_TUS_L, 1617 phy_tus); 1618 if (err) 1619 return err; 1620 1621 /* P_REG_PAR_RX_TUS */ 1622 if (e822_vernier[link_spd].rx_par_clk) 1623 phy_tus = div_u64(tu_per_sec, 1624 e822_vernier[link_spd].rx_par_clk); 1625 else 1626 phy_tus = 0; 1627 1628 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PAR_RX_TUS_L, 1629 phy_tus); 1630 if (err) 1631 return err; 1632 1633 /* P_REG_PCS_TX_TUS */ 1634 if (e822_vernier[link_spd].tx_pcs_clk) 1635 phy_tus = div_u64(tu_per_sec, 1636 e822_vernier[link_spd].tx_pcs_clk); 1637 else 1638 phy_tus = 0; 1639 1640 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PCS_TX_TUS_L, 1641 phy_tus); 1642 if (err) 1643 return err; 1644 1645 /* P_REG_PCS_RX_TUS */ 1646 if (e822_vernier[link_spd].rx_pcs_clk) 1647 phy_tus = div_u64(tu_per_sec, 1648 e822_vernier[link_spd].rx_pcs_clk); 1649 else 1650 phy_tus = 0; 1651 1652 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PCS_RX_TUS_L, 1653 phy_tus); 1654 if (err) 1655 return err; 1656 1657 /* P_REG_DESK_PAR_TX_TUS */ 1658 if (e822_vernier[link_spd].tx_desk_rsgb_par) 1659 phy_tus = div_u64(tu_per_sec, 1660 e822_vernier[link_spd].tx_desk_rsgb_par); 1661 else 1662 phy_tus = 0; 1663 1664 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PAR_TX_TUS_L, 1665 phy_tus); 1666 if (err) 1667 return err; 1668 1669 /* P_REG_DESK_PAR_RX_TUS */ 1670 if (e822_vernier[link_spd].rx_desk_rsgb_par) 1671 phy_tus = div_u64(tu_per_sec, 1672 e822_vernier[link_spd].rx_desk_rsgb_par); 1673 else 1674 phy_tus = 0; 1675 1676 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PAR_RX_TUS_L, 1677 phy_tus); 1678 if (err) 1679 return err; 1680 1681 /* P_REG_DESK_PCS_TX_TUS */ 1682 if (e822_vernier[link_spd].tx_desk_rsgb_pcs) 1683 phy_tus = div_u64(tu_per_sec, 1684 e822_vernier[link_spd].tx_desk_rsgb_pcs); 1685 else 1686 phy_tus = 0; 1687 1688 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PCS_TX_TUS_L, 1689 phy_tus); 1690 if (err) 1691 return err; 1692 1693 /* P_REG_DESK_PCS_RX_TUS */ 1694 if (e822_vernier[link_spd].rx_desk_rsgb_pcs) 1695 phy_tus = div_u64(tu_per_sec, 1696 e822_vernier[link_spd].rx_desk_rsgb_pcs); 1697 else 1698 phy_tus = 0; 1699 1700 return ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PCS_RX_TUS_L, 1701 phy_tus); 1702 } 1703 1704 /** 1705 * ice_calc_fixed_tx_offset_e822 - Calculated Fixed Tx offset for a port 1706 * @hw: pointer to the HW struct 1707 * @link_spd: the Link speed to calculate for 1708 * 1709 * Calculate the fixed offset due to known static latency data. 1710 */ 1711 static u64 1712 ice_calc_fixed_tx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) 1713 { 1714 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset; 1715 1716 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw)); 1717 clk_incval = ice_ptp_read_src_incval(hw); 1718 1719 /* Calculate TUs per second */ 1720 tu_per_sec = cur_freq * clk_incval; 1721 1722 /* Calculate number of TUs to add for the fixed Tx latency. Since the 1723 * latency measurement is in 1/100th of a nanosecond, we need to 1724 * multiply by tu_per_sec and then divide by 1e11. This calculation 1725 * overflows 64 bit integer arithmetic, so break it up into two 1726 * divisions by 1e4 first then by 1e7. 1727 */ 1728 fixed_offset = div_u64(tu_per_sec, 10000); 1729 fixed_offset *= e822_vernier[link_spd].tx_fixed_delay; 1730 fixed_offset = div_u64(fixed_offset, 10000000); 1731 1732 return fixed_offset; 1733 } 1734 1735 /** 1736 * ice_phy_cfg_tx_offset_e822 - Configure total Tx timestamp offset 1737 * @hw: pointer to the HW struct 1738 * @port: the PHY port to configure 1739 * 1740 * Program the P_REG_TOTAL_TX_OFFSET register with the total number of TUs to 1741 * adjust Tx timestamps by. This is calculated by combining some known static 1742 * latency along with the Vernier offset computations done by hardware. 1743 * 1744 * This function will not return successfully until the Tx offset calculations 1745 * have been completed, which requires waiting until at least one packet has 1746 * been transmitted by the device. It is safe to call this function 1747 * periodically until calibration succeeds, as it will only program the offset 1748 * once. 1749 * 1750 * To avoid overflow, when calculating the offset based on the known static 1751 * latency values, we use measurements in 1/100th of a nanosecond, and divide 1752 * the TUs per second up front. This avoids overflow while allowing 1753 * calculation of the adjustment using integer arithmetic. 1754 * 1755 * Returns zero on success, -EBUSY if the hardware vernier offset 1756 * calibration has not completed, or another error code on failure. 1757 */ 1758 int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port) 1759 { 1760 enum ice_ptp_link_spd link_spd; 1761 enum ice_ptp_fec_mode fec_mode; 1762 u64 total_offset, val; 1763 int err; 1764 u32 reg; 1765 1766 /* Nothing to do if we've already programmed the offset */ 1767 err = ice_read_phy_reg_e822(hw, port, P_REG_TX_OR, ®); 1768 if (err) { 1769 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OR for port %u, err %d\n", 1770 port, err); 1771 return err; 1772 } 1773 1774 if (reg) 1775 return 0; 1776 1777 err = ice_read_phy_reg_e822(hw, port, P_REG_TX_OV_STATUS, ®); 1778 if (err) { 1779 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for port %u, err %d\n", 1780 port, err); 1781 return err; 1782 } 1783 1784 if (!(reg & P_REG_TX_OV_STATUS_OV_M)) 1785 return -EBUSY; 1786 1787 err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode); 1788 if (err) 1789 return err; 1790 1791 total_offset = ice_calc_fixed_tx_offset_e822(hw, link_spd); 1792 1793 /* Read the first Vernier offset from the PHY register and add it to 1794 * the total offset. 1795 */ 1796 if (link_spd == ICE_PTP_LNK_SPD_1G || 1797 link_spd == ICE_PTP_LNK_SPD_10G || 1798 link_spd == ICE_PTP_LNK_SPD_25G || 1799 link_spd == ICE_PTP_LNK_SPD_25G_RS || 1800 link_spd == ICE_PTP_LNK_SPD_40G || 1801 link_spd == ICE_PTP_LNK_SPD_50G) { 1802 err = ice_read_64b_phy_reg_e822(hw, port, 1803 P_REG_PAR_PCS_TX_OFFSET_L, 1804 &val); 1805 if (err) 1806 return err; 1807 1808 total_offset += val; 1809 } 1810 1811 /* For Tx, we only need to use the second Vernier offset for 1812 * multi-lane link speeds with RS-FEC. The lanes will always be 1813 * aligned. 1814 */ 1815 if (link_spd == ICE_PTP_LNK_SPD_50G_RS || 1816 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 1817 err = ice_read_64b_phy_reg_e822(hw, port, 1818 P_REG_PAR_TX_TIME_L, 1819 &val); 1820 if (err) 1821 return err; 1822 1823 total_offset += val; 1824 } 1825 1826 /* Now that the total offset has been calculated, program it to the 1827 * PHY and indicate that the Tx offset is ready. After this, 1828 * timestamps will be enabled. 1829 */ 1830 err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L, 1831 total_offset); 1832 if (err) 1833 return err; 1834 1835 err = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1); 1836 if (err) 1837 return err; 1838 1839 dev_info(ice_hw_to_dev(hw), "Port=%d Tx vernier offset calibration complete\n", 1840 port); 1841 1842 return 0; 1843 } 1844 1845 /** 1846 * ice_phy_calc_pmd_adj_e822 - Calculate PMD adjustment for Rx 1847 * @hw: pointer to the HW struct 1848 * @port: the PHY port to adjust for 1849 * @link_spd: the current link speed of the PHY 1850 * @fec_mode: the current FEC mode of the PHY 1851 * @pmd_adj: on return, the amount to adjust the Rx total offset by 1852 * 1853 * Calculates the adjustment to Rx timestamps due to PMD alignment in the PHY. 1854 * This varies by link speed and FEC mode. The value calculated accounts for 1855 * various delays caused when receiving a packet. 1856 */ 1857 static int 1858 ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port, 1859 enum ice_ptp_link_spd link_spd, 1860 enum ice_ptp_fec_mode fec_mode, u64 *pmd_adj) 1861 { 1862 u64 cur_freq, clk_incval, tu_per_sec, mult, adj; 1863 u8 pmd_align; 1864 u32 val; 1865 int err; 1866 1867 err = ice_read_phy_reg_e822(hw, port, P_REG_PMD_ALIGNMENT, &val); 1868 if (err) { 1869 ice_debug(hw, ICE_DBG_PTP, "Failed to read PMD alignment, err %d\n", 1870 err); 1871 return err; 1872 } 1873 1874 pmd_align = (u8)val; 1875 1876 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw)); 1877 clk_incval = ice_ptp_read_src_incval(hw); 1878 1879 /* Calculate TUs per second */ 1880 tu_per_sec = cur_freq * clk_incval; 1881 1882 /* The PMD alignment adjustment measurement depends on the link speed, 1883 * and whether FEC is enabled. For each link speed, the alignment 1884 * adjustment is calculated by dividing a value by the length of 1885 * a Time Unit in nanoseconds. 1886 * 1887 * 1G: align == 4 ? 10 * 0.8 : (align + 6 % 10) * 0.8 1888 * 10G: align == 65 ? 0 : (align * 0.1 * 32/33) 1889 * 10G w/FEC: align * 0.1 * 32/33 1890 * 25G: align == 65 ? 0 : (align * 0.4 * 32/33) 1891 * 25G w/FEC: align * 0.4 * 32/33 1892 * 40G: align == 65 ? 0 : (align * 0.1 * 32/33) 1893 * 40G w/FEC: align * 0.1 * 32/33 1894 * 50G: align == 65 ? 0 : (align * 0.4 * 32/33) 1895 * 50G w/FEC: align * 0.8 * 32/33 1896 * 1897 * For RS-FEC, if align is < 17 then we must also add 1.6 * 32/33. 1898 * 1899 * To allow for calculating this value using integer arithmetic, we 1900 * instead start with the number of TUs per second, (inverse of the 1901 * length of a Time Unit in nanoseconds), multiply by a value based 1902 * on the PMD alignment register, and then divide by the right value 1903 * calculated based on the table above. To avoid integer overflow this 1904 * division is broken up into a step of dividing by 125 first. 1905 */ 1906 if (link_spd == ICE_PTP_LNK_SPD_1G) { 1907 if (pmd_align == 4) 1908 mult = 10; 1909 else 1910 mult = (pmd_align + 6) % 10; 1911 } else if (link_spd == ICE_PTP_LNK_SPD_10G || 1912 link_spd == ICE_PTP_LNK_SPD_25G || 1913 link_spd == ICE_PTP_LNK_SPD_40G || 1914 link_spd == ICE_PTP_LNK_SPD_50G) { 1915 /* If Clause 74 FEC, always calculate PMD adjust */ 1916 if (pmd_align != 65 || fec_mode == ICE_PTP_FEC_MODE_CLAUSE74) 1917 mult = pmd_align; 1918 else 1919 mult = 0; 1920 } else if (link_spd == ICE_PTP_LNK_SPD_25G_RS || 1921 link_spd == ICE_PTP_LNK_SPD_50G_RS || 1922 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 1923 if (pmd_align < 17) 1924 mult = pmd_align + 40; 1925 else 1926 mult = pmd_align; 1927 } else { 1928 ice_debug(hw, ICE_DBG_PTP, "Unknown link speed %d, skipping PMD adjustment\n", 1929 link_spd); 1930 mult = 0; 1931 } 1932 1933 /* In some cases, there's no need to adjust for the PMD alignment */ 1934 if (!mult) { 1935 *pmd_adj = 0; 1936 return 0; 1937 } 1938 1939 /* Calculate the adjustment by multiplying TUs per second by the 1940 * appropriate multiplier and divisor. To avoid overflow, we first 1941 * divide by 125, and then handle remaining divisor based on the link 1942 * speed pmd_adj_divisor value. 1943 */ 1944 adj = div_u64(tu_per_sec, 125); 1945 adj *= mult; 1946 adj = div_u64(adj, e822_vernier[link_spd].pmd_adj_divisor); 1947 1948 /* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx 1949 * cycle count is necessary. 1950 */ 1951 if (link_spd == ICE_PTP_LNK_SPD_25G_RS) { 1952 u64 cycle_adj; 1953 u8 rx_cycle; 1954 1955 err = ice_read_phy_reg_e822(hw, port, P_REG_RX_40_TO_160_CNT, 1956 &val); 1957 if (err) { 1958 ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, err %d\n", 1959 err); 1960 return err; 1961 } 1962 1963 rx_cycle = val & P_REG_RX_40_TO_160_CNT_RXCYC_M; 1964 if (rx_cycle) { 1965 mult = (4 - rx_cycle) * 40; 1966 1967 cycle_adj = div_u64(tu_per_sec, 125); 1968 cycle_adj *= mult; 1969 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor); 1970 1971 adj += cycle_adj; 1972 } 1973 } else if (link_spd == ICE_PTP_LNK_SPD_50G_RS) { 1974 u64 cycle_adj; 1975 u8 rx_cycle; 1976 1977 err = ice_read_phy_reg_e822(hw, port, P_REG_RX_80_TO_160_CNT, 1978 &val); 1979 if (err) { 1980 ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, err %d\n", 1981 err); 1982 return err; 1983 } 1984 1985 rx_cycle = val & P_REG_RX_80_TO_160_CNT_RXCYC_M; 1986 if (rx_cycle) { 1987 mult = rx_cycle * 40; 1988 1989 cycle_adj = div_u64(tu_per_sec, 125); 1990 cycle_adj *= mult; 1991 cycle_adj = div_u64(cycle_adj, e822_vernier[link_spd].pmd_adj_divisor); 1992 1993 adj += cycle_adj; 1994 } 1995 } 1996 1997 /* Return the calculated adjustment */ 1998 *pmd_adj = adj; 1999 2000 return 0; 2001 } 2002 2003 /** 2004 * ice_calc_fixed_rx_offset_e822 - Calculated the fixed Rx offset for a port 2005 * @hw: pointer to HW struct 2006 * @link_spd: The Link speed to calculate for 2007 * 2008 * Determine the fixed Rx latency for a given link speed. 2009 */ 2010 static u64 2011 ice_calc_fixed_rx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) 2012 { 2013 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset; 2014 2015 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw)); 2016 clk_incval = ice_ptp_read_src_incval(hw); 2017 2018 /* Calculate TUs per second */ 2019 tu_per_sec = cur_freq * clk_incval; 2020 2021 /* Calculate number of TUs to add for the fixed Rx latency. Since the 2022 * latency measurement is in 1/100th of a nanosecond, we need to 2023 * multiply by tu_per_sec and then divide by 1e11. This calculation 2024 * overflows 64 bit integer arithmetic, so break it up into two 2025 * divisions by 1e4 first then by 1e7. 2026 */ 2027 fixed_offset = div_u64(tu_per_sec, 10000); 2028 fixed_offset *= e822_vernier[link_spd].rx_fixed_delay; 2029 fixed_offset = div_u64(fixed_offset, 10000000); 2030 2031 return fixed_offset; 2032 } 2033 2034 /** 2035 * ice_phy_cfg_rx_offset_e822 - Configure total Rx timestamp offset 2036 * @hw: pointer to the HW struct 2037 * @port: the PHY port to configure 2038 * 2039 * Program the P_REG_TOTAL_RX_OFFSET register with the number of Time Units to 2040 * adjust Rx timestamps by. This combines calculations from the Vernier offset 2041 * measurements taken in hardware with some data about known fixed delay as 2042 * well as adjusting for multi-lane alignment delay. 2043 * 2044 * This function will not return successfully until the Rx offset calculations 2045 * have been completed, which requires waiting until at least one packet has 2046 * been received by the device. It is safe to call this function periodically 2047 * until calibration succeeds, as it will only program the offset once. 2048 * 2049 * This function must be called only after the offset registers are valid, 2050 * i.e. after the Vernier calibration wait has passed, to ensure that the PHY 2051 * has measured the offset. 2052 * 2053 * To avoid overflow, when calculating the offset based on the known static 2054 * latency values, we use measurements in 1/100th of a nanosecond, and divide 2055 * the TUs per second up front. This avoids overflow while allowing 2056 * calculation of the adjustment using integer arithmetic. 2057 * 2058 * Returns zero on success, -EBUSY if the hardware vernier offset 2059 * calibration has not completed, or another error code on failure. 2060 */ 2061 int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port) 2062 { 2063 enum ice_ptp_link_spd link_spd; 2064 enum ice_ptp_fec_mode fec_mode; 2065 u64 total_offset, pmd, val; 2066 int err; 2067 u32 reg; 2068 2069 /* Nothing to do if we've already programmed the offset */ 2070 err = ice_read_phy_reg_e822(hw, port, P_REG_RX_OR, ®); 2071 if (err) { 2072 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OR for port %u, err %d\n", 2073 port, err); 2074 return err; 2075 } 2076 2077 if (reg) 2078 return 0; 2079 2080 err = ice_read_phy_reg_e822(hw, port, P_REG_RX_OV_STATUS, ®); 2081 if (err) { 2082 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for port %u, err %d\n", 2083 port, err); 2084 return err; 2085 } 2086 2087 if (!(reg & P_REG_RX_OV_STATUS_OV_M)) 2088 return -EBUSY; 2089 2090 err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode); 2091 if (err) 2092 return err; 2093 2094 total_offset = ice_calc_fixed_rx_offset_e822(hw, link_spd); 2095 2096 /* Read the first Vernier offset from the PHY register and add it to 2097 * the total offset. 2098 */ 2099 err = ice_read_64b_phy_reg_e822(hw, port, 2100 P_REG_PAR_PCS_RX_OFFSET_L, 2101 &val); 2102 if (err) 2103 return err; 2104 2105 total_offset += val; 2106 2107 /* For Rx, all multi-lane link speeds include a second Vernier 2108 * calibration, because the lanes might not be aligned. 2109 */ 2110 if (link_spd == ICE_PTP_LNK_SPD_40G || 2111 link_spd == ICE_PTP_LNK_SPD_50G || 2112 link_spd == ICE_PTP_LNK_SPD_50G_RS || 2113 link_spd == ICE_PTP_LNK_SPD_100G_RS) { 2114 err = ice_read_64b_phy_reg_e822(hw, port, 2115 P_REG_PAR_RX_TIME_L, 2116 &val); 2117 if (err) 2118 return err; 2119 2120 total_offset += val; 2121 } 2122 2123 /* In addition, Rx must account for the PMD alignment */ 2124 err = ice_phy_calc_pmd_adj_e822(hw, port, link_spd, fec_mode, &pmd); 2125 if (err) 2126 return err; 2127 2128 /* For RS-FEC, this adjustment adds delay, but for other modes, it 2129 * subtracts delay. 2130 */ 2131 if (fec_mode == ICE_PTP_FEC_MODE_RS_FEC) 2132 total_offset += pmd; 2133 else 2134 total_offset -= pmd; 2135 2136 /* Now that the total offset has been calculated, program it to the 2137 * PHY and indicate that the Rx offset is ready. After this, 2138 * timestamps will be enabled. 2139 */ 2140 err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L, 2141 total_offset); 2142 if (err) 2143 return err; 2144 2145 err = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1); 2146 if (err) 2147 return err; 2148 2149 dev_info(ice_hw_to_dev(hw), "Port=%d Rx vernier offset calibration complete\n", 2150 port); 2151 2152 return 0; 2153 } 2154 2155 /** 2156 * ice_read_phy_and_phc_time_e822 - Simultaneously capture PHC and PHY time 2157 * @hw: pointer to the HW struct 2158 * @port: the PHY port to read 2159 * @phy_time: on return, the 64bit PHY timer value 2160 * @phc_time: on return, the lower 64bits of PHC time 2161 * 2162 * Issue a READ_TIME timer command to simultaneously capture the PHY and PHC 2163 * timer values. 2164 */ 2165 static int 2166 ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8 port, u64 *phy_time, 2167 u64 *phc_time) 2168 { 2169 u64 tx_time, rx_time; 2170 u32 zo, lo; 2171 u8 tmr_idx; 2172 int err; 2173 2174 tmr_idx = ice_get_ptp_src_clock_index(hw); 2175 2176 /* Prepare the PHC timer for a READ_TIME capture command */ 2177 ice_ptp_src_cmd(hw, READ_TIME); 2178 2179 /* Prepare the PHY timer for a READ_TIME capture command */ 2180 err = ice_ptp_one_port_cmd(hw, port, READ_TIME); 2181 if (err) 2182 return err; 2183 2184 /* Issue the sync to start the READ_TIME capture */ 2185 ice_ptp_exec_tmr_cmd(hw); 2186 2187 /* Read the captured PHC time from the shadow time registers */ 2188 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx)); 2189 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx)); 2190 *phc_time = (u64)lo << 32 | zo; 2191 2192 /* Read the captured PHY time from the PHY shadow registers */ 2193 err = ice_ptp_read_port_capture(hw, port, &tx_time, &rx_time); 2194 if (err) 2195 return err; 2196 2197 /* If the PHY Tx and Rx timers don't match, log a warning message. 2198 * Note that this should not happen in normal circumstances since the 2199 * driver always programs them together. 2200 */ 2201 if (tx_time != rx_time) 2202 dev_warn(ice_hw_to_dev(hw), 2203 "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n", 2204 port, (unsigned long long)tx_time, 2205 (unsigned long long)rx_time); 2206 2207 *phy_time = tx_time; 2208 2209 return 0; 2210 } 2211 2212 /** 2213 * ice_sync_phy_timer_e822 - Synchronize the PHY timer with PHC timer 2214 * @hw: pointer to the HW struct 2215 * @port: the PHY port to synchronize 2216 * 2217 * Perform an adjustment to ensure that the PHY and PHC timers are in sync. 2218 * This is done by issuing a READ_TIME command which triggers a simultaneous 2219 * read of the PHY timer and PHC timer. Then we use the difference to 2220 * calculate an appropriate 2s complement addition to add to the PHY timer in 2221 * order to ensure it reads the same value as the primary PHC timer. 2222 */ 2223 static int ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port) 2224 { 2225 u64 phc_time, phy_time, difference; 2226 int err; 2227 2228 if (!ice_ptp_lock(hw)) { 2229 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n"); 2230 return -EBUSY; 2231 } 2232 2233 err = ice_read_phy_and_phc_time_e822(hw, port, &phy_time, &phc_time); 2234 if (err) 2235 goto err_unlock; 2236 2237 /* Calculate the amount required to add to the port time in order for 2238 * it to match the PHC time. 2239 * 2240 * Note that the port adjustment is done using 2s complement 2241 * arithmetic. This is convenient since it means that we can simply 2242 * calculate the difference between the PHC time and the port time, 2243 * and it will be interpreted correctly. 2244 */ 2245 difference = phc_time - phy_time; 2246 2247 err = ice_ptp_prep_port_adj_e822(hw, port, (s64)difference); 2248 if (err) 2249 goto err_unlock; 2250 2251 err = ice_ptp_one_port_cmd(hw, port, ADJ_TIME); 2252 if (err) 2253 goto err_unlock; 2254 2255 /* Issue the sync to activate the time adjustment */ 2256 ice_ptp_exec_tmr_cmd(hw); 2257 2258 /* Re-capture the timer values to flush the command registers and 2259 * verify that the time was properly adjusted. 2260 */ 2261 err = ice_read_phy_and_phc_time_e822(hw, port, &phy_time, &phc_time); 2262 if (err) 2263 goto err_unlock; 2264 2265 dev_info(ice_hw_to_dev(hw), 2266 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n", 2267 port, (unsigned long long)phy_time, 2268 (unsigned long long)phc_time); 2269 2270 ice_ptp_unlock(hw); 2271 2272 return 0; 2273 2274 err_unlock: 2275 ice_ptp_unlock(hw); 2276 return err; 2277 } 2278 2279 /** 2280 * ice_stop_phy_timer_e822 - Stop the PHY clock timer 2281 * @hw: pointer to the HW struct 2282 * @port: the PHY port to stop 2283 * @soft_reset: if true, hold the SOFT_RESET bit of P_REG_PS 2284 * 2285 * Stop the clock of a PHY port. This must be done as part of the flow to 2286 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 2287 * initialized or when link speed changes. 2288 */ 2289 int 2290 ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset) 2291 { 2292 int err; 2293 u32 val; 2294 2295 err = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 0); 2296 if (err) 2297 return err; 2298 2299 err = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 0); 2300 if (err) 2301 return err; 2302 2303 err = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val); 2304 if (err) 2305 return err; 2306 2307 val &= ~P_REG_PS_START_M; 2308 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 2309 if (err) 2310 return err; 2311 2312 val &= ~P_REG_PS_ENA_CLK_M; 2313 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 2314 if (err) 2315 return err; 2316 2317 if (soft_reset) { 2318 val |= P_REG_PS_SFT_RESET_M; 2319 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 2320 if (err) 2321 return err; 2322 } 2323 2324 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port); 2325 2326 return 0; 2327 } 2328 2329 /** 2330 * ice_start_phy_timer_e822 - Start the PHY clock timer 2331 * @hw: pointer to the HW struct 2332 * @port: the PHY port to start 2333 * 2334 * Start the clock of a PHY port. This must be done as part of the flow to 2335 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 2336 * initialized or when link speed changes. 2337 * 2338 * Hardware will take Vernier measurements on Tx or Rx of packets. 2339 */ 2340 int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port) 2341 { 2342 u32 lo, hi, val; 2343 u64 incval; 2344 u8 tmr_idx; 2345 int err; 2346 2347 tmr_idx = ice_get_ptp_src_clock_index(hw); 2348 2349 err = ice_stop_phy_timer_e822(hw, port, false); 2350 if (err) 2351 return err; 2352 2353 ice_phy_cfg_lane_e822(hw, port); 2354 2355 err = ice_phy_cfg_uix_e822(hw, port); 2356 if (err) 2357 return err; 2358 2359 err = ice_phy_cfg_parpcs_e822(hw, port); 2360 if (err) 2361 return err; 2362 2363 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 2364 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 2365 incval = (u64)hi << 32 | lo; 2366 2367 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L, incval); 2368 if (err) 2369 return err; 2370 2371 err = ice_ptp_one_port_cmd(hw, port, INIT_INCVAL); 2372 if (err) 2373 return err; 2374 2375 ice_ptp_exec_tmr_cmd(hw); 2376 2377 err = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val); 2378 if (err) 2379 return err; 2380 2381 val |= P_REG_PS_SFT_RESET_M; 2382 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 2383 if (err) 2384 return err; 2385 2386 val |= P_REG_PS_START_M; 2387 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 2388 if (err) 2389 return err; 2390 2391 val &= ~P_REG_PS_SFT_RESET_M; 2392 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 2393 if (err) 2394 return err; 2395 2396 err = ice_ptp_one_port_cmd(hw, port, INIT_INCVAL); 2397 if (err) 2398 return err; 2399 2400 ice_ptp_exec_tmr_cmd(hw); 2401 2402 val |= P_REG_PS_ENA_CLK_M; 2403 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 2404 if (err) 2405 return err; 2406 2407 val |= P_REG_PS_LOAD_OFFSET_M; 2408 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 2409 if (err) 2410 return err; 2411 2412 ice_ptp_exec_tmr_cmd(hw); 2413 2414 err = ice_sync_phy_timer_e822(hw, port); 2415 if (err) 2416 return err; 2417 2418 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port); 2419 2420 return 0; 2421 } 2422 2423 /** 2424 * ice_get_phy_tx_tstamp_ready_e822 - Read Tx memory status register 2425 * @hw: pointer to the HW struct 2426 * @quad: the timestamp quad to read from 2427 * @tstamp_ready: contents of the Tx memory status register 2428 * 2429 * Read the Q_REG_TX_MEMORY_STATUS register indicating which timestamps in 2430 * the PHY are ready. A set bit means the corresponding timestamp is valid and 2431 * ready to be captured from the PHY timestamp block. 2432 */ 2433 static int 2434 ice_get_phy_tx_tstamp_ready_e822(struct ice_hw *hw, u8 quad, u64 *tstamp_ready) 2435 { 2436 u32 hi, lo; 2437 int err; 2438 2439 err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEMORY_STATUS_U, &hi); 2440 if (err) { 2441 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_U for quad %u, err %d\n", 2442 quad, err); 2443 return err; 2444 } 2445 2446 err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEMORY_STATUS_L, &lo); 2447 if (err) { 2448 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_L for quad %u, err %d\n", 2449 quad, err); 2450 return err; 2451 } 2452 2453 *tstamp_ready = (u64)hi << 32 | (u64)lo; 2454 2455 return 0; 2456 } 2457 2458 /* E810 functions 2459 * 2460 * The following functions operate on the E810 series devices which use 2461 * a separate external PHY. 2462 */ 2463 2464 /** 2465 * ice_read_phy_reg_e810 - Read register from external PHY on E810 2466 * @hw: pointer to the HW struct 2467 * @addr: the address to read from 2468 * @val: On return, the value read from the PHY 2469 * 2470 * Read a register from the external PHY on the E810 device. 2471 */ 2472 static int ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val) 2473 { 2474 struct ice_sbq_msg_input msg = {0}; 2475 int err; 2476 2477 msg.msg_addr_low = lower_16_bits(addr); 2478 msg.msg_addr_high = upper_16_bits(addr); 2479 msg.opcode = ice_sbq_msg_rd; 2480 msg.dest_dev = rmn_0; 2481 2482 err = ice_sbq_rw_reg(hw, &msg); 2483 if (err) { 2484 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2485 err); 2486 return err; 2487 } 2488 2489 *val = msg.data; 2490 2491 return 0; 2492 } 2493 2494 /** 2495 * ice_write_phy_reg_e810 - Write register on external PHY on E810 2496 * @hw: pointer to the HW struct 2497 * @addr: the address to writem to 2498 * @val: the value to write to the PHY 2499 * 2500 * Write a value to a register of the external PHY on the E810 device. 2501 */ 2502 static int ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val) 2503 { 2504 struct ice_sbq_msg_input msg = {0}; 2505 int err; 2506 2507 msg.msg_addr_low = lower_16_bits(addr); 2508 msg.msg_addr_high = upper_16_bits(addr); 2509 msg.opcode = ice_sbq_msg_wr; 2510 msg.dest_dev = rmn_0; 2511 msg.data = val; 2512 2513 err = ice_sbq_rw_reg(hw, &msg); 2514 if (err) { 2515 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 2516 err); 2517 return err; 2518 } 2519 2520 return 0; 2521 } 2522 2523 /** 2524 * ice_read_phy_tstamp_ll_e810 - Read a PHY timestamp registers through the FW 2525 * @hw: pointer to the HW struct 2526 * @idx: the timestamp index to read 2527 * @hi: 8 bit timestamp high value 2528 * @lo: 32 bit timestamp low value 2529 * 2530 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the 2531 * timestamp block of the external PHY on the E810 device using the low latency 2532 * timestamp read. 2533 */ 2534 static int 2535 ice_read_phy_tstamp_ll_e810(struct ice_hw *hw, u8 idx, u8 *hi, u32 *lo) 2536 { 2537 u32 val; 2538 u8 i; 2539 2540 /* Write TS index to read to the PF register so the FW can read it */ 2541 val = FIELD_PREP(TS_LL_READ_TS_IDX, idx) | TS_LL_READ_TS; 2542 wr32(hw, PF_SB_ATQBAL, val); 2543 2544 /* Read the register repeatedly until the FW provides us the TS */ 2545 for (i = TS_LL_READ_RETRIES; i > 0; i--) { 2546 val = rd32(hw, PF_SB_ATQBAL); 2547 2548 /* When the bit is cleared, the TS is ready in the register */ 2549 if (!(FIELD_GET(TS_LL_READ_TS, val))) { 2550 /* High 8 bit value of the TS is on the bits 16:23 */ 2551 *hi = FIELD_GET(TS_LL_READ_TS_HIGH, val); 2552 2553 /* Read the low 32 bit value and set the TS valid bit */ 2554 *lo = rd32(hw, PF_SB_ATQBAH) | TS_VALID; 2555 return 0; 2556 } 2557 2558 udelay(10); 2559 } 2560 2561 /* FW failed to provide the TS in time */ 2562 ice_debug(hw, ICE_DBG_PTP, "Failed to read PTP timestamp using low latency read\n"); 2563 return -EINVAL; 2564 } 2565 2566 /** 2567 * ice_read_phy_tstamp_sbq_e810 - Read a PHY timestamp registers through the sbq 2568 * @hw: pointer to the HW struct 2569 * @lport: the lport to read from 2570 * @idx: the timestamp index to read 2571 * @hi: 8 bit timestamp high value 2572 * @lo: 32 bit timestamp low value 2573 * 2574 * Read a 8bit timestamp high value and 32 bit timestamp low value out of the 2575 * timestamp block of the external PHY on the E810 device using sideband queue. 2576 */ 2577 static int 2578 ice_read_phy_tstamp_sbq_e810(struct ice_hw *hw, u8 lport, u8 idx, u8 *hi, 2579 u32 *lo) 2580 { 2581 u32 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); 2582 u32 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); 2583 u32 lo_val, hi_val; 2584 int err; 2585 2586 err = ice_read_phy_reg_e810(hw, lo_addr, &lo_val); 2587 if (err) { 2588 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 2589 err); 2590 return err; 2591 } 2592 2593 err = ice_read_phy_reg_e810(hw, hi_addr, &hi_val); 2594 if (err) { 2595 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 2596 err); 2597 return err; 2598 } 2599 2600 *lo = lo_val; 2601 *hi = (u8)hi_val; 2602 2603 return 0; 2604 } 2605 2606 /** 2607 * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY 2608 * @hw: pointer to the HW struct 2609 * @lport: the lport to read from 2610 * @idx: the timestamp index to read 2611 * @tstamp: on return, the 40bit timestamp value 2612 * 2613 * Read a 40bit timestamp value out of the timestamp block of the external PHY 2614 * on the E810 device. 2615 */ 2616 static int 2617 ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) 2618 { 2619 u32 lo = 0; 2620 u8 hi = 0; 2621 int err; 2622 2623 if (hw->dev_caps.ts_dev_info.ts_ll_read) 2624 err = ice_read_phy_tstamp_ll_e810(hw, idx, &hi, &lo); 2625 else 2626 err = ice_read_phy_tstamp_sbq_e810(hw, lport, idx, &hi, &lo); 2627 2628 if (err) 2629 return err; 2630 2631 /* For E810 devices, the timestamp is reported with the lower 32 bits 2632 * in the low register, and the upper 8 bits in the high register. 2633 */ 2634 *tstamp = ((u64)hi) << TS_HIGH_S | ((u64)lo & TS_LOW_M); 2635 2636 return 0; 2637 } 2638 2639 /** 2640 * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY 2641 * @hw: pointer to the HW struct 2642 * @lport: the lport to read from 2643 * @idx: the timestamp index to reset 2644 * 2645 * Clear a timestamp, resetting its valid bit, from the timestamp block of the 2646 * external PHY on the E810 device. 2647 */ 2648 static int ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx) 2649 { 2650 u32 lo_addr, hi_addr; 2651 int err; 2652 2653 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); 2654 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); 2655 2656 err = ice_write_phy_reg_e810(hw, lo_addr, 0); 2657 if (err) { 2658 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, err %d\n", 2659 err); 2660 return err; 2661 } 2662 2663 err = ice_write_phy_reg_e810(hw, hi_addr, 0); 2664 if (err) { 2665 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, err %d\n", 2666 err); 2667 return err; 2668 } 2669 2670 return 0; 2671 } 2672 2673 /** 2674 * ice_ptp_init_phy_e810 - Enable PTP function on the external PHY 2675 * @hw: pointer to HW struct 2676 * 2677 * Enable the timesync PTP functionality for the external PHY connected to 2678 * this function. 2679 */ 2680 int ice_ptp_init_phy_e810(struct ice_hw *hw) 2681 { 2682 u8 tmr_idx; 2683 int err; 2684 2685 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 2686 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx), 2687 GLTSYN_ENA_TSYN_ENA_M); 2688 if (err) 2689 ice_debug(hw, ICE_DBG_PTP, "PTP failed in ena_phy_time_syn %d\n", 2690 err); 2691 2692 return err; 2693 } 2694 2695 /** 2696 * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization 2697 * @hw: pointer to HW struct 2698 * 2699 * Perform E810-specific PTP hardware clock initialization steps. 2700 */ 2701 static int ice_ptp_init_phc_e810(struct ice_hw *hw) 2702 { 2703 /* Ensure synchronization delay is zero */ 2704 wr32(hw, GLTSYN_SYNC_DLAY, 0); 2705 2706 /* Initialize the PHY */ 2707 return ice_ptp_init_phy_e810(hw); 2708 } 2709 2710 /** 2711 * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time 2712 * @hw: Board private structure 2713 * @time: Time to initialize the PHY port clock to 2714 * 2715 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the 2716 * initial clock time. The time will not actually be programmed until the 2717 * driver issues an INIT_TIME command. 2718 * 2719 * The time value is the upper 32 bits of the PHY timer, usually in units of 2720 * nominal nanoseconds. 2721 */ 2722 static int ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time) 2723 { 2724 u8 tmr_idx; 2725 int err; 2726 2727 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 2728 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0); 2729 if (err) { 2730 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, err %d\n", 2731 err); 2732 return err; 2733 } 2734 2735 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx), time); 2736 if (err) { 2737 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, err %d\n", 2738 err); 2739 return err; 2740 } 2741 2742 return 0; 2743 } 2744 2745 /** 2746 * ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment 2747 * @hw: pointer to HW struct 2748 * @adj: adjustment value to program 2749 * 2750 * Prepare the PHY port for an atomic adjustment by programming the PHY 2751 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual adjustment 2752 * is completed by issuing an ADJ_TIME sync command. 2753 * 2754 * The adjustment value only contains the portion used for the upper 32bits of 2755 * the PHY timer, usually in units of nominal nanoseconds. Negative 2756 * adjustments are supported using 2s complement arithmetic. 2757 */ 2758 static int ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj) 2759 { 2760 u8 tmr_idx; 2761 int err; 2762 2763 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 2764 2765 /* Adjustments are represented as signed 2's complement values in 2766 * nanoseconds. Sub-nanosecond adjustment is not supported. 2767 */ 2768 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), 0); 2769 if (err) { 2770 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, err %d\n", 2771 err); 2772 return err; 2773 } 2774 2775 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), adj); 2776 if (err) { 2777 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, err %d\n", 2778 err); 2779 return err; 2780 } 2781 2782 return 0; 2783 } 2784 2785 /** 2786 * ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change 2787 * @hw: pointer to HW struct 2788 * @incval: The new 40bit increment value to prepare 2789 * 2790 * Prepare the PHY port for a new increment value by programming the PHY 2791 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual change is 2792 * completed by issuing an INIT_INCVAL command. 2793 */ 2794 static int ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval) 2795 { 2796 u32 high, low; 2797 u8 tmr_idx; 2798 int err; 2799 2800 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 2801 low = lower_32_bits(incval); 2802 high = upper_32_bits(incval); 2803 2804 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), low); 2805 if (err) { 2806 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, err %d\n", 2807 err); 2808 return err; 2809 } 2810 2811 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), high); 2812 if (err) { 2813 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, err %d\n", 2814 err); 2815 return err; 2816 } 2817 2818 return 0; 2819 } 2820 2821 /** 2822 * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command 2823 * @hw: pointer to HW struct 2824 * @cmd: Command to be sent to the port 2825 * 2826 * Prepare the external PHYs connected to this device for a timer sync 2827 * command. 2828 */ 2829 static int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 2830 { 2831 u32 cmd_val, val; 2832 int err; 2833 2834 switch (cmd) { 2835 case INIT_TIME: 2836 cmd_val = GLTSYN_CMD_INIT_TIME; 2837 break; 2838 case INIT_INCVAL: 2839 cmd_val = GLTSYN_CMD_INIT_INCVAL; 2840 break; 2841 case ADJ_TIME: 2842 cmd_val = GLTSYN_CMD_ADJ_TIME; 2843 break; 2844 case READ_TIME: 2845 cmd_val = GLTSYN_CMD_READ_TIME; 2846 break; 2847 case ADJ_TIME_AT_TIME: 2848 cmd_val = GLTSYN_CMD_ADJ_INIT_TIME; 2849 break; 2850 } 2851 2852 /* Read, modify, write */ 2853 err = ice_read_phy_reg_e810(hw, ETH_GLTSYN_CMD, &val); 2854 if (err) { 2855 ice_debug(hw, ICE_DBG_PTP, "Failed to read GLTSYN_CMD, err %d\n", err); 2856 return err; 2857 } 2858 2859 /* Modify necessary bits only and perform write */ 2860 val &= ~TS_CMD_MASK_E810; 2861 val |= cmd_val; 2862 2863 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_CMD, val); 2864 if (err) { 2865 ice_debug(hw, ICE_DBG_PTP, "Failed to write back GLTSYN_CMD, err %d\n", err); 2866 return err; 2867 } 2868 2869 return 0; 2870 } 2871 2872 /** 2873 * ice_get_phy_tx_tstamp_ready_e810 - Read Tx memory status register 2874 * @hw: pointer to the HW struct 2875 * @port: the PHY port to read 2876 * @tstamp_ready: contents of the Tx memory status register 2877 * 2878 * E810 devices do not use a Tx memory status register. Instead simply 2879 * indicate that all timestamps are currently ready. 2880 */ 2881 static int 2882 ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready) 2883 { 2884 *tstamp_ready = 0xFFFFFFFFFFFFFFFF; 2885 return 0; 2886 } 2887 2888 /* E810T SMA functions 2889 * 2890 * The following functions operate specifically on E810T hardware and are used 2891 * to access the extended GPIOs available. 2892 */ 2893 2894 /** 2895 * ice_get_pca9575_handle 2896 * @hw: pointer to the hw struct 2897 * @pca9575_handle: GPIO controller's handle 2898 * 2899 * Find and return the GPIO controller's handle in the netlist. 2900 * When found - the value will be cached in the hw structure and following calls 2901 * will return cached value 2902 */ 2903 static int 2904 ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) 2905 { 2906 struct ice_aqc_get_link_topo *cmd; 2907 struct ice_aq_desc desc; 2908 int status; 2909 u8 idx; 2910 2911 /* If handle was read previously return cached value */ 2912 if (hw->io_expander_handle) { 2913 *pca9575_handle = hw->io_expander_handle; 2914 return 0; 2915 } 2916 2917 /* If handle was not detected read it from the netlist */ 2918 cmd = &desc.params.get_link_topo; 2919 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 2920 2921 /* Set node type to GPIO controller */ 2922 cmd->addr.topo_params.node_type_ctx = 2923 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & 2924 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL); 2925 2926 #define SW_PCA9575_SFP_TOPO_IDX 2 2927 #define SW_PCA9575_QSFP_TOPO_IDX 1 2928 2929 /* Check if the SW IO expander controlling SMA exists in the netlist. */ 2930 if (hw->device_id == ICE_DEV_ID_E810C_SFP) 2931 idx = SW_PCA9575_SFP_TOPO_IDX; 2932 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP) 2933 idx = SW_PCA9575_QSFP_TOPO_IDX; 2934 else 2935 return -EOPNOTSUPP; 2936 2937 cmd->addr.topo_params.index = idx; 2938 2939 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2940 if (status) 2941 return -EOPNOTSUPP; 2942 2943 /* Verify if we found the right IO expander type */ 2944 if (desc.params.get_link_topo.node_part_num != 2945 ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575) 2946 return -EOPNOTSUPP; 2947 2948 /* If present save the handle and return it */ 2949 hw->io_expander_handle = 2950 le16_to_cpu(desc.params.get_link_topo.addr.handle); 2951 *pca9575_handle = hw->io_expander_handle; 2952 2953 return 0; 2954 } 2955 2956 /** 2957 * ice_read_sma_ctrl_e810t 2958 * @hw: pointer to the hw struct 2959 * @data: pointer to data to be read from the GPIO controller 2960 * 2961 * Read the SMA controller state. It is connected to pins 3-7 of Port 1 of the 2962 * PCA9575 expander, so only bits 3-7 in data are valid. 2963 */ 2964 int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data) 2965 { 2966 int status; 2967 u16 handle; 2968 u8 i; 2969 2970 status = ice_get_pca9575_handle(hw, &handle); 2971 if (status) 2972 return status; 2973 2974 *data = 0; 2975 2976 for (i = ICE_SMA_MIN_BIT_E810T; i <= ICE_SMA_MAX_BIT_E810T; i++) { 2977 bool pin; 2978 2979 status = ice_aq_get_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, 2980 &pin, NULL); 2981 if (status) 2982 break; 2983 *data |= (u8)(!pin) << i; 2984 } 2985 2986 return status; 2987 } 2988 2989 /** 2990 * ice_write_sma_ctrl_e810t 2991 * @hw: pointer to the hw struct 2992 * @data: data to be written to the GPIO controller 2993 * 2994 * Write the data to the SMA controller. It is connected to pins 3-7 of Port 1 2995 * of the PCA9575 expander, so only bits 3-7 in data are valid. 2996 */ 2997 int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data) 2998 { 2999 int status; 3000 u16 handle; 3001 u8 i; 3002 3003 status = ice_get_pca9575_handle(hw, &handle); 3004 if (status) 3005 return status; 3006 3007 for (i = ICE_SMA_MIN_BIT_E810T; i <= ICE_SMA_MAX_BIT_E810T; i++) { 3008 bool pin; 3009 3010 pin = !(data & (1 << i)); 3011 status = ice_aq_set_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, 3012 pin, NULL); 3013 if (status) 3014 break; 3015 } 3016 3017 return status; 3018 } 3019 3020 /** 3021 * ice_read_pca9575_reg_e810t 3022 * @hw: pointer to the hw struct 3023 * @offset: GPIO controller register offset 3024 * @data: pointer to data to be read from the GPIO controller 3025 * 3026 * Read the register from the GPIO controller 3027 */ 3028 int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data) 3029 { 3030 struct ice_aqc_link_topo_addr link_topo; 3031 __le16 addr; 3032 u16 handle; 3033 int err; 3034 3035 memset(&link_topo, 0, sizeof(link_topo)); 3036 3037 err = ice_get_pca9575_handle(hw, &handle); 3038 if (err) 3039 return err; 3040 3041 link_topo.handle = cpu_to_le16(handle); 3042 link_topo.topo_params.node_type_ctx = 3043 FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M, 3044 ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED); 3045 3046 addr = cpu_to_le16((u16)offset); 3047 3048 return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL); 3049 } 3050 3051 /* Device agnostic functions 3052 * 3053 * The following functions implement shared behavior common to both E822 and 3054 * E810 devices, possibly calling a device specific implementation where 3055 * necessary. 3056 */ 3057 3058 /** 3059 * ice_ptp_lock - Acquire PTP global semaphore register lock 3060 * @hw: pointer to the HW struct 3061 * 3062 * Acquire the global PTP hardware semaphore lock. Returns true if the lock 3063 * was acquired, false otherwise. 3064 * 3065 * The PFTSYN_SEM register sets the busy bit on read, returning the previous 3066 * value. If software sees the busy bit cleared, this means that this function 3067 * acquired the lock (and the busy bit is now set). If software sees the busy 3068 * bit set, it means that another function acquired the lock. 3069 * 3070 * Software must clear the busy bit with a write to release the lock for other 3071 * functions when done. 3072 */ 3073 bool ice_ptp_lock(struct ice_hw *hw) 3074 { 3075 u32 hw_lock; 3076 int i; 3077 3078 #define MAX_TRIES 15 3079 3080 for (i = 0; i < MAX_TRIES; i++) { 3081 hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id)); 3082 hw_lock = hw_lock & PFTSYN_SEM_BUSY_M; 3083 if (hw_lock) { 3084 /* Somebody is holding the lock */ 3085 usleep_range(5000, 6000); 3086 continue; 3087 } 3088 3089 break; 3090 } 3091 3092 return !hw_lock; 3093 } 3094 3095 /** 3096 * ice_ptp_unlock - Release PTP global semaphore register lock 3097 * @hw: pointer to the HW struct 3098 * 3099 * Release the global PTP hardware semaphore lock. This is done by writing to 3100 * the PFTSYN_SEM register. 3101 */ 3102 void ice_ptp_unlock(struct ice_hw *hw) 3103 { 3104 wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0); 3105 } 3106 3107 /** 3108 * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command 3109 * @hw: pointer to HW struct 3110 * @cmd: the command to issue 3111 * 3112 * Prepare the source timer and PHY timers and then trigger the requested 3113 * command. This causes the shadow registers previously written in preparation 3114 * for the command to be synchronously applied to both the source and PHY 3115 * timers. 3116 */ 3117 static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 3118 { 3119 int err; 3120 3121 /* First, prepare the source timer */ 3122 ice_ptp_src_cmd(hw, cmd); 3123 3124 /* Next, prepare the ports */ 3125 if (ice_is_e810(hw)) 3126 err = ice_ptp_port_cmd_e810(hw, cmd); 3127 else 3128 err = ice_ptp_port_cmd_e822(hw, cmd); 3129 if (err) { 3130 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, err %d\n", 3131 cmd, err); 3132 return err; 3133 } 3134 3135 /* Write the sync command register to drive both source and PHY timer 3136 * commands synchronously 3137 */ 3138 ice_ptp_exec_tmr_cmd(hw); 3139 3140 return 0; 3141 } 3142 3143 /** 3144 * ice_ptp_init_time - Initialize device time to provided value 3145 * @hw: pointer to HW struct 3146 * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H) 3147 * 3148 * Initialize the device to the specified time provided. This requires a three 3149 * step process: 3150 * 3151 * 1) write the new init time to the source timer shadow registers 3152 * 2) write the new init time to the PHY timer shadow registers 3153 * 3) issue an init_time timer command to synchronously switch both the source 3154 * and port timers to the new init time value at the next clock cycle. 3155 */ 3156 int ice_ptp_init_time(struct ice_hw *hw, u64 time) 3157 { 3158 u8 tmr_idx; 3159 int err; 3160 3161 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 3162 3163 /* Source timers */ 3164 wr32(hw, GLTSYN_SHTIME_L(tmr_idx), lower_32_bits(time)); 3165 wr32(hw, GLTSYN_SHTIME_H(tmr_idx), upper_32_bits(time)); 3166 wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0); 3167 3168 /* PHY timers */ 3169 /* Fill Rx and Tx ports and send msg to PHY */ 3170 if (ice_is_e810(hw)) 3171 err = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF); 3172 else 3173 err = ice_ptp_prep_phy_time_e822(hw, time & 0xFFFFFFFF); 3174 if (err) 3175 return err; 3176 3177 return ice_ptp_tmr_cmd(hw, INIT_TIME); 3178 } 3179 3180 /** 3181 * ice_ptp_write_incval - Program PHC with new increment value 3182 * @hw: pointer to HW struct 3183 * @incval: Source timer increment value per clock cycle 3184 * 3185 * Program the PHC with a new increment value. This requires a three-step 3186 * process: 3187 * 3188 * 1) Write the increment value to the source timer shadow registers 3189 * 2) Write the increment value to the PHY timer shadow registers 3190 * 3) Issue an INIT_INCVAL timer command to synchronously switch both the 3191 * source and port timers to the new increment value at the next clock 3192 * cycle. 3193 */ 3194 int ice_ptp_write_incval(struct ice_hw *hw, u64 incval) 3195 { 3196 u8 tmr_idx; 3197 int err; 3198 3199 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 3200 3201 /* Shadow Adjust */ 3202 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), lower_32_bits(incval)); 3203 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), upper_32_bits(incval)); 3204 3205 if (ice_is_e810(hw)) 3206 err = ice_ptp_prep_phy_incval_e810(hw, incval); 3207 else 3208 err = ice_ptp_prep_phy_incval_e822(hw, incval); 3209 if (err) 3210 return err; 3211 3212 return ice_ptp_tmr_cmd(hw, INIT_INCVAL); 3213 } 3214 3215 /** 3216 * ice_ptp_write_incval_locked - Program new incval while holding semaphore 3217 * @hw: pointer to HW struct 3218 * @incval: Source timer increment value per clock cycle 3219 * 3220 * Program a new PHC incval while holding the PTP semaphore. 3221 */ 3222 int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval) 3223 { 3224 int err; 3225 3226 if (!ice_ptp_lock(hw)) 3227 return -EBUSY; 3228 3229 err = ice_ptp_write_incval(hw, incval); 3230 3231 ice_ptp_unlock(hw); 3232 3233 return err; 3234 } 3235 3236 /** 3237 * ice_ptp_adj_clock - Adjust PHC clock time atomically 3238 * @hw: pointer to HW struct 3239 * @adj: Adjustment in nanoseconds 3240 * 3241 * Perform an atomic adjustment of the PHC time by the specified number of 3242 * nanoseconds. This requires a three-step process: 3243 * 3244 * 1) Write the adjustment to the source timer shadow registers 3245 * 2) Write the adjustment to the PHY timer shadow registers 3246 * 3) Issue an ADJ_TIME timer command to synchronously apply the adjustment to 3247 * both the source and port timers at the next clock cycle. 3248 */ 3249 int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj) 3250 { 3251 u8 tmr_idx; 3252 int err; 3253 3254 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 3255 3256 /* Write the desired clock adjustment into the GLTSYN_SHADJ register. 3257 * For an ADJ_TIME command, this set of registers represents the value 3258 * to add to the clock time. It supports subtraction by interpreting 3259 * the value as a 2's complement integer. 3260 */ 3261 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0); 3262 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj); 3263 3264 if (ice_is_e810(hw)) 3265 err = ice_ptp_prep_phy_adj_e810(hw, adj); 3266 else 3267 err = ice_ptp_prep_phy_adj_e822(hw, adj); 3268 if (err) 3269 return err; 3270 3271 return ice_ptp_tmr_cmd(hw, ADJ_TIME); 3272 } 3273 3274 /** 3275 * ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block 3276 * @hw: pointer to the HW struct 3277 * @block: the block to read from 3278 * @idx: the timestamp index to read 3279 * @tstamp: on return, the 40bit timestamp value 3280 * 3281 * Read a 40bit timestamp value out of the timestamp block. For E822 devices, 3282 * the block is the quad to read from. For E810 devices, the block is the 3283 * logical port to read from. 3284 */ 3285 int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp) 3286 { 3287 if (ice_is_e810(hw)) 3288 return ice_read_phy_tstamp_e810(hw, block, idx, tstamp); 3289 else 3290 return ice_read_phy_tstamp_e822(hw, block, idx, tstamp); 3291 } 3292 3293 /** 3294 * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block 3295 * @hw: pointer to the HW struct 3296 * @block: the block to read from 3297 * @idx: the timestamp index to reset 3298 * 3299 * Clear a timestamp, resetting its valid bit, from the timestamp block. For 3300 * E822 devices, the block is the quad to clear from. For E810 devices, the 3301 * block is the logical port to clear from. 3302 */ 3303 int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx) 3304 { 3305 if (ice_is_e810(hw)) 3306 return ice_clear_phy_tstamp_e810(hw, block, idx); 3307 else 3308 return ice_clear_phy_tstamp_e822(hw, block, idx); 3309 } 3310 3311 /** 3312 * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks 3313 * @hw: pointer to the HW struct 3314 */ 3315 void ice_ptp_reset_ts_memory(struct ice_hw *hw) 3316 { 3317 if (ice_is_e810(hw)) 3318 return; 3319 3320 ice_ptp_reset_ts_memory_e822(hw); 3321 } 3322 3323 /** 3324 * ice_ptp_init_phc - Initialize PTP hardware clock 3325 * @hw: pointer to the HW struct 3326 * 3327 * Perform the steps required to initialize the PTP hardware clock. 3328 */ 3329 int ice_ptp_init_phc(struct ice_hw *hw) 3330 { 3331 u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned; 3332 3333 /* Enable source clocks */ 3334 wr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M); 3335 3336 /* Clear event err indications for auxiliary pins */ 3337 (void)rd32(hw, GLTSYN_STAT(src_idx)); 3338 3339 if (ice_is_e810(hw)) 3340 return ice_ptp_init_phc_e810(hw); 3341 else 3342 return ice_ptp_init_phc_e822(hw); 3343 } 3344 3345 /** 3346 * ice_get_phy_tx_tstamp_ready - Read PHY Tx memory status indication 3347 * @hw: pointer to the HW struct 3348 * @block: the timestamp block to check 3349 * @tstamp_ready: storage for the PHY Tx memory status information 3350 * 3351 * Check the PHY for Tx timestamp memory status. This reports a 64 bit value 3352 * which indicates which timestamps in the block may be captured. A set bit 3353 * means the timestamp can be read. An unset bit means the timestamp is not 3354 * ready and software should avoid reading the register. 3355 */ 3356 int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready) 3357 { 3358 if (ice_is_e810(hw)) 3359 return ice_get_phy_tx_tstamp_ready_e810(hw, block, 3360 tstamp_ready); 3361 else 3362 return ice_get_phy_tx_tstamp_ready_e822(hw, block, 3363 tstamp_ready); 3364 } 3365