1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (C) 2021, Intel Corporation. */ 3 4 #include "ice_common.h" 5 #include "ice_ptp_hw.h" 6 #include "ice_ptp_consts.h" 7 8 /* Low level functions for interacting with and managing the device clock used 9 * for the Precision Time Protocol. 10 * 11 * The ice hardware represents the current time using three registers: 12 * 13 * GLTSYN_TIME_H GLTSYN_TIME_L GLTSYN_TIME_R 14 * +---------------+ +---------------+ +---------------+ 15 * | 32 bits | | 32 bits | | 32 bits | 16 * +---------------+ +---------------+ +---------------+ 17 * 18 * The registers are incremented every clock tick using a 40bit increment 19 * value defined over two registers: 20 * 21 * GLTSYN_INCVAL_H GLTSYN_INCVAL_L 22 * +---------------+ +---------------+ 23 * | 8 bit s | | 32 bits | 24 * +---------------+ +---------------+ 25 * 26 * The increment value is added to the GLSTYN_TIME_R and GLSTYN_TIME_L 27 * registers every clock source tick. Depending on the specific device 28 * configuration, the clock source frequency could be one of a number of 29 * values. 30 * 31 * For E810 devices, the increment frequency is 812.5 MHz 32 * 33 * For E822 devices the clock can be derived from different sources, and the 34 * increment has an effective frequency of one of the following: 35 * - 823.4375 MHz 36 * - 783.36 MHz 37 * - 796.875 MHz 38 * - 816 MHz 39 * - 830.078125 MHz 40 * - 783.36 MHz 41 * 42 * The hardware captures timestamps in the PHY for incoming packets, and for 43 * outgoing packets on request. To support this, the PHY maintains a timer 44 * that matches the lower 64 bits of the global source timer. 45 * 46 * In order to ensure that the PHY timers and the source timer are equivalent, 47 * shadow registers are used to prepare the desired initial values. A special 48 * sync command is issued to trigger copying from the shadow registers into 49 * the appropriate source and PHY registers simultaneously. 50 * 51 * The driver supports devices which have different PHYs with subtly different 52 * mechanisms to program and control the timers. We divide the devices into 53 * families named after the first major device, E810 and similar devices, and 54 * E822 and similar devices. 55 * 56 * - E822 based devices have additional support for fine grained Vernier 57 * calibration which requires significant setup 58 * - The layout of timestamp data in the PHY register blocks is different 59 * - The way timer synchronization commands are issued is different. 60 * 61 * To support this, very low level functions have an e810 or e822 suffix 62 * indicating what type of device they work on. Higher level abstractions for 63 * tasks that can be done on both devices do not have the suffix and will 64 * correctly look up the appropriate low level function when running. 65 * 66 * Functions which only make sense on a single device family may not have 67 * a suitable generic implementation 68 */ 69 70 /** 71 * ice_get_ptp_src_clock_index - determine source clock index 72 * @hw: pointer to HW struct 73 * 74 * Determine the source clock index currently in use, based on device 75 * capabilities reported during initialization. 76 */ 77 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw) 78 { 79 return hw->func_caps.ts_func_info.tmr_index_assoc; 80 } 81 82 /** 83 * ice_ptp_read_src_incval - Read source timer increment value 84 * @hw: pointer to HW struct 85 * 86 * Read the increment value of the source timer and return it. 87 */ 88 static u64 ice_ptp_read_src_incval(struct ice_hw *hw) 89 { 90 u32 lo, hi; 91 u8 tmr_idx; 92 93 tmr_idx = ice_get_ptp_src_clock_index(hw); 94 95 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 96 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 97 98 return ((u64)(hi & INCVAL_HIGH_M) << 32) | lo; 99 } 100 101 /** 102 * ice_ptp_src_cmd - Prepare source timer for a timer command 103 * @hw: pointer to HW structure 104 * @cmd: Timer command 105 * 106 * Prepare the source timer for an upcoming timer sync command. 107 */ 108 static void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 109 { 110 u32 cmd_val; 111 u8 tmr_idx; 112 113 tmr_idx = ice_get_ptp_src_clock_index(hw); 114 cmd_val = tmr_idx << SEL_CPK_SRC; 115 116 switch (cmd) { 117 case INIT_TIME: 118 cmd_val |= GLTSYN_CMD_INIT_TIME; 119 break; 120 case INIT_INCVAL: 121 cmd_val |= GLTSYN_CMD_INIT_INCVAL; 122 break; 123 case ADJ_TIME: 124 cmd_val |= GLTSYN_CMD_ADJ_TIME; 125 break; 126 case ADJ_TIME_AT_TIME: 127 cmd_val |= GLTSYN_CMD_ADJ_INIT_TIME; 128 break; 129 case READ_TIME: 130 cmd_val |= GLTSYN_CMD_READ_TIME; 131 break; 132 } 133 134 wr32(hw, GLTSYN_CMD, cmd_val); 135 } 136 137 /** 138 * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands 139 * @hw: pointer to HW struct 140 * 141 * Write the SYNC_EXEC_CMD bit to the GLTSYN_CMD_SYNC register, and flush the 142 * write immediately. This triggers the hardware to begin executing all of the 143 * source and PHY timer commands synchronously. 144 */ 145 static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw) 146 { 147 wr32(hw, GLTSYN_CMD_SYNC, SYNC_EXEC_CMD); 148 ice_flush(hw); 149 } 150 151 /* E822 family functions 152 * 153 * The following functions operate on the E822 family of devices. 154 */ 155 156 /** 157 * ice_fill_phy_msg_e822 - Fill message data for a PHY register access 158 * @msg: the PHY message buffer to fill in 159 * @port: the port to access 160 * @offset: the register offset 161 */ 162 static void 163 ice_fill_phy_msg_e822(struct ice_sbq_msg_input *msg, u8 port, u16 offset) 164 { 165 int phy_port, phy, quadtype; 166 167 phy_port = port % ICE_PORTS_PER_PHY; 168 phy = port / ICE_PORTS_PER_PHY; 169 quadtype = (port / ICE_PORTS_PER_QUAD) % ICE_NUM_QUAD_TYPE; 170 171 if (quadtype == 0) { 172 msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port); 173 msg->msg_addr_high = P_Q0_H(P_0_BASE + offset, phy_port); 174 } else { 175 msg->msg_addr_low = P_Q1_L(P_4_BASE + offset, phy_port); 176 msg->msg_addr_high = P_Q1_H(P_4_BASE + offset, phy_port); 177 } 178 179 if (phy == 0) 180 msg->dest_dev = rmn_0; 181 else if (phy == 1) 182 msg->dest_dev = rmn_1; 183 else 184 msg->dest_dev = rmn_2; 185 } 186 187 /** 188 * ice_is_64b_phy_reg_e822 - Check if this is a 64bit PHY register 189 * @low_addr: the low address to check 190 * @high_addr: on return, contains the high address of the 64bit register 191 * 192 * Checks if the provided low address is one of the known 64bit PHY values 193 * represented as two 32bit registers. If it is, return the appropriate high 194 * register offset to use. 195 */ 196 static bool ice_is_64b_phy_reg_e822(u16 low_addr, u16 *high_addr) 197 { 198 switch (low_addr) { 199 case P_REG_PAR_PCS_TX_OFFSET_L: 200 *high_addr = P_REG_PAR_PCS_TX_OFFSET_U; 201 return true; 202 case P_REG_PAR_PCS_RX_OFFSET_L: 203 *high_addr = P_REG_PAR_PCS_RX_OFFSET_U; 204 return true; 205 case P_REG_PAR_TX_TIME_L: 206 *high_addr = P_REG_PAR_TX_TIME_U; 207 return true; 208 case P_REG_PAR_RX_TIME_L: 209 *high_addr = P_REG_PAR_RX_TIME_U; 210 return true; 211 case P_REG_TOTAL_TX_OFFSET_L: 212 *high_addr = P_REG_TOTAL_TX_OFFSET_U; 213 return true; 214 case P_REG_TOTAL_RX_OFFSET_L: 215 *high_addr = P_REG_TOTAL_RX_OFFSET_U; 216 return true; 217 case P_REG_UIX66_10G_40G_L: 218 *high_addr = P_REG_UIX66_10G_40G_U; 219 return true; 220 case P_REG_UIX66_25G_100G_L: 221 *high_addr = P_REG_UIX66_25G_100G_U; 222 return true; 223 case P_REG_TX_CAPTURE_L: 224 *high_addr = P_REG_TX_CAPTURE_U; 225 return true; 226 case P_REG_RX_CAPTURE_L: 227 *high_addr = P_REG_RX_CAPTURE_U; 228 return true; 229 case P_REG_TX_TIMER_INC_PRE_L: 230 *high_addr = P_REG_TX_TIMER_INC_PRE_U; 231 return true; 232 case P_REG_RX_TIMER_INC_PRE_L: 233 *high_addr = P_REG_RX_TIMER_INC_PRE_U; 234 return true; 235 default: 236 return false; 237 } 238 } 239 240 /** 241 * ice_is_40b_phy_reg_e822 - Check if this is a 40bit PHY register 242 * @low_addr: the low address to check 243 * @high_addr: on return, contains the high address of the 40bit value 244 * 245 * Checks if the provided low address is one of the known 40bit PHY values 246 * split into two registers with the lower 8 bits in the low register and the 247 * upper 32 bits in the high register. If it is, return the appropriate high 248 * register offset to use. 249 */ 250 static bool ice_is_40b_phy_reg_e822(u16 low_addr, u16 *high_addr) 251 { 252 switch (low_addr) { 253 case P_REG_TIMETUS_L: 254 *high_addr = P_REG_TIMETUS_U; 255 return true; 256 case P_REG_PAR_RX_TUS_L: 257 *high_addr = P_REG_PAR_RX_TUS_U; 258 return true; 259 case P_REG_PAR_TX_TUS_L: 260 *high_addr = P_REG_PAR_TX_TUS_U; 261 return true; 262 case P_REG_PCS_RX_TUS_L: 263 *high_addr = P_REG_PCS_RX_TUS_U; 264 return true; 265 case P_REG_PCS_TX_TUS_L: 266 *high_addr = P_REG_PCS_TX_TUS_U; 267 return true; 268 case P_REG_DESK_PAR_RX_TUS_L: 269 *high_addr = P_REG_DESK_PAR_RX_TUS_U; 270 return true; 271 case P_REG_DESK_PAR_TX_TUS_L: 272 *high_addr = P_REG_DESK_PAR_TX_TUS_U; 273 return true; 274 case P_REG_DESK_PCS_RX_TUS_L: 275 *high_addr = P_REG_DESK_PCS_RX_TUS_U; 276 return true; 277 case P_REG_DESK_PCS_TX_TUS_L: 278 *high_addr = P_REG_DESK_PCS_TX_TUS_U; 279 return true; 280 default: 281 return false; 282 } 283 } 284 285 /** 286 * ice_read_phy_reg_e822 - Read a PHY register 287 * @hw: pointer to the HW struct 288 * @port: PHY port to read from 289 * @offset: PHY register offset to read 290 * @val: on return, the contents read from the PHY 291 * 292 * Read a PHY register for the given port over the device sideband queue. 293 */ 294 int 295 ice_read_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 *val) 296 { 297 struct ice_sbq_msg_input msg = {0}; 298 int err; 299 300 ice_fill_phy_msg_e822(&msg, port, offset); 301 msg.opcode = ice_sbq_msg_rd; 302 303 err = ice_sbq_rw_reg(hw, &msg); 304 if (err) { 305 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 306 err); 307 return err; 308 } 309 310 *val = msg.data; 311 312 return 0; 313 } 314 315 /** 316 * ice_read_64b_phy_reg_e822 - Read a 64bit value from PHY registers 317 * @hw: pointer to the HW struct 318 * @port: PHY port to read from 319 * @low_addr: offset of the lower register to read from 320 * @val: on return, the contents of the 64bit value from the PHY registers 321 * 322 * Reads the two registers associated with a 64bit value and returns it in the 323 * val pointer. The offset always specifies the lower register offset to use. 324 * The high offset is looked up. This function only operates on registers 325 * known to be two parts of a 64bit value. 326 */ 327 static int 328 ice_read_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val) 329 { 330 u32 low, high; 331 u16 high_addr; 332 int err; 333 334 /* Only operate on registers known to be split into two 32bit 335 * registers. 336 */ 337 if (!ice_is_64b_phy_reg_e822(low_addr, &high_addr)) { 338 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n", 339 low_addr); 340 return -EINVAL; 341 } 342 343 err = ice_read_phy_reg_e822(hw, port, low_addr, &low); 344 if (err) { 345 ice_debug(hw, ICE_DBG_PTP, "Failed to read from low register 0x%08x\n, err %d", 346 low_addr, err); 347 return err; 348 } 349 350 err = ice_read_phy_reg_e822(hw, port, high_addr, &high); 351 if (err) { 352 ice_debug(hw, ICE_DBG_PTP, "Failed to read from high register 0x%08x\n, err %d", 353 high_addr, err); 354 return err; 355 } 356 357 *val = (u64)high << 32 | low; 358 359 return 0; 360 } 361 362 /** 363 * ice_write_phy_reg_e822 - Write a PHY register 364 * @hw: pointer to the HW struct 365 * @port: PHY port to write to 366 * @offset: PHY register offset to write 367 * @val: The value to write to the register 368 * 369 * Write a PHY register for the given port over the device sideband queue. 370 */ 371 int 372 ice_write_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 val) 373 { 374 struct ice_sbq_msg_input msg = {0}; 375 int err; 376 377 ice_fill_phy_msg_e822(&msg, port, offset); 378 msg.opcode = ice_sbq_msg_wr; 379 msg.data = val; 380 381 err = ice_sbq_rw_reg(hw, &msg); 382 if (err) { 383 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 384 err); 385 return err; 386 } 387 388 return 0; 389 } 390 391 /** 392 * ice_write_40b_phy_reg_e822 - Write a 40b value to the PHY 393 * @hw: pointer to the HW struct 394 * @port: port to write to 395 * @low_addr: offset of the low register 396 * @val: 40b value to write 397 * 398 * Write the provided 40b value to the two associated registers by splitting 399 * it up into two chunks, the lower 8 bits and the upper 32 bits. 400 */ 401 static int 402 ice_write_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) 403 { 404 u32 low, high; 405 u16 high_addr; 406 int err; 407 408 /* Only operate on registers known to be split into a lower 8 bit 409 * register and an upper 32 bit register. 410 */ 411 if (!ice_is_40b_phy_reg_e822(low_addr, &high_addr)) { 412 ice_debug(hw, ICE_DBG_PTP, "Invalid 40b register addr 0x%08x\n", 413 low_addr); 414 return -EINVAL; 415 } 416 417 low = (u32)(val & P_REG_40B_LOW_M); 418 high = (u32)(val >> P_REG_40B_HIGH_S); 419 420 err = ice_write_phy_reg_e822(hw, port, low_addr, low); 421 if (err) { 422 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 423 low_addr, err); 424 return err; 425 } 426 427 err = ice_write_phy_reg_e822(hw, port, high_addr, high); 428 if (err) { 429 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 430 high_addr, err); 431 return err; 432 } 433 434 return 0; 435 } 436 437 /** 438 * ice_write_64b_phy_reg_e822 - Write a 64bit value to PHY registers 439 * @hw: pointer to the HW struct 440 * @port: PHY port to read from 441 * @low_addr: offset of the lower register to read from 442 * @val: the contents of the 64bit value to write to PHY 443 * 444 * Write the 64bit value to the two associated 32bit PHY registers. The offset 445 * is always specified as the lower register, and the high address is looked 446 * up. This function only operates on registers known to be two parts of 447 * a 64bit value. 448 */ 449 static int 450 ice_write_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val) 451 { 452 u32 low, high; 453 u16 high_addr; 454 int err; 455 456 /* Only operate on registers known to be split into two 32bit 457 * registers. 458 */ 459 if (!ice_is_64b_phy_reg_e822(low_addr, &high_addr)) { 460 ice_debug(hw, ICE_DBG_PTP, "Invalid 64b register addr 0x%08x\n", 461 low_addr); 462 return -EINVAL; 463 } 464 465 low = lower_32_bits(val); 466 high = upper_32_bits(val); 467 468 err = ice_write_phy_reg_e822(hw, port, low_addr, low); 469 if (err) { 470 ice_debug(hw, ICE_DBG_PTP, "Failed to write to low register 0x%08x\n, err %d", 471 low_addr, err); 472 return err; 473 } 474 475 err = ice_write_phy_reg_e822(hw, port, high_addr, high); 476 if (err) { 477 ice_debug(hw, ICE_DBG_PTP, "Failed to write to high register 0x%08x\n, err %d", 478 high_addr, err); 479 return err; 480 } 481 482 return 0; 483 } 484 485 /** 486 * ice_fill_quad_msg_e822 - Fill message data for quad register access 487 * @msg: the PHY message buffer to fill in 488 * @quad: the quad to access 489 * @offset: the register offset 490 * 491 * Fill a message buffer for accessing a register in a quad shared between 492 * multiple PHYs. 493 */ 494 static void 495 ice_fill_quad_msg_e822(struct ice_sbq_msg_input *msg, u8 quad, u16 offset) 496 { 497 u32 addr; 498 499 msg->dest_dev = rmn_0; 500 501 if ((quad % ICE_NUM_QUAD_TYPE) == 0) 502 addr = Q_0_BASE + offset; 503 else 504 addr = Q_1_BASE + offset; 505 506 msg->msg_addr_low = lower_16_bits(addr); 507 msg->msg_addr_high = upper_16_bits(addr); 508 } 509 510 /** 511 * ice_read_quad_reg_e822 - Read a PHY quad register 512 * @hw: pointer to the HW struct 513 * @quad: quad to read from 514 * @offset: quad register offset to read 515 * @val: on return, the contents read from the quad 516 * 517 * Read a quad register over the device sideband queue. Quad registers are 518 * shared between multiple PHYs. 519 */ 520 int 521 ice_read_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 *val) 522 { 523 struct ice_sbq_msg_input msg = {0}; 524 int err; 525 526 if (quad >= ICE_MAX_QUAD) 527 return -EINVAL; 528 529 ice_fill_quad_msg_e822(&msg, quad, offset); 530 msg.opcode = ice_sbq_msg_rd; 531 532 err = ice_sbq_rw_reg(hw, &msg); 533 if (err) { 534 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 535 err); 536 return err; 537 } 538 539 *val = msg.data; 540 541 return 0; 542 } 543 544 /** 545 * ice_write_quad_reg_e822 - Write a PHY quad register 546 * @hw: pointer to the HW struct 547 * @quad: quad to write to 548 * @offset: quad register offset to write 549 * @val: The value to write to the register 550 * 551 * Write a quad register over the device sideband queue. Quad registers are 552 * shared between multiple PHYs. 553 */ 554 int 555 ice_write_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 val) 556 { 557 struct ice_sbq_msg_input msg = {0}; 558 int err; 559 560 if (quad >= ICE_MAX_QUAD) 561 return -EINVAL; 562 563 ice_fill_quad_msg_e822(&msg, quad, offset); 564 msg.opcode = ice_sbq_msg_wr; 565 msg.data = val; 566 567 err = ice_sbq_rw_reg(hw, &msg); 568 if (err) { 569 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 570 err); 571 return err; 572 } 573 574 return 0; 575 } 576 577 /** 578 * ice_read_phy_tstamp_e822 - Read a PHY timestamp out of the quad block 579 * @hw: pointer to the HW struct 580 * @quad: the quad to read from 581 * @idx: the timestamp index to read 582 * @tstamp: on return, the 40bit timestamp value 583 * 584 * Read a 40bit timestamp value out of the two associated registers in the 585 * quad memory block that is shared between the internal PHYs of the E822 586 * family of devices. 587 */ 588 static int 589 ice_read_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp) 590 { 591 u16 lo_addr, hi_addr; 592 u32 lo, hi; 593 int err; 594 595 lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx); 596 hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx); 597 598 err = ice_read_quad_reg_e822(hw, quad, lo_addr, &lo); 599 if (err) { 600 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 601 err); 602 return err; 603 } 604 605 err = ice_read_quad_reg_e822(hw, quad, hi_addr, &hi); 606 if (err) { 607 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 608 err); 609 return err; 610 } 611 612 /* For E822 based internal PHYs, the timestamp is reported with the 613 * lower 8 bits in the low register, and the upper 32 bits in the high 614 * register. 615 */ 616 *tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M); 617 618 return 0; 619 } 620 621 /** 622 * ice_clear_phy_tstamp_e822 - Clear a timestamp from the quad block 623 * @hw: pointer to the HW struct 624 * @quad: the quad to read from 625 * @idx: the timestamp index to reset 626 * 627 * Clear a timestamp, resetting its valid bit, from the PHY quad block that is 628 * shared between the internal PHYs on the E822 devices. 629 */ 630 static int 631 ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx) 632 { 633 u16 lo_addr, hi_addr; 634 int err; 635 636 lo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx); 637 hi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx); 638 639 err = ice_write_quad_reg_e822(hw, quad, lo_addr, 0); 640 if (err) { 641 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, err %d\n", 642 err); 643 return err; 644 } 645 646 err = ice_write_quad_reg_e822(hw, quad, hi_addr, 0); 647 if (err) { 648 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, err %d\n", 649 err); 650 return err; 651 } 652 653 return 0; 654 } 655 656 /** 657 * ice_ptp_set_vernier_wl - Set the window length for vernier calibration 658 * @hw: pointer to the HW struct 659 * 660 * Set the window length used for the vernier port calibration process. 661 */ 662 static int ice_ptp_set_vernier_wl(struct ice_hw *hw) 663 { 664 u8 port; 665 666 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { 667 int err; 668 669 err = ice_write_phy_reg_e822(hw, port, P_REG_WL, 670 PTP_VERNIER_WL); 671 if (err) { 672 ice_debug(hw, ICE_DBG_PTP, "Failed to set vernier window length for port %u, err %d\n", 673 port, err); 674 return err; 675 } 676 } 677 678 return 0; 679 } 680 681 /** 682 * ice_ptp_init_phc_e822 - Perform E822 specific PHC initialization 683 * @hw: pointer to HW struct 684 * 685 * Perform PHC initialization steps specific to E822 devices. 686 */ 687 static int ice_ptp_init_phc_e822(struct ice_hw *hw) 688 { 689 u32 regval; 690 691 /* Enable reading switch and PHY registers over the sideband queue */ 692 #define PF_SB_REM_DEV_CTL_SWITCH_READ BIT(1) 693 #define PF_SB_REM_DEV_CTL_PHY0 BIT(2) 694 regval = rd32(hw, PF_SB_REM_DEV_CTL); 695 regval |= (PF_SB_REM_DEV_CTL_SWITCH_READ | 696 PF_SB_REM_DEV_CTL_PHY0); 697 wr32(hw, PF_SB_REM_DEV_CTL, regval); 698 699 /* Set window length for all the ports */ 700 return ice_ptp_set_vernier_wl(hw); 701 } 702 703 /** 704 * ice_ptp_prep_phy_time_e822 - Prepare PHY port with initial time 705 * @hw: pointer to the HW struct 706 * @time: Time to initialize the PHY port clocks to 707 * 708 * Program the PHY port registers with a new initial time value. The port 709 * clock will be initialized once the driver issues an INIT_TIME sync 710 * command. The time value is the upper 32 bits of the PHY timer, usually in 711 * units of nominal nanoseconds. 712 */ 713 static int 714 ice_ptp_prep_phy_time_e822(struct ice_hw *hw, u32 time) 715 { 716 u64 phy_time; 717 u8 port; 718 int err; 719 720 /* The time represents the upper 32 bits of the PHY timer, so we need 721 * to shift to account for this when programming. 722 */ 723 phy_time = (u64)time << 32; 724 725 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { 726 /* Tx case */ 727 err = ice_write_64b_phy_reg_e822(hw, port, 728 P_REG_TX_TIMER_INC_PRE_L, 729 phy_time); 730 if (err) 731 goto exit_err; 732 733 /* Rx case */ 734 err = ice_write_64b_phy_reg_e822(hw, port, 735 P_REG_RX_TIMER_INC_PRE_L, 736 phy_time); 737 if (err) 738 goto exit_err; 739 } 740 741 return 0; 742 743 exit_err: 744 ice_debug(hw, ICE_DBG_PTP, "Failed to write init time for port %u, err %d\n", 745 port, err); 746 747 return err; 748 } 749 750 /** 751 * ice_ptp_prep_port_adj_e822 - Prepare a single port for time adjust 752 * @hw: pointer to HW struct 753 * @port: Port number to be programmed 754 * @time: time in cycles to adjust the port Tx and Rx clocks 755 * 756 * Program the port for an atomic adjustment by writing the Tx and Rx timer 757 * registers. The atomic adjustment won't be completed until the driver issues 758 * an ADJ_TIME command. 759 * 760 * Note that time is not in units of nanoseconds. It is in clock time 761 * including the lower sub-nanosecond portion of the port timer. 762 * 763 * Negative adjustments are supported using 2s complement arithmetic. 764 */ 765 int 766 ice_ptp_prep_port_adj_e822(struct ice_hw *hw, u8 port, s64 time) 767 { 768 u32 l_time, u_time; 769 int err; 770 771 l_time = lower_32_bits(time); 772 u_time = upper_32_bits(time); 773 774 /* Tx case */ 775 err = ice_write_phy_reg_e822(hw, port, P_REG_TX_TIMER_INC_PRE_L, 776 l_time); 777 if (err) 778 goto exit_err; 779 780 err = ice_write_phy_reg_e822(hw, port, P_REG_TX_TIMER_INC_PRE_U, 781 u_time); 782 if (err) 783 goto exit_err; 784 785 /* Rx case */ 786 err = ice_write_phy_reg_e822(hw, port, P_REG_RX_TIMER_INC_PRE_L, 787 l_time); 788 if (err) 789 goto exit_err; 790 791 err = ice_write_phy_reg_e822(hw, port, P_REG_RX_TIMER_INC_PRE_U, 792 u_time); 793 if (err) 794 goto exit_err; 795 796 return 0; 797 798 exit_err: 799 ice_debug(hw, ICE_DBG_PTP, "Failed to write time adjust for port %u, err %d\n", 800 port, err); 801 return err; 802 } 803 804 /** 805 * ice_ptp_prep_phy_adj_e822 - Prep PHY ports for a time adjustment 806 * @hw: pointer to HW struct 807 * @adj: adjustment in nanoseconds 808 * 809 * Prepare the PHY ports for an atomic time adjustment by programming the PHY 810 * Tx and Rx port registers. The actual adjustment is completed by issuing an 811 * ADJ_TIME or ADJ_TIME_AT_TIME sync command. 812 */ 813 static int 814 ice_ptp_prep_phy_adj_e822(struct ice_hw *hw, s32 adj) 815 { 816 s64 cycles; 817 u8 port; 818 819 /* The port clock supports adjustment of the sub-nanosecond portion of 820 * the clock. We shift the provided adjustment in nanoseconds to 821 * calculate the appropriate adjustment to program into the PHY ports. 822 */ 823 if (adj > 0) 824 cycles = (s64)adj << 32; 825 else 826 cycles = -(((s64)-adj) << 32); 827 828 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { 829 int err; 830 831 err = ice_ptp_prep_port_adj_e822(hw, port, cycles); 832 if (err) 833 return err; 834 } 835 836 return 0; 837 } 838 839 /** 840 * ice_ptp_prep_phy_incval_e822 - Prepare PHY ports for time adjustment 841 * @hw: pointer to HW struct 842 * @incval: new increment value to prepare 843 * 844 * Prepare each of the PHY ports for a new increment value by programming the 845 * port's TIMETUS registers. The new increment value will be updated after 846 * issuing an INIT_INCVAL command. 847 */ 848 static int 849 ice_ptp_prep_phy_incval_e822(struct ice_hw *hw, u64 incval) 850 { 851 int err; 852 u8 port; 853 854 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { 855 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L, 856 incval); 857 if (err) 858 goto exit_err; 859 } 860 861 return 0; 862 863 exit_err: 864 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval for port %u, err %d\n", 865 port, err); 866 867 return err; 868 } 869 870 /** 871 * ice_ptp_read_port_capture - Read a port's local time capture 872 * @hw: pointer to HW struct 873 * @port: Port number to read 874 * @tx_ts: on return, the Tx port time capture 875 * @rx_ts: on return, the Rx port time capture 876 * 877 * Read the port's Tx and Rx local time capture values. 878 * 879 * Note this has no equivalent for the E810 devices. 880 */ 881 static int 882 ice_ptp_read_port_capture(struct ice_hw *hw, u8 port, u64 *tx_ts, u64 *rx_ts) 883 { 884 int err; 885 886 /* Tx case */ 887 err = ice_read_64b_phy_reg_e822(hw, port, P_REG_TX_CAPTURE_L, tx_ts); 888 if (err) { 889 ice_debug(hw, ICE_DBG_PTP, "Failed to read REG_TX_CAPTURE, err %d\n", 890 err); 891 return err; 892 } 893 894 ice_debug(hw, ICE_DBG_PTP, "tx_init = 0x%016llx\n", 895 (unsigned long long)*tx_ts); 896 897 /* Rx case */ 898 err = ice_read_64b_phy_reg_e822(hw, port, P_REG_RX_CAPTURE_L, rx_ts); 899 if (err) { 900 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_CAPTURE, err %d\n", 901 err); 902 return err; 903 } 904 905 ice_debug(hw, ICE_DBG_PTP, "rx_init = 0x%016llx\n", 906 (unsigned long long)*rx_ts); 907 908 return 0; 909 } 910 911 /** 912 * ice_ptp_one_port_cmd - Prepare a single PHY port for a timer command 913 * @hw: pointer to HW struct 914 * @port: Port to which cmd has to be sent 915 * @cmd: Command to be sent to the port 916 * 917 * Prepare the requested port for an upcoming timer sync command. 918 * 919 * Note there is no equivalent of this operation on E810, as that device 920 * always handles all external PHYs internally. 921 */ 922 static int 923 ice_ptp_one_port_cmd(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd) 924 { 925 u32 cmd_val, val; 926 u8 tmr_idx; 927 int err; 928 929 tmr_idx = ice_get_ptp_src_clock_index(hw); 930 cmd_val = tmr_idx << SEL_PHY_SRC; 931 switch (cmd) { 932 case INIT_TIME: 933 cmd_val |= PHY_CMD_INIT_TIME; 934 break; 935 case INIT_INCVAL: 936 cmd_val |= PHY_CMD_INIT_INCVAL; 937 break; 938 case ADJ_TIME: 939 cmd_val |= PHY_CMD_ADJ_TIME; 940 break; 941 case READ_TIME: 942 cmd_val |= PHY_CMD_READ_TIME; 943 break; 944 case ADJ_TIME_AT_TIME: 945 cmd_val |= PHY_CMD_ADJ_TIME_AT_TIME; 946 break; 947 } 948 949 /* Tx case */ 950 /* Read, modify, write */ 951 err = ice_read_phy_reg_e822(hw, port, P_REG_TX_TMR_CMD, &val); 952 if (err) { 953 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_TMR_CMD, err %d\n", 954 err); 955 return err; 956 } 957 958 /* Modify necessary bits only and perform write */ 959 val &= ~TS_CMD_MASK; 960 val |= cmd_val; 961 962 err = ice_write_phy_reg_e822(hw, port, P_REG_TX_TMR_CMD, val); 963 if (err) { 964 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_TMR_CMD, err %d\n", 965 err); 966 return err; 967 } 968 969 /* Rx case */ 970 /* Read, modify, write */ 971 err = ice_read_phy_reg_e822(hw, port, P_REG_RX_TMR_CMD, &val); 972 if (err) { 973 ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_TMR_CMD, err %d\n", 974 err); 975 return err; 976 } 977 978 /* Modify necessary bits only and perform write */ 979 val &= ~TS_CMD_MASK; 980 val |= cmd_val; 981 982 err = ice_write_phy_reg_e822(hw, port, P_REG_RX_TMR_CMD, val); 983 if (err) { 984 ice_debug(hw, ICE_DBG_PTP, "Failed to write back RX_TMR_CMD, err %d\n", 985 err); 986 return err; 987 } 988 989 return 0; 990 } 991 992 /** 993 * ice_ptp_port_cmd_e822 - Prepare all ports for a timer command 994 * @hw: pointer to the HW struct 995 * @cmd: timer command to prepare 996 * 997 * Prepare all ports connected to this device for an upcoming timer sync 998 * command. 999 */ 1000 static int 1001 ice_ptp_port_cmd_e822(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 1002 { 1003 u8 port; 1004 1005 for (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) { 1006 int err; 1007 1008 err = ice_ptp_one_port_cmd(hw, port, cmd); 1009 if (err) 1010 return err; 1011 } 1012 1013 return 0; 1014 } 1015 1016 /* E822 Vernier calibration functions 1017 * 1018 * The following functions are used as part of the vernier calibration of 1019 * a port. This calibration increases the precision of the timestamps on the 1020 * port. 1021 */ 1022 1023 /** 1024 * ice_phy_get_speed_and_fec_e822 - Get link speed and FEC based on serdes mode 1025 * @hw: pointer to HW struct 1026 * @port: the port to read from 1027 * @link_out: if non-NULL, holds link speed on success 1028 * @fec_out: if non-NULL, holds FEC algorithm on success 1029 * 1030 * Read the serdes data for the PHY port and extract the link speed and FEC 1031 * algorithm. 1032 */ 1033 static int 1034 ice_phy_get_speed_and_fec_e822(struct ice_hw *hw, u8 port, 1035 enum ice_ptp_link_spd *link_out, 1036 enum ice_ptp_fec_mode *fec_out) 1037 { 1038 enum ice_ptp_link_spd link; 1039 enum ice_ptp_fec_mode fec; 1040 u32 serdes; 1041 int err; 1042 1043 err = ice_read_phy_reg_e822(hw, port, P_REG_LINK_SPEED, &serdes); 1044 if (err) { 1045 ice_debug(hw, ICE_DBG_PTP, "Failed to read serdes info\n"); 1046 return err; 1047 } 1048 1049 /* Determine the FEC algorithm */ 1050 fec = (enum ice_ptp_fec_mode)P_REG_LINK_SPEED_FEC_MODE(serdes); 1051 1052 serdes &= P_REG_LINK_SPEED_SERDES_M; 1053 1054 /* Determine the link speed */ 1055 if (fec == ICE_PTP_FEC_MODE_RS_FEC) { 1056 switch (serdes) { 1057 case ICE_PTP_SERDES_25G: 1058 link = ICE_PTP_LNK_SPD_25G_RS; 1059 break; 1060 case ICE_PTP_SERDES_50G: 1061 link = ICE_PTP_LNK_SPD_50G_RS; 1062 break; 1063 case ICE_PTP_SERDES_100G: 1064 link = ICE_PTP_LNK_SPD_100G_RS; 1065 break; 1066 default: 1067 return -EIO; 1068 } 1069 } else { 1070 switch (serdes) { 1071 case ICE_PTP_SERDES_1G: 1072 link = ICE_PTP_LNK_SPD_1G; 1073 break; 1074 case ICE_PTP_SERDES_10G: 1075 link = ICE_PTP_LNK_SPD_10G; 1076 break; 1077 case ICE_PTP_SERDES_25G: 1078 link = ICE_PTP_LNK_SPD_25G; 1079 break; 1080 case ICE_PTP_SERDES_40G: 1081 link = ICE_PTP_LNK_SPD_40G; 1082 break; 1083 case ICE_PTP_SERDES_50G: 1084 link = ICE_PTP_LNK_SPD_50G; 1085 break; 1086 default: 1087 return -EIO; 1088 } 1089 } 1090 1091 if (link_out) 1092 *link_out = link; 1093 if (fec_out) 1094 *fec_out = fec; 1095 1096 return 0; 1097 } 1098 1099 /** 1100 * ice_phy_cfg_lane_e822 - Configure PHY quad for single/multi-lane timestamp 1101 * @hw: pointer to HW struct 1102 * @port: to configure the quad for 1103 */ 1104 static void ice_phy_cfg_lane_e822(struct ice_hw *hw, u8 port) 1105 { 1106 enum ice_ptp_link_spd link_spd; 1107 int err; 1108 u32 val; 1109 u8 quad; 1110 1111 err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, NULL); 1112 if (err) { 1113 ice_debug(hw, ICE_DBG_PTP, "Failed to get PHY link speed, err %d\n", 1114 err); 1115 return; 1116 } 1117 1118 quad = port / ICE_PORTS_PER_QUAD; 1119 1120 err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val); 1121 if (err) { 1122 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEM_GLB_CFG, err %d\n", 1123 err); 1124 return; 1125 } 1126 1127 if (link_spd >= ICE_PTP_LNK_SPD_40G) 1128 val &= ~Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M; 1129 else 1130 val |= Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M; 1131 1132 err = ice_write_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG, val); 1133 if (err) { 1134 ice_debug(hw, ICE_DBG_PTP, "Failed to write back TX_MEM_GBL_CFG, err %d\n", 1135 err); 1136 return; 1137 } 1138 } 1139 1140 /** 1141 * ice_phy_cfg_uix_e822 - Configure Serdes UI to TU conversion for E822 1142 * @hw: pointer to the HW structure 1143 * @port: the port to configure 1144 * 1145 * Program the conversion ration of Serdes clock "unit intervals" (UIs) to PHC 1146 * hardware clock time units (TUs). That is, determine the number of TUs per 1147 * serdes unit interval, and program the UIX registers with this conversion. 1148 * 1149 * This conversion is used as part of the calibration process when determining 1150 * the additional error of a timestamp vs the real time of transmission or 1151 * receipt of the packet. 1152 * 1153 * Hardware uses the number of TUs per 66 UIs, written to the UIX registers 1154 * for the two main serdes clock rates, 10G/40G and 25G/100G serdes clocks. 1155 * 1156 * To calculate the conversion ratio, we use the following facts: 1157 * 1158 * a) the clock frequency in Hz (cycles per second) 1159 * b) the number of TUs per cycle (the increment value of the clock) 1160 * c) 1 second per 1 billion nanoseconds 1161 * d) the duration of 66 UIs in nanoseconds 1162 * 1163 * Given these facts, we can use the following table to work out what ratios 1164 * to multiply in order to get the number of TUs per 66 UIs: 1165 * 1166 * cycles | 1 second | incval (TUs) | nanoseconds 1167 * -------+--------------+--------------+------------- 1168 * second | 1 billion ns | cycle | 66 UIs 1169 * 1170 * To perform the multiplication using integers without too much loss of 1171 * precision, we can take use the following equation: 1172 * 1173 * (freq * incval * 6600 LINE_UI ) / ( 100 * 1 billion) 1174 * 1175 * We scale up to using 6600 UI instead of 66 in order to avoid fractional 1176 * nanosecond UIs (66 UI at 10G/40G is 6.4 ns) 1177 * 1178 * The increment value has a maximum expected range of about 34 bits, while 1179 * the frequency value is about 29 bits. Multiplying these values shouldn't 1180 * overflow the 64 bits. However, we must then further multiply them again by 1181 * the Serdes unit interval duration. To avoid overflow here, we split the 1182 * overall divide by 1e11 into a divide by 256 (shift down by 8 bits) and 1183 * a divide by 390,625,000. This does lose some precision, but avoids 1184 * miscalculation due to arithmetic overflow. 1185 */ 1186 static int ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port) 1187 { 1188 u64 cur_freq, clk_incval, tu_per_sec, uix; 1189 int err; 1190 1191 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw)); 1192 clk_incval = ice_ptp_read_src_incval(hw); 1193 1194 /* Calculate TUs per second divided by 256 */ 1195 tu_per_sec = (cur_freq * clk_incval) >> 8; 1196 1197 #define LINE_UI_10G_40G 640 /* 6600 UIs is 640 nanoseconds at 10Gb/40Gb */ 1198 #define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */ 1199 1200 /* Program the 10Gb/40Gb conversion ratio */ 1201 uix = div_u64(tu_per_sec * LINE_UI_10G_40G, 390625000); 1202 1203 err = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_10G_40G_L, 1204 uix); 1205 if (err) { 1206 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_10G_40G, err %d\n", 1207 err); 1208 return err; 1209 } 1210 1211 /* Program the 25Gb/100Gb conversion ratio */ 1212 uix = div_u64(tu_per_sec * LINE_UI_25G_100G, 390625000); 1213 1214 err = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_25G_100G_L, 1215 uix); 1216 if (err) { 1217 ice_debug(hw, ICE_DBG_PTP, "Failed to write UIX66_25G_100G, err %d\n", 1218 err); 1219 return err; 1220 } 1221 1222 return 0; 1223 } 1224 1225 /** 1226 * ice_phy_cfg_parpcs_e822 - Configure TUs per PAR/PCS clock cycle 1227 * @hw: pointer to the HW struct 1228 * @port: port to configure 1229 * 1230 * Configure the number of TUs for the PAR and PCS clocks used as part of the 1231 * timestamp calibration process. This depends on the link speed, as the PHY 1232 * uses different markers depending on the speed. 1233 * 1234 * 1Gb/10Gb/25Gb: 1235 * - Tx/Rx PAR/PCS markers 1236 * 1237 * 25Gb RS: 1238 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers 1239 * 1240 * 40Gb/50Gb: 1241 * - Tx/Rx PAR/PCS markers 1242 * - Rx Deskew PAR/PCS markers 1243 * 1244 * 50G RS and 100GB RS: 1245 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers 1246 * - Rx Deskew PAR/PCS markers 1247 * - Tx PAR/PCS markers 1248 * 1249 * To calculate the conversion, we use the PHC clock frequency (cycles per 1250 * second), the increment value (TUs per cycle), and the related PHY clock 1251 * frequency to calculate the TUs per unit of the PHY link clock. The 1252 * following table shows how the units convert: 1253 * 1254 * cycles | TUs | second 1255 * -------+-------+-------- 1256 * second | cycle | cycles 1257 * 1258 * For each conversion register, look up the appropriate frequency from the 1259 * e822 PAR/PCS table and calculate the TUs per unit of that clock. Program 1260 * this to the appropriate register, preparing hardware to perform timestamp 1261 * calibration to calculate the total Tx or Rx offset to adjust the timestamp 1262 * in order to calibrate for the internal PHY delays. 1263 * 1264 * Note that the increment value ranges up to ~34 bits, and the clock 1265 * frequency is ~29 bits, so multiplying them together should fit within the 1266 * 64 bit arithmetic. 1267 */ 1268 static int ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port) 1269 { 1270 u64 cur_freq, clk_incval, tu_per_sec, phy_tus; 1271 enum ice_ptp_link_spd link_spd; 1272 enum ice_ptp_fec_mode fec_mode; 1273 int err; 1274 1275 err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode); 1276 if (err) 1277 return err; 1278 1279 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw)); 1280 clk_incval = ice_ptp_read_src_incval(hw); 1281 1282 /* Calculate TUs per cycle of the PHC clock */ 1283 tu_per_sec = cur_freq * clk_incval; 1284 1285 /* For each PHY conversion register, look up the appropriate link 1286 * speed frequency and determine the TUs per that clock's cycle time. 1287 * Split this into a high and low value and then program the 1288 * appropriate register. If that link speed does not use the 1289 * associated register, write zeros to clear it instead. 1290 */ 1291 1292 /* P_REG_PAR_TX_TUS */ 1293 if (e822_vernier[link_spd].tx_par_clk) 1294 phy_tus = div_u64(tu_per_sec, 1295 e822_vernier[link_spd].tx_par_clk); 1296 else 1297 phy_tus = 0; 1298 1299 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PAR_TX_TUS_L, 1300 phy_tus); 1301 if (err) 1302 return err; 1303 1304 /* P_REG_PAR_RX_TUS */ 1305 if (e822_vernier[link_spd].rx_par_clk) 1306 phy_tus = div_u64(tu_per_sec, 1307 e822_vernier[link_spd].rx_par_clk); 1308 else 1309 phy_tus = 0; 1310 1311 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PAR_RX_TUS_L, 1312 phy_tus); 1313 if (err) 1314 return err; 1315 1316 /* P_REG_PCS_TX_TUS */ 1317 if (e822_vernier[link_spd].tx_pcs_clk) 1318 phy_tus = div_u64(tu_per_sec, 1319 e822_vernier[link_spd].tx_pcs_clk); 1320 else 1321 phy_tus = 0; 1322 1323 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PCS_TX_TUS_L, 1324 phy_tus); 1325 if (err) 1326 return err; 1327 1328 /* P_REG_PCS_RX_TUS */ 1329 if (e822_vernier[link_spd].rx_pcs_clk) 1330 phy_tus = div_u64(tu_per_sec, 1331 e822_vernier[link_spd].rx_pcs_clk); 1332 else 1333 phy_tus = 0; 1334 1335 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_PCS_RX_TUS_L, 1336 phy_tus); 1337 if (err) 1338 return err; 1339 1340 /* P_REG_DESK_PAR_TX_TUS */ 1341 if (e822_vernier[link_spd].tx_desk_rsgb_par) 1342 phy_tus = div_u64(tu_per_sec, 1343 e822_vernier[link_spd].tx_desk_rsgb_par); 1344 else 1345 phy_tus = 0; 1346 1347 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PAR_TX_TUS_L, 1348 phy_tus); 1349 if (err) 1350 return err; 1351 1352 /* P_REG_DESK_PAR_RX_TUS */ 1353 if (e822_vernier[link_spd].rx_desk_rsgb_par) 1354 phy_tus = div_u64(tu_per_sec, 1355 e822_vernier[link_spd].rx_desk_rsgb_par); 1356 else 1357 phy_tus = 0; 1358 1359 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PAR_RX_TUS_L, 1360 phy_tus); 1361 if (err) 1362 return err; 1363 1364 /* P_REG_DESK_PCS_TX_TUS */ 1365 if (e822_vernier[link_spd].tx_desk_rsgb_pcs) 1366 phy_tus = div_u64(tu_per_sec, 1367 e822_vernier[link_spd].tx_desk_rsgb_pcs); 1368 else 1369 phy_tus = 0; 1370 1371 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PCS_TX_TUS_L, 1372 phy_tus); 1373 if (err) 1374 return err; 1375 1376 /* P_REG_DESK_PCS_RX_TUS */ 1377 if (e822_vernier[link_spd].rx_desk_rsgb_pcs) 1378 phy_tus = div_u64(tu_per_sec, 1379 e822_vernier[link_spd].rx_desk_rsgb_pcs); 1380 else 1381 phy_tus = 0; 1382 1383 return ice_write_40b_phy_reg_e822(hw, port, P_REG_DESK_PCS_RX_TUS_L, 1384 phy_tus); 1385 } 1386 1387 /** 1388 * ice_calc_fixed_tx_offset_e822 - Calculated Fixed Tx offset for a port 1389 * @hw: pointer to the HW struct 1390 * @link_spd: the Link speed to calculate for 1391 * 1392 * Calculate the fixed offset due to known static latency data. 1393 */ 1394 static u64 1395 ice_calc_fixed_tx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) 1396 { 1397 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset; 1398 1399 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw)); 1400 clk_incval = ice_ptp_read_src_incval(hw); 1401 1402 /* Calculate TUs per second */ 1403 tu_per_sec = cur_freq * clk_incval; 1404 1405 /* Calculate number of TUs to add for the fixed Tx latency. Since the 1406 * latency measurement is in 1/100th of a nanosecond, we need to 1407 * multiply by tu_per_sec and then divide by 1e11. This calculation 1408 * overflows 64 bit integer arithmetic, so break it up into two 1409 * divisions by 1e4 first then by 1e7. 1410 */ 1411 fixed_offset = div_u64(tu_per_sec, 10000); 1412 fixed_offset *= e822_vernier[link_spd].tx_fixed_delay; 1413 fixed_offset = div_u64(fixed_offset, 10000000); 1414 1415 return fixed_offset; 1416 } 1417 1418 /** 1419 * ice_phy_cfg_fixed_tx_offset_e822 - Configure Tx offset for bypass mode 1420 * @hw: pointer to the HW struct 1421 * @port: the PHY port to configure 1422 * 1423 * Calculate and program the fixed Tx offset, and indicate that the offset is 1424 * ready. This can be used when operating in bypass mode. 1425 */ 1426 static int 1427 ice_phy_cfg_fixed_tx_offset_e822(struct ice_hw *hw, u8 port) 1428 { 1429 enum ice_ptp_link_spd link_spd; 1430 enum ice_ptp_fec_mode fec_mode; 1431 u64 total_offset; 1432 int err; 1433 1434 err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode); 1435 if (err) 1436 return err; 1437 1438 total_offset = ice_calc_fixed_tx_offset_e822(hw, link_spd); 1439 1440 /* Program the fixed Tx offset into the P_REG_TOTAL_TX_OFFSET_L 1441 * register, then indicate that the Tx offset is ready. After this, 1442 * timestamps will be enabled. 1443 * 1444 * Note that this skips including the more precise offsets generated 1445 * by the Vernier calibration. 1446 */ 1447 err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L, 1448 total_offset); 1449 if (err) 1450 return err; 1451 1452 err = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1); 1453 if (err) 1454 return err; 1455 1456 return 0; 1457 } 1458 1459 /** 1460 * ice_calc_fixed_rx_offset_e822 - Calculated the fixed Rx offset for a port 1461 * @hw: pointer to HW struct 1462 * @link_spd: The Link speed to calculate for 1463 * 1464 * Determine the fixed Rx latency for a given link speed. 1465 */ 1466 static u64 1467 ice_calc_fixed_rx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd) 1468 { 1469 u64 cur_freq, clk_incval, tu_per_sec, fixed_offset; 1470 1471 cur_freq = ice_e822_pll_freq(ice_e822_time_ref(hw)); 1472 clk_incval = ice_ptp_read_src_incval(hw); 1473 1474 /* Calculate TUs per second */ 1475 tu_per_sec = cur_freq * clk_incval; 1476 1477 /* Calculate number of TUs to add for the fixed Rx latency. Since the 1478 * latency measurement is in 1/100th of a nanosecond, we need to 1479 * multiply by tu_per_sec and then divide by 1e11. This calculation 1480 * overflows 64 bit integer arithmetic, so break it up into two 1481 * divisions by 1e4 first then by 1e7. 1482 */ 1483 fixed_offset = div_u64(tu_per_sec, 10000); 1484 fixed_offset *= e822_vernier[link_spd].rx_fixed_delay; 1485 fixed_offset = div_u64(fixed_offset, 10000000); 1486 1487 return fixed_offset; 1488 } 1489 1490 /** 1491 * ice_phy_cfg_fixed_rx_offset_e822 - Configure fixed Rx offset for bypass mode 1492 * @hw: pointer to the HW struct 1493 * @port: the PHY port to configure 1494 * 1495 * Calculate and program the fixed Rx offset, and indicate that the offset is 1496 * ready. This can be used when operating in bypass mode. 1497 */ 1498 static int 1499 ice_phy_cfg_fixed_rx_offset_e822(struct ice_hw *hw, u8 port) 1500 { 1501 enum ice_ptp_link_spd link_spd; 1502 enum ice_ptp_fec_mode fec_mode; 1503 u64 total_offset; 1504 int err; 1505 1506 err = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode); 1507 if (err) 1508 return err; 1509 1510 total_offset = ice_calc_fixed_rx_offset_e822(hw, link_spd); 1511 1512 /* Program the fixed Rx offset into the P_REG_TOTAL_RX_OFFSET_L 1513 * register, then indicate that the Rx offset is ready. After this, 1514 * timestamps will be enabled. 1515 * 1516 * Note that this skips including the more precise offsets generated 1517 * by Vernier calibration. 1518 */ 1519 err = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L, 1520 total_offset); 1521 if (err) 1522 return err; 1523 1524 err = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1); 1525 if (err) 1526 return err; 1527 1528 return 0; 1529 } 1530 1531 /** 1532 * ice_read_phy_and_phc_time_e822 - Simultaneously capture PHC and PHY time 1533 * @hw: pointer to the HW struct 1534 * @port: the PHY port to read 1535 * @phy_time: on return, the 64bit PHY timer value 1536 * @phc_time: on return, the lower 64bits of PHC time 1537 * 1538 * Issue a READ_TIME timer command to simultaneously capture the PHY and PHC 1539 * timer values. 1540 */ 1541 static int 1542 ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8 port, u64 *phy_time, 1543 u64 *phc_time) 1544 { 1545 u64 tx_time, rx_time; 1546 u32 zo, lo; 1547 u8 tmr_idx; 1548 int err; 1549 1550 tmr_idx = ice_get_ptp_src_clock_index(hw); 1551 1552 /* Prepare the PHC timer for a READ_TIME capture command */ 1553 ice_ptp_src_cmd(hw, READ_TIME); 1554 1555 /* Prepare the PHY timer for a READ_TIME capture command */ 1556 err = ice_ptp_one_port_cmd(hw, port, READ_TIME); 1557 if (err) 1558 return err; 1559 1560 /* Issue the sync to start the READ_TIME capture */ 1561 ice_ptp_exec_tmr_cmd(hw); 1562 1563 /* Read the captured PHC time from the shadow time registers */ 1564 zo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx)); 1565 lo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx)); 1566 *phc_time = (u64)lo << 32 | zo; 1567 1568 /* Read the captured PHY time from the PHY shadow registers */ 1569 err = ice_ptp_read_port_capture(hw, port, &tx_time, &rx_time); 1570 if (err) 1571 return err; 1572 1573 /* If the PHY Tx and Rx timers don't match, log a warning message. 1574 * Note that this should not happen in normal circumstances since the 1575 * driver always programs them together. 1576 */ 1577 if (tx_time != rx_time) 1578 dev_warn(ice_hw_to_dev(hw), 1579 "PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\n", 1580 port, (unsigned long long)tx_time, 1581 (unsigned long long)rx_time); 1582 1583 *phy_time = tx_time; 1584 1585 return 0; 1586 } 1587 1588 /** 1589 * ice_sync_phy_timer_e822 - Synchronize the PHY timer with PHC timer 1590 * @hw: pointer to the HW struct 1591 * @port: the PHY port to synchronize 1592 * 1593 * Perform an adjustment to ensure that the PHY and PHC timers are in sync. 1594 * This is done by issuing a READ_TIME command which triggers a simultaneous 1595 * read of the PHY timer and PHC timer. Then we use the difference to 1596 * calculate an appropriate 2s complement addition to add to the PHY timer in 1597 * order to ensure it reads the same value as the primary PHC timer. 1598 */ 1599 static int ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port) 1600 { 1601 u64 phc_time, phy_time, difference; 1602 int err; 1603 1604 if (!ice_ptp_lock(hw)) { 1605 ice_debug(hw, ICE_DBG_PTP, "Failed to acquire PTP semaphore\n"); 1606 return -EBUSY; 1607 } 1608 1609 err = ice_read_phy_and_phc_time_e822(hw, port, &phy_time, &phc_time); 1610 if (err) 1611 goto err_unlock; 1612 1613 /* Calculate the amount required to add to the port time in order for 1614 * it to match the PHC time. 1615 * 1616 * Note that the port adjustment is done using 2s complement 1617 * arithmetic. This is convenient since it means that we can simply 1618 * calculate the difference between the PHC time and the port time, 1619 * and it will be interpreted correctly. 1620 */ 1621 difference = phc_time - phy_time; 1622 1623 err = ice_ptp_prep_port_adj_e822(hw, port, (s64)difference); 1624 if (err) 1625 goto err_unlock; 1626 1627 err = ice_ptp_one_port_cmd(hw, port, ADJ_TIME); 1628 if (err) 1629 goto err_unlock; 1630 1631 /* Issue the sync to activate the time adjustment */ 1632 ice_ptp_exec_tmr_cmd(hw); 1633 1634 /* Re-capture the timer values to flush the command registers and 1635 * verify that the time was properly adjusted. 1636 */ 1637 err = ice_read_phy_and_phc_time_e822(hw, port, &phy_time, &phc_time); 1638 if (err) 1639 goto err_unlock; 1640 1641 dev_info(ice_hw_to_dev(hw), 1642 "Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\n", 1643 port, (unsigned long long)phy_time, 1644 (unsigned long long)phc_time); 1645 1646 ice_ptp_unlock(hw); 1647 1648 return 0; 1649 1650 err_unlock: 1651 ice_ptp_unlock(hw); 1652 return err; 1653 } 1654 1655 /** 1656 * ice_stop_phy_timer_e822 - Stop the PHY clock timer 1657 * @hw: pointer to the HW struct 1658 * @port: the PHY port to stop 1659 * @soft_reset: if true, hold the SOFT_RESET bit of P_REG_PS 1660 * 1661 * Stop the clock of a PHY port. This must be done as part of the flow to 1662 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 1663 * initialized or when link speed changes. 1664 */ 1665 int 1666 ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset) 1667 { 1668 int err; 1669 u32 val; 1670 1671 err = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 0); 1672 if (err) 1673 return err; 1674 1675 err = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 0); 1676 if (err) 1677 return err; 1678 1679 err = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val); 1680 if (err) 1681 return err; 1682 1683 val &= ~P_REG_PS_START_M; 1684 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 1685 if (err) 1686 return err; 1687 1688 val &= ~P_REG_PS_ENA_CLK_M; 1689 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 1690 if (err) 1691 return err; 1692 1693 if (soft_reset) { 1694 val |= P_REG_PS_SFT_RESET_M; 1695 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 1696 if (err) 1697 return err; 1698 } 1699 1700 ice_debug(hw, ICE_DBG_PTP, "Disabled clock on PHY port %u\n", port); 1701 1702 return 0; 1703 } 1704 1705 /** 1706 * ice_start_phy_timer_e822 - Start the PHY clock timer 1707 * @hw: pointer to the HW struct 1708 * @port: the PHY port to start 1709 * @bypass: if true, start the PHY in bypass mode 1710 * 1711 * Start the clock of a PHY port. This must be done as part of the flow to 1712 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is 1713 * initialized or when link speed changes. 1714 * 1715 * Bypass mode enables timestamps immediately without waiting for Vernier 1716 * calibration to complete. Hardware will still continue taking Vernier 1717 * measurements on Tx or Rx of packets, but they will not be applied to 1718 * timestamps. Use ice_phy_exit_bypass_e822 to exit bypass mode once hardware 1719 * has completed offset calculation. 1720 */ 1721 int 1722 ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass) 1723 { 1724 u32 lo, hi, val; 1725 u64 incval; 1726 u8 tmr_idx; 1727 int err; 1728 1729 tmr_idx = ice_get_ptp_src_clock_index(hw); 1730 1731 err = ice_stop_phy_timer_e822(hw, port, false); 1732 if (err) 1733 return err; 1734 1735 ice_phy_cfg_lane_e822(hw, port); 1736 1737 err = ice_phy_cfg_uix_e822(hw, port); 1738 if (err) 1739 return err; 1740 1741 err = ice_phy_cfg_parpcs_e822(hw, port); 1742 if (err) 1743 return err; 1744 1745 lo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx)); 1746 hi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx)); 1747 incval = (u64)hi << 32 | lo; 1748 1749 err = ice_write_40b_phy_reg_e822(hw, port, P_REG_TIMETUS_L, incval); 1750 if (err) 1751 return err; 1752 1753 err = ice_ptp_one_port_cmd(hw, port, INIT_INCVAL); 1754 if (err) 1755 return err; 1756 1757 ice_ptp_exec_tmr_cmd(hw); 1758 1759 err = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val); 1760 if (err) 1761 return err; 1762 1763 val |= P_REG_PS_SFT_RESET_M; 1764 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 1765 if (err) 1766 return err; 1767 1768 val |= P_REG_PS_START_M; 1769 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 1770 if (err) 1771 return err; 1772 1773 val &= ~P_REG_PS_SFT_RESET_M; 1774 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 1775 if (err) 1776 return err; 1777 1778 err = ice_ptp_one_port_cmd(hw, port, INIT_INCVAL); 1779 if (err) 1780 return err; 1781 1782 ice_ptp_exec_tmr_cmd(hw); 1783 1784 val |= P_REG_PS_ENA_CLK_M; 1785 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 1786 if (err) 1787 return err; 1788 1789 val |= P_REG_PS_LOAD_OFFSET_M; 1790 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 1791 if (err) 1792 return err; 1793 1794 ice_ptp_exec_tmr_cmd(hw); 1795 1796 err = ice_sync_phy_timer_e822(hw, port); 1797 if (err) 1798 return err; 1799 1800 if (bypass) { 1801 val |= P_REG_PS_BYPASS_MODE_M; 1802 /* Enter BYPASS mode, enabling timestamps immediately. */ 1803 err = ice_write_phy_reg_e822(hw, port, P_REG_PS, val); 1804 if (err) 1805 return err; 1806 1807 /* Program the fixed Tx offset */ 1808 err = ice_phy_cfg_fixed_tx_offset_e822(hw, port); 1809 if (err) 1810 return err; 1811 1812 /* Program the fixed Rx offset */ 1813 err = ice_phy_cfg_fixed_rx_offset_e822(hw, port); 1814 if (err) 1815 return err; 1816 } 1817 1818 ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port); 1819 1820 return 0; 1821 } 1822 1823 /* E810 functions 1824 * 1825 * The following functions operate on the E810 series devices which use 1826 * a separate external PHY. 1827 */ 1828 1829 /** 1830 * ice_read_phy_reg_e810 - Read register from external PHY on E810 1831 * @hw: pointer to the HW struct 1832 * @addr: the address to read from 1833 * @val: On return, the value read from the PHY 1834 * 1835 * Read a register from the external PHY on the E810 device. 1836 */ 1837 static int ice_read_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 *val) 1838 { 1839 struct ice_sbq_msg_input msg = {0}; 1840 int err; 1841 1842 msg.msg_addr_low = lower_16_bits(addr); 1843 msg.msg_addr_high = upper_16_bits(addr); 1844 msg.opcode = ice_sbq_msg_rd; 1845 msg.dest_dev = rmn_0; 1846 1847 err = ice_sbq_rw_reg(hw, &msg); 1848 if (err) { 1849 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 1850 err); 1851 return err; 1852 } 1853 1854 *val = msg.data; 1855 1856 return 0; 1857 } 1858 1859 /** 1860 * ice_write_phy_reg_e810 - Write register on external PHY on E810 1861 * @hw: pointer to the HW struct 1862 * @addr: the address to writem to 1863 * @val: the value to write to the PHY 1864 * 1865 * Write a value to a register of the external PHY on the E810 device. 1866 */ 1867 static int ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val) 1868 { 1869 struct ice_sbq_msg_input msg = {0}; 1870 int err; 1871 1872 msg.msg_addr_low = lower_16_bits(addr); 1873 msg.msg_addr_high = upper_16_bits(addr); 1874 msg.opcode = ice_sbq_msg_wr; 1875 msg.dest_dev = rmn_0; 1876 msg.data = val; 1877 1878 err = ice_sbq_rw_reg(hw, &msg); 1879 if (err) { 1880 ice_debug(hw, ICE_DBG_PTP, "Failed to send message to PHY, err %d\n", 1881 err); 1882 return err; 1883 } 1884 1885 return 0; 1886 } 1887 1888 /** 1889 * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY 1890 * @hw: pointer to the HW struct 1891 * @lport: the lport to read from 1892 * @idx: the timestamp index to read 1893 * @tstamp: on return, the 40bit timestamp value 1894 * 1895 * Read a 40bit timestamp value out of the timestamp block of the external PHY 1896 * on the E810 device. 1897 */ 1898 static int 1899 ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) 1900 { 1901 u32 lo_addr, hi_addr, lo, hi; 1902 int err; 1903 1904 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); 1905 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); 1906 1907 err = ice_read_phy_reg_e810(hw, lo_addr, &lo); 1908 if (err) { 1909 ice_debug(hw, ICE_DBG_PTP, "Failed to read low PTP timestamp register, err %d\n", 1910 err); 1911 return err; 1912 } 1913 1914 err = ice_read_phy_reg_e810(hw, hi_addr, &hi); 1915 if (err) { 1916 ice_debug(hw, ICE_DBG_PTP, "Failed to read high PTP timestamp register, err %d\n", 1917 err); 1918 return err; 1919 } 1920 1921 /* For E810 devices, the timestamp is reported with the lower 32 bits 1922 * in the low register, and the upper 8 bits in the high register. 1923 */ 1924 *tstamp = ((u64)hi) << TS_HIGH_S | ((u64)lo & TS_LOW_M); 1925 1926 return 0; 1927 } 1928 1929 /** 1930 * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY 1931 * @hw: pointer to the HW struct 1932 * @lport: the lport to read from 1933 * @idx: the timestamp index to reset 1934 * 1935 * Clear a timestamp, resetting its valid bit, from the timestamp block of the 1936 * external PHY on the E810 device. 1937 */ 1938 static int ice_clear_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx) 1939 { 1940 u32 lo_addr, hi_addr; 1941 int err; 1942 1943 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx); 1944 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx); 1945 1946 err = ice_write_phy_reg_e810(hw, lo_addr, 0); 1947 if (err) { 1948 ice_debug(hw, ICE_DBG_PTP, "Failed to clear low PTP timestamp register, err %d\n", 1949 err); 1950 return err; 1951 } 1952 1953 err = ice_write_phy_reg_e810(hw, hi_addr, 0); 1954 if (err) { 1955 ice_debug(hw, ICE_DBG_PTP, "Failed to clear high PTP timestamp register, err %d\n", 1956 err); 1957 return err; 1958 } 1959 1960 return 0; 1961 } 1962 1963 /** 1964 * ice_ptp_init_phy_e810 - Enable PTP function on the external PHY 1965 * @hw: pointer to HW struct 1966 * 1967 * Enable the timesync PTP functionality for the external PHY connected to 1968 * this function. 1969 */ 1970 int ice_ptp_init_phy_e810(struct ice_hw *hw) 1971 { 1972 u8 tmr_idx; 1973 int err; 1974 1975 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 1976 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_ENA(tmr_idx), 1977 GLTSYN_ENA_TSYN_ENA_M); 1978 if (err) 1979 ice_debug(hw, ICE_DBG_PTP, "PTP failed in ena_phy_time_syn %d\n", 1980 err); 1981 1982 return err; 1983 } 1984 1985 /** 1986 * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization 1987 * @hw: pointer to HW struct 1988 * 1989 * Perform E810-specific PTP hardware clock initialization steps. 1990 */ 1991 static int ice_ptp_init_phc_e810(struct ice_hw *hw) 1992 { 1993 /* Ensure synchronization delay is zero */ 1994 wr32(hw, GLTSYN_SYNC_DLAY, 0); 1995 1996 /* Initialize the PHY */ 1997 return ice_ptp_init_phy_e810(hw); 1998 } 1999 2000 /** 2001 * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time 2002 * @hw: Board private structure 2003 * @time: Time to initialize the PHY port clock to 2004 * 2005 * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the 2006 * initial clock time. The time will not actually be programmed until the 2007 * driver issues an INIT_TIME command. 2008 * 2009 * The time value is the upper 32 bits of the PHY timer, usually in units of 2010 * nominal nanoseconds. 2011 */ 2012 static int ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time) 2013 { 2014 u8 tmr_idx; 2015 int err; 2016 2017 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 2018 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_0(tmr_idx), 0); 2019 if (err) { 2020 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_0, err %d\n", 2021 err); 2022 return err; 2023 } 2024 2025 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHTIME_L(tmr_idx), time); 2026 if (err) { 2027 ice_debug(hw, ICE_DBG_PTP, "Failed to write SHTIME_L, err %d\n", 2028 err); 2029 return err; 2030 } 2031 2032 return 0; 2033 } 2034 2035 /** 2036 * ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment 2037 * @hw: pointer to HW struct 2038 * @adj: adjustment value to program 2039 * 2040 * Prepare the PHY port for an atomic adjustment by programming the PHY 2041 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual adjustment 2042 * is completed by issuing an ADJ_TIME sync command. 2043 * 2044 * The adjustment value only contains the portion used for the upper 32bits of 2045 * the PHY timer, usually in units of nominal nanoseconds. Negative 2046 * adjustments are supported using 2s complement arithmetic. 2047 */ 2048 static int ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj) 2049 { 2050 u8 tmr_idx; 2051 int err; 2052 2053 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 2054 2055 /* Adjustments are represented as signed 2's complement values in 2056 * nanoseconds. Sub-nanosecond adjustment is not supported. 2057 */ 2058 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), 0); 2059 if (err) { 2060 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_L, err %d\n", 2061 err); 2062 return err; 2063 } 2064 2065 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), adj); 2066 if (err) { 2067 ice_debug(hw, ICE_DBG_PTP, "Failed to write adj to PHY SHADJ_H, err %d\n", 2068 err); 2069 return err; 2070 } 2071 2072 return 0; 2073 } 2074 2075 /** 2076 * ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change 2077 * @hw: pointer to HW struct 2078 * @incval: The new 40bit increment value to prepare 2079 * 2080 * Prepare the PHY port for a new increment value by programming the PHY 2081 * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual change is 2082 * completed by issuing an INIT_INCVAL command. 2083 */ 2084 static int ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval) 2085 { 2086 u32 high, low; 2087 u8 tmr_idx; 2088 int err; 2089 2090 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 2091 low = lower_32_bits(incval); 2092 high = upper_32_bits(incval); 2093 2094 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_L(tmr_idx), low); 2095 if (err) { 2096 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval to PHY SHADJ_L, err %d\n", 2097 err); 2098 return err; 2099 } 2100 2101 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_SHADJ_H(tmr_idx), high); 2102 if (err) { 2103 ice_debug(hw, ICE_DBG_PTP, "Failed to write incval PHY SHADJ_H, err %d\n", 2104 err); 2105 return err; 2106 } 2107 2108 return 0; 2109 } 2110 2111 /** 2112 * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command 2113 * @hw: pointer to HW struct 2114 * @cmd: Command to be sent to the port 2115 * 2116 * Prepare the external PHYs connected to this device for a timer sync 2117 * command. 2118 */ 2119 static int ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 2120 { 2121 u32 cmd_val, val; 2122 int err; 2123 2124 switch (cmd) { 2125 case INIT_TIME: 2126 cmd_val = GLTSYN_CMD_INIT_TIME; 2127 break; 2128 case INIT_INCVAL: 2129 cmd_val = GLTSYN_CMD_INIT_INCVAL; 2130 break; 2131 case ADJ_TIME: 2132 cmd_val = GLTSYN_CMD_ADJ_TIME; 2133 break; 2134 case READ_TIME: 2135 cmd_val = GLTSYN_CMD_READ_TIME; 2136 break; 2137 case ADJ_TIME_AT_TIME: 2138 cmd_val = GLTSYN_CMD_ADJ_INIT_TIME; 2139 break; 2140 } 2141 2142 /* Read, modify, write */ 2143 err = ice_read_phy_reg_e810(hw, ETH_GLTSYN_CMD, &val); 2144 if (err) { 2145 ice_debug(hw, ICE_DBG_PTP, "Failed to read GLTSYN_CMD, err %d\n", err); 2146 return err; 2147 } 2148 2149 /* Modify necessary bits only and perform write */ 2150 val &= ~TS_CMD_MASK_E810; 2151 val |= cmd_val; 2152 2153 err = ice_write_phy_reg_e810(hw, ETH_GLTSYN_CMD, val); 2154 if (err) { 2155 ice_debug(hw, ICE_DBG_PTP, "Failed to write back GLTSYN_CMD, err %d\n", err); 2156 return err; 2157 } 2158 2159 return 0; 2160 } 2161 2162 /* Device agnostic functions 2163 * 2164 * The following functions implement shared behavior common to both E822 and 2165 * E810 devices, possibly calling a device specific implementation where 2166 * necessary. 2167 */ 2168 2169 /** 2170 * ice_ptp_lock - Acquire PTP global semaphore register lock 2171 * @hw: pointer to the HW struct 2172 * 2173 * Acquire the global PTP hardware semaphore lock. Returns true if the lock 2174 * was acquired, false otherwise. 2175 * 2176 * The PFTSYN_SEM register sets the busy bit on read, returning the previous 2177 * value. If software sees the busy bit cleared, this means that this function 2178 * acquired the lock (and the busy bit is now set). If software sees the busy 2179 * bit set, it means that another function acquired the lock. 2180 * 2181 * Software must clear the busy bit with a write to release the lock for other 2182 * functions when done. 2183 */ 2184 bool ice_ptp_lock(struct ice_hw *hw) 2185 { 2186 u32 hw_lock; 2187 int i; 2188 2189 #define MAX_TRIES 5 2190 2191 for (i = 0; i < MAX_TRIES; i++) { 2192 hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id)); 2193 hw_lock = hw_lock & PFTSYN_SEM_BUSY_M; 2194 if (!hw_lock) 2195 break; 2196 2197 /* Somebody is holding the lock */ 2198 usleep_range(10000, 20000); 2199 } 2200 2201 return !hw_lock; 2202 } 2203 2204 /** 2205 * ice_ptp_unlock - Release PTP global semaphore register lock 2206 * @hw: pointer to the HW struct 2207 * 2208 * Release the global PTP hardware semaphore lock. This is done by writing to 2209 * the PFTSYN_SEM register. 2210 */ 2211 void ice_ptp_unlock(struct ice_hw *hw) 2212 { 2213 wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0); 2214 } 2215 2216 /** 2217 * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command 2218 * @hw: pointer to HW struct 2219 * @cmd: the command to issue 2220 * 2221 * Prepare the source timer and PHY timers and then trigger the requested 2222 * command. This causes the shadow registers previously written in preparation 2223 * for the command to be synchronously applied to both the source and PHY 2224 * timers. 2225 */ 2226 static int ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd) 2227 { 2228 int err; 2229 2230 /* First, prepare the source timer */ 2231 ice_ptp_src_cmd(hw, cmd); 2232 2233 /* Next, prepare the ports */ 2234 if (ice_is_e810(hw)) 2235 err = ice_ptp_port_cmd_e810(hw, cmd); 2236 else 2237 err = ice_ptp_port_cmd_e822(hw, cmd); 2238 if (err) { 2239 ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for timer command %u, err %d\n", 2240 cmd, err); 2241 return err; 2242 } 2243 2244 /* Write the sync command register to drive both source and PHY timer 2245 * commands synchronously 2246 */ 2247 ice_ptp_exec_tmr_cmd(hw); 2248 2249 return 0; 2250 } 2251 2252 /** 2253 * ice_ptp_init_time - Initialize device time to provided value 2254 * @hw: pointer to HW struct 2255 * @time: 64bits of time (GLTSYN_TIME_L and GLTSYN_TIME_H) 2256 * 2257 * Initialize the device to the specified time provided. This requires a three 2258 * step process: 2259 * 2260 * 1) write the new init time to the source timer shadow registers 2261 * 2) write the new init time to the PHY timer shadow registers 2262 * 3) issue an init_time timer command to synchronously switch both the source 2263 * and port timers to the new init time value at the next clock cycle. 2264 */ 2265 int ice_ptp_init_time(struct ice_hw *hw, u64 time) 2266 { 2267 u8 tmr_idx; 2268 int err; 2269 2270 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 2271 2272 /* Source timers */ 2273 wr32(hw, GLTSYN_SHTIME_L(tmr_idx), lower_32_bits(time)); 2274 wr32(hw, GLTSYN_SHTIME_H(tmr_idx), upper_32_bits(time)); 2275 wr32(hw, GLTSYN_SHTIME_0(tmr_idx), 0); 2276 2277 /* PHY timers */ 2278 /* Fill Rx and Tx ports and send msg to PHY */ 2279 if (ice_is_e810(hw)) 2280 err = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF); 2281 else 2282 err = ice_ptp_prep_phy_time_e822(hw, time & 0xFFFFFFFF); 2283 if (err) 2284 return err; 2285 2286 return ice_ptp_tmr_cmd(hw, INIT_TIME); 2287 } 2288 2289 /** 2290 * ice_ptp_write_incval - Program PHC with new increment value 2291 * @hw: pointer to HW struct 2292 * @incval: Source timer increment value per clock cycle 2293 * 2294 * Program the PHC with a new increment value. This requires a three-step 2295 * process: 2296 * 2297 * 1) Write the increment value to the source timer shadow registers 2298 * 2) Write the increment value to the PHY timer shadow registers 2299 * 3) Issue an INIT_INCVAL timer command to synchronously switch both the 2300 * source and port timers to the new increment value at the next clock 2301 * cycle. 2302 */ 2303 int ice_ptp_write_incval(struct ice_hw *hw, u64 incval) 2304 { 2305 u8 tmr_idx; 2306 int err; 2307 2308 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 2309 2310 /* Shadow Adjust */ 2311 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), lower_32_bits(incval)); 2312 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), upper_32_bits(incval)); 2313 2314 if (ice_is_e810(hw)) 2315 err = ice_ptp_prep_phy_incval_e810(hw, incval); 2316 else 2317 err = ice_ptp_prep_phy_incval_e822(hw, incval); 2318 if (err) 2319 return err; 2320 2321 return ice_ptp_tmr_cmd(hw, INIT_INCVAL); 2322 } 2323 2324 /** 2325 * ice_ptp_write_incval_locked - Program new incval while holding semaphore 2326 * @hw: pointer to HW struct 2327 * @incval: Source timer increment value per clock cycle 2328 * 2329 * Program a new PHC incval while holding the PTP semaphore. 2330 */ 2331 int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval) 2332 { 2333 int err; 2334 2335 if (!ice_ptp_lock(hw)) 2336 return -EBUSY; 2337 2338 err = ice_ptp_write_incval(hw, incval); 2339 2340 ice_ptp_unlock(hw); 2341 2342 return err; 2343 } 2344 2345 /** 2346 * ice_ptp_adj_clock - Adjust PHC clock time atomically 2347 * @hw: pointer to HW struct 2348 * @adj: Adjustment in nanoseconds 2349 * 2350 * Perform an atomic adjustment of the PHC time by the specified number of 2351 * nanoseconds. This requires a three-step process: 2352 * 2353 * 1) Write the adjustment to the source timer shadow registers 2354 * 2) Write the adjustment to the PHY timer shadow registers 2355 * 3) Issue an ADJ_TIME timer command to synchronously apply the adjustment to 2356 * both the source and port timers at the next clock cycle. 2357 */ 2358 int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj) 2359 { 2360 u8 tmr_idx; 2361 int err; 2362 2363 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 2364 2365 /* Write the desired clock adjustment into the GLTSYN_SHADJ register. 2366 * For an ADJ_TIME command, this set of registers represents the value 2367 * to add to the clock time. It supports subtraction by interpreting 2368 * the value as a 2's complement integer. 2369 */ 2370 wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0); 2371 wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj); 2372 2373 if (ice_is_e810(hw)) 2374 err = ice_ptp_prep_phy_adj_e810(hw, adj); 2375 else 2376 err = ice_ptp_prep_phy_adj_e822(hw, adj); 2377 if (err) 2378 return err; 2379 2380 return ice_ptp_tmr_cmd(hw, ADJ_TIME); 2381 } 2382 2383 /** 2384 * ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block 2385 * @hw: pointer to the HW struct 2386 * @block: the block to read from 2387 * @idx: the timestamp index to read 2388 * @tstamp: on return, the 40bit timestamp value 2389 * 2390 * Read a 40bit timestamp value out of the timestamp block. For E822 devices, 2391 * the block is the quad to read from. For E810 devices, the block is the 2392 * logical port to read from. 2393 */ 2394 int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp) 2395 { 2396 if (ice_is_e810(hw)) 2397 return ice_read_phy_tstamp_e810(hw, block, idx, tstamp); 2398 else 2399 return ice_read_phy_tstamp_e822(hw, block, idx, tstamp); 2400 } 2401 2402 /** 2403 * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block 2404 * @hw: pointer to the HW struct 2405 * @block: the block to read from 2406 * @idx: the timestamp index to reset 2407 * 2408 * Clear a timestamp, resetting its valid bit, from the timestamp block. For 2409 * E822 devices, the block is the quad to clear from. For E810 devices, the 2410 * block is the logical port to clear from. 2411 */ 2412 int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx) 2413 { 2414 if (ice_is_e810(hw)) 2415 return ice_clear_phy_tstamp_e810(hw, block, idx); 2416 else 2417 return ice_clear_phy_tstamp_e822(hw, block, idx); 2418 } 2419 2420 /* E810T SMA functions 2421 * 2422 * The following functions operate specifically on E810T hardware and are used 2423 * to access the extended GPIOs available. 2424 */ 2425 2426 /** 2427 * ice_get_pca9575_handle 2428 * @hw: pointer to the hw struct 2429 * @pca9575_handle: GPIO controller's handle 2430 * 2431 * Find and return the GPIO controller's handle in the netlist. 2432 * When found - the value will be cached in the hw structure and following calls 2433 * will return cached value 2434 */ 2435 static int 2436 ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle) 2437 { 2438 struct ice_aqc_get_link_topo *cmd; 2439 struct ice_aq_desc desc; 2440 int status; 2441 u8 idx; 2442 2443 /* If handle was read previously return cached value */ 2444 if (hw->io_expander_handle) { 2445 *pca9575_handle = hw->io_expander_handle; 2446 return 0; 2447 } 2448 2449 /* If handle was not detected read it from the netlist */ 2450 cmd = &desc.params.get_link_topo; 2451 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo); 2452 2453 /* Set node type to GPIO controller */ 2454 cmd->addr.topo_params.node_type_ctx = 2455 (ICE_AQC_LINK_TOPO_NODE_TYPE_M & 2456 ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL); 2457 2458 #define SW_PCA9575_SFP_TOPO_IDX 2 2459 #define SW_PCA9575_QSFP_TOPO_IDX 1 2460 2461 /* Check if the SW IO expander controlling SMA exists in the netlist. */ 2462 if (hw->device_id == ICE_DEV_ID_E810C_SFP) 2463 idx = SW_PCA9575_SFP_TOPO_IDX; 2464 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP) 2465 idx = SW_PCA9575_QSFP_TOPO_IDX; 2466 else 2467 return -EOPNOTSUPP; 2468 2469 cmd->addr.topo_params.index = idx; 2470 2471 status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL); 2472 if (status) 2473 return -EOPNOTSUPP; 2474 2475 /* Verify if we found the right IO expander type */ 2476 if (desc.params.get_link_topo.node_part_num != 2477 ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575) 2478 return -EOPNOTSUPP; 2479 2480 /* If present save the handle and return it */ 2481 hw->io_expander_handle = 2482 le16_to_cpu(desc.params.get_link_topo.addr.handle); 2483 *pca9575_handle = hw->io_expander_handle; 2484 2485 return 0; 2486 } 2487 2488 /** 2489 * ice_read_sma_ctrl_e810t 2490 * @hw: pointer to the hw struct 2491 * @data: pointer to data to be read from the GPIO controller 2492 * 2493 * Read the SMA controller state. It is connected to pins 3-7 of Port 1 of the 2494 * PCA9575 expander, so only bits 3-7 in data are valid. 2495 */ 2496 int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data) 2497 { 2498 int status; 2499 u16 handle; 2500 u8 i; 2501 2502 status = ice_get_pca9575_handle(hw, &handle); 2503 if (status) 2504 return status; 2505 2506 *data = 0; 2507 2508 for (i = ICE_SMA_MIN_BIT_E810T; i <= ICE_SMA_MAX_BIT_E810T; i++) { 2509 bool pin; 2510 2511 status = ice_aq_get_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, 2512 &pin, NULL); 2513 if (status) 2514 break; 2515 *data |= (u8)(!pin) << i; 2516 } 2517 2518 return status; 2519 } 2520 2521 /** 2522 * ice_write_sma_ctrl_e810t 2523 * @hw: pointer to the hw struct 2524 * @data: data to be written to the GPIO controller 2525 * 2526 * Write the data to the SMA controller. It is connected to pins 3-7 of Port 1 2527 * of the PCA9575 expander, so only bits 3-7 in data are valid. 2528 */ 2529 int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data) 2530 { 2531 int status; 2532 u16 handle; 2533 u8 i; 2534 2535 status = ice_get_pca9575_handle(hw, &handle); 2536 if (status) 2537 return status; 2538 2539 for (i = ICE_SMA_MIN_BIT_E810T; i <= ICE_SMA_MAX_BIT_E810T; i++) { 2540 bool pin; 2541 2542 pin = !(data & (1 << i)); 2543 status = ice_aq_set_gpio(hw, handle, i + ICE_PCA9575_P1_OFFSET, 2544 pin, NULL); 2545 if (status) 2546 break; 2547 } 2548 2549 return status; 2550 } 2551 2552 /** 2553 * ice_is_pca9575_present 2554 * @hw: pointer to the hw struct 2555 * 2556 * Check if the SW IO expander is present in the netlist 2557 */ 2558 bool ice_is_pca9575_present(struct ice_hw *hw) 2559 { 2560 u16 handle = 0; 2561 int status; 2562 2563 if (!ice_is_e810t(hw)) 2564 return false; 2565 2566 status = ice_get_pca9575_handle(hw, &handle); 2567 2568 return !status && handle; 2569 } 2570 2571 /** 2572 * ice_ptp_init_phc - Initialize PTP hardware clock 2573 * @hw: pointer to the HW struct 2574 * 2575 * Perform the steps required to initialize the PTP hardware clock. 2576 */ 2577 int ice_ptp_init_phc(struct ice_hw *hw) 2578 { 2579 u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned; 2580 2581 /* Enable source clocks */ 2582 wr32(hw, GLTSYN_ENA(src_idx), GLTSYN_ENA_TSYN_ENA_M); 2583 2584 /* Clear event err indications for auxiliary pins */ 2585 (void)rd32(hw, GLTSYN_STAT(src_idx)); 2586 2587 if (ice_is_e810(hw)) 2588 return ice_ptp_init_phc_e810(hw); 2589 else 2590 return ice_ptp_init_phc_e822(hw); 2591 } 2592