1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2021, Intel Corporation. */
3 
4 #include "ice.h"
5 #include "ice_lib.h"
6 #include "ice_trace.h"
7 
8 #define E810_OUT_PROP_DELAY_NS 1
9 
10 #define UNKNOWN_INCVAL_E822 0x100000000ULL
11 
12 static const struct ptp_pin_desc ice_pin_desc_e810t[] = {
13 	/* name    idx   func         chan */
14 	{ "GNSS",  GNSS, PTP_PF_EXTTS, 0, { 0, } },
15 	{ "SMA1",  SMA1, PTP_PF_NONE, 1, { 0, } },
16 	{ "U.FL1", UFL1, PTP_PF_NONE, 1, { 0, } },
17 	{ "SMA2",  SMA2, PTP_PF_NONE, 2, { 0, } },
18 	{ "U.FL2", UFL2, PTP_PF_NONE, 2, { 0, } },
19 };
20 
21 /**
22  * ice_get_sma_config_e810t
23  * @hw: pointer to the hw struct
24  * @ptp_pins: pointer to the ptp_pin_desc struture
25  *
26  * Read the configuration of the SMA control logic and put it into the
27  * ptp_pin_desc structure
28  */
29 static int
30 ice_get_sma_config_e810t(struct ice_hw *hw, struct ptp_pin_desc *ptp_pins)
31 {
32 	u8 data, i;
33 	int status;
34 
35 	/* Read initial pin state */
36 	status = ice_read_sma_ctrl_e810t(hw, &data);
37 	if (status)
38 		return status;
39 
40 	/* initialize with defaults */
41 	for (i = 0; i < NUM_PTP_PINS_E810T; i++) {
42 		snprintf(ptp_pins[i].name, sizeof(ptp_pins[i].name),
43 			 "%s", ice_pin_desc_e810t[i].name);
44 		ptp_pins[i].index = ice_pin_desc_e810t[i].index;
45 		ptp_pins[i].func = ice_pin_desc_e810t[i].func;
46 		ptp_pins[i].chan = ice_pin_desc_e810t[i].chan;
47 	}
48 
49 	/* Parse SMA1/UFL1 */
50 	switch (data & ICE_SMA1_MASK_E810T) {
51 	case ICE_SMA1_MASK_E810T:
52 	default:
53 		ptp_pins[SMA1].func = PTP_PF_NONE;
54 		ptp_pins[UFL1].func = PTP_PF_NONE;
55 		break;
56 	case ICE_SMA1_DIR_EN_E810T:
57 		ptp_pins[SMA1].func = PTP_PF_PEROUT;
58 		ptp_pins[UFL1].func = PTP_PF_NONE;
59 		break;
60 	case ICE_SMA1_TX_EN_E810T:
61 		ptp_pins[SMA1].func = PTP_PF_EXTTS;
62 		ptp_pins[UFL1].func = PTP_PF_NONE;
63 		break;
64 	case 0:
65 		ptp_pins[SMA1].func = PTP_PF_EXTTS;
66 		ptp_pins[UFL1].func = PTP_PF_PEROUT;
67 		break;
68 	}
69 
70 	/* Parse SMA2/UFL2 */
71 	switch (data & ICE_SMA2_MASK_E810T) {
72 	case ICE_SMA2_MASK_E810T:
73 	default:
74 		ptp_pins[SMA2].func = PTP_PF_NONE;
75 		ptp_pins[UFL2].func = PTP_PF_NONE;
76 		break;
77 	case (ICE_SMA2_TX_EN_E810T | ICE_SMA2_UFL2_RX_DIS_E810T):
78 		ptp_pins[SMA2].func = PTP_PF_EXTTS;
79 		ptp_pins[UFL2].func = PTP_PF_NONE;
80 		break;
81 	case (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_UFL2_RX_DIS_E810T):
82 		ptp_pins[SMA2].func = PTP_PF_PEROUT;
83 		ptp_pins[UFL2].func = PTP_PF_NONE;
84 		break;
85 	case (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_TX_EN_E810T):
86 		ptp_pins[SMA2].func = PTP_PF_NONE;
87 		ptp_pins[UFL2].func = PTP_PF_EXTTS;
88 		break;
89 	case ICE_SMA2_DIR_EN_E810T:
90 		ptp_pins[SMA2].func = PTP_PF_PEROUT;
91 		ptp_pins[UFL2].func = PTP_PF_EXTTS;
92 		break;
93 	}
94 
95 	return 0;
96 }
97 
98 /**
99  * ice_ptp_set_sma_config_e810t
100  * @hw: pointer to the hw struct
101  * @ptp_pins: pointer to the ptp_pin_desc struture
102  *
103  * Set the configuration of the SMA control logic based on the configuration in
104  * num_pins parameter
105  */
106 static int
107 ice_ptp_set_sma_config_e810t(struct ice_hw *hw,
108 			     const struct ptp_pin_desc *ptp_pins)
109 {
110 	int status;
111 	u8 data;
112 
113 	/* SMA1 and UFL1 cannot be set to TX at the same time */
114 	if (ptp_pins[SMA1].func == PTP_PF_PEROUT &&
115 	    ptp_pins[UFL1].func == PTP_PF_PEROUT)
116 		return -EINVAL;
117 
118 	/* SMA2 and UFL2 cannot be set to RX at the same time */
119 	if (ptp_pins[SMA2].func == PTP_PF_EXTTS &&
120 	    ptp_pins[UFL2].func == PTP_PF_EXTTS)
121 		return -EINVAL;
122 
123 	/* Read initial pin state value */
124 	status = ice_read_sma_ctrl_e810t(hw, &data);
125 	if (status)
126 		return status;
127 
128 	/* Set the right sate based on the desired configuration */
129 	data &= ~ICE_SMA1_MASK_E810T;
130 	if (ptp_pins[SMA1].func == PTP_PF_NONE &&
131 	    ptp_pins[UFL1].func == PTP_PF_NONE) {
132 		dev_info(ice_hw_to_dev(hw), "SMA1 + U.FL1 disabled");
133 		data |= ICE_SMA1_MASK_E810T;
134 	} else if (ptp_pins[SMA1].func == PTP_PF_EXTTS &&
135 		   ptp_pins[UFL1].func == PTP_PF_NONE) {
136 		dev_info(ice_hw_to_dev(hw), "SMA1 RX");
137 		data |= ICE_SMA1_TX_EN_E810T;
138 	} else if (ptp_pins[SMA1].func == PTP_PF_NONE &&
139 		   ptp_pins[UFL1].func == PTP_PF_PEROUT) {
140 		/* U.FL 1 TX will always enable SMA 1 RX */
141 		dev_info(ice_hw_to_dev(hw), "SMA1 RX + U.FL1 TX");
142 	} else if (ptp_pins[SMA1].func == PTP_PF_EXTTS &&
143 		   ptp_pins[UFL1].func == PTP_PF_PEROUT) {
144 		dev_info(ice_hw_to_dev(hw), "SMA1 RX + U.FL1 TX");
145 	} else if (ptp_pins[SMA1].func == PTP_PF_PEROUT &&
146 		   ptp_pins[UFL1].func == PTP_PF_NONE) {
147 		dev_info(ice_hw_to_dev(hw), "SMA1 TX");
148 		data |= ICE_SMA1_DIR_EN_E810T;
149 	}
150 
151 	data &= ~ICE_SMA2_MASK_E810T;
152 	if (ptp_pins[SMA2].func == PTP_PF_NONE &&
153 	    ptp_pins[UFL2].func == PTP_PF_NONE) {
154 		dev_info(ice_hw_to_dev(hw), "SMA2 + U.FL2 disabled");
155 		data |= ICE_SMA2_MASK_E810T;
156 	} else if (ptp_pins[SMA2].func == PTP_PF_EXTTS &&
157 			ptp_pins[UFL2].func == PTP_PF_NONE) {
158 		dev_info(ice_hw_to_dev(hw), "SMA2 RX");
159 		data |= (ICE_SMA2_TX_EN_E810T |
160 			 ICE_SMA2_UFL2_RX_DIS_E810T);
161 	} else if (ptp_pins[SMA2].func == PTP_PF_NONE &&
162 		   ptp_pins[UFL2].func == PTP_PF_EXTTS) {
163 		dev_info(ice_hw_to_dev(hw), "UFL2 RX");
164 		data |= (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_TX_EN_E810T);
165 	} else if (ptp_pins[SMA2].func == PTP_PF_PEROUT &&
166 		   ptp_pins[UFL2].func == PTP_PF_NONE) {
167 		dev_info(ice_hw_to_dev(hw), "SMA2 TX");
168 		data |= (ICE_SMA2_DIR_EN_E810T |
169 			 ICE_SMA2_UFL2_RX_DIS_E810T);
170 	} else if (ptp_pins[SMA2].func == PTP_PF_PEROUT &&
171 		   ptp_pins[UFL2].func == PTP_PF_EXTTS) {
172 		dev_info(ice_hw_to_dev(hw), "SMA2 TX + U.FL2 RX");
173 		data |= ICE_SMA2_DIR_EN_E810T;
174 	}
175 
176 	return ice_write_sma_ctrl_e810t(hw, data);
177 }
178 
179 /**
180  * ice_ptp_set_sma_e810t
181  * @info: the driver's PTP info structure
182  * @pin: pin index in kernel structure
183  * @func: Pin function to be set (PTP_PF_NONE, PTP_PF_EXTTS or PTP_PF_PEROUT)
184  *
185  * Set the configuration of a single SMA pin
186  */
187 static int
188 ice_ptp_set_sma_e810t(struct ptp_clock_info *info, unsigned int pin,
189 		      enum ptp_pin_function func)
190 {
191 	struct ptp_pin_desc ptp_pins[NUM_PTP_PINS_E810T];
192 	struct ice_pf *pf = ptp_info_to_pf(info);
193 	struct ice_hw *hw = &pf->hw;
194 	int err;
195 
196 	if (pin < SMA1 || func > PTP_PF_PEROUT)
197 		return -EOPNOTSUPP;
198 
199 	err = ice_get_sma_config_e810t(hw, ptp_pins);
200 	if (err)
201 		return err;
202 
203 	/* Disable the same function on the other pin sharing the channel */
204 	if (pin == SMA1 && ptp_pins[UFL1].func == func)
205 		ptp_pins[UFL1].func = PTP_PF_NONE;
206 	if (pin == UFL1 && ptp_pins[SMA1].func == func)
207 		ptp_pins[SMA1].func = PTP_PF_NONE;
208 
209 	if (pin == SMA2 && ptp_pins[UFL2].func == func)
210 		ptp_pins[UFL2].func = PTP_PF_NONE;
211 	if (pin == UFL2 && ptp_pins[SMA2].func == func)
212 		ptp_pins[SMA2].func = PTP_PF_NONE;
213 
214 	/* Set up new pin function in the temp table */
215 	ptp_pins[pin].func = func;
216 
217 	return ice_ptp_set_sma_config_e810t(hw, ptp_pins);
218 }
219 
220 /**
221  * ice_verify_pin_e810t
222  * @info: the driver's PTP info structure
223  * @pin: Pin index
224  * @func: Assigned function
225  * @chan: Assigned channel
226  *
227  * Verify if pin supports requested pin function. If the Check pins consistency.
228  * Reconfigure the SMA logic attached to the given pin to enable its
229  * desired functionality
230  */
231 static int
232 ice_verify_pin_e810t(struct ptp_clock_info *info, unsigned int pin,
233 		     enum ptp_pin_function func, unsigned int chan)
234 {
235 	/* Don't allow channel reassignment */
236 	if (chan != ice_pin_desc_e810t[pin].chan)
237 		return -EOPNOTSUPP;
238 
239 	/* Check if functions are properly assigned */
240 	switch (func) {
241 	case PTP_PF_NONE:
242 		break;
243 	case PTP_PF_EXTTS:
244 		if (pin == UFL1)
245 			return -EOPNOTSUPP;
246 		break;
247 	case PTP_PF_PEROUT:
248 		if (pin == UFL2 || pin == GNSS)
249 			return -EOPNOTSUPP;
250 		break;
251 	case PTP_PF_PHYSYNC:
252 		return -EOPNOTSUPP;
253 	}
254 
255 	return ice_ptp_set_sma_e810t(info, pin, func);
256 }
257 
258 /**
259  * ice_set_tx_tstamp - Enable or disable Tx timestamping
260  * @pf: The PF pointer to search in
261  * @on: bool value for whether timestamps are enabled or disabled
262  */
263 static void ice_set_tx_tstamp(struct ice_pf *pf, bool on)
264 {
265 	struct ice_vsi *vsi;
266 	u32 val;
267 	u16 i;
268 
269 	vsi = ice_get_main_vsi(pf);
270 	if (!vsi)
271 		return;
272 
273 	/* Set the timestamp enable flag for all the Tx rings */
274 	ice_for_each_txq(vsi, i) {
275 		if (!vsi->tx_rings[i])
276 			continue;
277 		vsi->tx_rings[i]->ptp_tx = on;
278 	}
279 
280 	/* Configure the Tx timestamp interrupt */
281 	val = rd32(&pf->hw, PFINT_OICR_ENA);
282 	if (on)
283 		val |= PFINT_OICR_TSYN_TX_M;
284 	else
285 		val &= ~PFINT_OICR_TSYN_TX_M;
286 	wr32(&pf->hw, PFINT_OICR_ENA, val);
287 
288 	pf->ptp.tstamp_config.tx_type = on ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
289 }
290 
291 /**
292  * ice_set_rx_tstamp - Enable or disable Rx timestamping
293  * @pf: The PF pointer to search in
294  * @on: bool value for whether timestamps are enabled or disabled
295  */
296 static void ice_set_rx_tstamp(struct ice_pf *pf, bool on)
297 {
298 	struct ice_vsi *vsi;
299 	u16 i;
300 
301 	vsi = ice_get_main_vsi(pf);
302 	if (!vsi)
303 		return;
304 
305 	/* Set the timestamp flag for all the Rx rings */
306 	ice_for_each_rxq(vsi, i) {
307 		if (!vsi->rx_rings[i])
308 			continue;
309 		vsi->rx_rings[i]->ptp_rx = on;
310 	}
311 
312 	pf->ptp.tstamp_config.rx_filter = on ? HWTSTAMP_FILTER_ALL :
313 					       HWTSTAMP_FILTER_NONE;
314 }
315 
316 /**
317  * ice_ptp_cfg_timestamp - Configure timestamp for init/deinit
318  * @pf: Board private structure
319  * @ena: bool value to enable or disable time stamp
320  *
321  * This function will configure timestamping during PTP initialization
322  * and deinitialization
323  */
324 void ice_ptp_cfg_timestamp(struct ice_pf *pf, bool ena)
325 {
326 	ice_set_tx_tstamp(pf, ena);
327 	ice_set_rx_tstamp(pf, ena);
328 }
329 
330 /**
331  * ice_get_ptp_clock_index - Get the PTP clock index
332  * @pf: the PF pointer
333  *
334  * Determine the clock index of the PTP clock associated with this device. If
335  * this is the PF controlling the clock, just use the local access to the
336  * clock device pointer.
337  *
338  * Otherwise, read from the driver shared parameters to determine the clock
339  * index value.
340  *
341  * Returns: the index of the PTP clock associated with this device, or -1 if
342  * there is no associated clock.
343  */
344 int ice_get_ptp_clock_index(struct ice_pf *pf)
345 {
346 	struct device *dev = ice_pf_to_dev(pf);
347 	enum ice_aqc_driver_params param_idx;
348 	struct ice_hw *hw = &pf->hw;
349 	u8 tmr_idx;
350 	u32 value;
351 	int err;
352 
353 	/* Use the ptp_clock structure if we're the main PF */
354 	if (pf->ptp.clock)
355 		return ptp_clock_index(pf->ptp.clock);
356 
357 	tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc;
358 	if (!tmr_idx)
359 		param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0;
360 	else
361 		param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1;
362 
363 	err = ice_aq_get_driver_param(hw, param_idx, &value, NULL);
364 	if (err) {
365 		dev_err(dev, "Failed to read PTP clock index parameter, err %d aq_err %s\n",
366 			err, ice_aq_str(hw->adminq.sq_last_status));
367 		return -1;
368 	}
369 
370 	/* The PTP clock index is an integer, and will be between 0 and
371 	 * INT_MAX. The highest bit of the driver shared parameter is used to
372 	 * indicate whether or not the currently stored clock index is valid.
373 	 */
374 	if (!(value & PTP_SHARED_CLK_IDX_VALID))
375 		return -1;
376 
377 	return value & ~PTP_SHARED_CLK_IDX_VALID;
378 }
379 
380 /**
381  * ice_set_ptp_clock_index - Set the PTP clock index
382  * @pf: the PF pointer
383  *
384  * Set the PTP clock index for this device into the shared driver parameters,
385  * so that other PFs associated with this device can read it.
386  *
387  * If the PF is unable to store the clock index, it will log an error, but
388  * will continue operating PTP.
389  */
390 static void ice_set_ptp_clock_index(struct ice_pf *pf)
391 {
392 	struct device *dev = ice_pf_to_dev(pf);
393 	enum ice_aqc_driver_params param_idx;
394 	struct ice_hw *hw = &pf->hw;
395 	u8 tmr_idx;
396 	u32 value;
397 	int err;
398 
399 	if (!pf->ptp.clock)
400 		return;
401 
402 	tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc;
403 	if (!tmr_idx)
404 		param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0;
405 	else
406 		param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1;
407 
408 	value = (u32)ptp_clock_index(pf->ptp.clock);
409 	if (value > INT_MAX) {
410 		dev_err(dev, "PTP Clock index is too large to store\n");
411 		return;
412 	}
413 	value |= PTP_SHARED_CLK_IDX_VALID;
414 
415 	err = ice_aq_set_driver_param(hw, param_idx, value, NULL);
416 	if (err) {
417 		dev_err(dev, "Failed to set PTP clock index parameter, err %d aq_err %s\n",
418 			err, ice_aq_str(hw->adminq.sq_last_status));
419 	}
420 }
421 
422 /**
423  * ice_clear_ptp_clock_index - Clear the PTP clock index
424  * @pf: the PF pointer
425  *
426  * Clear the PTP clock index for this device. Must be called when
427  * unregistering the PTP clock, in order to ensure other PFs stop reporting
428  * a clock object that no longer exists.
429  */
430 static void ice_clear_ptp_clock_index(struct ice_pf *pf)
431 {
432 	struct device *dev = ice_pf_to_dev(pf);
433 	enum ice_aqc_driver_params param_idx;
434 	struct ice_hw *hw = &pf->hw;
435 	u8 tmr_idx;
436 	int err;
437 
438 	/* Do not clear the index if we don't own the timer */
439 	if (!hw->func_caps.ts_func_info.src_tmr_owned)
440 		return;
441 
442 	tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc;
443 	if (!tmr_idx)
444 		param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0;
445 	else
446 		param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1;
447 
448 	err = ice_aq_set_driver_param(hw, param_idx, 0, NULL);
449 	if (err) {
450 		dev_dbg(dev, "Failed to clear PTP clock index parameter, err %d aq_err %s\n",
451 			err, ice_aq_str(hw->adminq.sq_last_status));
452 	}
453 }
454 
455 /**
456  * ice_ptp_read_src_clk_reg - Read the source clock register
457  * @pf: Board private structure
458  * @sts: Optional parameter for holding a pair of system timestamps from
459  *       the system clock. Will be ignored if NULL is given.
460  */
461 static u64
462 ice_ptp_read_src_clk_reg(struct ice_pf *pf, struct ptp_system_timestamp *sts)
463 {
464 	struct ice_hw *hw = &pf->hw;
465 	u32 hi, lo, lo2;
466 	u8 tmr_idx;
467 
468 	tmr_idx = ice_get_ptp_src_clock_index(hw);
469 	/* Read the system timestamp pre PHC read */
470 	ptp_read_system_prets(sts);
471 
472 	lo = rd32(hw, GLTSYN_TIME_L(tmr_idx));
473 
474 	/* Read the system timestamp post PHC read */
475 	ptp_read_system_postts(sts);
476 
477 	hi = rd32(hw, GLTSYN_TIME_H(tmr_idx));
478 	lo2 = rd32(hw, GLTSYN_TIME_L(tmr_idx));
479 
480 	if (lo2 < lo) {
481 		/* if TIME_L rolled over read TIME_L again and update
482 		 * system timestamps
483 		 */
484 		ptp_read_system_prets(sts);
485 		lo = rd32(hw, GLTSYN_TIME_L(tmr_idx));
486 		ptp_read_system_postts(sts);
487 		hi = rd32(hw, GLTSYN_TIME_H(tmr_idx));
488 	}
489 
490 	return ((u64)hi << 32) | lo;
491 }
492 
493 /**
494  * ice_ptp_extend_32b_ts - Convert a 32b nanoseconds timestamp to 64b
495  * @cached_phc_time: recently cached copy of PHC time
496  * @in_tstamp: Ingress/egress 32b nanoseconds timestamp value
497  *
498  * Hardware captures timestamps which contain only 32 bits of nominal
499  * nanoseconds, as opposed to the 64bit timestamps that the stack expects.
500  * Note that the captured timestamp values may be 40 bits, but the lower
501  * 8 bits are sub-nanoseconds and generally discarded.
502  *
503  * Extend the 32bit nanosecond timestamp using the following algorithm and
504  * assumptions:
505  *
506  * 1) have a recently cached copy of the PHC time
507  * 2) assume that the in_tstamp was captured 2^31 nanoseconds (~2.1
508  *    seconds) before or after the PHC time was captured.
509  * 3) calculate the delta between the cached time and the timestamp
510  * 4) if the delta is smaller than 2^31 nanoseconds, then the timestamp was
511  *    captured after the PHC time. In this case, the full timestamp is just
512  *    the cached PHC time plus the delta.
513  * 5) otherwise, if the delta is larger than 2^31 nanoseconds, then the
514  *    timestamp was captured *before* the PHC time, i.e. because the PHC
515  *    cache was updated after the timestamp was captured by hardware. In this
516  *    case, the full timestamp is the cached time minus the inverse delta.
517  *
518  * This algorithm works even if the PHC time was updated after a Tx timestamp
519  * was requested, but before the Tx timestamp event was reported from
520  * hardware.
521  *
522  * This calculation primarily relies on keeping the cached PHC time up to
523  * date. If the timestamp was captured more than 2^31 nanoseconds after the
524  * PHC time, it is possible that the lower 32bits of PHC time have
525  * overflowed more than once, and we might generate an incorrect timestamp.
526  *
527  * This is prevented by (a) periodically updating the cached PHC time once
528  * a second, and (b) discarding any Tx timestamp packet if it has waited for
529  * a timestamp for more than one second.
530  */
531 static u64 ice_ptp_extend_32b_ts(u64 cached_phc_time, u32 in_tstamp)
532 {
533 	u32 delta, phc_time_lo;
534 	u64 ns;
535 
536 	/* Extract the lower 32 bits of the PHC time */
537 	phc_time_lo = (u32)cached_phc_time;
538 
539 	/* Calculate the delta between the lower 32bits of the cached PHC
540 	 * time and the in_tstamp value
541 	 */
542 	delta = (in_tstamp - phc_time_lo);
543 
544 	/* Do not assume that the in_tstamp is always more recent than the
545 	 * cached PHC time. If the delta is large, it indicates that the
546 	 * in_tstamp was taken in the past, and should be converted
547 	 * forward.
548 	 */
549 	if (delta > (U32_MAX / 2)) {
550 		/* reverse the delta calculation here */
551 		delta = (phc_time_lo - in_tstamp);
552 		ns = cached_phc_time - delta;
553 	} else {
554 		ns = cached_phc_time + delta;
555 	}
556 
557 	return ns;
558 }
559 
560 /**
561  * ice_ptp_extend_40b_ts - Convert a 40b timestamp to 64b nanoseconds
562  * @pf: Board private structure
563  * @in_tstamp: Ingress/egress 40b timestamp value
564  *
565  * The Tx and Rx timestamps are 40 bits wide, including 32 bits of nominal
566  * nanoseconds, 7 bits of sub-nanoseconds, and a valid bit.
567  *
568  *  *--------------------------------------------------------------*
569  *  | 32 bits of nanoseconds | 7 high bits of sub ns underflow | v |
570  *  *--------------------------------------------------------------*
571  *
572  * The low bit is an indicator of whether the timestamp is valid. The next
573  * 7 bits are a capture of the upper 7 bits of the sub-nanosecond underflow,
574  * and the remaining 32 bits are the lower 32 bits of the PHC timer.
575  *
576  * It is assumed that the caller verifies the timestamp is valid prior to
577  * calling this function.
578  *
579  * Extract the 32bit nominal nanoseconds and extend them. Use the cached PHC
580  * time stored in the device private PTP structure as the basis for timestamp
581  * extension.
582  *
583  * See ice_ptp_extend_32b_ts for a detailed explanation of the extension
584  * algorithm.
585  */
586 static u64 ice_ptp_extend_40b_ts(struct ice_pf *pf, u64 in_tstamp)
587 {
588 	const u64 mask = GENMASK_ULL(31, 0);
589 	unsigned long discard_time;
590 
591 	/* Discard the hardware timestamp if the cached PHC time is too old */
592 	discard_time = pf->ptp.cached_phc_jiffies + msecs_to_jiffies(2000);
593 	if (time_is_before_jiffies(discard_time)) {
594 		pf->ptp.tx_hwtstamp_discarded++;
595 		return 0;
596 	}
597 
598 	return ice_ptp_extend_32b_ts(pf->ptp.cached_phc_time,
599 				     (in_tstamp >> 8) & mask);
600 }
601 
602 /**
603  * ice_ptp_tx_tstamp - Process Tx timestamps for a port
604  * @tx: the PTP Tx timestamp tracker
605  *
606  * Process timestamps captured by the PHY associated with this port. To do
607  * this, loop over each index with a waiting skb.
608  *
609  * If a given index has a valid timestamp, perform the following steps:
610  *
611  * 1) copy the timestamp out of the PHY register
612  * 4) clear the timestamp valid bit in the PHY register
613  * 5) unlock the index by clearing the associated in_use bit.
614  * 2) extend the 40b timestamp value to get a 64bit timestamp
615  * 3) send that timestamp to the stack
616  *
617  * After looping, if we still have waiting SKBs, return true. This may cause us
618  * effectively poll even when not strictly necessary. We do this because it's
619  * possible a new timestamp was requested around the same time as the interrupt.
620  * In some cases hardware might not interrupt us again when the timestamp is
621  * captured.
622  *
623  * Note that we only take the tracking lock when clearing the bit and when
624  * checking if we need to re-queue this task. The only place where bits can be
625  * set is the hard xmit routine where an SKB has a request flag set. The only
626  * places where we clear bits are this work function, or the periodic cleanup
627  * thread. If the cleanup thread clears a bit we're processing we catch it
628  * when we lock to clear the bit and then grab the SKB pointer. If a Tx thread
629  * starts a new timestamp, we might not begin processing it right away but we
630  * will notice it at the end when we re-queue the task. If a Tx thread starts
631  * a new timestamp just after this function exits without re-queuing,
632  * the interrupt when the timestamp finishes should trigger. Avoiding holding
633  * the lock for the entire function is important in order to ensure that Tx
634  * threads do not get blocked while waiting for the lock.
635  */
636 static bool ice_ptp_tx_tstamp(struct ice_ptp_tx *tx)
637 {
638 	struct ice_ptp_port *ptp_port;
639 	bool ts_handled = true;
640 	struct ice_pf *pf;
641 	u8 idx;
642 
643 	if (!tx->init)
644 		return false;
645 
646 	ptp_port = container_of(tx, struct ice_ptp_port, tx);
647 	pf = ptp_port_to_pf(ptp_port);
648 
649 	for_each_set_bit(idx, tx->in_use, tx->len) {
650 		struct skb_shared_hwtstamps shhwtstamps = {};
651 		u8 phy_idx = idx + tx->quad_offset;
652 		u64 raw_tstamp, tstamp;
653 		struct sk_buff *skb;
654 		int err;
655 
656 		ice_trace(tx_tstamp_fw_req, tx->tstamps[idx].skb, idx);
657 
658 		err = ice_read_phy_tstamp(&pf->hw, tx->quad, phy_idx,
659 					  &raw_tstamp);
660 		if (err)
661 			continue;
662 
663 		ice_trace(tx_tstamp_fw_done, tx->tstamps[idx].skb, idx);
664 
665 		/* Check if the timestamp is invalid or stale */
666 		if (!(raw_tstamp & ICE_PTP_TS_VALID) ||
667 		    raw_tstamp == tx->tstamps[idx].cached_tstamp)
668 			continue;
669 
670 		/* The timestamp is valid, so we'll go ahead and clear this
671 		 * index and then send the timestamp up to the stack.
672 		 */
673 		spin_lock(&tx->lock);
674 		tx->tstamps[idx].cached_tstamp = raw_tstamp;
675 		clear_bit(idx, tx->in_use);
676 		skb = tx->tstamps[idx].skb;
677 		tx->tstamps[idx].skb = NULL;
678 		spin_unlock(&tx->lock);
679 
680 		/* it's (unlikely but) possible we raced with the cleanup
681 		 * thread for discarding old timestamp requests.
682 		 */
683 		if (!skb)
684 			continue;
685 
686 		/* Extend the timestamp using cached PHC time */
687 		tstamp = ice_ptp_extend_40b_ts(pf, raw_tstamp);
688 		if (tstamp) {
689 			shhwtstamps.hwtstamp = ns_to_ktime(tstamp);
690 			ice_trace(tx_tstamp_complete, skb, idx);
691 		}
692 
693 		skb_tstamp_tx(skb, &shhwtstamps);
694 		dev_kfree_skb_any(skb);
695 	}
696 
697 	/* Check if we still have work to do. If so, re-queue this task to
698 	 * poll for remaining timestamps.
699 	 */
700 	spin_lock(&tx->lock);
701 	if (!bitmap_empty(tx->in_use, tx->len))
702 		ts_handled = false;
703 	spin_unlock(&tx->lock);
704 
705 	return ts_handled;
706 }
707 
708 /**
709  * ice_ptp_alloc_tx_tracker - Initialize tracking for Tx timestamps
710  * @tx: Tx tracking structure to initialize
711  *
712  * Assumes that the length has already been initialized. Do not call directly,
713  * use the ice_ptp_init_tx_e822 or ice_ptp_init_tx_e810 instead.
714  */
715 static int
716 ice_ptp_alloc_tx_tracker(struct ice_ptp_tx *tx)
717 {
718 	tx->tstamps = kcalloc(tx->len, sizeof(*tx->tstamps), GFP_KERNEL);
719 	if (!tx->tstamps)
720 		return -ENOMEM;
721 
722 	tx->in_use = bitmap_zalloc(tx->len, GFP_KERNEL);
723 	if (!tx->in_use) {
724 		kfree(tx->tstamps);
725 		tx->tstamps = NULL;
726 		return -ENOMEM;
727 	}
728 
729 	spin_lock_init(&tx->lock);
730 
731 	tx->init = 1;
732 
733 	return 0;
734 }
735 
736 /**
737  * ice_ptp_flush_tx_tracker - Flush any remaining timestamps from the tracker
738  * @pf: Board private structure
739  * @tx: the tracker to flush
740  */
741 static void
742 ice_ptp_flush_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx)
743 {
744 	u8 idx;
745 
746 	for (idx = 0; idx < tx->len; idx++) {
747 		u8 phy_idx = idx + tx->quad_offset;
748 
749 		spin_lock(&tx->lock);
750 		if (tx->tstamps[idx].skb) {
751 			dev_kfree_skb_any(tx->tstamps[idx].skb);
752 			tx->tstamps[idx].skb = NULL;
753 			pf->ptp.tx_hwtstamp_flushed++;
754 		}
755 		clear_bit(idx, tx->in_use);
756 		spin_unlock(&tx->lock);
757 
758 		/* Clear any potential residual timestamp in the PHY block */
759 		if (!pf->hw.reset_ongoing)
760 			ice_clear_phy_tstamp(&pf->hw, tx->quad, phy_idx);
761 	}
762 }
763 
764 /**
765  * ice_ptp_release_tx_tracker - Release allocated memory for Tx tracker
766  * @pf: Board private structure
767  * @tx: Tx tracking structure to release
768  *
769  * Free memory associated with the Tx timestamp tracker.
770  */
771 static void
772 ice_ptp_release_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx)
773 {
774 	tx->init = 0;
775 
776 	ice_ptp_flush_tx_tracker(pf, tx);
777 
778 	kfree(tx->tstamps);
779 	tx->tstamps = NULL;
780 
781 	bitmap_free(tx->in_use);
782 	tx->in_use = NULL;
783 
784 	tx->len = 0;
785 }
786 
787 /**
788  * ice_ptp_init_tx_e822 - Initialize tracking for Tx timestamps
789  * @pf: Board private structure
790  * @tx: the Tx tracking structure to initialize
791  * @port: the port this structure tracks
792  *
793  * Initialize the Tx timestamp tracker for this port. For generic MAC devices,
794  * the timestamp block is shared for all ports in the same quad. To avoid
795  * ports using the same timestamp index, logically break the block of
796  * registers into chunks based on the port number.
797  */
798 static int
799 ice_ptp_init_tx_e822(struct ice_pf *pf, struct ice_ptp_tx *tx, u8 port)
800 {
801 	tx->quad = port / ICE_PORTS_PER_QUAD;
802 	tx->quad_offset = (port % ICE_PORTS_PER_QUAD) * INDEX_PER_PORT;
803 	tx->len = INDEX_PER_PORT;
804 
805 	return ice_ptp_alloc_tx_tracker(tx);
806 }
807 
808 /**
809  * ice_ptp_init_tx_e810 - Initialize tracking for Tx timestamps
810  * @pf: Board private structure
811  * @tx: the Tx tracking structure to initialize
812  *
813  * Initialize the Tx timestamp tracker for this PF. For E810 devices, each
814  * port has its own block of timestamps, independent of the other ports.
815  */
816 static int
817 ice_ptp_init_tx_e810(struct ice_pf *pf, struct ice_ptp_tx *tx)
818 {
819 	tx->quad = pf->hw.port_info->lport;
820 	tx->quad_offset = 0;
821 	tx->len = INDEX_PER_QUAD;
822 
823 	return ice_ptp_alloc_tx_tracker(tx);
824 }
825 
826 /**
827  * ice_ptp_tx_tstamp_cleanup - Cleanup old timestamp requests that got dropped
828  * @pf: pointer to the PF struct
829  * @tx: PTP Tx tracker to clean up
830  *
831  * Loop through the Tx timestamp requests and see if any of them have been
832  * waiting for a long time. Discard any SKBs that have been waiting for more
833  * than 2 seconds. This is long enough to be reasonably sure that the
834  * timestamp will never be captured. This might happen if the packet gets
835  * discarded before it reaches the PHY timestamping block.
836  */
837 static void ice_ptp_tx_tstamp_cleanup(struct ice_pf *pf, struct ice_ptp_tx *tx)
838 {
839 	struct ice_hw *hw = &pf->hw;
840 	u8 idx;
841 
842 	if (!tx->init)
843 		return;
844 
845 	for_each_set_bit(idx, tx->in_use, tx->len) {
846 		struct sk_buff *skb;
847 		u64 raw_tstamp;
848 
849 		/* Check if this SKB has been waiting for too long */
850 		if (time_is_after_jiffies(tx->tstamps[idx].start + 2 * HZ))
851 			continue;
852 
853 		/* Read tstamp to be able to use this register again */
854 		ice_read_phy_tstamp(hw, tx->quad, idx + tx->quad_offset,
855 				    &raw_tstamp);
856 
857 		spin_lock(&tx->lock);
858 		skb = tx->tstamps[idx].skb;
859 		tx->tstamps[idx].skb = NULL;
860 		clear_bit(idx, tx->in_use);
861 		spin_unlock(&tx->lock);
862 
863 		/* Count the number of Tx timestamps which have timed out */
864 		pf->ptp.tx_hwtstamp_timeouts++;
865 
866 		/* Free the SKB after we've cleared the bit */
867 		dev_kfree_skb_any(skb);
868 	}
869 }
870 
871 /**
872  * ice_ptp_update_cached_phctime - Update the cached PHC time values
873  * @pf: Board specific private structure
874  *
875  * This function updates the system time values which are cached in the PF
876  * structure and the Rx rings.
877  *
878  * This function must be called periodically to ensure that the cached value
879  * is never more than 2 seconds old.
880  *
881  * Note that the cached copy in the PF PTP structure is always updated, even
882  * if we can't update the copy in the Rx rings.
883  *
884  * Return:
885  * * 0 - OK, successfully updated
886  * * -EAGAIN - PF was busy, need to reschedule the update
887  */
888 static int ice_ptp_update_cached_phctime(struct ice_pf *pf)
889 {
890 	struct device *dev = ice_pf_to_dev(pf);
891 	unsigned long update_before;
892 	u64 systime;
893 	int i;
894 
895 	update_before = pf->ptp.cached_phc_jiffies + msecs_to_jiffies(2000);
896 	if (pf->ptp.cached_phc_time &&
897 	    time_is_before_jiffies(update_before)) {
898 		unsigned long time_taken = jiffies - pf->ptp.cached_phc_jiffies;
899 
900 		dev_warn(dev, "%u msecs passed between update to cached PHC time\n",
901 			 jiffies_to_msecs(time_taken));
902 		pf->ptp.late_cached_phc_updates++;
903 	}
904 
905 	/* Read the current PHC time */
906 	systime = ice_ptp_read_src_clk_reg(pf, NULL);
907 
908 	/* Update the cached PHC time stored in the PF structure */
909 	WRITE_ONCE(pf->ptp.cached_phc_time, systime);
910 	WRITE_ONCE(pf->ptp.cached_phc_jiffies, jiffies);
911 
912 	if (test_and_set_bit(ICE_CFG_BUSY, pf->state))
913 		return -EAGAIN;
914 
915 	ice_for_each_vsi(pf, i) {
916 		struct ice_vsi *vsi = pf->vsi[i];
917 		int j;
918 
919 		if (!vsi)
920 			continue;
921 
922 		if (vsi->type != ICE_VSI_PF)
923 			continue;
924 
925 		ice_for_each_rxq(vsi, j) {
926 			if (!vsi->rx_rings[j])
927 				continue;
928 			WRITE_ONCE(vsi->rx_rings[j]->cached_phctime, systime);
929 		}
930 	}
931 	clear_bit(ICE_CFG_BUSY, pf->state);
932 
933 	return 0;
934 }
935 
936 /**
937  * ice_ptp_reset_cached_phctime - Reset cached PHC time after an update
938  * @pf: Board specific private structure
939  *
940  * This function must be called when the cached PHC time is no longer valid,
941  * such as after a time adjustment. It discards any outstanding Tx timestamps,
942  * and updates the cached PHC time for both the PF and Rx rings. If updating
943  * the PHC time cannot be done immediately, a warning message is logged and
944  * the work item is scheduled.
945  *
946  * These steps are required in order to ensure that we do not accidentally
947  * report a timestamp extended by the wrong PHC cached copy. Note that we
948  * do not directly update the cached timestamp here because it is possible
949  * this might produce an error when ICE_CFG_BUSY is set. If this occurred, we
950  * would have to try again. During that time window, timestamps might be
951  * requested and returned with an invalid extension. Thus, on failure to
952  * immediately update the cached PHC time we would need to zero the value
953  * anyways. For this reason, we just zero the value immediately and queue the
954  * update work item.
955  */
956 static void ice_ptp_reset_cached_phctime(struct ice_pf *pf)
957 {
958 	struct device *dev = ice_pf_to_dev(pf);
959 	int err;
960 
961 	/* Update the cached PHC time immediately if possible, otherwise
962 	 * schedule the work item to execute soon.
963 	 */
964 	err = ice_ptp_update_cached_phctime(pf);
965 	if (err) {
966 		/* If another thread is updating the Rx rings, we won't
967 		 * properly reset them here. This could lead to reporting of
968 		 * invalid timestamps, but there isn't much we can do.
969 		 */
970 		dev_warn(dev, "%s: ICE_CFG_BUSY, unable to immediately update cached PHC time\n",
971 			 __func__);
972 
973 		/* Queue the work item to update the Rx rings when possible */
974 		kthread_queue_delayed_work(pf->ptp.kworker, &pf->ptp.work,
975 					   msecs_to_jiffies(10));
976 	}
977 
978 	/* Flush any outstanding Tx timestamps */
979 	ice_ptp_flush_tx_tracker(pf, &pf->ptp.port.tx);
980 }
981 
982 /**
983  * ice_ptp_read_time - Read the time from the device
984  * @pf: Board private structure
985  * @ts: timespec structure to hold the current time value
986  * @sts: Optional parameter for holding a pair of system timestamps from
987  *       the system clock. Will be ignored if NULL is given.
988  *
989  * This function reads the source clock registers and stores them in a timespec.
990  * However, since the registers are 64 bits of nanoseconds, we must convert the
991  * result to a timespec before we can return.
992  */
993 static void
994 ice_ptp_read_time(struct ice_pf *pf, struct timespec64 *ts,
995 		  struct ptp_system_timestamp *sts)
996 {
997 	u64 time_ns = ice_ptp_read_src_clk_reg(pf, sts);
998 
999 	*ts = ns_to_timespec64(time_ns);
1000 }
1001 
1002 /**
1003  * ice_ptp_write_init - Set PHC time to provided value
1004  * @pf: Board private structure
1005  * @ts: timespec structure that holds the new time value
1006  *
1007  * Set the PHC time to the specified time provided in the timespec.
1008  */
1009 static int ice_ptp_write_init(struct ice_pf *pf, struct timespec64 *ts)
1010 {
1011 	u64 ns = timespec64_to_ns(ts);
1012 	struct ice_hw *hw = &pf->hw;
1013 
1014 	return ice_ptp_init_time(hw, ns);
1015 }
1016 
1017 /**
1018  * ice_ptp_write_adj - Adjust PHC clock time atomically
1019  * @pf: Board private structure
1020  * @adj: Adjustment in nanoseconds
1021  *
1022  * Perform an atomic adjustment of the PHC time by the specified number of
1023  * nanoseconds.
1024  */
1025 static int ice_ptp_write_adj(struct ice_pf *pf, s32 adj)
1026 {
1027 	struct ice_hw *hw = &pf->hw;
1028 
1029 	return ice_ptp_adj_clock(hw, adj);
1030 }
1031 
1032 /**
1033  * ice_base_incval - Get base timer increment value
1034  * @pf: Board private structure
1035  *
1036  * Look up the base timer increment value for this device. The base increment
1037  * value is used to define the nominal clock tick rate. This increment value
1038  * is programmed during device initialization. It is also used as the basis
1039  * for calculating adjustments using scaled_ppm.
1040  */
1041 static u64 ice_base_incval(struct ice_pf *pf)
1042 {
1043 	struct ice_hw *hw = &pf->hw;
1044 	u64 incval;
1045 
1046 	if (ice_is_e810(hw))
1047 		incval = ICE_PTP_NOMINAL_INCVAL_E810;
1048 	else if (ice_e822_time_ref(hw) < NUM_ICE_TIME_REF_FREQ)
1049 		incval = ice_e822_nominal_incval(ice_e822_time_ref(hw));
1050 	else
1051 		incval = UNKNOWN_INCVAL_E822;
1052 
1053 	dev_dbg(ice_pf_to_dev(pf), "PTP: using base increment value of 0x%016llx\n",
1054 		incval);
1055 
1056 	return incval;
1057 }
1058 
1059 /**
1060  * ice_ptp_reset_ts_memory_quad - Reset timestamp memory for one quad
1061  * @pf: The PF private data structure
1062  * @quad: The quad (0-4)
1063  */
1064 static void ice_ptp_reset_ts_memory_quad(struct ice_pf *pf, int quad)
1065 {
1066 	struct ice_hw *hw = &pf->hw;
1067 
1068 	ice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M);
1069 	ice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M);
1070 }
1071 
1072 /**
1073  * ice_ptp_check_tx_fifo - Check whether Tx FIFO is in an OK state
1074  * @port: PTP port for which Tx FIFO is checked
1075  */
1076 static int ice_ptp_check_tx_fifo(struct ice_ptp_port *port)
1077 {
1078 	int quad = port->port_num / ICE_PORTS_PER_QUAD;
1079 	int offs = port->port_num % ICE_PORTS_PER_QUAD;
1080 	struct ice_pf *pf;
1081 	struct ice_hw *hw;
1082 	u32 val, phy_sts;
1083 	int err;
1084 
1085 	pf = ptp_port_to_pf(port);
1086 	hw = &pf->hw;
1087 
1088 	if (port->tx_fifo_busy_cnt == FIFO_OK)
1089 		return 0;
1090 
1091 	/* need to read FIFO state */
1092 	if (offs == 0 || offs == 1)
1093 		err = ice_read_quad_reg_e822(hw, quad, Q_REG_FIFO01_STATUS,
1094 					     &val);
1095 	else
1096 		err = ice_read_quad_reg_e822(hw, quad, Q_REG_FIFO23_STATUS,
1097 					     &val);
1098 
1099 	if (err) {
1100 		dev_err(ice_pf_to_dev(pf), "PTP failed to check port %d Tx FIFO, err %d\n",
1101 			port->port_num, err);
1102 		return err;
1103 	}
1104 
1105 	if (offs & 0x1)
1106 		phy_sts = (val & Q_REG_FIFO13_M) >> Q_REG_FIFO13_S;
1107 	else
1108 		phy_sts = (val & Q_REG_FIFO02_M) >> Q_REG_FIFO02_S;
1109 
1110 	if (phy_sts & FIFO_EMPTY) {
1111 		port->tx_fifo_busy_cnt = FIFO_OK;
1112 		return 0;
1113 	}
1114 
1115 	port->tx_fifo_busy_cnt++;
1116 
1117 	dev_dbg(ice_pf_to_dev(pf), "Try %d, port %d FIFO not empty\n",
1118 		port->tx_fifo_busy_cnt, port->port_num);
1119 
1120 	if (port->tx_fifo_busy_cnt == ICE_PTP_FIFO_NUM_CHECKS) {
1121 		dev_dbg(ice_pf_to_dev(pf),
1122 			"Port %d Tx FIFO still not empty; resetting quad %d\n",
1123 			port->port_num, quad);
1124 		ice_ptp_reset_ts_memory_quad(pf, quad);
1125 		port->tx_fifo_busy_cnt = FIFO_OK;
1126 		return 0;
1127 	}
1128 
1129 	return -EAGAIN;
1130 }
1131 
1132 /**
1133  * ice_ptp_check_tx_offset_valid - Check if the Tx PHY offset is valid
1134  * @port: the PTP port to check
1135  *
1136  * Checks whether the Tx offset for the PHY associated with this port is
1137  * valid. Returns 0 if the offset is valid, and a non-zero error code if it is
1138  * not.
1139  */
1140 static int ice_ptp_check_tx_offset_valid(struct ice_ptp_port *port)
1141 {
1142 	struct ice_pf *pf = ptp_port_to_pf(port);
1143 	struct device *dev = ice_pf_to_dev(pf);
1144 	struct ice_hw *hw = &pf->hw;
1145 	u32 val;
1146 	int err;
1147 
1148 	err = ice_ptp_check_tx_fifo(port);
1149 	if (err)
1150 		return err;
1151 
1152 	err = ice_read_phy_reg_e822(hw, port->port_num, P_REG_TX_OV_STATUS,
1153 				    &val);
1154 	if (err) {
1155 		dev_err(dev, "Failed to read TX_OV_STATUS for port %d, err %d\n",
1156 			port->port_num, err);
1157 		return -EAGAIN;
1158 	}
1159 
1160 	if (!(val & P_REG_TX_OV_STATUS_OV_M))
1161 		return -EAGAIN;
1162 
1163 	return 0;
1164 }
1165 
1166 /**
1167  * ice_ptp_check_rx_offset_valid - Check if the Rx PHY offset is valid
1168  * @port: the PTP port to check
1169  *
1170  * Checks whether the Rx offset for the PHY associated with this port is
1171  * valid. Returns 0 if the offset is valid, and a non-zero error code if it is
1172  * not.
1173  */
1174 static int ice_ptp_check_rx_offset_valid(struct ice_ptp_port *port)
1175 {
1176 	struct ice_pf *pf = ptp_port_to_pf(port);
1177 	struct device *dev = ice_pf_to_dev(pf);
1178 	struct ice_hw *hw = &pf->hw;
1179 	int err;
1180 	u32 val;
1181 
1182 	err = ice_read_phy_reg_e822(hw, port->port_num, P_REG_RX_OV_STATUS,
1183 				    &val);
1184 	if (err) {
1185 		dev_err(dev, "Failed to read RX_OV_STATUS for port %d, err %d\n",
1186 			port->port_num, err);
1187 		return err;
1188 	}
1189 
1190 	if (!(val & P_REG_RX_OV_STATUS_OV_M))
1191 		return -EAGAIN;
1192 
1193 	return 0;
1194 }
1195 
1196 /**
1197  * ice_ptp_check_offset_valid - Check port offset valid bit
1198  * @port: Port for which offset valid bit is checked
1199  *
1200  * Returns 0 if both Tx and Rx offset are valid, and -EAGAIN if one of the
1201  * offset is not ready.
1202  */
1203 static int ice_ptp_check_offset_valid(struct ice_ptp_port *port)
1204 {
1205 	int tx_err, rx_err;
1206 
1207 	/* always check both Tx and Rx offset validity */
1208 	tx_err = ice_ptp_check_tx_offset_valid(port);
1209 	rx_err = ice_ptp_check_rx_offset_valid(port);
1210 
1211 	if (tx_err || rx_err)
1212 		return -EAGAIN;
1213 
1214 	return 0;
1215 }
1216 
1217 /**
1218  * ice_ptp_wait_for_offset_valid - Check for valid Tx and Rx offsets
1219  * @work: Pointer to the kthread_work structure for this task
1220  *
1221  * Check whether both the Tx and Rx offsets are valid for enabling the vernier
1222  * calibration.
1223  *
1224  * Once we have valid offsets from hardware, update the total Tx and Rx
1225  * offsets, and exit bypass mode. This enables more precise timestamps using
1226  * the extra data measured during the vernier calibration process.
1227  */
1228 static void ice_ptp_wait_for_offset_valid(struct kthread_work *work)
1229 {
1230 	struct ice_ptp_port *port;
1231 	int err;
1232 	struct device *dev;
1233 	struct ice_pf *pf;
1234 	struct ice_hw *hw;
1235 
1236 	port = container_of(work, struct ice_ptp_port, ov_work.work);
1237 	pf = ptp_port_to_pf(port);
1238 	hw = &pf->hw;
1239 	dev = ice_pf_to_dev(pf);
1240 
1241 	if (ice_is_reset_in_progress(pf->state))
1242 		return;
1243 
1244 	if (ice_ptp_check_offset_valid(port)) {
1245 		/* Offsets not ready yet, try again later */
1246 		kthread_queue_delayed_work(pf->ptp.kworker,
1247 					   &port->ov_work,
1248 					   msecs_to_jiffies(100));
1249 		return;
1250 	}
1251 
1252 	/* Offsets are valid, so it is safe to exit bypass mode */
1253 	err = ice_phy_exit_bypass_e822(hw, port->port_num);
1254 	if (err) {
1255 		dev_warn(dev, "Failed to exit bypass mode for PHY port %u, err %d\n",
1256 			 port->port_num, err);
1257 		return;
1258 	}
1259 }
1260 
1261 /**
1262  * ice_ptp_port_phy_stop - Stop timestamping for a PHY port
1263  * @ptp_port: PTP port to stop
1264  */
1265 static int
1266 ice_ptp_port_phy_stop(struct ice_ptp_port *ptp_port)
1267 {
1268 	struct ice_pf *pf = ptp_port_to_pf(ptp_port);
1269 	u8 port = ptp_port->port_num;
1270 	struct ice_hw *hw = &pf->hw;
1271 	int err;
1272 
1273 	if (ice_is_e810(hw))
1274 		return 0;
1275 
1276 	mutex_lock(&ptp_port->ps_lock);
1277 
1278 	kthread_cancel_delayed_work_sync(&ptp_port->ov_work);
1279 
1280 	err = ice_stop_phy_timer_e822(hw, port, true);
1281 	if (err)
1282 		dev_err(ice_pf_to_dev(pf), "PTP failed to set PHY port %d down, err %d\n",
1283 			port, err);
1284 
1285 	mutex_unlock(&ptp_port->ps_lock);
1286 
1287 	return err;
1288 }
1289 
1290 /**
1291  * ice_ptp_port_phy_restart - (Re)start and calibrate PHY timestamping
1292  * @ptp_port: PTP port for which the PHY start is set
1293  *
1294  * Start the PHY timestamping block, and initiate Vernier timestamping
1295  * calibration. If timestamping cannot be calibrated (such as if link is down)
1296  * then disable the timestamping block instead.
1297  */
1298 static int
1299 ice_ptp_port_phy_restart(struct ice_ptp_port *ptp_port)
1300 {
1301 	struct ice_pf *pf = ptp_port_to_pf(ptp_port);
1302 	u8 port = ptp_port->port_num;
1303 	struct ice_hw *hw = &pf->hw;
1304 	int err;
1305 
1306 	if (ice_is_e810(hw))
1307 		return 0;
1308 
1309 	if (!ptp_port->link_up)
1310 		return ice_ptp_port_phy_stop(ptp_port);
1311 
1312 	mutex_lock(&ptp_port->ps_lock);
1313 
1314 	kthread_cancel_delayed_work_sync(&ptp_port->ov_work);
1315 
1316 	/* temporarily disable Tx timestamps while calibrating PHY offset */
1317 	ptp_port->tx.calibrating = true;
1318 	ptp_port->tx_fifo_busy_cnt = 0;
1319 
1320 	/* Start the PHY timer in bypass mode */
1321 	err = ice_start_phy_timer_e822(hw, port, true);
1322 	if (err)
1323 		goto out_unlock;
1324 
1325 	/* Enable Tx timestamps right away */
1326 	ptp_port->tx.calibrating = false;
1327 
1328 	kthread_queue_delayed_work(pf->ptp.kworker, &ptp_port->ov_work, 0);
1329 
1330 out_unlock:
1331 	if (err)
1332 		dev_err(ice_pf_to_dev(pf), "PTP failed to set PHY port %d up, err %d\n",
1333 			port, err);
1334 
1335 	mutex_unlock(&ptp_port->ps_lock);
1336 
1337 	return err;
1338 }
1339 
1340 /**
1341  * ice_ptp_link_change - Set or clear port registers for timestamping
1342  * @pf: Board private structure
1343  * @port: Port for which the PHY start is set
1344  * @linkup: Link is up or down
1345  */
1346 int ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup)
1347 {
1348 	struct ice_ptp_port *ptp_port;
1349 
1350 	if (!test_bit(ICE_FLAG_PTP_SUPPORTED, pf->flags))
1351 		return 0;
1352 
1353 	if (port >= ICE_NUM_EXTERNAL_PORTS)
1354 		return -EINVAL;
1355 
1356 	ptp_port = &pf->ptp.port;
1357 	if (ptp_port->port_num != port)
1358 		return -EINVAL;
1359 
1360 	/* Update cached link err for this port immediately */
1361 	ptp_port->link_up = linkup;
1362 
1363 	if (!test_bit(ICE_FLAG_PTP, pf->flags))
1364 		/* PTP is not setup */
1365 		return -EAGAIN;
1366 
1367 	return ice_ptp_port_phy_restart(ptp_port);
1368 }
1369 
1370 /**
1371  * ice_ptp_reset_ts_memory - Reset timestamp memory for all quads
1372  * @pf: The PF private data structure
1373  */
1374 static void ice_ptp_reset_ts_memory(struct ice_pf *pf)
1375 {
1376 	int quad;
1377 
1378 	quad = pf->hw.port_info->lport / ICE_PORTS_PER_QUAD;
1379 	ice_ptp_reset_ts_memory_quad(pf, quad);
1380 }
1381 
1382 /**
1383  * ice_ptp_tx_ena_intr - Enable or disable the Tx timestamp interrupt
1384  * @pf: PF private structure
1385  * @ena: bool value to enable or disable interrupt
1386  * @threshold: Minimum number of packets at which intr is triggered
1387  *
1388  * Utility function to enable or disable Tx timestamp interrupt and threshold
1389  */
1390 static int ice_ptp_tx_ena_intr(struct ice_pf *pf, bool ena, u32 threshold)
1391 {
1392 	struct ice_hw *hw = &pf->hw;
1393 	int err = 0;
1394 	int quad;
1395 	u32 val;
1396 
1397 	ice_ptp_reset_ts_memory(pf);
1398 
1399 	for (quad = 0; quad < ICE_MAX_QUAD; quad++) {
1400 		err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG,
1401 					     &val);
1402 		if (err)
1403 			break;
1404 
1405 		if (ena) {
1406 			val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
1407 			val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M;
1408 			val |= ((threshold << Q_REG_TX_MEM_GBL_CFG_INTR_THR_S) &
1409 				Q_REG_TX_MEM_GBL_CFG_INTR_THR_M);
1410 		} else {
1411 			val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
1412 		}
1413 
1414 		err = ice_write_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG,
1415 					      val);
1416 		if (err)
1417 			break;
1418 	}
1419 
1420 	if (err)
1421 		dev_err(ice_pf_to_dev(pf), "PTP failed in intr ena, err %d\n",
1422 			err);
1423 	return err;
1424 }
1425 
1426 /**
1427  * ice_ptp_reset_phy_timestamping - Reset PHY timestamping block
1428  * @pf: Board private structure
1429  */
1430 static void ice_ptp_reset_phy_timestamping(struct ice_pf *pf)
1431 {
1432 	ice_ptp_port_phy_restart(&pf->ptp.port);
1433 }
1434 
1435 /**
1436  * ice_ptp_adjfine - Adjust clock increment rate
1437  * @info: the driver's PTP info structure
1438  * @scaled_ppm: Parts per million with 16-bit fractional field
1439  *
1440  * Adjust the frequency of the clock by the indicated scaled ppm from the
1441  * base frequency.
1442  */
1443 static int ice_ptp_adjfine(struct ptp_clock_info *info, long scaled_ppm)
1444 {
1445 	struct ice_pf *pf = ptp_info_to_pf(info);
1446 	struct ice_hw *hw = &pf->hw;
1447 	u64 incval, diff;
1448 	int neg_adj = 0;
1449 	int err;
1450 
1451 	incval = ice_base_incval(pf);
1452 
1453 	if (scaled_ppm < 0) {
1454 		neg_adj = 1;
1455 		scaled_ppm = -scaled_ppm;
1456 	}
1457 
1458 	diff = mul_u64_u64_div_u64(incval, (u64)scaled_ppm,
1459 				   1000000ULL << 16);
1460 	if (neg_adj)
1461 		incval -= diff;
1462 	else
1463 		incval += diff;
1464 
1465 	err = ice_ptp_write_incval_locked(hw, incval);
1466 	if (err) {
1467 		dev_err(ice_pf_to_dev(pf), "PTP failed to set incval, err %d\n",
1468 			err);
1469 		return -EIO;
1470 	}
1471 
1472 	return 0;
1473 }
1474 
1475 /**
1476  * ice_ptp_extts_work - Workqueue task function
1477  * @work: external timestamp work structure
1478  *
1479  * Service for PTP external clock event
1480  */
1481 static void ice_ptp_extts_work(struct kthread_work *work)
1482 {
1483 	struct ice_ptp *ptp = container_of(work, struct ice_ptp, extts_work);
1484 	struct ice_pf *pf = container_of(ptp, struct ice_pf, ptp);
1485 	struct ptp_clock_event event;
1486 	struct ice_hw *hw = &pf->hw;
1487 	u8 chan, tmr_idx;
1488 	u32 hi, lo;
1489 
1490 	tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
1491 	/* Event time is captured by one of the two matched registers
1492 	 *      GLTSYN_EVNT_L: 32 LSB of sampled time event
1493 	 *      GLTSYN_EVNT_H: 32 MSB of sampled time event
1494 	 * Event is defined in GLTSYN_EVNT_0 register
1495 	 */
1496 	for (chan = 0; chan < GLTSYN_EVNT_H_IDX_MAX; chan++) {
1497 		/* Check if channel is enabled */
1498 		if (pf->ptp.ext_ts_irq & (1 << chan)) {
1499 			lo = rd32(hw, GLTSYN_EVNT_L(chan, tmr_idx));
1500 			hi = rd32(hw, GLTSYN_EVNT_H(chan, tmr_idx));
1501 			event.timestamp = (((u64)hi) << 32) | lo;
1502 			event.type = PTP_CLOCK_EXTTS;
1503 			event.index = chan;
1504 
1505 			/* Fire event */
1506 			ptp_clock_event(pf->ptp.clock, &event);
1507 			pf->ptp.ext_ts_irq &= ~(1 << chan);
1508 		}
1509 	}
1510 }
1511 
1512 /**
1513  * ice_ptp_cfg_extts - Configure EXTTS pin and channel
1514  * @pf: Board private structure
1515  * @ena: true to enable; false to disable
1516  * @chan: GPIO channel (0-3)
1517  * @gpio_pin: GPIO pin
1518  * @extts_flags: request flags from the ptp_extts_request.flags
1519  */
1520 static int
1521 ice_ptp_cfg_extts(struct ice_pf *pf, bool ena, unsigned int chan, u32 gpio_pin,
1522 		  unsigned int extts_flags)
1523 {
1524 	u32 func, aux_reg, gpio_reg, irq_reg;
1525 	struct ice_hw *hw = &pf->hw;
1526 	u8 tmr_idx;
1527 
1528 	if (chan > (unsigned int)pf->ptp.info.n_ext_ts)
1529 		return -EINVAL;
1530 
1531 	tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
1532 
1533 	irq_reg = rd32(hw, PFINT_OICR_ENA);
1534 
1535 	if (ena) {
1536 		/* Enable the interrupt */
1537 		irq_reg |= PFINT_OICR_TSYN_EVNT_M;
1538 		aux_reg = GLTSYN_AUX_IN_0_INT_ENA_M;
1539 
1540 #define GLTSYN_AUX_IN_0_EVNTLVL_RISING_EDGE	BIT(0)
1541 #define GLTSYN_AUX_IN_0_EVNTLVL_FALLING_EDGE	BIT(1)
1542 
1543 		/* set event level to requested edge */
1544 		if (extts_flags & PTP_FALLING_EDGE)
1545 			aux_reg |= GLTSYN_AUX_IN_0_EVNTLVL_FALLING_EDGE;
1546 		if (extts_flags & PTP_RISING_EDGE)
1547 			aux_reg |= GLTSYN_AUX_IN_0_EVNTLVL_RISING_EDGE;
1548 
1549 		/* Write GPIO CTL reg.
1550 		 * 0x1 is input sampled by EVENT register(channel)
1551 		 * + num_in_channels * tmr_idx
1552 		 */
1553 		func = 1 + chan + (tmr_idx * 3);
1554 		gpio_reg = ((func << GLGEN_GPIO_CTL_PIN_FUNC_S) &
1555 			    GLGEN_GPIO_CTL_PIN_FUNC_M);
1556 		pf->ptp.ext_ts_chan |= (1 << chan);
1557 	} else {
1558 		/* clear the values we set to reset defaults */
1559 		aux_reg = 0;
1560 		gpio_reg = 0;
1561 		pf->ptp.ext_ts_chan &= ~(1 << chan);
1562 		if (!pf->ptp.ext_ts_chan)
1563 			irq_reg &= ~PFINT_OICR_TSYN_EVNT_M;
1564 	}
1565 
1566 	wr32(hw, PFINT_OICR_ENA, irq_reg);
1567 	wr32(hw, GLTSYN_AUX_IN(chan, tmr_idx), aux_reg);
1568 	wr32(hw, GLGEN_GPIO_CTL(gpio_pin), gpio_reg);
1569 
1570 	return 0;
1571 }
1572 
1573 /**
1574  * ice_ptp_cfg_clkout - Configure clock to generate periodic wave
1575  * @pf: Board private structure
1576  * @chan: GPIO channel (0-3)
1577  * @config: desired periodic clk configuration. NULL will disable channel
1578  * @store: If set to true the values will be stored
1579  *
1580  * Configure the internal clock generator modules to generate the clock wave of
1581  * specified period.
1582  */
1583 static int ice_ptp_cfg_clkout(struct ice_pf *pf, unsigned int chan,
1584 			      struct ice_perout_channel *config, bool store)
1585 {
1586 	u64 current_time, period, start_time, phase;
1587 	struct ice_hw *hw = &pf->hw;
1588 	u32 func, val, gpio_pin;
1589 	u8 tmr_idx;
1590 
1591 	tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
1592 
1593 	/* 0. Reset mode & out_en in AUX_OUT */
1594 	wr32(hw, GLTSYN_AUX_OUT(chan, tmr_idx), 0);
1595 
1596 	/* If we're disabling the output, clear out CLKO and TGT and keep
1597 	 * output level low
1598 	 */
1599 	if (!config || !config->ena) {
1600 		wr32(hw, GLTSYN_CLKO(chan, tmr_idx), 0);
1601 		wr32(hw, GLTSYN_TGT_L(chan, tmr_idx), 0);
1602 		wr32(hw, GLTSYN_TGT_H(chan, tmr_idx), 0);
1603 
1604 		val = GLGEN_GPIO_CTL_PIN_DIR_M;
1605 		gpio_pin = pf->ptp.perout_channels[chan].gpio_pin;
1606 		wr32(hw, GLGEN_GPIO_CTL(gpio_pin), val);
1607 
1608 		/* Store the value if requested */
1609 		if (store)
1610 			memset(&pf->ptp.perout_channels[chan], 0,
1611 			       sizeof(struct ice_perout_channel));
1612 
1613 		return 0;
1614 	}
1615 	period = config->period;
1616 	start_time = config->start_time;
1617 	div64_u64_rem(start_time, period, &phase);
1618 	gpio_pin = config->gpio_pin;
1619 
1620 	/* 1. Write clkout with half of required period value */
1621 	if (period & 0x1) {
1622 		dev_err(ice_pf_to_dev(pf), "CLK Period must be an even value\n");
1623 		goto err;
1624 	}
1625 
1626 	period >>= 1;
1627 
1628 	/* For proper operation, the GLTSYN_CLKO must be larger than clock tick
1629 	 */
1630 #define MIN_PULSE 3
1631 	if (period <= MIN_PULSE || period > U32_MAX) {
1632 		dev_err(ice_pf_to_dev(pf), "CLK Period must be > %d && < 2^33",
1633 			MIN_PULSE * 2);
1634 		goto err;
1635 	}
1636 
1637 	wr32(hw, GLTSYN_CLKO(chan, tmr_idx), lower_32_bits(period));
1638 
1639 	/* Allow time for programming before start_time is hit */
1640 	current_time = ice_ptp_read_src_clk_reg(pf, NULL);
1641 
1642 	/* if start time is in the past start the timer at the nearest second
1643 	 * maintaining phase
1644 	 */
1645 	if (start_time < current_time)
1646 		start_time = div64_u64(current_time + NSEC_PER_SEC - 1,
1647 				       NSEC_PER_SEC) * NSEC_PER_SEC + phase;
1648 
1649 	if (ice_is_e810(hw))
1650 		start_time -= E810_OUT_PROP_DELAY_NS;
1651 	else
1652 		start_time -= ice_e822_pps_delay(ice_e822_time_ref(hw));
1653 
1654 	/* 2. Write TARGET time */
1655 	wr32(hw, GLTSYN_TGT_L(chan, tmr_idx), lower_32_bits(start_time));
1656 	wr32(hw, GLTSYN_TGT_H(chan, tmr_idx), upper_32_bits(start_time));
1657 
1658 	/* 3. Write AUX_OUT register */
1659 	val = GLTSYN_AUX_OUT_0_OUT_ENA_M | GLTSYN_AUX_OUT_0_OUTMOD_M;
1660 	wr32(hw, GLTSYN_AUX_OUT(chan, tmr_idx), val);
1661 
1662 	/* 4. write GPIO CTL reg */
1663 	func = 8 + chan + (tmr_idx * 4);
1664 	val = GLGEN_GPIO_CTL_PIN_DIR_M |
1665 	      ((func << GLGEN_GPIO_CTL_PIN_FUNC_S) & GLGEN_GPIO_CTL_PIN_FUNC_M);
1666 	wr32(hw, GLGEN_GPIO_CTL(gpio_pin), val);
1667 
1668 	/* Store the value if requested */
1669 	if (store) {
1670 		memcpy(&pf->ptp.perout_channels[chan], config,
1671 		       sizeof(struct ice_perout_channel));
1672 		pf->ptp.perout_channels[chan].start_time = phase;
1673 	}
1674 
1675 	return 0;
1676 err:
1677 	dev_err(ice_pf_to_dev(pf), "PTP failed to cfg per_clk\n");
1678 	return -EFAULT;
1679 }
1680 
1681 /**
1682  * ice_ptp_disable_all_clkout - Disable all currently configured outputs
1683  * @pf: pointer to the PF structure
1684  *
1685  * Disable all currently configured clock outputs. This is necessary before
1686  * certain changes to the PTP hardware clock. Use ice_ptp_enable_all_clkout to
1687  * re-enable the clocks again.
1688  */
1689 static void ice_ptp_disable_all_clkout(struct ice_pf *pf)
1690 {
1691 	uint i;
1692 
1693 	for (i = 0; i < pf->ptp.info.n_per_out; i++)
1694 		if (pf->ptp.perout_channels[i].ena)
1695 			ice_ptp_cfg_clkout(pf, i, NULL, false);
1696 }
1697 
1698 /**
1699  * ice_ptp_enable_all_clkout - Enable all configured periodic clock outputs
1700  * @pf: pointer to the PF structure
1701  *
1702  * Enable all currently configured clock outputs. Use this after
1703  * ice_ptp_disable_all_clkout to reconfigure the output signals according to
1704  * their configuration.
1705  */
1706 static void ice_ptp_enable_all_clkout(struct ice_pf *pf)
1707 {
1708 	uint i;
1709 
1710 	for (i = 0; i < pf->ptp.info.n_per_out; i++)
1711 		if (pf->ptp.perout_channels[i].ena)
1712 			ice_ptp_cfg_clkout(pf, i, &pf->ptp.perout_channels[i],
1713 					   false);
1714 }
1715 
1716 /**
1717  * ice_ptp_gpio_enable_e810 - Enable/disable ancillary features of PHC
1718  * @info: the driver's PTP info structure
1719  * @rq: The requested feature to change
1720  * @on: Enable/disable flag
1721  */
1722 static int
1723 ice_ptp_gpio_enable_e810(struct ptp_clock_info *info,
1724 			 struct ptp_clock_request *rq, int on)
1725 {
1726 	struct ice_pf *pf = ptp_info_to_pf(info);
1727 	struct ice_perout_channel clk_cfg = {0};
1728 	bool sma_pres = false;
1729 	unsigned int chan;
1730 	u32 gpio_pin;
1731 	int err;
1732 
1733 	if (ice_is_feature_supported(pf, ICE_F_SMA_CTRL))
1734 		sma_pres = true;
1735 
1736 	switch (rq->type) {
1737 	case PTP_CLK_REQ_PEROUT:
1738 		chan = rq->perout.index;
1739 		if (sma_pres) {
1740 			if (chan == ice_pin_desc_e810t[SMA1].chan)
1741 				clk_cfg.gpio_pin = GPIO_20;
1742 			else if (chan == ice_pin_desc_e810t[SMA2].chan)
1743 				clk_cfg.gpio_pin = GPIO_22;
1744 			else
1745 				return -1;
1746 		} else if (ice_is_e810t(&pf->hw)) {
1747 			if (chan == 0)
1748 				clk_cfg.gpio_pin = GPIO_20;
1749 			else
1750 				clk_cfg.gpio_pin = GPIO_22;
1751 		} else if (chan == PPS_CLK_GEN_CHAN) {
1752 			clk_cfg.gpio_pin = PPS_PIN_INDEX;
1753 		} else {
1754 			clk_cfg.gpio_pin = chan;
1755 		}
1756 
1757 		clk_cfg.period = ((rq->perout.period.sec * NSEC_PER_SEC) +
1758 				   rq->perout.period.nsec);
1759 		clk_cfg.start_time = ((rq->perout.start.sec * NSEC_PER_SEC) +
1760 				       rq->perout.start.nsec);
1761 		clk_cfg.ena = !!on;
1762 
1763 		err = ice_ptp_cfg_clkout(pf, chan, &clk_cfg, true);
1764 		break;
1765 	case PTP_CLK_REQ_EXTTS:
1766 		chan = rq->extts.index;
1767 		if (sma_pres) {
1768 			if (chan < ice_pin_desc_e810t[SMA2].chan)
1769 				gpio_pin = GPIO_21;
1770 			else
1771 				gpio_pin = GPIO_23;
1772 		} else if (ice_is_e810t(&pf->hw)) {
1773 			if (chan == 0)
1774 				gpio_pin = GPIO_21;
1775 			else
1776 				gpio_pin = GPIO_23;
1777 		} else {
1778 			gpio_pin = chan;
1779 		}
1780 
1781 		err = ice_ptp_cfg_extts(pf, !!on, chan, gpio_pin,
1782 					rq->extts.flags);
1783 		break;
1784 	default:
1785 		return -EOPNOTSUPP;
1786 	}
1787 
1788 	return err;
1789 }
1790 
1791 /**
1792  * ice_ptp_gettimex64 - Get the time of the clock
1793  * @info: the driver's PTP info structure
1794  * @ts: timespec64 structure to hold the current time value
1795  * @sts: Optional parameter for holding a pair of system timestamps from
1796  *       the system clock. Will be ignored if NULL is given.
1797  *
1798  * Read the device clock and return the correct value on ns, after converting it
1799  * into a timespec struct.
1800  */
1801 static int
1802 ice_ptp_gettimex64(struct ptp_clock_info *info, struct timespec64 *ts,
1803 		   struct ptp_system_timestamp *sts)
1804 {
1805 	struct ice_pf *pf = ptp_info_to_pf(info);
1806 	struct ice_hw *hw = &pf->hw;
1807 
1808 	if (!ice_ptp_lock(hw)) {
1809 		dev_err(ice_pf_to_dev(pf), "PTP failed to get time\n");
1810 		return -EBUSY;
1811 	}
1812 
1813 	ice_ptp_read_time(pf, ts, sts);
1814 	ice_ptp_unlock(hw);
1815 
1816 	return 0;
1817 }
1818 
1819 /**
1820  * ice_ptp_settime64 - Set the time of the clock
1821  * @info: the driver's PTP info structure
1822  * @ts: timespec64 structure that holds the new time value
1823  *
1824  * Set the device clock to the user input value. The conversion from timespec
1825  * to ns happens in the write function.
1826  */
1827 static int
1828 ice_ptp_settime64(struct ptp_clock_info *info, const struct timespec64 *ts)
1829 {
1830 	struct ice_pf *pf = ptp_info_to_pf(info);
1831 	struct timespec64 ts64 = *ts;
1832 	struct ice_hw *hw = &pf->hw;
1833 	int err;
1834 
1835 	/* For Vernier mode, we need to recalibrate after new settime
1836 	 * Start with disabling timestamp block
1837 	 */
1838 	if (pf->ptp.port.link_up)
1839 		ice_ptp_port_phy_stop(&pf->ptp.port);
1840 
1841 	if (!ice_ptp_lock(hw)) {
1842 		err = -EBUSY;
1843 		goto exit;
1844 	}
1845 
1846 	/* Disable periodic outputs */
1847 	ice_ptp_disable_all_clkout(pf);
1848 
1849 	err = ice_ptp_write_init(pf, &ts64);
1850 	ice_ptp_unlock(hw);
1851 
1852 	if (!err)
1853 		ice_ptp_reset_cached_phctime(pf);
1854 
1855 	/* Reenable periodic outputs */
1856 	ice_ptp_enable_all_clkout(pf);
1857 
1858 	/* Recalibrate and re-enable timestamp block */
1859 	if (pf->ptp.port.link_up)
1860 		ice_ptp_port_phy_restart(&pf->ptp.port);
1861 exit:
1862 	if (err) {
1863 		dev_err(ice_pf_to_dev(pf), "PTP failed to set time %d\n", err);
1864 		return err;
1865 	}
1866 
1867 	return 0;
1868 }
1869 
1870 /**
1871  * ice_ptp_adjtime_nonatomic - Do a non-atomic clock adjustment
1872  * @info: the driver's PTP info structure
1873  * @delta: Offset in nanoseconds to adjust the time by
1874  */
1875 static int ice_ptp_adjtime_nonatomic(struct ptp_clock_info *info, s64 delta)
1876 {
1877 	struct timespec64 now, then;
1878 	int ret;
1879 
1880 	then = ns_to_timespec64(delta);
1881 	ret = ice_ptp_gettimex64(info, &now, NULL);
1882 	if (ret)
1883 		return ret;
1884 	now = timespec64_add(now, then);
1885 
1886 	return ice_ptp_settime64(info, (const struct timespec64 *)&now);
1887 }
1888 
1889 /**
1890  * ice_ptp_adjtime - Adjust the time of the clock by the indicated delta
1891  * @info: the driver's PTP info structure
1892  * @delta: Offset in nanoseconds to adjust the time by
1893  */
1894 static int ice_ptp_adjtime(struct ptp_clock_info *info, s64 delta)
1895 {
1896 	struct ice_pf *pf = ptp_info_to_pf(info);
1897 	struct ice_hw *hw = &pf->hw;
1898 	struct device *dev;
1899 	int err;
1900 
1901 	dev = ice_pf_to_dev(pf);
1902 
1903 	/* Hardware only supports atomic adjustments using signed 32-bit
1904 	 * integers. For any adjustment outside this range, perform
1905 	 * a non-atomic get->adjust->set flow.
1906 	 */
1907 	if (delta > S32_MAX || delta < S32_MIN) {
1908 		dev_dbg(dev, "delta = %lld, adjtime non-atomic\n", delta);
1909 		return ice_ptp_adjtime_nonatomic(info, delta);
1910 	}
1911 
1912 	if (!ice_ptp_lock(hw)) {
1913 		dev_err(dev, "PTP failed to acquire semaphore in adjtime\n");
1914 		return -EBUSY;
1915 	}
1916 
1917 	/* Disable periodic outputs */
1918 	ice_ptp_disable_all_clkout(pf);
1919 
1920 	err = ice_ptp_write_adj(pf, delta);
1921 
1922 	/* Reenable periodic outputs */
1923 	ice_ptp_enable_all_clkout(pf);
1924 
1925 	ice_ptp_unlock(hw);
1926 
1927 	if (err) {
1928 		dev_err(dev, "PTP failed to adjust time, err %d\n", err);
1929 		return err;
1930 	}
1931 
1932 	ice_ptp_reset_cached_phctime(pf);
1933 
1934 	return 0;
1935 }
1936 
1937 #ifdef CONFIG_ICE_HWTS
1938 /**
1939  * ice_ptp_get_syncdevicetime - Get the cross time stamp info
1940  * @device: Current device time
1941  * @system: System counter value read synchronously with device time
1942  * @ctx: Context provided by timekeeping code
1943  *
1944  * Read device and system (ART) clock simultaneously and return the corrected
1945  * clock values in ns.
1946  */
1947 static int
1948 ice_ptp_get_syncdevicetime(ktime_t *device,
1949 			   struct system_counterval_t *system,
1950 			   void *ctx)
1951 {
1952 	struct ice_pf *pf = (struct ice_pf *)ctx;
1953 	struct ice_hw *hw = &pf->hw;
1954 	u32 hh_lock, hh_art_ctl;
1955 	int i;
1956 
1957 	/* Get the HW lock */
1958 	hh_lock = rd32(hw, PFHH_SEM + (PFTSYN_SEM_BYTES * hw->pf_id));
1959 	if (hh_lock & PFHH_SEM_BUSY_M) {
1960 		dev_err(ice_pf_to_dev(pf), "PTP failed to get hh lock\n");
1961 		return -EFAULT;
1962 	}
1963 
1964 	/* Start the ART and device clock sync sequence */
1965 	hh_art_ctl = rd32(hw, GLHH_ART_CTL);
1966 	hh_art_ctl = hh_art_ctl | GLHH_ART_CTL_ACTIVE_M;
1967 	wr32(hw, GLHH_ART_CTL, hh_art_ctl);
1968 
1969 #define MAX_HH_LOCK_TRIES 100
1970 
1971 	for (i = 0; i < MAX_HH_LOCK_TRIES; i++) {
1972 		/* Wait for sync to complete */
1973 		hh_art_ctl = rd32(hw, GLHH_ART_CTL);
1974 		if (hh_art_ctl & GLHH_ART_CTL_ACTIVE_M) {
1975 			udelay(1);
1976 			continue;
1977 		} else {
1978 			u32 hh_ts_lo, hh_ts_hi, tmr_idx;
1979 			u64 hh_ts;
1980 
1981 			tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc;
1982 			/* Read ART time */
1983 			hh_ts_lo = rd32(hw, GLHH_ART_TIME_L);
1984 			hh_ts_hi = rd32(hw, GLHH_ART_TIME_H);
1985 			hh_ts = ((u64)hh_ts_hi << 32) | hh_ts_lo;
1986 			*system = convert_art_ns_to_tsc(hh_ts);
1987 			/* Read Device source clock time */
1988 			hh_ts_lo = rd32(hw, GLTSYN_HHTIME_L(tmr_idx));
1989 			hh_ts_hi = rd32(hw, GLTSYN_HHTIME_H(tmr_idx));
1990 			hh_ts = ((u64)hh_ts_hi << 32) | hh_ts_lo;
1991 			*device = ns_to_ktime(hh_ts);
1992 			break;
1993 		}
1994 	}
1995 	/* Release HW lock */
1996 	hh_lock = rd32(hw, PFHH_SEM + (PFTSYN_SEM_BYTES * hw->pf_id));
1997 	hh_lock = hh_lock & ~PFHH_SEM_BUSY_M;
1998 	wr32(hw, PFHH_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), hh_lock);
1999 
2000 	if (i == MAX_HH_LOCK_TRIES)
2001 		return -ETIMEDOUT;
2002 
2003 	return 0;
2004 }
2005 
2006 /**
2007  * ice_ptp_getcrosststamp_e822 - Capture a device cross timestamp
2008  * @info: the driver's PTP info structure
2009  * @cts: The memory to fill the cross timestamp info
2010  *
2011  * Capture a cross timestamp between the ART and the device PTP hardware
2012  * clock. Fill the cross timestamp information and report it back to the
2013  * caller.
2014  *
2015  * This is only valid for E822 devices which have support for generating the
2016  * cross timestamp via PCIe PTM.
2017  *
2018  * In order to correctly correlate the ART timestamp back to the TSC time, the
2019  * CPU must have X86_FEATURE_TSC_KNOWN_FREQ.
2020  */
2021 static int
2022 ice_ptp_getcrosststamp_e822(struct ptp_clock_info *info,
2023 			    struct system_device_crosststamp *cts)
2024 {
2025 	struct ice_pf *pf = ptp_info_to_pf(info);
2026 
2027 	return get_device_system_crosststamp(ice_ptp_get_syncdevicetime,
2028 					     pf, NULL, cts);
2029 }
2030 #endif /* CONFIG_ICE_HWTS */
2031 
2032 /**
2033  * ice_ptp_get_ts_config - ioctl interface to read the timestamping config
2034  * @pf: Board private structure
2035  * @ifr: ioctl data
2036  *
2037  * Copy the timestamping config to user buffer
2038  */
2039 int ice_ptp_get_ts_config(struct ice_pf *pf, struct ifreq *ifr)
2040 {
2041 	struct hwtstamp_config *config;
2042 
2043 	if (!test_bit(ICE_FLAG_PTP, pf->flags))
2044 		return -EIO;
2045 
2046 	config = &pf->ptp.tstamp_config;
2047 
2048 	return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
2049 		-EFAULT : 0;
2050 }
2051 
2052 /**
2053  * ice_ptp_set_timestamp_mode - Setup driver for requested timestamp mode
2054  * @pf: Board private structure
2055  * @config: hwtstamp settings requested or saved
2056  */
2057 static int
2058 ice_ptp_set_timestamp_mode(struct ice_pf *pf, struct hwtstamp_config *config)
2059 {
2060 	switch (config->tx_type) {
2061 	case HWTSTAMP_TX_OFF:
2062 		ice_set_tx_tstamp(pf, false);
2063 		break;
2064 	case HWTSTAMP_TX_ON:
2065 		ice_set_tx_tstamp(pf, true);
2066 		break;
2067 	default:
2068 		return -ERANGE;
2069 	}
2070 
2071 	switch (config->rx_filter) {
2072 	case HWTSTAMP_FILTER_NONE:
2073 		ice_set_rx_tstamp(pf, false);
2074 		break;
2075 	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2076 	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2077 	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2078 	case HWTSTAMP_FILTER_PTP_V2_EVENT:
2079 	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2080 	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2081 	case HWTSTAMP_FILTER_PTP_V2_SYNC:
2082 	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2083 	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2084 	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2085 	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2086 	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2087 	case HWTSTAMP_FILTER_NTP_ALL:
2088 	case HWTSTAMP_FILTER_ALL:
2089 		ice_set_rx_tstamp(pf, true);
2090 		break;
2091 	default:
2092 		return -ERANGE;
2093 	}
2094 
2095 	return 0;
2096 }
2097 
2098 /**
2099  * ice_ptp_set_ts_config - ioctl interface to control the timestamping
2100  * @pf: Board private structure
2101  * @ifr: ioctl data
2102  *
2103  * Get the user config and store it
2104  */
2105 int ice_ptp_set_ts_config(struct ice_pf *pf, struct ifreq *ifr)
2106 {
2107 	struct hwtstamp_config config;
2108 	int err;
2109 
2110 	if (!test_bit(ICE_FLAG_PTP, pf->flags))
2111 		return -EAGAIN;
2112 
2113 	if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2114 		return -EFAULT;
2115 
2116 	err = ice_ptp_set_timestamp_mode(pf, &config);
2117 	if (err)
2118 		return err;
2119 
2120 	/* Return the actual configuration set */
2121 	config = pf->ptp.tstamp_config;
2122 
2123 	return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
2124 		-EFAULT : 0;
2125 }
2126 
2127 /**
2128  * ice_ptp_rx_hwtstamp - Check for an Rx timestamp
2129  * @rx_ring: Ring to get the VSI info
2130  * @rx_desc: Receive descriptor
2131  * @skb: Particular skb to send timestamp with
2132  *
2133  * The driver receives a notification in the receive descriptor with timestamp.
2134  * The timestamp is in ns, so we must convert the result first.
2135  */
2136 void
2137 ice_ptp_rx_hwtstamp(struct ice_rx_ring *rx_ring,
2138 		    union ice_32b_rx_flex_desc *rx_desc, struct sk_buff *skb)
2139 {
2140 	struct skb_shared_hwtstamps *hwtstamps;
2141 	u64 ts_ns, cached_time;
2142 	u32 ts_high;
2143 
2144 	if (!(rx_desc->wb.time_stamp_low & ICE_PTP_TS_VALID))
2145 		return;
2146 
2147 	cached_time = READ_ONCE(rx_ring->cached_phctime);
2148 
2149 	/* Do not report a timestamp if we don't have a cached PHC time */
2150 	if (!cached_time)
2151 		return;
2152 
2153 	/* Use ice_ptp_extend_32b_ts directly, using the ring-specific cached
2154 	 * PHC value, rather than accessing the PF. This also allows us to
2155 	 * simply pass the upper 32bits of nanoseconds directly. Calling
2156 	 * ice_ptp_extend_40b_ts is unnecessary as it would just discard these
2157 	 * bits itself.
2158 	 */
2159 	ts_high = le32_to_cpu(rx_desc->wb.flex_ts.ts_high);
2160 	ts_ns = ice_ptp_extend_32b_ts(cached_time, ts_high);
2161 
2162 	hwtstamps = skb_hwtstamps(skb);
2163 	memset(hwtstamps, 0, sizeof(*hwtstamps));
2164 	hwtstamps->hwtstamp = ns_to_ktime(ts_ns);
2165 }
2166 
2167 /**
2168  * ice_ptp_disable_sma_pins_e810t - Disable E810-T SMA pins
2169  * @pf: pointer to the PF structure
2170  * @info: PTP clock info structure
2171  *
2172  * Disable the OS access to the SMA pins. Called to clear out the OS
2173  * indications of pin support when we fail to setup the E810-T SMA control
2174  * register.
2175  */
2176 static void
2177 ice_ptp_disable_sma_pins_e810t(struct ice_pf *pf, struct ptp_clock_info *info)
2178 {
2179 	struct device *dev = ice_pf_to_dev(pf);
2180 
2181 	dev_warn(dev, "Failed to configure E810-T SMA pin control\n");
2182 
2183 	info->enable = NULL;
2184 	info->verify = NULL;
2185 	info->n_pins = 0;
2186 	info->n_ext_ts = 0;
2187 	info->n_per_out = 0;
2188 }
2189 
2190 /**
2191  * ice_ptp_setup_sma_pins_e810t - Setup the SMA pins
2192  * @pf: pointer to the PF structure
2193  * @info: PTP clock info structure
2194  *
2195  * Finish setting up the SMA pins by allocating pin_config, and setting it up
2196  * according to the current status of the SMA. On failure, disable all of the
2197  * extended SMA pin support.
2198  */
2199 static void
2200 ice_ptp_setup_sma_pins_e810t(struct ice_pf *pf, struct ptp_clock_info *info)
2201 {
2202 	struct device *dev = ice_pf_to_dev(pf);
2203 	int err;
2204 
2205 	/* Allocate memory for kernel pins interface */
2206 	info->pin_config = devm_kcalloc(dev, info->n_pins,
2207 					sizeof(*info->pin_config), GFP_KERNEL);
2208 	if (!info->pin_config) {
2209 		ice_ptp_disable_sma_pins_e810t(pf, info);
2210 		return;
2211 	}
2212 
2213 	/* Read current SMA status */
2214 	err = ice_get_sma_config_e810t(&pf->hw, info->pin_config);
2215 	if (err)
2216 		ice_ptp_disable_sma_pins_e810t(pf, info);
2217 }
2218 
2219 /**
2220  * ice_ptp_setup_pins_e810 - Setup PTP pins in sysfs
2221  * @pf: pointer to the PF instance
2222  * @info: PTP clock capabilities
2223  */
2224 static void
2225 ice_ptp_setup_pins_e810(struct ice_pf *pf, struct ptp_clock_info *info)
2226 {
2227 	info->n_per_out = N_PER_OUT_E810;
2228 
2229 	if (ice_is_feature_supported(pf, ICE_F_PTP_EXTTS))
2230 		info->n_ext_ts = N_EXT_TS_E810;
2231 
2232 	if (ice_is_feature_supported(pf, ICE_F_SMA_CTRL)) {
2233 		info->n_ext_ts = N_EXT_TS_E810;
2234 		info->n_pins = NUM_PTP_PINS_E810T;
2235 		info->verify = ice_verify_pin_e810t;
2236 
2237 		/* Complete setup of the SMA pins */
2238 		ice_ptp_setup_sma_pins_e810t(pf, info);
2239 	}
2240 }
2241 
2242 /**
2243  * ice_ptp_set_funcs_e822 - Set specialized functions for E822 support
2244  * @pf: Board private structure
2245  * @info: PTP info to fill
2246  *
2247  * Assign functions to the PTP capabiltiies structure for E822 devices.
2248  * Functions which operate across all device families should be set directly
2249  * in ice_ptp_set_caps. Only add functions here which are distinct for E822
2250  * devices.
2251  */
2252 static void
2253 ice_ptp_set_funcs_e822(struct ice_pf *pf, struct ptp_clock_info *info)
2254 {
2255 #ifdef CONFIG_ICE_HWTS
2256 	if (boot_cpu_has(X86_FEATURE_ART) &&
2257 	    boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ))
2258 		info->getcrosststamp = ice_ptp_getcrosststamp_e822;
2259 #endif /* CONFIG_ICE_HWTS */
2260 }
2261 
2262 /**
2263  * ice_ptp_set_funcs_e810 - Set specialized functions for E810 support
2264  * @pf: Board private structure
2265  * @info: PTP info to fill
2266  *
2267  * Assign functions to the PTP capabiltiies structure for E810 devices.
2268  * Functions which operate across all device families should be set directly
2269  * in ice_ptp_set_caps. Only add functions here which are distinct for e810
2270  * devices.
2271  */
2272 static void
2273 ice_ptp_set_funcs_e810(struct ice_pf *pf, struct ptp_clock_info *info)
2274 {
2275 	info->enable = ice_ptp_gpio_enable_e810;
2276 	ice_ptp_setup_pins_e810(pf, info);
2277 }
2278 
2279 /**
2280  * ice_ptp_set_caps - Set PTP capabilities
2281  * @pf: Board private structure
2282  */
2283 static void ice_ptp_set_caps(struct ice_pf *pf)
2284 {
2285 	struct ptp_clock_info *info = &pf->ptp.info;
2286 	struct device *dev = ice_pf_to_dev(pf);
2287 
2288 	snprintf(info->name, sizeof(info->name) - 1, "%s-%s-clk",
2289 		 dev_driver_string(dev), dev_name(dev));
2290 	info->owner = THIS_MODULE;
2291 	info->max_adj = 999999999;
2292 	info->adjtime = ice_ptp_adjtime;
2293 	info->adjfine = ice_ptp_adjfine;
2294 	info->gettimex64 = ice_ptp_gettimex64;
2295 	info->settime64 = ice_ptp_settime64;
2296 
2297 	if (ice_is_e810(&pf->hw))
2298 		ice_ptp_set_funcs_e810(pf, info);
2299 	else
2300 		ice_ptp_set_funcs_e822(pf, info);
2301 }
2302 
2303 /**
2304  * ice_ptp_create_clock - Create PTP clock device for userspace
2305  * @pf: Board private structure
2306  *
2307  * This function creates a new PTP clock device. It only creates one if we
2308  * don't already have one. Will return error if it can't create one, but success
2309  * if we already have a device. Should be used by ice_ptp_init to create clock
2310  * initially, and prevent global resets from creating new clock devices.
2311  */
2312 static long ice_ptp_create_clock(struct ice_pf *pf)
2313 {
2314 	struct ptp_clock_info *info;
2315 	struct ptp_clock *clock;
2316 	struct device *dev;
2317 
2318 	/* No need to create a clock device if we already have one */
2319 	if (pf->ptp.clock)
2320 		return 0;
2321 
2322 	ice_ptp_set_caps(pf);
2323 
2324 	info = &pf->ptp.info;
2325 	dev = ice_pf_to_dev(pf);
2326 
2327 	/* Attempt to register the clock before enabling the hardware. */
2328 	clock = ptp_clock_register(info, dev);
2329 	if (IS_ERR(clock))
2330 		return PTR_ERR(clock);
2331 
2332 	pf->ptp.clock = clock;
2333 
2334 	return 0;
2335 }
2336 
2337 /**
2338  * ice_ptp_request_ts - Request an available Tx timestamp index
2339  * @tx: the PTP Tx timestamp tracker to request from
2340  * @skb: the SKB to associate with this timestamp request
2341  */
2342 s8 ice_ptp_request_ts(struct ice_ptp_tx *tx, struct sk_buff *skb)
2343 {
2344 	u8 idx;
2345 
2346 	/* Check if this tracker is initialized */
2347 	if (!tx->init || tx->calibrating)
2348 		return -1;
2349 
2350 	spin_lock(&tx->lock);
2351 	/* Find and set the first available index */
2352 	idx = find_first_zero_bit(tx->in_use, tx->len);
2353 	if (idx < tx->len) {
2354 		/* We got a valid index that no other thread could have set. Store
2355 		 * a reference to the skb and the start time to allow discarding old
2356 		 * requests.
2357 		 */
2358 		set_bit(idx, tx->in_use);
2359 		tx->tstamps[idx].start = jiffies;
2360 		tx->tstamps[idx].skb = skb_get(skb);
2361 		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2362 		ice_trace(tx_tstamp_request, skb, idx);
2363 	}
2364 
2365 	spin_unlock(&tx->lock);
2366 
2367 	/* return the appropriate PHY timestamp register index, -1 if no
2368 	 * indexes were available.
2369 	 */
2370 	if (idx >= tx->len)
2371 		return -1;
2372 	else
2373 		return idx + tx->quad_offset;
2374 }
2375 
2376 /**
2377  * ice_ptp_process_ts - Process the PTP Tx timestamps
2378  * @pf: Board private structure
2379  *
2380  * Returns true if timestamps are processed.
2381  */
2382 bool ice_ptp_process_ts(struct ice_pf *pf)
2383 {
2384 	if (pf->ptp.port.tx.init)
2385 		return ice_ptp_tx_tstamp(&pf->ptp.port.tx);
2386 
2387 	return false;
2388 }
2389 
2390 static void ice_ptp_periodic_work(struct kthread_work *work)
2391 {
2392 	struct ice_ptp *ptp = container_of(work, struct ice_ptp, work.work);
2393 	struct ice_pf *pf = container_of(ptp, struct ice_pf, ptp);
2394 	int err;
2395 
2396 	if (!test_bit(ICE_FLAG_PTP, pf->flags))
2397 		return;
2398 
2399 	err = ice_ptp_update_cached_phctime(pf);
2400 
2401 	ice_ptp_tx_tstamp_cleanup(pf, &pf->ptp.port.tx);
2402 
2403 	/* Run twice a second or reschedule if phc update failed */
2404 	kthread_queue_delayed_work(ptp->kworker, &ptp->work,
2405 				   msecs_to_jiffies(err ? 10 : 500));
2406 }
2407 
2408 /**
2409  * ice_ptp_reset - Initialize PTP hardware clock support after reset
2410  * @pf: Board private structure
2411  */
2412 void ice_ptp_reset(struct ice_pf *pf)
2413 {
2414 	struct ice_ptp *ptp = &pf->ptp;
2415 	struct ice_hw *hw = &pf->hw;
2416 	struct timespec64 ts;
2417 	int err, itr = 1;
2418 	u64 time_diff;
2419 
2420 	if (test_bit(ICE_PFR_REQ, pf->state))
2421 		goto pfr;
2422 
2423 	if (!hw->func_caps.ts_func_info.src_tmr_owned)
2424 		goto reset_ts;
2425 
2426 	err = ice_ptp_init_phc(hw);
2427 	if (err)
2428 		goto err;
2429 
2430 	/* Acquire the global hardware lock */
2431 	if (!ice_ptp_lock(hw)) {
2432 		err = -EBUSY;
2433 		goto err;
2434 	}
2435 
2436 	/* Write the increment time value to PHY and LAN */
2437 	err = ice_ptp_write_incval(hw, ice_base_incval(pf));
2438 	if (err) {
2439 		ice_ptp_unlock(hw);
2440 		goto err;
2441 	}
2442 
2443 	/* Write the initial Time value to PHY and LAN using the cached PHC
2444 	 * time before the reset and time difference between stopping and
2445 	 * starting the clock.
2446 	 */
2447 	if (ptp->cached_phc_time) {
2448 		time_diff = ktime_get_real_ns() - ptp->reset_time;
2449 		ts = ns_to_timespec64(ptp->cached_phc_time + time_diff);
2450 	} else {
2451 		ts = ktime_to_timespec64(ktime_get_real());
2452 	}
2453 	err = ice_ptp_write_init(pf, &ts);
2454 	if (err) {
2455 		ice_ptp_unlock(hw);
2456 		goto err;
2457 	}
2458 
2459 	/* Release the global hardware lock */
2460 	ice_ptp_unlock(hw);
2461 
2462 	if (!ice_is_e810(hw)) {
2463 		/* Enable quad interrupts */
2464 		err = ice_ptp_tx_ena_intr(pf, true, itr);
2465 		if (err)
2466 			goto err;
2467 	}
2468 
2469 reset_ts:
2470 	/* Restart the PHY timestamping block */
2471 	ice_ptp_reset_phy_timestamping(pf);
2472 
2473 pfr:
2474 	/* Init Tx structures */
2475 	if (ice_is_e810(&pf->hw)) {
2476 		err = ice_ptp_init_tx_e810(pf, &ptp->port.tx);
2477 	} else {
2478 		kthread_init_delayed_work(&ptp->port.ov_work,
2479 					  ice_ptp_wait_for_offset_valid);
2480 		err = ice_ptp_init_tx_e822(pf, &ptp->port.tx,
2481 					   ptp->port.port_num);
2482 	}
2483 	if (err)
2484 		goto err;
2485 
2486 	set_bit(ICE_FLAG_PTP, pf->flags);
2487 
2488 	/* Start periodic work going */
2489 	kthread_queue_delayed_work(ptp->kworker, &ptp->work, 0);
2490 
2491 	dev_info(ice_pf_to_dev(pf), "PTP reset successful\n");
2492 	return;
2493 
2494 err:
2495 	dev_err(ice_pf_to_dev(pf), "PTP reset failed %d\n", err);
2496 }
2497 
2498 /**
2499  * ice_ptp_prepare_for_reset - Prepare PTP for reset
2500  * @pf: Board private structure
2501  */
2502 void ice_ptp_prepare_for_reset(struct ice_pf *pf)
2503 {
2504 	struct ice_ptp *ptp = &pf->ptp;
2505 	u8 src_tmr;
2506 
2507 	clear_bit(ICE_FLAG_PTP, pf->flags);
2508 
2509 	/* Disable timestamping for both Tx and Rx */
2510 	ice_ptp_cfg_timestamp(pf, false);
2511 
2512 	kthread_cancel_delayed_work_sync(&ptp->work);
2513 	kthread_cancel_work_sync(&ptp->extts_work);
2514 
2515 	if (test_bit(ICE_PFR_REQ, pf->state))
2516 		return;
2517 
2518 	ice_ptp_release_tx_tracker(pf, &pf->ptp.port.tx);
2519 
2520 	/* Disable periodic outputs */
2521 	ice_ptp_disable_all_clkout(pf);
2522 
2523 	src_tmr = ice_get_ptp_src_clock_index(&pf->hw);
2524 
2525 	/* Disable source clock */
2526 	wr32(&pf->hw, GLTSYN_ENA(src_tmr), (u32)~GLTSYN_ENA_TSYN_ENA_M);
2527 
2528 	/* Acquire PHC and system timer to restore after reset */
2529 	ptp->reset_time = ktime_get_real_ns();
2530 }
2531 
2532 /**
2533  * ice_ptp_init_owner - Initialize PTP_1588_CLOCK device
2534  * @pf: Board private structure
2535  *
2536  * Setup and initialize a PTP clock device that represents the device hardware
2537  * clock. Save the clock index for other functions connected to the same
2538  * hardware resource.
2539  */
2540 static int ice_ptp_init_owner(struct ice_pf *pf)
2541 {
2542 	struct ice_hw *hw = &pf->hw;
2543 	struct timespec64 ts;
2544 	int err, itr = 1;
2545 
2546 	err = ice_ptp_init_phc(hw);
2547 	if (err) {
2548 		dev_err(ice_pf_to_dev(pf), "Failed to initialize PHC, err %d\n",
2549 			err);
2550 		return err;
2551 	}
2552 
2553 	/* Acquire the global hardware lock */
2554 	if (!ice_ptp_lock(hw)) {
2555 		err = -EBUSY;
2556 		goto err_exit;
2557 	}
2558 
2559 	/* Write the increment time value to PHY and LAN */
2560 	err = ice_ptp_write_incval(hw, ice_base_incval(pf));
2561 	if (err) {
2562 		ice_ptp_unlock(hw);
2563 		goto err_exit;
2564 	}
2565 
2566 	ts = ktime_to_timespec64(ktime_get_real());
2567 	/* Write the initial Time value to PHY and LAN */
2568 	err = ice_ptp_write_init(pf, &ts);
2569 	if (err) {
2570 		ice_ptp_unlock(hw);
2571 		goto err_exit;
2572 	}
2573 
2574 	/* Release the global hardware lock */
2575 	ice_ptp_unlock(hw);
2576 
2577 	if (!ice_is_e810(hw)) {
2578 		/* Enable quad interrupts */
2579 		err = ice_ptp_tx_ena_intr(pf, true, itr);
2580 		if (err)
2581 			goto err_exit;
2582 	}
2583 
2584 	/* Ensure we have a clock device */
2585 	err = ice_ptp_create_clock(pf);
2586 	if (err)
2587 		goto err_clk;
2588 
2589 	/* Store the PTP clock index for other PFs */
2590 	ice_set_ptp_clock_index(pf);
2591 
2592 	return 0;
2593 
2594 err_clk:
2595 	pf->ptp.clock = NULL;
2596 err_exit:
2597 	return err;
2598 }
2599 
2600 /**
2601  * ice_ptp_init_work - Initialize PTP work threads
2602  * @pf: Board private structure
2603  * @ptp: PF PTP structure
2604  */
2605 static int ice_ptp_init_work(struct ice_pf *pf, struct ice_ptp *ptp)
2606 {
2607 	struct kthread_worker *kworker;
2608 
2609 	/* Initialize work functions */
2610 	kthread_init_delayed_work(&ptp->work, ice_ptp_periodic_work);
2611 	kthread_init_work(&ptp->extts_work, ice_ptp_extts_work);
2612 
2613 	/* Allocate a kworker for handling work required for the ports
2614 	 * connected to the PTP hardware clock.
2615 	 */
2616 	kworker = kthread_create_worker(0, "ice-ptp-%s",
2617 					dev_name(ice_pf_to_dev(pf)));
2618 	if (IS_ERR(kworker))
2619 		return PTR_ERR(kworker);
2620 
2621 	ptp->kworker = kworker;
2622 
2623 	/* Start periodic work going */
2624 	kthread_queue_delayed_work(ptp->kworker, &ptp->work, 0);
2625 
2626 	return 0;
2627 }
2628 
2629 /**
2630  * ice_ptp_init_port - Initialize PTP port structure
2631  * @pf: Board private structure
2632  * @ptp_port: PTP port structure
2633  */
2634 static int ice_ptp_init_port(struct ice_pf *pf, struct ice_ptp_port *ptp_port)
2635 {
2636 	mutex_init(&ptp_port->ps_lock);
2637 
2638 	if (ice_is_e810(&pf->hw))
2639 		return ice_ptp_init_tx_e810(pf, &ptp_port->tx);
2640 
2641 	kthread_init_delayed_work(&ptp_port->ov_work,
2642 				  ice_ptp_wait_for_offset_valid);
2643 	return ice_ptp_init_tx_e822(pf, &ptp_port->tx, ptp_port->port_num);
2644 }
2645 
2646 /**
2647  * ice_ptp_init - Initialize PTP hardware clock support
2648  * @pf: Board private structure
2649  *
2650  * Set up the device for interacting with the PTP hardware clock for all
2651  * functions, both the function that owns the clock hardware, and the
2652  * functions connected to the clock hardware.
2653  *
2654  * The clock owner will allocate and register a ptp_clock with the
2655  * PTP_1588_CLOCK infrastructure. All functions allocate a kthread and work
2656  * items used for asynchronous work such as Tx timestamps and periodic work.
2657  */
2658 void ice_ptp_init(struct ice_pf *pf)
2659 {
2660 	struct ice_ptp *ptp = &pf->ptp;
2661 	struct ice_hw *hw = &pf->hw;
2662 	int err;
2663 
2664 	/* If this function owns the clock hardware, it must allocate and
2665 	 * configure the PTP clock device to represent it.
2666 	 */
2667 	if (hw->func_caps.ts_func_info.src_tmr_owned) {
2668 		err = ice_ptp_init_owner(pf);
2669 		if (err)
2670 			goto err;
2671 	}
2672 
2673 	ptp->port.port_num = hw->pf_id;
2674 	err = ice_ptp_init_port(pf, &ptp->port);
2675 	if (err)
2676 		goto err;
2677 
2678 	/* Start the PHY timestamping block */
2679 	ice_ptp_reset_phy_timestamping(pf);
2680 
2681 	set_bit(ICE_FLAG_PTP, pf->flags);
2682 	err = ice_ptp_init_work(pf, ptp);
2683 	if (err)
2684 		goto err;
2685 
2686 	dev_info(ice_pf_to_dev(pf), "PTP init successful\n");
2687 	return;
2688 
2689 err:
2690 	/* If we registered a PTP clock, release it */
2691 	if (pf->ptp.clock) {
2692 		ptp_clock_unregister(ptp->clock);
2693 		pf->ptp.clock = NULL;
2694 	}
2695 	clear_bit(ICE_FLAG_PTP, pf->flags);
2696 	dev_err(ice_pf_to_dev(pf), "PTP failed %d\n", err);
2697 }
2698 
2699 /**
2700  * ice_ptp_release - Disable the driver/HW support and unregister the clock
2701  * @pf: Board private structure
2702  *
2703  * This function handles the cleanup work required from the initialization by
2704  * clearing out the important information and unregistering the clock
2705  */
2706 void ice_ptp_release(struct ice_pf *pf)
2707 {
2708 	if (!test_bit(ICE_FLAG_PTP, pf->flags))
2709 		return;
2710 
2711 	/* Disable timestamping for both Tx and Rx */
2712 	ice_ptp_cfg_timestamp(pf, false);
2713 
2714 	ice_ptp_release_tx_tracker(pf, &pf->ptp.port.tx);
2715 
2716 	clear_bit(ICE_FLAG_PTP, pf->flags);
2717 
2718 	kthread_cancel_delayed_work_sync(&pf->ptp.work);
2719 
2720 	ice_ptp_port_phy_stop(&pf->ptp.port);
2721 	mutex_destroy(&pf->ptp.port.ps_lock);
2722 	if (pf->ptp.kworker) {
2723 		kthread_destroy_worker(pf->ptp.kworker);
2724 		pf->ptp.kworker = NULL;
2725 	}
2726 
2727 	if (!pf->ptp.clock)
2728 		return;
2729 
2730 	/* Disable periodic outputs */
2731 	ice_ptp_disable_all_clkout(pf);
2732 
2733 	ice_clear_ptp_clock_index(pf);
2734 	ptp_clock_unregister(pf->ptp.clock);
2735 	pf->ptp.clock = NULL;
2736 
2737 	dev_info(ice_pf_to_dev(pf), "Removed PTP clock\n");
2738 }
2739