1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (C) 2021, Intel Corporation. */ 3 4 #include "ice.h" 5 #include "ice_lib.h" 6 #include "ice_trace.h" 7 8 #define E810_OUT_PROP_DELAY_NS 1 9 10 #define UNKNOWN_INCVAL_E822 0x100000000ULL 11 12 static const struct ptp_pin_desc ice_pin_desc_e810t[] = { 13 /* name idx func chan */ 14 { "GNSS", GNSS, PTP_PF_EXTTS, 0, { 0, } }, 15 { "SMA1", SMA1, PTP_PF_NONE, 1, { 0, } }, 16 { "U.FL1", UFL1, PTP_PF_NONE, 1, { 0, } }, 17 { "SMA2", SMA2, PTP_PF_NONE, 2, { 0, } }, 18 { "U.FL2", UFL2, PTP_PF_NONE, 2, { 0, } }, 19 }; 20 21 /** 22 * ice_get_sma_config_e810t 23 * @hw: pointer to the hw struct 24 * @ptp_pins: pointer to the ptp_pin_desc struture 25 * 26 * Read the configuration of the SMA control logic and put it into the 27 * ptp_pin_desc structure 28 */ 29 static int 30 ice_get_sma_config_e810t(struct ice_hw *hw, struct ptp_pin_desc *ptp_pins) 31 { 32 u8 data, i; 33 int status; 34 35 /* Read initial pin state */ 36 status = ice_read_sma_ctrl_e810t(hw, &data); 37 if (status) 38 return status; 39 40 /* initialize with defaults */ 41 for (i = 0; i < NUM_PTP_PINS_E810T; i++) { 42 snprintf(ptp_pins[i].name, sizeof(ptp_pins[i].name), 43 "%s", ice_pin_desc_e810t[i].name); 44 ptp_pins[i].index = ice_pin_desc_e810t[i].index; 45 ptp_pins[i].func = ice_pin_desc_e810t[i].func; 46 ptp_pins[i].chan = ice_pin_desc_e810t[i].chan; 47 } 48 49 /* Parse SMA1/UFL1 */ 50 switch (data & ICE_SMA1_MASK_E810T) { 51 case ICE_SMA1_MASK_E810T: 52 default: 53 ptp_pins[SMA1].func = PTP_PF_NONE; 54 ptp_pins[UFL1].func = PTP_PF_NONE; 55 break; 56 case ICE_SMA1_DIR_EN_E810T: 57 ptp_pins[SMA1].func = PTP_PF_PEROUT; 58 ptp_pins[UFL1].func = PTP_PF_NONE; 59 break; 60 case ICE_SMA1_TX_EN_E810T: 61 ptp_pins[SMA1].func = PTP_PF_EXTTS; 62 ptp_pins[UFL1].func = PTP_PF_NONE; 63 break; 64 case 0: 65 ptp_pins[SMA1].func = PTP_PF_EXTTS; 66 ptp_pins[UFL1].func = PTP_PF_PEROUT; 67 break; 68 } 69 70 /* Parse SMA2/UFL2 */ 71 switch (data & ICE_SMA2_MASK_E810T) { 72 case ICE_SMA2_MASK_E810T: 73 default: 74 ptp_pins[SMA2].func = PTP_PF_NONE; 75 ptp_pins[UFL2].func = PTP_PF_NONE; 76 break; 77 case (ICE_SMA2_TX_EN_E810T | ICE_SMA2_UFL2_RX_DIS_E810T): 78 ptp_pins[SMA2].func = PTP_PF_EXTTS; 79 ptp_pins[UFL2].func = PTP_PF_NONE; 80 break; 81 case (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_UFL2_RX_DIS_E810T): 82 ptp_pins[SMA2].func = PTP_PF_PEROUT; 83 ptp_pins[UFL2].func = PTP_PF_NONE; 84 break; 85 case (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_TX_EN_E810T): 86 ptp_pins[SMA2].func = PTP_PF_NONE; 87 ptp_pins[UFL2].func = PTP_PF_EXTTS; 88 break; 89 case ICE_SMA2_DIR_EN_E810T: 90 ptp_pins[SMA2].func = PTP_PF_PEROUT; 91 ptp_pins[UFL2].func = PTP_PF_EXTTS; 92 break; 93 } 94 95 return 0; 96 } 97 98 /** 99 * ice_ptp_set_sma_config_e810t 100 * @hw: pointer to the hw struct 101 * @ptp_pins: pointer to the ptp_pin_desc struture 102 * 103 * Set the configuration of the SMA control logic based on the configuration in 104 * num_pins parameter 105 */ 106 static int 107 ice_ptp_set_sma_config_e810t(struct ice_hw *hw, 108 const struct ptp_pin_desc *ptp_pins) 109 { 110 int status; 111 u8 data; 112 113 /* SMA1 and UFL1 cannot be set to TX at the same time */ 114 if (ptp_pins[SMA1].func == PTP_PF_PEROUT && 115 ptp_pins[UFL1].func == PTP_PF_PEROUT) 116 return -EINVAL; 117 118 /* SMA2 and UFL2 cannot be set to RX at the same time */ 119 if (ptp_pins[SMA2].func == PTP_PF_EXTTS && 120 ptp_pins[UFL2].func == PTP_PF_EXTTS) 121 return -EINVAL; 122 123 /* Read initial pin state value */ 124 status = ice_read_sma_ctrl_e810t(hw, &data); 125 if (status) 126 return status; 127 128 /* Set the right sate based on the desired configuration */ 129 data &= ~ICE_SMA1_MASK_E810T; 130 if (ptp_pins[SMA1].func == PTP_PF_NONE && 131 ptp_pins[UFL1].func == PTP_PF_NONE) { 132 dev_info(ice_hw_to_dev(hw), "SMA1 + U.FL1 disabled"); 133 data |= ICE_SMA1_MASK_E810T; 134 } else if (ptp_pins[SMA1].func == PTP_PF_EXTTS && 135 ptp_pins[UFL1].func == PTP_PF_NONE) { 136 dev_info(ice_hw_to_dev(hw), "SMA1 RX"); 137 data |= ICE_SMA1_TX_EN_E810T; 138 } else if (ptp_pins[SMA1].func == PTP_PF_NONE && 139 ptp_pins[UFL1].func == PTP_PF_PEROUT) { 140 /* U.FL 1 TX will always enable SMA 1 RX */ 141 dev_info(ice_hw_to_dev(hw), "SMA1 RX + U.FL1 TX"); 142 } else if (ptp_pins[SMA1].func == PTP_PF_EXTTS && 143 ptp_pins[UFL1].func == PTP_PF_PEROUT) { 144 dev_info(ice_hw_to_dev(hw), "SMA1 RX + U.FL1 TX"); 145 } else if (ptp_pins[SMA1].func == PTP_PF_PEROUT && 146 ptp_pins[UFL1].func == PTP_PF_NONE) { 147 dev_info(ice_hw_to_dev(hw), "SMA1 TX"); 148 data |= ICE_SMA1_DIR_EN_E810T; 149 } 150 151 data &= ~ICE_SMA2_MASK_E810T; 152 if (ptp_pins[SMA2].func == PTP_PF_NONE && 153 ptp_pins[UFL2].func == PTP_PF_NONE) { 154 dev_info(ice_hw_to_dev(hw), "SMA2 + U.FL2 disabled"); 155 data |= ICE_SMA2_MASK_E810T; 156 } else if (ptp_pins[SMA2].func == PTP_PF_EXTTS && 157 ptp_pins[UFL2].func == PTP_PF_NONE) { 158 dev_info(ice_hw_to_dev(hw), "SMA2 RX"); 159 data |= (ICE_SMA2_TX_EN_E810T | 160 ICE_SMA2_UFL2_RX_DIS_E810T); 161 } else if (ptp_pins[SMA2].func == PTP_PF_NONE && 162 ptp_pins[UFL2].func == PTP_PF_EXTTS) { 163 dev_info(ice_hw_to_dev(hw), "UFL2 RX"); 164 data |= (ICE_SMA2_DIR_EN_E810T | ICE_SMA2_TX_EN_E810T); 165 } else if (ptp_pins[SMA2].func == PTP_PF_PEROUT && 166 ptp_pins[UFL2].func == PTP_PF_NONE) { 167 dev_info(ice_hw_to_dev(hw), "SMA2 TX"); 168 data |= (ICE_SMA2_DIR_EN_E810T | 169 ICE_SMA2_UFL2_RX_DIS_E810T); 170 } else if (ptp_pins[SMA2].func == PTP_PF_PEROUT && 171 ptp_pins[UFL2].func == PTP_PF_EXTTS) { 172 dev_info(ice_hw_to_dev(hw), "SMA2 TX + U.FL2 RX"); 173 data |= ICE_SMA2_DIR_EN_E810T; 174 } 175 176 return ice_write_sma_ctrl_e810t(hw, data); 177 } 178 179 /** 180 * ice_ptp_set_sma_e810t 181 * @info: the driver's PTP info structure 182 * @pin: pin index in kernel structure 183 * @func: Pin function to be set (PTP_PF_NONE, PTP_PF_EXTTS or PTP_PF_PEROUT) 184 * 185 * Set the configuration of a single SMA pin 186 */ 187 static int 188 ice_ptp_set_sma_e810t(struct ptp_clock_info *info, unsigned int pin, 189 enum ptp_pin_function func) 190 { 191 struct ptp_pin_desc ptp_pins[NUM_PTP_PINS_E810T]; 192 struct ice_pf *pf = ptp_info_to_pf(info); 193 struct ice_hw *hw = &pf->hw; 194 int err; 195 196 if (pin < SMA1 || func > PTP_PF_PEROUT) 197 return -EOPNOTSUPP; 198 199 err = ice_get_sma_config_e810t(hw, ptp_pins); 200 if (err) 201 return err; 202 203 /* Disable the same function on the other pin sharing the channel */ 204 if (pin == SMA1 && ptp_pins[UFL1].func == func) 205 ptp_pins[UFL1].func = PTP_PF_NONE; 206 if (pin == UFL1 && ptp_pins[SMA1].func == func) 207 ptp_pins[SMA1].func = PTP_PF_NONE; 208 209 if (pin == SMA2 && ptp_pins[UFL2].func == func) 210 ptp_pins[UFL2].func = PTP_PF_NONE; 211 if (pin == UFL2 && ptp_pins[SMA2].func == func) 212 ptp_pins[SMA2].func = PTP_PF_NONE; 213 214 /* Set up new pin function in the temp table */ 215 ptp_pins[pin].func = func; 216 217 return ice_ptp_set_sma_config_e810t(hw, ptp_pins); 218 } 219 220 /** 221 * ice_verify_pin_e810t 222 * @info: the driver's PTP info structure 223 * @pin: Pin index 224 * @func: Assigned function 225 * @chan: Assigned channel 226 * 227 * Verify if pin supports requested pin function. If the Check pins consistency. 228 * Reconfigure the SMA logic attached to the given pin to enable its 229 * desired functionality 230 */ 231 static int 232 ice_verify_pin_e810t(struct ptp_clock_info *info, unsigned int pin, 233 enum ptp_pin_function func, unsigned int chan) 234 { 235 /* Don't allow channel reassignment */ 236 if (chan != ice_pin_desc_e810t[pin].chan) 237 return -EOPNOTSUPP; 238 239 /* Check if functions are properly assigned */ 240 switch (func) { 241 case PTP_PF_NONE: 242 break; 243 case PTP_PF_EXTTS: 244 if (pin == UFL1) 245 return -EOPNOTSUPP; 246 break; 247 case PTP_PF_PEROUT: 248 if (pin == UFL2 || pin == GNSS) 249 return -EOPNOTSUPP; 250 break; 251 case PTP_PF_PHYSYNC: 252 return -EOPNOTSUPP; 253 } 254 255 return ice_ptp_set_sma_e810t(info, pin, func); 256 } 257 258 /** 259 * ice_set_tx_tstamp - Enable or disable Tx timestamping 260 * @pf: The PF pointer to search in 261 * @on: bool value for whether timestamps are enabled or disabled 262 */ 263 static void ice_set_tx_tstamp(struct ice_pf *pf, bool on) 264 { 265 struct ice_vsi *vsi; 266 u32 val; 267 u16 i; 268 269 vsi = ice_get_main_vsi(pf); 270 if (!vsi) 271 return; 272 273 /* Set the timestamp enable flag for all the Tx rings */ 274 ice_for_each_txq(vsi, i) { 275 if (!vsi->tx_rings[i]) 276 continue; 277 vsi->tx_rings[i]->ptp_tx = on; 278 } 279 280 /* Configure the Tx timestamp interrupt */ 281 val = rd32(&pf->hw, PFINT_OICR_ENA); 282 if (on) 283 val |= PFINT_OICR_TSYN_TX_M; 284 else 285 val &= ~PFINT_OICR_TSYN_TX_M; 286 wr32(&pf->hw, PFINT_OICR_ENA, val); 287 288 pf->ptp.tstamp_config.tx_type = on ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 289 } 290 291 /** 292 * ice_set_rx_tstamp - Enable or disable Rx timestamping 293 * @pf: The PF pointer to search in 294 * @on: bool value for whether timestamps are enabled or disabled 295 */ 296 static void ice_set_rx_tstamp(struct ice_pf *pf, bool on) 297 { 298 struct ice_vsi *vsi; 299 u16 i; 300 301 vsi = ice_get_main_vsi(pf); 302 if (!vsi) 303 return; 304 305 /* Set the timestamp flag for all the Rx rings */ 306 ice_for_each_rxq(vsi, i) { 307 if (!vsi->rx_rings[i]) 308 continue; 309 vsi->rx_rings[i]->ptp_rx = on; 310 } 311 312 pf->ptp.tstamp_config.rx_filter = on ? HWTSTAMP_FILTER_ALL : 313 HWTSTAMP_FILTER_NONE; 314 } 315 316 /** 317 * ice_ptp_cfg_timestamp - Configure timestamp for init/deinit 318 * @pf: Board private structure 319 * @ena: bool value to enable or disable time stamp 320 * 321 * This function will configure timestamping during PTP initialization 322 * and deinitialization 323 */ 324 void ice_ptp_cfg_timestamp(struct ice_pf *pf, bool ena) 325 { 326 ice_set_tx_tstamp(pf, ena); 327 ice_set_rx_tstamp(pf, ena); 328 } 329 330 /** 331 * ice_get_ptp_clock_index - Get the PTP clock index 332 * @pf: the PF pointer 333 * 334 * Determine the clock index of the PTP clock associated with this device. If 335 * this is the PF controlling the clock, just use the local access to the 336 * clock device pointer. 337 * 338 * Otherwise, read from the driver shared parameters to determine the clock 339 * index value. 340 * 341 * Returns: the index of the PTP clock associated with this device, or -1 if 342 * there is no associated clock. 343 */ 344 int ice_get_ptp_clock_index(struct ice_pf *pf) 345 { 346 struct device *dev = ice_pf_to_dev(pf); 347 enum ice_aqc_driver_params param_idx; 348 struct ice_hw *hw = &pf->hw; 349 u8 tmr_idx; 350 u32 value; 351 int err; 352 353 /* Use the ptp_clock structure if we're the main PF */ 354 if (pf->ptp.clock) 355 return ptp_clock_index(pf->ptp.clock); 356 357 tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc; 358 if (!tmr_idx) 359 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0; 360 else 361 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1; 362 363 err = ice_aq_get_driver_param(hw, param_idx, &value, NULL); 364 if (err) { 365 dev_err(dev, "Failed to read PTP clock index parameter, err %d aq_err %s\n", 366 err, ice_aq_str(hw->adminq.sq_last_status)); 367 return -1; 368 } 369 370 /* The PTP clock index is an integer, and will be between 0 and 371 * INT_MAX. The highest bit of the driver shared parameter is used to 372 * indicate whether or not the currently stored clock index is valid. 373 */ 374 if (!(value & PTP_SHARED_CLK_IDX_VALID)) 375 return -1; 376 377 return value & ~PTP_SHARED_CLK_IDX_VALID; 378 } 379 380 /** 381 * ice_set_ptp_clock_index - Set the PTP clock index 382 * @pf: the PF pointer 383 * 384 * Set the PTP clock index for this device into the shared driver parameters, 385 * so that other PFs associated with this device can read it. 386 * 387 * If the PF is unable to store the clock index, it will log an error, but 388 * will continue operating PTP. 389 */ 390 static void ice_set_ptp_clock_index(struct ice_pf *pf) 391 { 392 struct device *dev = ice_pf_to_dev(pf); 393 enum ice_aqc_driver_params param_idx; 394 struct ice_hw *hw = &pf->hw; 395 u8 tmr_idx; 396 u32 value; 397 int err; 398 399 if (!pf->ptp.clock) 400 return; 401 402 tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc; 403 if (!tmr_idx) 404 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0; 405 else 406 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1; 407 408 value = (u32)ptp_clock_index(pf->ptp.clock); 409 if (value > INT_MAX) { 410 dev_err(dev, "PTP Clock index is too large to store\n"); 411 return; 412 } 413 value |= PTP_SHARED_CLK_IDX_VALID; 414 415 err = ice_aq_set_driver_param(hw, param_idx, value, NULL); 416 if (err) { 417 dev_err(dev, "Failed to set PTP clock index parameter, err %d aq_err %s\n", 418 err, ice_aq_str(hw->adminq.sq_last_status)); 419 } 420 } 421 422 /** 423 * ice_clear_ptp_clock_index - Clear the PTP clock index 424 * @pf: the PF pointer 425 * 426 * Clear the PTP clock index for this device. Must be called when 427 * unregistering the PTP clock, in order to ensure other PFs stop reporting 428 * a clock object that no longer exists. 429 */ 430 static void ice_clear_ptp_clock_index(struct ice_pf *pf) 431 { 432 struct device *dev = ice_pf_to_dev(pf); 433 enum ice_aqc_driver_params param_idx; 434 struct ice_hw *hw = &pf->hw; 435 u8 tmr_idx; 436 int err; 437 438 /* Do not clear the index if we don't own the timer */ 439 if (!hw->func_caps.ts_func_info.src_tmr_owned) 440 return; 441 442 tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc; 443 if (!tmr_idx) 444 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0; 445 else 446 param_idx = ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1; 447 448 err = ice_aq_set_driver_param(hw, param_idx, 0, NULL); 449 if (err) { 450 dev_dbg(dev, "Failed to clear PTP clock index parameter, err %d aq_err %s\n", 451 err, ice_aq_str(hw->adminq.sq_last_status)); 452 } 453 } 454 455 /** 456 * ice_ptp_read_src_clk_reg - Read the source clock register 457 * @pf: Board private structure 458 * @sts: Optional parameter for holding a pair of system timestamps from 459 * the system clock. Will be ignored if NULL is given. 460 */ 461 static u64 462 ice_ptp_read_src_clk_reg(struct ice_pf *pf, struct ptp_system_timestamp *sts) 463 { 464 struct ice_hw *hw = &pf->hw; 465 u32 hi, lo, lo2; 466 u8 tmr_idx; 467 468 tmr_idx = ice_get_ptp_src_clock_index(hw); 469 /* Read the system timestamp pre PHC read */ 470 ptp_read_system_prets(sts); 471 472 lo = rd32(hw, GLTSYN_TIME_L(tmr_idx)); 473 474 /* Read the system timestamp post PHC read */ 475 ptp_read_system_postts(sts); 476 477 hi = rd32(hw, GLTSYN_TIME_H(tmr_idx)); 478 lo2 = rd32(hw, GLTSYN_TIME_L(tmr_idx)); 479 480 if (lo2 < lo) { 481 /* if TIME_L rolled over read TIME_L again and update 482 * system timestamps 483 */ 484 ptp_read_system_prets(sts); 485 lo = rd32(hw, GLTSYN_TIME_L(tmr_idx)); 486 ptp_read_system_postts(sts); 487 hi = rd32(hw, GLTSYN_TIME_H(tmr_idx)); 488 } 489 490 return ((u64)hi << 32) | lo; 491 } 492 493 /** 494 * ice_ptp_extend_32b_ts - Convert a 32b nanoseconds timestamp to 64b 495 * @cached_phc_time: recently cached copy of PHC time 496 * @in_tstamp: Ingress/egress 32b nanoseconds timestamp value 497 * 498 * Hardware captures timestamps which contain only 32 bits of nominal 499 * nanoseconds, as opposed to the 64bit timestamps that the stack expects. 500 * Note that the captured timestamp values may be 40 bits, but the lower 501 * 8 bits are sub-nanoseconds and generally discarded. 502 * 503 * Extend the 32bit nanosecond timestamp using the following algorithm and 504 * assumptions: 505 * 506 * 1) have a recently cached copy of the PHC time 507 * 2) assume that the in_tstamp was captured 2^31 nanoseconds (~2.1 508 * seconds) before or after the PHC time was captured. 509 * 3) calculate the delta between the cached time and the timestamp 510 * 4) if the delta is smaller than 2^31 nanoseconds, then the timestamp was 511 * captured after the PHC time. In this case, the full timestamp is just 512 * the cached PHC time plus the delta. 513 * 5) otherwise, if the delta is larger than 2^31 nanoseconds, then the 514 * timestamp was captured *before* the PHC time, i.e. because the PHC 515 * cache was updated after the timestamp was captured by hardware. In this 516 * case, the full timestamp is the cached time minus the inverse delta. 517 * 518 * This algorithm works even if the PHC time was updated after a Tx timestamp 519 * was requested, but before the Tx timestamp event was reported from 520 * hardware. 521 * 522 * This calculation primarily relies on keeping the cached PHC time up to 523 * date. If the timestamp was captured more than 2^31 nanoseconds after the 524 * PHC time, it is possible that the lower 32bits of PHC time have 525 * overflowed more than once, and we might generate an incorrect timestamp. 526 * 527 * This is prevented by (a) periodically updating the cached PHC time once 528 * a second, and (b) discarding any Tx timestamp packet if it has waited for 529 * a timestamp for more than one second. 530 */ 531 static u64 ice_ptp_extend_32b_ts(u64 cached_phc_time, u32 in_tstamp) 532 { 533 u32 delta, phc_time_lo; 534 u64 ns; 535 536 /* Extract the lower 32 bits of the PHC time */ 537 phc_time_lo = (u32)cached_phc_time; 538 539 /* Calculate the delta between the lower 32bits of the cached PHC 540 * time and the in_tstamp value 541 */ 542 delta = (in_tstamp - phc_time_lo); 543 544 /* Do not assume that the in_tstamp is always more recent than the 545 * cached PHC time. If the delta is large, it indicates that the 546 * in_tstamp was taken in the past, and should be converted 547 * forward. 548 */ 549 if (delta > (U32_MAX / 2)) { 550 /* reverse the delta calculation here */ 551 delta = (phc_time_lo - in_tstamp); 552 ns = cached_phc_time - delta; 553 } else { 554 ns = cached_phc_time + delta; 555 } 556 557 return ns; 558 } 559 560 /** 561 * ice_ptp_extend_40b_ts - Convert a 40b timestamp to 64b nanoseconds 562 * @pf: Board private structure 563 * @in_tstamp: Ingress/egress 40b timestamp value 564 * 565 * The Tx and Rx timestamps are 40 bits wide, including 32 bits of nominal 566 * nanoseconds, 7 bits of sub-nanoseconds, and a valid bit. 567 * 568 * *--------------------------------------------------------------* 569 * | 32 bits of nanoseconds | 7 high bits of sub ns underflow | v | 570 * *--------------------------------------------------------------* 571 * 572 * The low bit is an indicator of whether the timestamp is valid. The next 573 * 7 bits are a capture of the upper 7 bits of the sub-nanosecond underflow, 574 * and the remaining 32 bits are the lower 32 bits of the PHC timer. 575 * 576 * It is assumed that the caller verifies the timestamp is valid prior to 577 * calling this function. 578 * 579 * Extract the 32bit nominal nanoseconds and extend them. Use the cached PHC 580 * time stored in the device private PTP structure as the basis for timestamp 581 * extension. 582 * 583 * See ice_ptp_extend_32b_ts for a detailed explanation of the extension 584 * algorithm. 585 */ 586 static u64 ice_ptp_extend_40b_ts(struct ice_pf *pf, u64 in_tstamp) 587 { 588 const u64 mask = GENMASK_ULL(31, 0); 589 unsigned long discard_time; 590 591 /* Discard the hardware timestamp if the cached PHC time is too old */ 592 discard_time = pf->ptp.cached_phc_jiffies + msecs_to_jiffies(2000); 593 if (time_is_before_jiffies(discard_time)) { 594 pf->ptp.tx_hwtstamp_discarded++; 595 return 0; 596 } 597 598 return ice_ptp_extend_32b_ts(pf->ptp.cached_phc_time, 599 (in_tstamp >> 8) & mask); 600 } 601 602 /** 603 * ice_ptp_tx_tstamp - Process Tx timestamps for a port 604 * @tx: the PTP Tx timestamp tracker 605 * 606 * Process timestamps captured by the PHY associated with this port. To do 607 * this, loop over each index with a waiting skb. 608 * 609 * If a given index has a valid timestamp, perform the following steps: 610 * 611 * 1) copy the timestamp out of the PHY register 612 * 4) clear the timestamp valid bit in the PHY register 613 * 5) unlock the index by clearing the associated in_use bit. 614 * 2) extend the 40b timestamp value to get a 64bit timestamp 615 * 3) send that timestamp to the stack 616 * 617 * Returns true if all timestamps were handled, and false if any slots remain 618 * without a timestamp. 619 * 620 * After looping, if we still have waiting SKBs, return false. This may cause 621 * us effectively poll even when not strictly necessary. We do this because 622 * it's possible a new timestamp was requested around the same time as the 623 * interrupt. In some cases hardware might not interrupt us again when the 624 * timestamp is captured. 625 * 626 * Note that we only take the tracking lock when clearing the bit and when 627 * checking if we need to re-queue this task. The only place where bits can be 628 * set is the hard xmit routine where an SKB has a request flag set. The only 629 * places where we clear bits are this work function, or the periodic cleanup 630 * thread. If the cleanup thread clears a bit we're processing we catch it 631 * when we lock to clear the bit and then grab the SKB pointer. If a Tx thread 632 * starts a new timestamp, we might not begin processing it right away but we 633 * will notice it at the end when we re-queue the task. If a Tx thread starts 634 * a new timestamp just after this function exits without re-queuing, 635 * the interrupt when the timestamp finishes should trigger. Avoiding holding 636 * the lock for the entire function is important in order to ensure that Tx 637 * threads do not get blocked while waiting for the lock. 638 */ 639 static bool ice_ptp_tx_tstamp(struct ice_ptp_tx *tx) 640 { 641 struct ice_ptp_port *ptp_port; 642 bool ts_handled = true; 643 struct ice_pf *pf; 644 u8 idx; 645 646 if (!tx->init) 647 return true; 648 649 ptp_port = container_of(tx, struct ice_ptp_port, tx); 650 pf = ptp_port_to_pf(ptp_port); 651 652 for_each_set_bit(idx, tx->in_use, tx->len) { 653 struct skb_shared_hwtstamps shhwtstamps = {}; 654 u8 phy_idx = idx + tx->offset; 655 u64 raw_tstamp, tstamp; 656 struct sk_buff *skb; 657 int err; 658 659 ice_trace(tx_tstamp_fw_req, tx->tstamps[idx].skb, idx); 660 661 err = ice_read_phy_tstamp(&pf->hw, tx->block, phy_idx, 662 &raw_tstamp); 663 if (err) 664 continue; 665 666 ice_trace(tx_tstamp_fw_done, tx->tstamps[idx].skb, idx); 667 668 /* Check if the timestamp is invalid or stale */ 669 if (!(raw_tstamp & ICE_PTP_TS_VALID) || 670 raw_tstamp == tx->tstamps[idx].cached_tstamp) 671 continue; 672 673 /* The timestamp is valid, so we'll go ahead and clear this 674 * index and then send the timestamp up to the stack. 675 */ 676 spin_lock(&tx->lock); 677 tx->tstamps[idx].cached_tstamp = raw_tstamp; 678 clear_bit(idx, tx->in_use); 679 skb = tx->tstamps[idx].skb; 680 tx->tstamps[idx].skb = NULL; 681 spin_unlock(&tx->lock); 682 683 /* it's (unlikely but) possible we raced with the cleanup 684 * thread for discarding old timestamp requests. 685 */ 686 if (!skb) 687 continue; 688 689 /* Extend the timestamp using cached PHC time */ 690 tstamp = ice_ptp_extend_40b_ts(pf, raw_tstamp); 691 if (tstamp) { 692 shhwtstamps.hwtstamp = ns_to_ktime(tstamp); 693 ice_trace(tx_tstamp_complete, skb, idx); 694 } 695 696 skb_tstamp_tx(skb, &shhwtstamps); 697 dev_kfree_skb_any(skb); 698 } 699 700 /* Check if we still have work to do. If so, re-queue this task to 701 * poll for remaining timestamps. 702 */ 703 spin_lock(&tx->lock); 704 if (!bitmap_empty(tx->in_use, tx->len)) 705 ts_handled = false; 706 spin_unlock(&tx->lock); 707 708 return ts_handled; 709 } 710 711 /** 712 * ice_ptp_alloc_tx_tracker - Initialize tracking for Tx timestamps 713 * @tx: Tx tracking structure to initialize 714 * 715 * Assumes that the length has already been initialized. Do not call directly, 716 * use the ice_ptp_init_tx_* instead. 717 */ 718 static int 719 ice_ptp_alloc_tx_tracker(struct ice_ptp_tx *tx) 720 { 721 tx->tstamps = kcalloc(tx->len, sizeof(*tx->tstamps), GFP_KERNEL); 722 if (!tx->tstamps) 723 return -ENOMEM; 724 725 tx->in_use = bitmap_zalloc(tx->len, GFP_KERNEL); 726 if (!tx->in_use) { 727 kfree(tx->tstamps); 728 tx->tstamps = NULL; 729 return -ENOMEM; 730 } 731 732 spin_lock_init(&tx->lock); 733 734 tx->init = 1; 735 736 return 0; 737 } 738 739 /** 740 * ice_ptp_flush_tx_tracker - Flush any remaining timestamps from the tracker 741 * @pf: Board private structure 742 * @tx: the tracker to flush 743 */ 744 static void 745 ice_ptp_flush_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx) 746 { 747 u8 idx; 748 749 for (idx = 0; idx < tx->len; idx++) { 750 u8 phy_idx = idx + tx->offset; 751 752 spin_lock(&tx->lock); 753 if (tx->tstamps[idx].skb) { 754 dev_kfree_skb_any(tx->tstamps[idx].skb); 755 tx->tstamps[idx].skb = NULL; 756 pf->ptp.tx_hwtstamp_flushed++; 757 } 758 clear_bit(idx, tx->in_use); 759 spin_unlock(&tx->lock); 760 761 /* Clear any potential residual timestamp in the PHY block */ 762 if (!pf->hw.reset_ongoing) 763 ice_clear_phy_tstamp(&pf->hw, tx->block, phy_idx); 764 } 765 } 766 767 /** 768 * ice_ptp_release_tx_tracker - Release allocated memory for Tx tracker 769 * @pf: Board private structure 770 * @tx: Tx tracking structure to release 771 * 772 * Free memory associated with the Tx timestamp tracker. 773 */ 774 static void 775 ice_ptp_release_tx_tracker(struct ice_pf *pf, struct ice_ptp_tx *tx) 776 { 777 tx->init = 0; 778 779 ice_ptp_flush_tx_tracker(pf, tx); 780 781 kfree(tx->tstamps); 782 tx->tstamps = NULL; 783 784 bitmap_free(tx->in_use); 785 tx->in_use = NULL; 786 787 tx->len = 0; 788 } 789 790 /** 791 * ice_ptp_init_tx_e822 - Initialize tracking for Tx timestamps 792 * @pf: Board private structure 793 * @tx: the Tx tracking structure to initialize 794 * @port: the port this structure tracks 795 * 796 * Initialize the Tx timestamp tracker for this port. For generic MAC devices, 797 * the timestamp block is shared for all ports in the same quad. To avoid 798 * ports using the same timestamp index, logically break the block of 799 * registers into chunks based on the port number. 800 */ 801 static int 802 ice_ptp_init_tx_e822(struct ice_pf *pf, struct ice_ptp_tx *tx, u8 port) 803 { 804 tx->block = port / ICE_PORTS_PER_QUAD; 805 tx->offset = (port % ICE_PORTS_PER_QUAD) * INDEX_PER_PORT_E822; 806 tx->len = INDEX_PER_PORT_E822; 807 808 return ice_ptp_alloc_tx_tracker(tx); 809 } 810 811 /** 812 * ice_ptp_init_tx_e810 - Initialize tracking for Tx timestamps 813 * @pf: Board private structure 814 * @tx: the Tx tracking structure to initialize 815 * 816 * Initialize the Tx timestamp tracker for this PF. For E810 devices, each 817 * port has its own block of timestamps, independent of the other ports. 818 */ 819 static int 820 ice_ptp_init_tx_e810(struct ice_pf *pf, struct ice_ptp_tx *tx) 821 { 822 tx->block = pf->hw.port_info->lport; 823 tx->offset = 0; 824 tx->len = INDEX_PER_PORT_E810; 825 826 return ice_ptp_alloc_tx_tracker(tx); 827 } 828 829 /** 830 * ice_ptp_tx_tstamp_cleanup - Cleanup old timestamp requests that got dropped 831 * @pf: pointer to the PF struct 832 * @tx: PTP Tx tracker to clean up 833 * 834 * Loop through the Tx timestamp requests and see if any of them have been 835 * waiting for a long time. Discard any SKBs that have been waiting for more 836 * than 2 seconds. This is long enough to be reasonably sure that the 837 * timestamp will never be captured. This might happen if the packet gets 838 * discarded before it reaches the PHY timestamping block. 839 */ 840 static void ice_ptp_tx_tstamp_cleanup(struct ice_pf *pf, struct ice_ptp_tx *tx) 841 { 842 struct ice_hw *hw = &pf->hw; 843 u8 idx; 844 845 if (!tx->init) 846 return; 847 848 for_each_set_bit(idx, tx->in_use, tx->len) { 849 struct sk_buff *skb; 850 u64 raw_tstamp; 851 852 /* Check if this SKB has been waiting for too long */ 853 if (time_is_after_jiffies(tx->tstamps[idx].start + 2 * HZ)) 854 continue; 855 856 /* Read tstamp to be able to use this register again */ 857 ice_read_phy_tstamp(hw, tx->block, idx + tx->offset, 858 &raw_tstamp); 859 860 spin_lock(&tx->lock); 861 skb = tx->tstamps[idx].skb; 862 tx->tstamps[idx].skb = NULL; 863 clear_bit(idx, tx->in_use); 864 spin_unlock(&tx->lock); 865 866 /* Count the number of Tx timestamps which have timed out */ 867 pf->ptp.tx_hwtstamp_timeouts++; 868 869 /* Free the SKB after we've cleared the bit */ 870 dev_kfree_skb_any(skb); 871 } 872 } 873 874 /** 875 * ice_ptp_update_cached_phctime - Update the cached PHC time values 876 * @pf: Board specific private structure 877 * 878 * This function updates the system time values which are cached in the PF 879 * structure and the Rx rings. 880 * 881 * This function must be called periodically to ensure that the cached value 882 * is never more than 2 seconds old. 883 * 884 * Note that the cached copy in the PF PTP structure is always updated, even 885 * if we can't update the copy in the Rx rings. 886 * 887 * Return: 888 * * 0 - OK, successfully updated 889 * * -EAGAIN - PF was busy, need to reschedule the update 890 */ 891 static int ice_ptp_update_cached_phctime(struct ice_pf *pf) 892 { 893 struct device *dev = ice_pf_to_dev(pf); 894 unsigned long update_before; 895 u64 systime; 896 int i; 897 898 update_before = pf->ptp.cached_phc_jiffies + msecs_to_jiffies(2000); 899 if (pf->ptp.cached_phc_time && 900 time_is_before_jiffies(update_before)) { 901 unsigned long time_taken = jiffies - pf->ptp.cached_phc_jiffies; 902 903 dev_warn(dev, "%u msecs passed between update to cached PHC time\n", 904 jiffies_to_msecs(time_taken)); 905 pf->ptp.late_cached_phc_updates++; 906 } 907 908 /* Read the current PHC time */ 909 systime = ice_ptp_read_src_clk_reg(pf, NULL); 910 911 /* Update the cached PHC time stored in the PF structure */ 912 WRITE_ONCE(pf->ptp.cached_phc_time, systime); 913 WRITE_ONCE(pf->ptp.cached_phc_jiffies, jiffies); 914 915 if (test_and_set_bit(ICE_CFG_BUSY, pf->state)) 916 return -EAGAIN; 917 918 ice_for_each_vsi(pf, i) { 919 struct ice_vsi *vsi = pf->vsi[i]; 920 int j; 921 922 if (!vsi) 923 continue; 924 925 if (vsi->type != ICE_VSI_PF) 926 continue; 927 928 ice_for_each_rxq(vsi, j) { 929 if (!vsi->rx_rings[j]) 930 continue; 931 WRITE_ONCE(vsi->rx_rings[j]->cached_phctime, systime); 932 } 933 } 934 clear_bit(ICE_CFG_BUSY, pf->state); 935 936 return 0; 937 } 938 939 /** 940 * ice_ptp_reset_cached_phctime - Reset cached PHC time after an update 941 * @pf: Board specific private structure 942 * 943 * This function must be called when the cached PHC time is no longer valid, 944 * such as after a time adjustment. It discards any outstanding Tx timestamps, 945 * and updates the cached PHC time for both the PF and Rx rings. If updating 946 * the PHC time cannot be done immediately, a warning message is logged and 947 * the work item is scheduled. 948 * 949 * These steps are required in order to ensure that we do not accidentally 950 * report a timestamp extended by the wrong PHC cached copy. Note that we 951 * do not directly update the cached timestamp here because it is possible 952 * this might produce an error when ICE_CFG_BUSY is set. If this occurred, we 953 * would have to try again. During that time window, timestamps might be 954 * requested and returned with an invalid extension. Thus, on failure to 955 * immediately update the cached PHC time we would need to zero the value 956 * anyways. For this reason, we just zero the value immediately and queue the 957 * update work item. 958 */ 959 static void ice_ptp_reset_cached_phctime(struct ice_pf *pf) 960 { 961 struct device *dev = ice_pf_to_dev(pf); 962 int err; 963 964 /* Update the cached PHC time immediately if possible, otherwise 965 * schedule the work item to execute soon. 966 */ 967 err = ice_ptp_update_cached_phctime(pf); 968 if (err) { 969 /* If another thread is updating the Rx rings, we won't 970 * properly reset them here. This could lead to reporting of 971 * invalid timestamps, but there isn't much we can do. 972 */ 973 dev_warn(dev, "%s: ICE_CFG_BUSY, unable to immediately update cached PHC time\n", 974 __func__); 975 976 /* Queue the work item to update the Rx rings when possible */ 977 kthread_queue_delayed_work(pf->ptp.kworker, &pf->ptp.work, 978 msecs_to_jiffies(10)); 979 } 980 981 /* Flush any outstanding Tx timestamps */ 982 ice_ptp_flush_tx_tracker(pf, &pf->ptp.port.tx); 983 } 984 985 /** 986 * ice_ptp_read_time - Read the time from the device 987 * @pf: Board private structure 988 * @ts: timespec structure to hold the current time value 989 * @sts: Optional parameter for holding a pair of system timestamps from 990 * the system clock. Will be ignored if NULL is given. 991 * 992 * This function reads the source clock registers and stores them in a timespec. 993 * However, since the registers are 64 bits of nanoseconds, we must convert the 994 * result to a timespec before we can return. 995 */ 996 static void 997 ice_ptp_read_time(struct ice_pf *pf, struct timespec64 *ts, 998 struct ptp_system_timestamp *sts) 999 { 1000 u64 time_ns = ice_ptp_read_src_clk_reg(pf, sts); 1001 1002 *ts = ns_to_timespec64(time_ns); 1003 } 1004 1005 /** 1006 * ice_ptp_write_init - Set PHC time to provided value 1007 * @pf: Board private structure 1008 * @ts: timespec structure that holds the new time value 1009 * 1010 * Set the PHC time to the specified time provided in the timespec. 1011 */ 1012 static int ice_ptp_write_init(struct ice_pf *pf, struct timespec64 *ts) 1013 { 1014 u64 ns = timespec64_to_ns(ts); 1015 struct ice_hw *hw = &pf->hw; 1016 1017 return ice_ptp_init_time(hw, ns); 1018 } 1019 1020 /** 1021 * ice_ptp_write_adj - Adjust PHC clock time atomically 1022 * @pf: Board private structure 1023 * @adj: Adjustment in nanoseconds 1024 * 1025 * Perform an atomic adjustment of the PHC time by the specified number of 1026 * nanoseconds. 1027 */ 1028 static int ice_ptp_write_adj(struct ice_pf *pf, s32 adj) 1029 { 1030 struct ice_hw *hw = &pf->hw; 1031 1032 return ice_ptp_adj_clock(hw, adj); 1033 } 1034 1035 /** 1036 * ice_base_incval - Get base timer increment value 1037 * @pf: Board private structure 1038 * 1039 * Look up the base timer increment value for this device. The base increment 1040 * value is used to define the nominal clock tick rate. This increment value 1041 * is programmed during device initialization. It is also used as the basis 1042 * for calculating adjustments using scaled_ppm. 1043 */ 1044 static u64 ice_base_incval(struct ice_pf *pf) 1045 { 1046 struct ice_hw *hw = &pf->hw; 1047 u64 incval; 1048 1049 if (ice_is_e810(hw)) 1050 incval = ICE_PTP_NOMINAL_INCVAL_E810; 1051 else if (ice_e822_time_ref(hw) < NUM_ICE_TIME_REF_FREQ) 1052 incval = ice_e822_nominal_incval(ice_e822_time_ref(hw)); 1053 else 1054 incval = UNKNOWN_INCVAL_E822; 1055 1056 dev_dbg(ice_pf_to_dev(pf), "PTP: using base increment value of 0x%016llx\n", 1057 incval); 1058 1059 return incval; 1060 } 1061 1062 /** 1063 * ice_ptp_check_tx_fifo - Check whether Tx FIFO is in an OK state 1064 * @port: PTP port for which Tx FIFO is checked 1065 */ 1066 static int ice_ptp_check_tx_fifo(struct ice_ptp_port *port) 1067 { 1068 int quad = port->port_num / ICE_PORTS_PER_QUAD; 1069 int offs = port->port_num % ICE_PORTS_PER_QUAD; 1070 struct ice_pf *pf; 1071 struct ice_hw *hw; 1072 u32 val, phy_sts; 1073 int err; 1074 1075 pf = ptp_port_to_pf(port); 1076 hw = &pf->hw; 1077 1078 if (port->tx_fifo_busy_cnt == FIFO_OK) 1079 return 0; 1080 1081 /* need to read FIFO state */ 1082 if (offs == 0 || offs == 1) 1083 err = ice_read_quad_reg_e822(hw, quad, Q_REG_FIFO01_STATUS, 1084 &val); 1085 else 1086 err = ice_read_quad_reg_e822(hw, quad, Q_REG_FIFO23_STATUS, 1087 &val); 1088 1089 if (err) { 1090 dev_err(ice_pf_to_dev(pf), "PTP failed to check port %d Tx FIFO, err %d\n", 1091 port->port_num, err); 1092 return err; 1093 } 1094 1095 if (offs & 0x1) 1096 phy_sts = (val & Q_REG_FIFO13_M) >> Q_REG_FIFO13_S; 1097 else 1098 phy_sts = (val & Q_REG_FIFO02_M) >> Q_REG_FIFO02_S; 1099 1100 if (phy_sts & FIFO_EMPTY) { 1101 port->tx_fifo_busy_cnt = FIFO_OK; 1102 return 0; 1103 } 1104 1105 port->tx_fifo_busy_cnt++; 1106 1107 dev_dbg(ice_pf_to_dev(pf), "Try %d, port %d FIFO not empty\n", 1108 port->tx_fifo_busy_cnt, port->port_num); 1109 1110 if (port->tx_fifo_busy_cnt == ICE_PTP_FIFO_NUM_CHECKS) { 1111 dev_dbg(ice_pf_to_dev(pf), 1112 "Port %d Tx FIFO still not empty; resetting quad %d\n", 1113 port->port_num, quad); 1114 ice_ptp_reset_ts_memory_quad_e822(hw, quad); 1115 port->tx_fifo_busy_cnt = FIFO_OK; 1116 return 0; 1117 } 1118 1119 return -EAGAIN; 1120 } 1121 1122 /** 1123 * ice_ptp_check_tx_offset_valid - Check if the Tx PHY offset is valid 1124 * @port: the PTP port to check 1125 * 1126 * Checks whether the Tx offset for the PHY associated with this port is 1127 * valid. Returns 0 if the offset is valid, and a non-zero error code if it is 1128 * not. 1129 */ 1130 static int ice_ptp_check_tx_offset_valid(struct ice_ptp_port *port) 1131 { 1132 struct ice_pf *pf = ptp_port_to_pf(port); 1133 struct device *dev = ice_pf_to_dev(pf); 1134 struct ice_hw *hw = &pf->hw; 1135 u32 val; 1136 int err; 1137 1138 err = ice_ptp_check_tx_fifo(port); 1139 if (err) 1140 return err; 1141 1142 err = ice_read_phy_reg_e822(hw, port->port_num, P_REG_TX_OV_STATUS, 1143 &val); 1144 if (err) { 1145 dev_err(dev, "Failed to read TX_OV_STATUS for port %d, err %d\n", 1146 port->port_num, err); 1147 return -EAGAIN; 1148 } 1149 1150 if (!(val & P_REG_TX_OV_STATUS_OV_M)) 1151 return -EAGAIN; 1152 1153 return 0; 1154 } 1155 1156 /** 1157 * ice_ptp_check_rx_offset_valid - Check if the Rx PHY offset is valid 1158 * @port: the PTP port to check 1159 * 1160 * Checks whether the Rx offset for the PHY associated with this port is 1161 * valid. Returns 0 if the offset is valid, and a non-zero error code if it is 1162 * not. 1163 */ 1164 static int ice_ptp_check_rx_offset_valid(struct ice_ptp_port *port) 1165 { 1166 struct ice_pf *pf = ptp_port_to_pf(port); 1167 struct device *dev = ice_pf_to_dev(pf); 1168 struct ice_hw *hw = &pf->hw; 1169 int err; 1170 u32 val; 1171 1172 err = ice_read_phy_reg_e822(hw, port->port_num, P_REG_RX_OV_STATUS, 1173 &val); 1174 if (err) { 1175 dev_err(dev, "Failed to read RX_OV_STATUS for port %d, err %d\n", 1176 port->port_num, err); 1177 return err; 1178 } 1179 1180 if (!(val & P_REG_RX_OV_STATUS_OV_M)) 1181 return -EAGAIN; 1182 1183 return 0; 1184 } 1185 1186 /** 1187 * ice_ptp_check_offset_valid - Check port offset valid bit 1188 * @port: Port for which offset valid bit is checked 1189 * 1190 * Returns 0 if both Tx and Rx offset are valid, and -EAGAIN if one of the 1191 * offset is not ready. 1192 */ 1193 static int ice_ptp_check_offset_valid(struct ice_ptp_port *port) 1194 { 1195 int tx_err, rx_err; 1196 1197 /* always check both Tx and Rx offset validity */ 1198 tx_err = ice_ptp_check_tx_offset_valid(port); 1199 rx_err = ice_ptp_check_rx_offset_valid(port); 1200 1201 if (tx_err || rx_err) 1202 return -EAGAIN; 1203 1204 return 0; 1205 } 1206 1207 /** 1208 * ice_ptp_wait_for_offset_valid - Check for valid Tx and Rx offsets 1209 * @work: Pointer to the kthread_work structure for this task 1210 * 1211 * Check whether both the Tx and Rx offsets are valid for enabling the vernier 1212 * calibration. 1213 * 1214 * Once we have valid offsets from hardware, update the total Tx and Rx 1215 * offsets, and exit bypass mode. This enables more precise timestamps using 1216 * the extra data measured during the vernier calibration process. 1217 */ 1218 static void ice_ptp_wait_for_offset_valid(struct kthread_work *work) 1219 { 1220 struct ice_ptp_port *port; 1221 int err; 1222 struct device *dev; 1223 struct ice_pf *pf; 1224 struct ice_hw *hw; 1225 1226 port = container_of(work, struct ice_ptp_port, ov_work.work); 1227 pf = ptp_port_to_pf(port); 1228 hw = &pf->hw; 1229 dev = ice_pf_to_dev(pf); 1230 1231 if (ice_is_reset_in_progress(pf->state)) 1232 return; 1233 1234 if (ice_ptp_check_offset_valid(port)) { 1235 /* Offsets not ready yet, try again later */ 1236 kthread_queue_delayed_work(pf->ptp.kworker, 1237 &port->ov_work, 1238 msecs_to_jiffies(100)); 1239 return; 1240 } 1241 1242 /* Offsets are valid, so Vernier mode calculations are started */ 1243 err = ice_phy_calc_vernier_e822(hw, port->port_num); 1244 if (err) { 1245 dev_warn(dev, "Failed to prepare Vernier mode for PHY port %u, err %d\n", 1246 port->port_num, err); 1247 return; 1248 } 1249 } 1250 1251 /** 1252 * ice_ptp_port_phy_stop - Stop timestamping for a PHY port 1253 * @ptp_port: PTP port to stop 1254 */ 1255 static int 1256 ice_ptp_port_phy_stop(struct ice_ptp_port *ptp_port) 1257 { 1258 struct ice_pf *pf = ptp_port_to_pf(ptp_port); 1259 u8 port = ptp_port->port_num; 1260 struct ice_hw *hw = &pf->hw; 1261 int err; 1262 1263 if (ice_is_e810(hw)) 1264 return 0; 1265 1266 mutex_lock(&ptp_port->ps_lock); 1267 1268 kthread_cancel_delayed_work_sync(&ptp_port->ov_work); 1269 1270 err = ice_stop_phy_timer_e822(hw, port, true); 1271 if (err) 1272 dev_err(ice_pf_to_dev(pf), "PTP failed to set PHY port %d down, err %d\n", 1273 port, err); 1274 1275 mutex_unlock(&ptp_port->ps_lock); 1276 1277 return err; 1278 } 1279 1280 /** 1281 * ice_ptp_port_phy_restart - (Re)start and calibrate PHY timestamping 1282 * @ptp_port: PTP port for which the PHY start is set 1283 * 1284 * Start the PHY timestamping block, and initiate Vernier timestamping 1285 * calibration. If timestamping cannot be calibrated (such as if link is down) 1286 * then disable the timestamping block instead. 1287 */ 1288 static int 1289 ice_ptp_port_phy_restart(struct ice_ptp_port *ptp_port) 1290 { 1291 struct ice_pf *pf = ptp_port_to_pf(ptp_port); 1292 u8 port = ptp_port->port_num; 1293 struct ice_hw *hw = &pf->hw; 1294 int err; 1295 1296 if (ice_is_e810(hw)) 1297 return 0; 1298 1299 if (!ptp_port->link_up) 1300 return ice_ptp_port_phy_stop(ptp_port); 1301 1302 mutex_lock(&ptp_port->ps_lock); 1303 1304 kthread_cancel_delayed_work_sync(&ptp_port->ov_work); 1305 1306 /* temporarily disable Tx timestamps while calibrating PHY offset */ 1307 ptp_port->tx.calibrating = true; 1308 ptp_port->tx_fifo_busy_cnt = 0; 1309 1310 /* Start the PHY timer in Vernier mode */ 1311 err = ice_start_phy_timer_e822(hw, port); 1312 if (err) 1313 goto out_unlock; 1314 1315 /* Enable Tx timestamps right away */ 1316 ptp_port->tx.calibrating = false; 1317 1318 kthread_queue_delayed_work(pf->ptp.kworker, &ptp_port->ov_work, 0); 1319 1320 out_unlock: 1321 if (err) 1322 dev_err(ice_pf_to_dev(pf), "PTP failed to set PHY port %d up, err %d\n", 1323 port, err); 1324 1325 mutex_unlock(&ptp_port->ps_lock); 1326 1327 return err; 1328 } 1329 1330 /** 1331 * ice_ptp_link_change - Set or clear port registers for timestamping 1332 * @pf: Board private structure 1333 * @port: Port for which the PHY start is set 1334 * @linkup: Link is up or down 1335 */ 1336 int ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup) 1337 { 1338 struct ice_ptp_port *ptp_port; 1339 1340 if (!test_bit(ICE_FLAG_PTP_SUPPORTED, pf->flags)) 1341 return 0; 1342 1343 if (port >= ICE_NUM_EXTERNAL_PORTS) 1344 return -EINVAL; 1345 1346 ptp_port = &pf->ptp.port; 1347 if (ptp_port->port_num != port) 1348 return -EINVAL; 1349 1350 /* Update cached link err for this port immediately */ 1351 ptp_port->link_up = linkup; 1352 1353 if (!test_bit(ICE_FLAG_PTP, pf->flags)) 1354 /* PTP is not setup */ 1355 return -EAGAIN; 1356 1357 return ice_ptp_port_phy_restart(ptp_port); 1358 } 1359 1360 /** 1361 * ice_ptp_tx_ena_intr - Enable or disable the Tx timestamp interrupt 1362 * @pf: PF private structure 1363 * @ena: bool value to enable or disable interrupt 1364 * @threshold: Minimum number of packets at which intr is triggered 1365 * 1366 * Utility function to enable or disable Tx timestamp interrupt and threshold 1367 */ 1368 static int ice_ptp_tx_ena_intr(struct ice_pf *pf, bool ena, u32 threshold) 1369 { 1370 struct ice_hw *hw = &pf->hw; 1371 int err = 0; 1372 int quad; 1373 u32 val; 1374 1375 ice_ptp_reset_ts_memory(hw); 1376 1377 for (quad = 0; quad < ICE_MAX_QUAD; quad++) { 1378 err = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG, 1379 &val); 1380 if (err) 1381 break; 1382 1383 if (ena) { 1384 val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; 1385 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M; 1386 val |= ((threshold << Q_REG_TX_MEM_GBL_CFG_INTR_THR_S) & 1387 Q_REG_TX_MEM_GBL_CFG_INTR_THR_M); 1388 } else { 1389 val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M; 1390 } 1391 1392 err = ice_write_quad_reg_e822(hw, quad, Q_REG_TX_MEM_GBL_CFG, 1393 val); 1394 if (err) 1395 break; 1396 } 1397 1398 if (err) 1399 dev_err(ice_pf_to_dev(pf), "PTP failed in intr ena, err %d\n", 1400 err); 1401 return err; 1402 } 1403 1404 /** 1405 * ice_ptp_reset_phy_timestamping - Reset PHY timestamping block 1406 * @pf: Board private structure 1407 */ 1408 static void ice_ptp_reset_phy_timestamping(struct ice_pf *pf) 1409 { 1410 ice_ptp_port_phy_restart(&pf->ptp.port); 1411 } 1412 1413 /** 1414 * ice_ptp_adjfine - Adjust clock increment rate 1415 * @info: the driver's PTP info structure 1416 * @scaled_ppm: Parts per million with 16-bit fractional field 1417 * 1418 * Adjust the frequency of the clock by the indicated scaled ppm from the 1419 * base frequency. 1420 */ 1421 static int ice_ptp_adjfine(struct ptp_clock_info *info, long scaled_ppm) 1422 { 1423 struct ice_pf *pf = ptp_info_to_pf(info); 1424 struct ice_hw *hw = &pf->hw; 1425 u64 incval; 1426 int err; 1427 1428 incval = adjust_by_scaled_ppm(ice_base_incval(pf), scaled_ppm); 1429 err = ice_ptp_write_incval_locked(hw, incval); 1430 if (err) { 1431 dev_err(ice_pf_to_dev(pf), "PTP failed to set incval, err %d\n", 1432 err); 1433 return -EIO; 1434 } 1435 1436 return 0; 1437 } 1438 1439 /** 1440 * ice_ptp_extts_work - Workqueue task function 1441 * @work: external timestamp work structure 1442 * 1443 * Service for PTP external clock event 1444 */ 1445 static void ice_ptp_extts_work(struct kthread_work *work) 1446 { 1447 struct ice_ptp *ptp = container_of(work, struct ice_ptp, extts_work); 1448 struct ice_pf *pf = container_of(ptp, struct ice_pf, ptp); 1449 struct ptp_clock_event event; 1450 struct ice_hw *hw = &pf->hw; 1451 u8 chan, tmr_idx; 1452 u32 hi, lo; 1453 1454 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 1455 /* Event time is captured by one of the two matched registers 1456 * GLTSYN_EVNT_L: 32 LSB of sampled time event 1457 * GLTSYN_EVNT_H: 32 MSB of sampled time event 1458 * Event is defined in GLTSYN_EVNT_0 register 1459 */ 1460 for (chan = 0; chan < GLTSYN_EVNT_H_IDX_MAX; chan++) { 1461 /* Check if channel is enabled */ 1462 if (pf->ptp.ext_ts_irq & (1 << chan)) { 1463 lo = rd32(hw, GLTSYN_EVNT_L(chan, tmr_idx)); 1464 hi = rd32(hw, GLTSYN_EVNT_H(chan, tmr_idx)); 1465 event.timestamp = (((u64)hi) << 32) | lo; 1466 event.type = PTP_CLOCK_EXTTS; 1467 event.index = chan; 1468 1469 /* Fire event */ 1470 ptp_clock_event(pf->ptp.clock, &event); 1471 pf->ptp.ext_ts_irq &= ~(1 << chan); 1472 } 1473 } 1474 } 1475 1476 /** 1477 * ice_ptp_cfg_extts - Configure EXTTS pin and channel 1478 * @pf: Board private structure 1479 * @ena: true to enable; false to disable 1480 * @chan: GPIO channel (0-3) 1481 * @gpio_pin: GPIO pin 1482 * @extts_flags: request flags from the ptp_extts_request.flags 1483 */ 1484 static int 1485 ice_ptp_cfg_extts(struct ice_pf *pf, bool ena, unsigned int chan, u32 gpio_pin, 1486 unsigned int extts_flags) 1487 { 1488 u32 func, aux_reg, gpio_reg, irq_reg; 1489 struct ice_hw *hw = &pf->hw; 1490 u8 tmr_idx; 1491 1492 if (chan > (unsigned int)pf->ptp.info.n_ext_ts) 1493 return -EINVAL; 1494 1495 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 1496 1497 irq_reg = rd32(hw, PFINT_OICR_ENA); 1498 1499 if (ena) { 1500 /* Enable the interrupt */ 1501 irq_reg |= PFINT_OICR_TSYN_EVNT_M; 1502 aux_reg = GLTSYN_AUX_IN_0_INT_ENA_M; 1503 1504 #define GLTSYN_AUX_IN_0_EVNTLVL_RISING_EDGE BIT(0) 1505 #define GLTSYN_AUX_IN_0_EVNTLVL_FALLING_EDGE BIT(1) 1506 1507 /* set event level to requested edge */ 1508 if (extts_flags & PTP_FALLING_EDGE) 1509 aux_reg |= GLTSYN_AUX_IN_0_EVNTLVL_FALLING_EDGE; 1510 if (extts_flags & PTP_RISING_EDGE) 1511 aux_reg |= GLTSYN_AUX_IN_0_EVNTLVL_RISING_EDGE; 1512 1513 /* Write GPIO CTL reg. 1514 * 0x1 is input sampled by EVENT register(channel) 1515 * + num_in_channels * tmr_idx 1516 */ 1517 func = 1 + chan + (tmr_idx * 3); 1518 gpio_reg = ((func << GLGEN_GPIO_CTL_PIN_FUNC_S) & 1519 GLGEN_GPIO_CTL_PIN_FUNC_M); 1520 pf->ptp.ext_ts_chan |= (1 << chan); 1521 } else { 1522 /* clear the values we set to reset defaults */ 1523 aux_reg = 0; 1524 gpio_reg = 0; 1525 pf->ptp.ext_ts_chan &= ~(1 << chan); 1526 if (!pf->ptp.ext_ts_chan) 1527 irq_reg &= ~PFINT_OICR_TSYN_EVNT_M; 1528 } 1529 1530 wr32(hw, PFINT_OICR_ENA, irq_reg); 1531 wr32(hw, GLTSYN_AUX_IN(chan, tmr_idx), aux_reg); 1532 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), gpio_reg); 1533 1534 return 0; 1535 } 1536 1537 /** 1538 * ice_ptp_cfg_clkout - Configure clock to generate periodic wave 1539 * @pf: Board private structure 1540 * @chan: GPIO channel (0-3) 1541 * @config: desired periodic clk configuration. NULL will disable channel 1542 * @store: If set to true the values will be stored 1543 * 1544 * Configure the internal clock generator modules to generate the clock wave of 1545 * specified period. 1546 */ 1547 static int ice_ptp_cfg_clkout(struct ice_pf *pf, unsigned int chan, 1548 struct ice_perout_channel *config, bool store) 1549 { 1550 u64 current_time, period, start_time, phase; 1551 struct ice_hw *hw = &pf->hw; 1552 u32 func, val, gpio_pin; 1553 u8 tmr_idx; 1554 1555 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; 1556 1557 /* 0. Reset mode & out_en in AUX_OUT */ 1558 wr32(hw, GLTSYN_AUX_OUT(chan, tmr_idx), 0); 1559 1560 /* If we're disabling the output, clear out CLKO and TGT and keep 1561 * output level low 1562 */ 1563 if (!config || !config->ena) { 1564 wr32(hw, GLTSYN_CLKO(chan, tmr_idx), 0); 1565 wr32(hw, GLTSYN_TGT_L(chan, tmr_idx), 0); 1566 wr32(hw, GLTSYN_TGT_H(chan, tmr_idx), 0); 1567 1568 val = GLGEN_GPIO_CTL_PIN_DIR_M; 1569 gpio_pin = pf->ptp.perout_channels[chan].gpio_pin; 1570 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), val); 1571 1572 /* Store the value if requested */ 1573 if (store) 1574 memset(&pf->ptp.perout_channels[chan], 0, 1575 sizeof(struct ice_perout_channel)); 1576 1577 return 0; 1578 } 1579 period = config->period; 1580 start_time = config->start_time; 1581 div64_u64_rem(start_time, period, &phase); 1582 gpio_pin = config->gpio_pin; 1583 1584 /* 1. Write clkout with half of required period value */ 1585 if (period & 0x1) { 1586 dev_err(ice_pf_to_dev(pf), "CLK Period must be an even value\n"); 1587 goto err; 1588 } 1589 1590 period >>= 1; 1591 1592 /* For proper operation, the GLTSYN_CLKO must be larger than clock tick 1593 */ 1594 #define MIN_PULSE 3 1595 if (period <= MIN_PULSE || period > U32_MAX) { 1596 dev_err(ice_pf_to_dev(pf), "CLK Period must be > %d && < 2^33", 1597 MIN_PULSE * 2); 1598 goto err; 1599 } 1600 1601 wr32(hw, GLTSYN_CLKO(chan, tmr_idx), lower_32_bits(period)); 1602 1603 /* Allow time for programming before start_time is hit */ 1604 current_time = ice_ptp_read_src_clk_reg(pf, NULL); 1605 1606 /* if start time is in the past start the timer at the nearest second 1607 * maintaining phase 1608 */ 1609 if (start_time < current_time) 1610 start_time = div64_u64(current_time + NSEC_PER_SEC - 1, 1611 NSEC_PER_SEC) * NSEC_PER_SEC + phase; 1612 1613 if (ice_is_e810(hw)) 1614 start_time -= E810_OUT_PROP_DELAY_NS; 1615 else 1616 start_time -= ice_e822_pps_delay(ice_e822_time_ref(hw)); 1617 1618 /* 2. Write TARGET time */ 1619 wr32(hw, GLTSYN_TGT_L(chan, tmr_idx), lower_32_bits(start_time)); 1620 wr32(hw, GLTSYN_TGT_H(chan, tmr_idx), upper_32_bits(start_time)); 1621 1622 /* 3. Write AUX_OUT register */ 1623 val = GLTSYN_AUX_OUT_0_OUT_ENA_M | GLTSYN_AUX_OUT_0_OUTMOD_M; 1624 wr32(hw, GLTSYN_AUX_OUT(chan, tmr_idx), val); 1625 1626 /* 4. write GPIO CTL reg */ 1627 func = 8 + chan + (tmr_idx * 4); 1628 val = GLGEN_GPIO_CTL_PIN_DIR_M | 1629 ((func << GLGEN_GPIO_CTL_PIN_FUNC_S) & GLGEN_GPIO_CTL_PIN_FUNC_M); 1630 wr32(hw, GLGEN_GPIO_CTL(gpio_pin), val); 1631 1632 /* Store the value if requested */ 1633 if (store) { 1634 memcpy(&pf->ptp.perout_channels[chan], config, 1635 sizeof(struct ice_perout_channel)); 1636 pf->ptp.perout_channels[chan].start_time = phase; 1637 } 1638 1639 return 0; 1640 err: 1641 dev_err(ice_pf_to_dev(pf), "PTP failed to cfg per_clk\n"); 1642 return -EFAULT; 1643 } 1644 1645 /** 1646 * ice_ptp_disable_all_clkout - Disable all currently configured outputs 1647 * @pf: pointer to the PF structure 1648 * 1649 * Disable all currently configured clock outputs. This is necessary before 1650 * certain changes to the PTP hardware clock. Use ice_ptp_enable_all_clkout to 1651 * re-enable the clocks again. 1652 */ 1653 static void ice_ptp_disable_all_clkout(struct ice_pf *pf) 1654 { 1655 uint i; 1656 1657 for (i = 0; i < pf->ptp.info.n_per_out; i++) 1658 if (pf->ptp.perout_channels[i].ena) 1659 ice_ptp_cfg_clkout(pf, i, NULL, false); 1660 } 1661 1662 /** 1663 * ice_ptp_enable_all_clkout - Enable all configured periodic clock outputs 1664 * @pf: pointer to the PF structure 1665 * 1666 * Enable all currently configured clock outputs. Use this after 1667 * ice_ptp_disable_all_clkout to reconfigure the output signals according to 1668 * their configuration. 1669 */ 1670 static void ice_ptp_enable_all_clkout(struct ice_pf *pf) 1671 { 1672 uint i; 1673 1674 for (i = 0; i < pf->ptp.info.n_per_out; i++) 1675 if (pf->ptp.perout_channels[i].ena) 1676 ice_ptp_cfg_clkout(pf, i, &pf->ptp.perout_channels[i], 1677 false); 1678 } 1679 1680 /** 1681 * ice_ptp_gpio_enable_e810 - Enable/disable ancillary features of PHC 1682 * @info: the driver's PTP info structure 1683 * @rq: The requested feature to change 1684 * @on: Enable/disable flag 1685 */ 1686 static int 1687 ice_ptp_gpio_enable_e810(struct ptp_clock_info *info, 1688 struct ptp_clock_request *rq, int on) 1689 { 1690 struct ice_pf *pf = ptp_info_to_pf(info); 1691 struct ice_perout_channel clk_cfg = {0}; 1692 bool sma_pres = false; 1693 unsigned int chan; 1694 u32 gpio_pin; 1695 int err; 1696 1697 if (ice_is_feature_supported(pf, ICE_F_SMA_CTRL)) 1698 sma_pres = true; 1699 1700 switch (rq->type) { 1701 case PTP_CLK_REQ_PEROUT: 1702 chan = rq->perout.index; 1703 if (sma_pres) { 1704 if (chan == ice_pin_desc_e810t[SMA1].chan) 1705 clk_cfg.gpio_pin = GPIO_20; 1706 else if (chan == ice_pin_desc_e810t[SMA2].chan) 1707 clk_cfg.gpio_pin = GPIO_22; 1708 else 1709 return -1; 1710 } else if (ice_is_e810t(&pf->hw)) { 1711 if (chan == 0) 1712 clk_cfg.gpio_pin = GPIO_20; 1713 else 1714 clk_cfg.gpio_pin = GPIO_22; 1715 } else if (chan == PPS_CLK_GEN_CHAN) { 1716 clk_cfg.gpio_pin = PPS_PIN_INDEX; 1717 } else { 1718 clk_cfg.gpio_pin = chan; 1719 } 1720 1721 clk_cfg.period = ((rq->perout.period.sec * NSEC_PER_SEC) + 1722 rq->perout.period.nsec); 1723 clk_cfg.start_time = ((rq->perout.start.sec * NSEC_PER_SEC) + 1724 rq->perout.start.nsec); 1725 clk_cfg.ena = !!on; 1726 1727 err = ice_ptp_cfg_clkout(pf, chan, &clk_cfg, true); 1728 break; 1729 case PTP_CLK_REQ_EXTTS: 1730 chan = rq->extts.index; 1731 if (sma_pres) { 1732 if (chan < ice_pin_desc_e810t[SMA2].chan) 1733 gpio_pin = GPIO_21; 1734 else 1735 gpio_pin = GPIO_23; 1736 } else if (ice_is_e810t(&pf->hw)) { 1737 if (chan == 0) 1738 gpio_pin = GPIO_21; 1739 else 1740 gpio_pin = GPIO_23; 1741 } else { 1742 gpio_pin = chan; 1743 } 1744 1745 err = ice_ptp_cfg_extts(pf, !!on, chan, gpio_pin, 1746 rq->extts.flags); 1747 break; 1748 default: 1749 return -EOPNOTSUPP; 1750 } 1751 1752 return err; 1753 } 1754 1755 /** 1756 * ice_ptp_gettimex64 - Get the time of the clock 1757 * @info: the driver's PTP info structure 1758 * @ts: timespec64 structure to hold the current time value 1759 * @sts: Optional parameter for holding a pair of system timestamps from 1760 * the system clock. Will be ignored if NULL is given. 1761 * 1762 * Read the device clock and return the correct value on ns, after converting it 1763 * into a timespec struct. 1764 */ 1765 static int 1766 ice_ptp_gettimex64(struct ptp_clock_info *info, struct timespec64 *ts, 1767 struct ptp_system_timestamp *sts) 1768 { 1769 struct ice_pf *pf = ptp_info_to_pf(info); 1770 struct ice_hw *hw = &pf->hw; 1771 1772 if (!ice_ptp_lock(hw)) { 1773 dev_err(ice_pf_to_dev(pf), "PTP failed to get time\n"); 1774 return -EBUSY; 1775 } 1776 1777 ice_ptp_read_time(pf, ts, sts); 1778 ice_ptp_unlock(hw); 1779 1780 return 0; 1781 } 1782 1783 /** 1784 * ice_ptp_settime64 - Set the time of the clock 1785 * @info: the driver's PTP info structure 1786 * @ts: timespec64 structure that holds the new time value 1787 * 1788 * Set the device clock to the user input value. The conversion from timespec 1789 * to ns happens in the write function. 1790 */ 1791 static int 1792 ice_ptp_settime64(struct ptp_clock_info *info, const struct timespec64 *ts) 1793 { 1794 struct ice_pf *pf = ptp_info_to_pf(info); 1795 struct timespec64 ts64 = *ts; 1796 struct ice_hw *hw = &pf->hw; 1797 int err; 1798 1799 /* For Vernier mode, we need to recalibrate after new settime 1800 * Start with disabling timestamp block 1801 */ 1802 if (pf->ptp.port.link_up) 1803 ice_ptp_port_phy_stop(&pf->ptp.port); 1804 1805 if (!ice_ptp_lock(hw)) { 1806 err = -EBUSY; 1807 goto exit; 1808 } 1809 1810 /* Disable periodic outputs */ 1811 ice_ptp_disable_all_clkout(pf); 1812 1813 err = ice_ptp_write_init(pf, &ts64); 1814 ice_ptp_unlock(hw); 1815 1816 if (!err) 1817 ice_ptp_reset_cached_phctime(pf); 1818 1819 /* Reenable periodic outputs */ 1820 ice_ptp_enable_all_clkout(pf); 1821 1822 /* Recalibrate and re-enable timestamp block */ 1823 if (pf->ptp.port.link_up) 1824 ice_ptp_port_phy_restart(&pf->ptp.port); 1825 exit: 1826 if (err) { 1827 dev_err(ice_pf_to_dev(pf), "PTP failed to set time %d\n", err); 1828 return err; 1829 } 1830 1831 return 0; 1832 } 1833 1834 /** 1835 * ice_ptp_adjtime_nonatomic - Do a non-atomic clock adjustment 1836 * @info: the driver's PTP info structure 1837 * @delta: Offset in nanoseconds to adjust the time by 1838 */ 1839 static int ice_ptp_adjtime_nonatomic(struct ptp_clock_info *info, s64 delta) 1840 { 1841 struct timespec64 now, then; 1842 int ret; 1843 1844 then = ns_to_timespec64(delta); 1845 ret = ice_ptp_gettimex64(info, &now, NULL); 1846 if (ret) 1847 return ret; 1848 now = timespec64_add(now, then); 1849 1850 return ice_ptp_settime64(info, (const struct timespec64 *)&now); 1851 } 1852 1853 /** 1854 * ice_ptp_adjtime - Adjust the time of the clock by the indicated delta 1855 * @info: the driver's PTP info structure 1856 * @delta: Offset in nanoseconds to adjust the time by 1857 */ 1858 static int ice_ptp_adjtime(struct ptp_clock_info *info, s64 delta) 1859 { 1860 struct ice_pf *pf = ptp_info_to_pf(info); 1861 struct ice_hw *hw = &pf->hw; 1862 struct device *dev; 1863 int err; 1864 1865 dev = ice_pf_to_dev(pf); 1866 1867 /* Hardware only supports atomic adjustments using signed 32-bit 1868 * integers. For any adjustment outside this range, perform 1869 * a non-atomic get->adjust->set flow. 1870 */ 1871 if (delta > S32_MAX || delta < S32_MIN) { 1872 dev_dbg(dev, "delta = %lld, adjtime non-atomic\n", delta); 1873 return ice_ptp_adjtime_nonatomic(info, delta); 1874 } 1875 1876 if (!ice_ptp_lock(hw)) { 1877 dev_err(dev, "PTP failed to acquire semaphore in adjtime\n"); 1878 return -EBUSY; 1879 } 1880 1881 /* Disable periodic outputs */ 1882 ice_ptp_disable_all_clkout(pf); 1883 1884 err = ice_ptp_write_adj(pf, delta); 1885 1886 /* Reenable periodic outputs */ 1887 ice_ptp_enable_all_clkout(pf); 1888 1889 ice_ptp_unlock(hw); 1890 1891 if (err) { 1892 dev_err(dev, "PTP failed to adjust time, err %d\n", err); 1893 return err; 1894 } 1895 1896 ice_ptp_reset_cached_phctime(pf); 1897 1898 return 0; 1899 } 1900 1901 #ifdef CONFIG_ICE_HWTS 1902 /** 1903 * ice_ptp_get_syncdevicetime - Get the cross time stamp info 1904 * @device: Current device time 1905 * @system: System counter value read synchronously with device time 1906 * @ctx: Context provided by timekeeping code 1907 * 1908 * Read device and system (ART) clock simultaneously and return the corrected 1909 * clock values in ns. 1910 */ 1911 static int 1912 ice_ptp_get_syncdevicetime(ktime_t *device, 1913 struct system_counterval_t *system, 1914 void *ctx) 1915 { 1916 struct ice_pf *pf = (struct ice_pf *)ctx; 1917 struct ice_hw *hw = &pf->hw; 1918 u32 hh_lock, hh_art_ctl; 1919 int i; 1920 1921 /* Get the HW lock */ 1922 hh_lock = rd32(hw, PFHH_SEM + (PFTSYN_SEM_BYTES * hw->pf_id)); 1923 if (hh_lock & PFHH_SEM_BUSY_M) { 1924 dev_err(ice_pf_to_dev(pf), "PTP failed to get hh lock\n"); 1925 return -EFAULT; 1926 } 1927 1928 /* Start the ART and device clock sync sequence */ 1929 hh_art_ctl = rd32(hw, GLHH_ART_CTL); 1930 hh_art_ctl = hh_art_ctl | GLHH_ART_CTL_ACTIVE_M; 1931 wr32(hw, GLHH_ART_CTL, hh_art_ctl); 1932 1933 #define MAX_HH_LOCK_TRIES 100 1934 1935 for (i = 0; i < MAX_HH_LOCK_TRIES; i++) { 1936 /* Wait for sync to complete */ 1937 hh_art_ctl = rd32(hw, GLHH_ART_CTL); 1938 if (hh_art_ctl & GLHH_ART_CTL_ACTIVE_M) { 1939 udelay(1); 1940 continue; 1941 } else { 1942 u32 hh_ts_lo, hh_ts_hi, tmr_idx; 1943 u64 hh_ts; 1944 1945 tmr_idx = hw->func_caps.ts_func_info.tmr_index_assoc; 1946 /* Read ART time */ 1947 hh_ts_lo = rd32(hw, GLHH_ART_TIME_L); 1948 hh_ts_hi = rd32(hw, GLHH_ART_TIME_H); 1949 hh_ts = ((u64)hh_ts_hi << 32) | hh_ts_lo; 1950 *system = convert_art_ns_to_tsc(hh_ts); 1951 /* Read Device source clock time */ 1952 hh_ts_lo = rd32(hw, GLTSYN_HHTIME_L(tmr_idx)); 1953 hh_ts_hi = rd32(hw, GLTSYN_HHTIME_H(tmr_idx)); 1954 hh_ts = ((u64)hh_ts_hi << 32) | hh_ts_lo; 1955 *device = ns_to_ktime(hh_ts); 1956 break; 1957 } 1958 } 1959 /* Release HW lock */ 1960 hh_lock = rd32(hw, PFHH_SEM + (PFTSYN_SEM_BYTES * hw->pf_id)); 1961 hh_lock = hh_lock & ~PFHH_SEM_BUSY_M; 1962 wr32(hw, PFHH_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), hh_lock); 1963 1964 if (i == MAX_HH_LOCK_TRIES) 1965 return -ETIMEDOUT; 1966 1967 return 0; 1968 } 1969 1970 /** 1971 * ice_ptp_getcrosststamp_e822 - Capture a device cross timestamp 1972 * @info: the driver's PTP info structure 1973 * @cts: The memory to fill the cross timestamp info 1974 * 1975 * Capture a cross timestamp between the ART and the device PTP hardware 1976 * clock. Fill the cross timestamp information and report it back to the 1977 * caller. 1978 * 1979 * This is only valid for E822 devices which have support for generating the 1980 * cross timestamp via PCIe PTM. 1981 * 1982 * In order to correctly correlate the ART timestamp back to the TSC time, the 1983 * CPU must have X86_FEATURE_TSC_KNOWN_FREQ. 1984 */ 1985 static int 1986 ice_ptp_getcrosststamp_e822(struct ptp_clock_info *info, 1987 struct system_device_crosststamp *cts) 1988 { 1989 struct ice_pf *pf = ptp_info_to_pf(info); 1990 1991 return get_device_system_crosststamp(ice_ptp_get_syncdevicetime, 1992 pf, NULL, cts); 1993 } 1994 #endif /* CONFIG_ICE_HWTS */ 1995 1996 /** 1997 * ice_ptp_get_ts_config - ioctl interface to read the timestamping config 1998 * @pf: Board private structure 1999 * @ifr: ioctl data 2000 * 2001 * Copy the timestamping config to user buffer 2002 */ 2003 int ice_ptp_get_ts_config(struct ice_pf *pf, struct ifreq *ifr) 2004 { 2005 struct hwtstamp_config *config; 2006 2007 if (!test_bit(ICE_FLAG_PTP, pf->flags)) 2008 return -EIO; 2009 2010 config = &pf->ptp.tstamp_config; 2011 2012 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ? 2013 -EFAULT : 0; 2014 } 2015 2016 /** 2017 * ice_ptp_set_timestamp_mode - Setup driver for requested timestamp mode 2018 * @pf: Board private structure 2019 * @config: hwtstamp settings requested or saved 2020 */ 2021 static int 2022 ice_ptp_set_timestamp_mode(struct ice_pf *pf, struct hwtstamp_config *config) 2023 { 2024 switch (config->tx_type) { 2025 case HWTSTAMP_TX_OFF: 2026 ice_set_tx_tstamp(pf, false); 2027 break; 2028 case HWTSTAMP_TX_ON: 2029 ice_set_tx_tstamp(pf, true); 2030 break; 2031 default: 2032 return -ERANGE; 2033 } 2034 2035 switch (config->rx_filter) { 2036 case HWTSTAMP_FILTER_NONE: 2037 ice_set_rx_tstamp(pf, false); 2038 break; 2039 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2040 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2041 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2042 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2043 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2044 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2045 case HWTSTAMP_FILTER_PTP_V2_SYNC: 2046 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 2047 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2048 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 2049 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 2050 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2051 case HWTSTAMP_FILTER_NTP_ALL: 2052 case HWTSTAMP_FILTER_ALL: 2053 ice_set_rx_tstamp(pf, true); 2054 break; 2055 default: 2056 return -ERANGE; 2057 } 2058 2059 return 0; 2060 } 2061 2062 /** 2063 * ice_ptp_set_ts_config - ioctl interface to control the timestamping 2064 * @pf: Board private structure 2065 * @ifr: ioctl data 2066 * 2067 * Get the user config and store it 2068 */ 2069 int ice_ptp_set_ts_config(struct ice_pf *pf, struct ifreq *ifr) 2070 { 2071 struct hwtstamp_config config; 2072 int err; 2073 2074 if (!test_bit(ICE_FLAG_PTP, pf->flags)) 2075 return -EAGAIN; 2076 2077 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 2078 return -EFAULT; 2079 2080 err = ice_ptp_set_timestamp_mode(pf, &config); 2081 if (err) 2082 return err; 2083 2084 /* Return the actual configuration set */ 2085 config = pf->ptp.tstamp_config; 2086 2087 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 2088 -EFAULT : 0; 2089 } 2090 2091 /** 2092 * ice_ptp_rx_hwtstamp - Check for an Rx timestamp 2093 * @rx_ring: Ring to get the VSI info 2094 * @rx_desc: Receive descriptor 2095 * @skb: Particular skb to send timestamp with 2096 * 2097 * The driver receives a notification in the receive descriptor with timestamp. 2098 * The timestamp is in ns, so we must convert the result first. 2099 */ 2100 void 2101 ice_ptp_rx_hwtstamp(struct ice_rx_ring *rx_ring, 2102 union ice_32b_rx_flex_desc *rx_desc, struct sk_buff *skb) 2103 { 2104 struct skb_shared_hwtstamps *hwtstamps; 2105 u64 ts_ns, cached_time; 2106 u32 ts_high; 2107 2108 if (!(rx_desc->wb.time_stamp_low & ICE_PTP_TS_VALID)) 2109 return; 2110 2111 cached_time = READ_ONCE(rx_ring->cached_phctime); 2112 2113 /* Do not report a timestamp if we don't have a cached PHC time */ 2114 if (!cached_time) 2115 return; 2116 2117 /* Use ice_ptp_extend_32b_ts directly, using the ring-specific cached 2118 * PHC value, rather than accessing the PF. This also allows us to 2119 * simply pass the upper 32bits of nanoseconds directly. Calling 2120 * ice_ptp_extend_40b_ts is unnecessary as it would just discard these 2121 * bits itself. 2122 */ 2123 ts_high = le32_to_cpu(rx_desc->wb.flex_ts.ts_high); 2124 ts_ns = ice_ptp_extend_32b_ts(cached_time, ts_high); 2125 2126 hwtstamps = skb_hwtstamps(skb); 2127 memset(hwtstamps, 0, sizeof(*hwtstamps)); 2128 hwtstamps->hwtstamp = ns_to_ktime(ts_ns); 2129 } 2130 2131 /** 2132 * ice_ptp_disable_sma_pins_e810t - Disable E810-T SMA pins 2133 * @pf: pointer to the PF structure 2134 * @info: PTP clock info structure 2135 * 2136 * Disable the OS access to the SMA pins. Called to clear out the OS 2137 * indications of pin support when we fail to setup the E810-T SMA control 2138 * register. 2139 */ 2140 static void 2141 ice_ptp_disable_sma_pins_e810t(struct ice_pf *pf, struct ptp_clock_info *info) 2142 { 2143 struct device *dev = ice_pf_to_dev(pf); 2144 2145 dev_warn(dev, "Failed to configure E810-T SMA pin control\n"); 2146 2147 info->enable = NULL; 2148 info->verify = NULL; 2149 info->n_pins = 0; 2150 info->n_ext_ts = 0; 2151 info->n_per_out = 0; 2152 } 2153 2154 /** 2155 * ice_ptp_setup_sma_pins_e810t - Setup the SMA pins 2156 * @pf: pointer to the PF structure 2157 * @info: PTP clock info structure 2158 * 2159 * Finish setting up the SMA pins by allocating pin_config, and setting it up 2160 * according to the current status of the SMA. On failure, disable all of the 2161 * extended SMA pin support. 2162 */ 2163 static void 2164 ice_ptp_setup_sma_pins_e810t(struct ice_pf *pf, struct ptp_clock_info *info) 2165 { 2166 struct device *dev = ice_pf_to_dev(pf); 2167 int err; 2168 2169 /* Allocate memory for kernel pins interface */ 2170 info->pin_config = devm_kcalloc(dev, info->n_pins, 2171 sizeof(*info->pin_config), GFP_KERNEL); 2172 if (!info->pin_config) { 2173 ice_ptp_disable_sma_pins_e810t(pf, info); 2174 return; 2175 } 2176 2177 /* Read current SMA status */ 2178 err = ice_get_sma_config_e810t(&pf->hw, info->pin_config); 2179 if (err) 2180 ice_ptp_disable_sma_pins_e810t(pf, info); 2181 } 2182 2183 /** 2184 * ice_ptp_setup_pins_e810 - Setup PTP pins in sysfs 2185 * @pf: pointer to the PF instance 2186 * @info: PTP clock capabilities 2187 */ 2188 static void 2189 ice_ptp_setup_pins_e810(struct ice_pf *pf, struct ptp_clock_info *info) 2190 { 2191 info->n_per_out = N_PER_OUT_E810; 2192 2193 if (ice_is_feature_supported(pf, ICE_F_PTP_EXTTS)) 2194 info->n_ext_ts = N_EXT_TS_E810; 2195 2196 if (ice_is_feature_supported(pf, ICE_F_SMA_CTRL)) { 2197 info->n_ext_ts = N_EXT_TS_E810; 2198 info->n_pins = NUM_PTP_PINS_E810T; 2199 info->verify = ice_verify_pin_e810t; 2200 2201 /* Complete setup of the SMA pins */ 2202 ice_ptp_setup_sma_pins_e810t(pf, info); 2203 } 2204 } 2205 2206 /** 2207 * ice_ptp_set_funcs_e822 - Set specialized functions for E822 support 2208 * @pf: Board private structure 2209 * @info: PTP info to fill 2210 * 2211 * Assign functions to the PTP capabiltiies structure for E822 devices. 2212 * Functions which operate across all device families should be set directly 2213 * in ice_ptp_set_caps. Only add functions here which are distinct for E822 2214 * devices. 2215 */ 2216 static void 2217 ice_ptp_set_funcs_e822(struct ice_pf *pf, struct ptp_clock_info *info) 2218 { 2219 #ifdef CONFIG_ICE_HWTS 2220 if (boot_cpu_has(X86_FEATURE_ART) && 2221 boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) 2222 info->getcrosststamp = ice_ptp_getcrosststamp_e822; 2223 #endif /* CONFIG_ICE_HWTS */ 2224 } 2225 2226 /** 2227 * ice_ptp_set_funcs_e810 - Set specialized functions for E810 support 2228 * @pf: Board private structure 2229 * @info: PTP info to fill 2230 * 2231 * Assign functions to the PTP capabiltiies structure for E810 devices. 2232 * Functions which operate across all device families should be set directly 2233 * in ice_ptp_set_caps. Only add functions here which are distinct for e810 2234 * devices. 2235 */ 2236 static void 2237 ice_ptp_set_funcs_e810(struct ice_pf *pf, struct ptp_clock_info *info) 2238 { 2239 info->enable = ice_ptp_gpio_enable_e810; 2240 ice_ptp_setup_pins_e810(pf, info); 2241 } 2242 2243 /** 2244 * ice_ptp_set_caps - Set PTP capabilities 2245 * @pf: Board private structure 2246 */ 2247 static void ice_ptp_set_caps(struct ice_pf *pf) 2248 { 2249 struct ptp_clock_info *info = &pf->ptp.info; 2250 struct device *dev = ice_pf_to_dev(pf); 2251 2252 snprintf(info->name, sizeof(info->name) - 1, "%s-%s-clk", 2253 dev_driver_string(dev), dev_name(dev)); 2254 info->owner = THIS_MODULE; 2255 info->max_adj = 999999999; 2256 info->adjtime = ice_ptp_adjtime; 2257 info->adjfine = ice_ptp_adjfine; 2258 info->gettimex64 = ice_ptp_gettimex64; 2259 info->settime64 = ice_ptp_settime64; 2260 2261 if (ice_is_e810(&pf->hw)) 2262 ice_ptp_set_funcs_e810(pf, info); 2263 else 2264 ice_ptp_set_funcs_e822(pf, info); 2265 } 2266 2267 /** 2268 * ice_ptp_create_clock - Create PTP clock device for userspace 2269 * @pf: Board private structure 2270 * 2271 * This function creates a new PTP clock device. It only creates one if we 2272 * don't already have one. Will return error if it can't create one, but success 2273 * if we already have a device. Should be used by ice_ptp_init to create clock 2274 * initially, and prevent global resets from creating new clock devices. 2275 */ 2276 static long ice_ptp_create_clock(struct ice_pf *pf) 2277 { 2278 struct ptp_clock_info *info; 2279 struct ptp_clock *clock; 2280 struct device *dev; 2281 2282 /* No need to create a clock device if we already have one */ 2283 if (pf->ptp.clock) 2284 return 0; 2285 2286 ice_ptp_set_caps(pf); 2287 2288 info = &pf->ptp.info; 2289 dev = ice_pf_to_dev(pf); 2290 2291 /* Attempt to register the clock before enabling the hardware. */ 2292 clock = ptp_clock_register(info, dev); 2293 if (IS_ERR(clock)) 2294 return PTR_ERR(clock); 2295 2296 pf->ptp.clock = clock; 2297 2298 return 0; 2299 } 2300 2301 /** 2302 * ice_ptp_request_ts - Request an available Tx timestamp index 2303 * @tx: the PTP Tx timestamp tracker to request from 2304 * @skb: the SKB to associate with this timestamp request 2305 */ 2306 s8 ice_ptp_request_ts(struct ice_ptp_tx *tx, struct sk_buff *skb) 2307 { 2308 u8 idx; 2309 2310 /* Check if this tracker is initialized */ 2311 if (!tx->init || tx->calibrating) 2312 return -1; 2313 2314 spin_lock(&tx->lock); 2315 /* Find and set the first available index */ 2316 idx = find_first_zero_bit(tx->in_use, tx->len); 2317 if (idx < tx->len) { 2318 /* We got a valid index that no other thread could have set. Store 2319 * a reference to the skb and the start time to allow discarding old 2320 * requests. 2321 */ 2322 set_bit(idx, tx->in_use); 2323 tx->tstamps[idx].start = jiffies; 2324 tx->tstamps[idx].skb = skb_get(skb); 2325 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2326 ice_trace(tx_tstamp_request, skb, idx); 2327 } 2328 2329 spin_unlock(&tx->lock); 2330 2331 /* return the appropriate PHY timestamp register index, -1 if no 2332 * indexes were available. 2333 */ 2334 if (idx >= tx->len) 2335 return -1; 2336 else 2337 return idx + tx->offset; 2338 } 2339 2340 /** 2341 * ice_ptp_process_ts - Process the PTP Tx timestamps 2342 * @pf: Board private structure 2343 * 2344 * Returns true if timestamps are processed. 2345 */ 2346 bool ice_ptp_process_ts(struct ice_pf *pf) 2347 { 2348 return ice_ptp_tx_tstamp(&pf->ptp.port.tx); 2349 } 2350 2351 static void ice_ptp_periodic_work(struct kthread_work *work) 2352 { 2353 struct ice_ptp *ptp = container_of(work, struct ice_ptp, work.work); 2354 struct ice_pf *pf = container_of(ptp, struct ice_pf, ptp); 2355 int err; 2356 2357 if (!test_bit(ICE_FLAG_PTP, pf->flags)) 2358 return; 2359 2360 err = ice_ptp_update_cached_phctime(pf); 2361 2362 ice_ptp_tx_tstamp_cleanup(pf, &pf->ptp.port.tx); 2363 2364 /* Run twice a second or reschedule if phc update failed */ 2365 kthread_queue_delayed_work(ptp->kworker, &ptp->work, 2366 msecs_to_jiffies(err ? 10 : 500)); 2367 } 2368 2369 /** 2370 * ice_ptp_reset - Initialize PTP hardware clock support after reset 2371 * @pf: Board private structure 2372 */ 2373 void ice_ptp_reset(struct ice_pf *pf) 2374 { 2375 struct ice_ptp *ptp = &pf->ptp; 2376 struct ice_hw *hw = &pf->hw; 2377 struct timespec64 ts; 2378 int err, itr = 1; 2379 u64 time_diff; 2380 2381 if (test_bit(ICE_PFR_REQ, pf->state)) 2382 goto pfr; 2383 2384 if (!hw->func_caps.ts_func_info.src_tmr_owned) 2385 goto reset_ts; 2386 2387 err = ice_ptp_init_phc(hw); 2388 if (err) 2389 goto err; 2390 2391 /* Acquire the global hardware lock */ 2392 if (!ice_ptp_lock(hw)) { 2393 err = -EBUSY; 2394 goto err; 2395 } 2396 2397 /* Write the increment time value to PHY and LAN */ 2398 err = ice_ptp_write_incval(hw, ice_base_incval(pf)); 2399 if (err) { 2400 ice_ptp_unlock(hw); 2401 goto err; 2402 } 2403 2404 /* Write the initial Time value to PHY and LAN using the cached PHC 2405 * time before the reset and time difference between stopping and 2406 * starting the clock. 2407 */ 2408 if (ptp->cached_phc_time) { 2409 time_diff = ktime_get_real_ns() - ptp->reset_time; 2410 ts = ns_to_timespec64(ptp->cached_phc_time + time_diff); 2411 } else { 2412 ts = ktime_to_timespec64(ktime_get_real()); 2413 } 2414 err = ice_ptp_write_init(pf, &ts); 2415 if (err) { 2416 ice_ptp_unlock(hw); 2417 goto err; 2418 } 2419 2420 /* Release the global hardware lock */ 2421 ice_ptp_unlock(hw); 2422 2423 if (!ice_is_e810(hw)) { 2424 /* Enable quad interrupts */ 2425 err = ice_ptp_tx_ena_intr(pf, true, itr); 2426 if (err) 2427 goto err; 2428 } 2429 2430 reset_ts: 2431 /* Restart the PHY timestamping block */ 2432 ice_ptp_reset_phy_timestamping(pf); 2433 2434 pfr: 2435 /* Init Tx structures */ 2436 if (ice_is_e810(&pf->hw)) { 2437 err = ice_ptp_init_tx_e810(pf, &ptp->port.tx); 2438 } else { 2439 kthread_init_delayed_work(&ptp->port.ov_work, 2440 ice_ptp_wait_for_offset_valid); 2441 err = ice_ptp_init_tx_e822(pf, &ptp->port.tx, 2442 ptp->port.port_num); 2443 } 2444 if (err) 2445 goto err; 2446 2447 set_bit(ICE_FLAG_PTP, pf->flags); 2448 2449 /* Start periodic work going */ 2450 kthread_queue_delayed_work(ptp->kworker, &ptp->work, 0); 2451 2452 dev_info(ice_pf_to_dev(pf), "PTP reset successful\n"); 2453 return; 2454 2455 err: 2456 dev_err(ice_pf_to_dev(pf), "PTP reset failed %d\n", err); 2457 } 2458 2459 /** 2460 * ice_ptp_prepare_for_reset - Prepare PTP for reset 2461 * @pf: Board private structure 2462 */ 2463 void ice_ptp_prepare_for_reset(struct ice_pf *pf) 2464 { 2465 struct ice_ptp *ptp = &pf->ptp; 2466 u8 src_tmr; 2467 2468 clear_bit(ICE_FLAG_PTP, pf->flags); 2469 2470 /* Disable timestamping for both Tx and Rx */ 2471 ice_ptp_cfg_timestamp(pf, false); 2472 2473 kthread_cancel_delayed_work_sync(&ptp->work); 2474 kthread_cancel_work_sync(&ptp->extts_work); 2475 2476 if (test_bit(ICE_PFR_REQ, pf->state)) 2477 return; 2478 2479 ice_ptp_release_tx_tracker(pf, &pf->ptp.port.tx); 2480 2481 /* Disable periodic outputs */ 2482 ice_ptp_disable_all_clkout(pf); 2483 2484 src_tmr = ice_get_ptp_src_clock_index(&pf->hw); 2485 2486 /* Disable source clock */ 2487 wr32(&pf->hw, GLTSYN_ENA(src_tmr), (u32)~GLTSYN_ENA_TSYN_ENA_M); 2488 2489 /* Acquire PHC and system timer to restore after reset */ 2490 ptp->reset_time = ktime_get_real_ns(); 2491 } 2492 2493 /** 2494 * ice_ptp_init_owner - Initialize PTP_1588_CLOCK device 2495 * @pf: Board private structure 2496 * 2497 * Setup and initialize a PTP clock device that represents the device hardware 2498 * clock. Save the clock index for other functions connected to the same 2499 * hardware resource. 2500 */ 2501 static int ice_ptp_init_owner(struct ice_pf *pf) 2502 { 2503 struct ice_hw *hw = &pf->hw; 2504 struct timespec64 ts; 2505 int err, itr = 1; 2506 2507 err = ice_ptp_init_phc(hw); 2508 if (err) { 2509 dev_err(ice_pf_to_dev(pf), "Failed to initialize PHC, err %d\n", 2510 err); 2511 return err; 2512 } 2513 2514 /* Acquire the global hardware lock */ 2515 if (!ice_ptp_lock(hw)) { 2516 err = -EBUSY; 2517 goto err_exit; 2518 } 2519 2520 /* Write the increment time value to PHY and LAN */ 2521 err = ice_ptp_write_incval(hw, ice_base_incval(pf)); 2522 if (err) { 2523 ice_ptp_unlock(hw); 2524 goto err_exit; 2525 } 2526 2527 ts = ktime_to_timespec64(ktime_get_real()); 2528 /* Write the initial Time value to PHY and LAN */ 2529 err = ice_ptp_write_init(pf, &ts); 2530 if (err) { 2531 ice_ptp_unlock(hw); 2532 goto err_exit; 2533 } 2534 2535 /* Release the global hardware lock */ 2536 ice_ptp_unlock(hw); 2537 2538 if (!ice_is_e810(hw)) { 2539 /* Enable quad interrupts */ 2540 err = ice_ptp_tx_ena_intr(pf, true, itr); 2541 if (err) 2542 goto err_exit; 2543 } 2544 2545 /* Ensure we have a clock device */ 2546 err = ice_ptp_create_clock(pf); 2547 if (err) 2548 goto err_clk; 2549 2550 /* Store the PTP clock index for other PFs */ 2551 ice_set_ptp_clock_index(pf); 2552 2553 return 0; 2554 2555 err_clk: 2556 pf->ptp.clock = NULL; 2557 err_exit: 2558 return err; 2559 } 2560 2561 /** 2562 * ice_ptp_init_work - Initialize PTP work threads 2563 * @pf: Board private structure 2564 * @ptp: PF PTP structure 2565 */ 2566 static int ice_ptp_init_work(struct ice_pf *pf, struct ice_ptp *ptp) 2567 { 2568 struct kthread_worker *kworker; 2569 2570 /* Initialize work functions */ 2571 kthread_init_delayed_work(&ptp->work, ice_ptp_periodic_work); 2572 kthread_init_work(&ptp->extts_work, ice_ptp_extts_work); 2573 2574 /* Allocate a kworker for handling work required for the ports 2575 * connected to the PTP hardware clock. 2576 */ 2577 kworker = kthread_create_worker(0, "ice-ptp-%s", 2578 dev_name(ice_pf_to_dev(pf))); 2579 if (IS_ERR(kworker)) 2580 return PTR_ERR(kworker); 2581 2582 ptp->kworker = kworker; 2583 2584 /* Start periodic work going */ 2585 kthread_queue_delayed_work(ptp->kworker, &ptp->work, 0); 2586 2587 return 0; 2588 } 2589 2590 /** 2591 * ice_ptp_init_port - Initialize PTP port structure 2592 * @pf: Board private structure 2593 * @ptp_port: PTP port structure 2594 */ 2595 static int ice_ptp_init_port(struct ice_pf *pf, struct ice_ptp_port *ptp_port) 2596 { 2597 mutex_init(&ptp_port->ps_lock); 2598 2599 if (ice_is_e810(&pf->hw)) 2600 return ice_ptp_init_tx_e810(pf, &ptp_port->tx); 2601 2602 kthread_init_delayed_work(&ptp_port->ov_work, 2603 ice_ptp_wait_for_offset_valid); 2604 return ice_ptp_init_tx_e822(pf, &ptp_port->tx, ptp_port->port_num); 2605 } 2606 2607 /** 2608 * ice_ptp_init - Initialize PTP hardware clock support 2609 * @pf: Board private structure 2610 * 2611 * Set up the device for interacting with the PTP hardware clock for all 2612 * functions, both the function that owns the clock hardware, and the 2613 * functions connected to the clock hardware. 2614 * 2615 * The clock owner will allocate and register a ptp_clock with the 2616 * PTP_1588_CLOCK infrastructure. All functions allocate a kthread and work 2617 * items used for asynchronous work such as Tx timestamps and periodic work. 2618 */ 2619 void ice_ptp_init(struct ice_pf *pf) 2620 { 2621 struct ice_ptp *ptp = &pf->ptp; 2622 struct ice_hw *hw = &pf->hw; 2623 int err; 2624 2625 /* If this function owns the clock hardware, it must allocate and 2626 * configure the PTP clock device to represent it. 2627 */ 2628 if (hw->func_caps.ts_func_info.src_tmr_owned) { 2629 err = ice_ptp_init_owner(pf); 2630 if (err) 2631 goto err; 2632 } 2633 2634 ptp->port.port_num = hw->pf_id; 2635 err = ice_ptp_init_port(pf, &ptp->port); 2636 if (err) 2637 goto err; 2638 2639 /* Start the PHY timestamping block */ 2640 ice_ptp_reset_phy_timestamping(pf); 2641 2642 set_bit(ICE_FLAG_PTP, pf->flags); 2643 err = ice_ptp_init_work(pf, ptp); 2644 if (err) 2645 goto err; 2646 2647 dev_info(ice_pf_to_dev(pf), "PTP init successful\n"); 2648 return; 2649 2650 err: 2651 /* If we registered a PTP clock, release it */ 2652 if (pf->ptp.clock) { 2653 ptp_clock_unregister(ptp->clock); 2654 pf->ptp.clock = NULL; 2655 } 2656 clear_bit(ICE_FLAG_PTP, pf->flags); 2657 dev_err(ice_pf_to_dev(pf), "PTP failed %d\n", err); 2658 } 2659 2660 /** 2661 * ice_ptp_release - Disable the driver/HW support and unregister the clock 2662 * @pf: Board private structure 2663 * 2664 * This function handles the cleanup work required from the initialization by 2665 * clearing out the important information and unregistering the clock 2666 */ 2667 void ice_ptp_release(struct ice_pf *pf) 2668 { 2669 if (!test_bit(ICE_FLAG_PTP, pf->flags)) 2670 return; 2671 2672 /* Disable timestamping for both Tx and Rx */ 2673 ice_ptp_cfg_timestamp(pf, false); 2674 2675 ice_ptp_release_tx_tracker(pf, &pf->ptp.port.tx); 2676 2677 clear_bit(ICE_FLAG_PTP, pf->flags); 2678 2679 kthread_cancel_delayed_work_sync(&pf->ptp.work); 2680 2681 ice_ptp_port_phy_stop(&pf->ptp.port); 2682 mutex_destroy(&pf->ptp.port.ps_lock); 2683 if (pf->ptp.kworker) { 2684 kthread_destroy_worker(pf->ptp.kworker); 2685 pf->ptp.kworker = NULL; 2686 } 2687 2688 if (!pf->ptp.clock) 2689 return; 2690 2691 /* Disable periodic outputs */ 2692 ice_ptp_disable_all_clkout(pf); 2693 2694 ice_clear_ptp_clock_index(pf); 2695 ptp_clock_unregister(pf->ptp.clock); 2696 pf->ptp.clock = NULL; 2697 2698 dev_info(ice_pf_to_dev(pf), "Removed PTP clock\n"); 2699 } 2700