1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #include "ice_common.h" 5 6 /** 7 * ice_aq_read_nvm 8 * @hw: pointer to the hw struct 9 * @module_typeid: module pointer location in words from the NVM beginning 10 * @offset: byte offset from the module beginning 11 * @length: length of the section to be read (in bytes from the offset) 12 * @data: command buffer (size [bytes] = length) 13 * @last_command: tells if this is the last command in a series 14 * @cd: pointer to command details structure or NULL 15 * 16 * Read the NVM using the admin queue commands (0x0701) 17 */ 18 static enum ice_status 19 ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length, 20 void *data, bool last_command, struct ice_sq_cd *cd) 21 { 22 struct ice_aq_desc desc; 23 struct ice_aqc_nvm *cmd; 24 25 cmd = &desc.params.nvm; 26 27 /* In offset the highest byte must be zeroed. */ 28 if (offset & 0xFF000000) 29 return ICE_ERR_PARAM; 30 31 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read); 32 33 /* If this is the last command in a series, set the proper flag. */ 34 if (last_command) 35 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD; 36 cmd->module_typeid = cpu_to_le16(module_typeid); 37 cmd->offset_low = cpu_to_le16(offset & 0xFFFF); 38 cmd->offset_high = (offset >> 16) & 0xFF; 39 cmd->length = cpu_to_le16(length); 40 41 return ice_aq_send_cmd(hw, &desc, data, length, cd); 42 } 43 44 /** 45 * ice_check_sr_access_params - verify params for Shadow RAM R/W operations. 46 * @hw: pointer to the HW structure 47 * @offset: offset in words from module start 48 * @words: number of words to access 49 */ 50 static enum ice_status 51 ice_check_sr_access_params(struct ice_hw *hw, u32 offset, u16 words) 52 { 53 if ((offset + words) > hw->nvm.sr_words) { 54 ice_debug(hw, ICE_DBG_NVM, 55 "NVM error: offset beyond SR lmt.\n"); 56 return ICE_ERR_PARAM; 57 } 58 59 if (words > ICE_SR_SECTOR_SIZE_IN_WORDS) { 60 /* We can access only up to 4KB (one sector), in one AQ write */ 61 ice_debug(hw, ICE_DBG_NVM, 62 "NVM error: tried to access %d words, limit is %d.\n", 63 words, ICE_SR_SECTOR_SIZE_IN_WORDS); 64 return ICE_ERR_PARAM; 65 } 66 67 if (((offset + (words - 1)) / ICE_SR_SECTOR_SIZE_IN_WORDS) != 68 (offset / ICE_SR_SECTOR_SIZE_IN_WORDS)) { 69 /* A single access cannot spread over two sectors */ 70 ice_debug(hw, ICE_DBG_NVM, 71 "NVM error: cannot spread over two sectors.\n"); 72 return ICE_ERR_PARAM; 73 } 74 75 return 0; 76 } 77 78 /** 79 * ice_read_sr_aq - Read Shadow RAM. 80 * @hw: pointer to the HW structure 81 * @offset: offset in words from module start 82 * @words: number of words to read 83 * @data: buffer for words reads from Shadow RAM 84 * @last_command: tells the AdminQ that this is the last command 85 * 86 * Reads 16-bit word buffers from the Shadow RAM using the admin command. 87 */ 88 static enum ice_status 89 ice_read_sr_aq(struct ice_hw *hw, u32 offset, u16 words, u16 *data, 90 bool last_command) 91 { 92 enum ice_status status; 93 94 status = ice_check_sr_access_params(hw, offset, words); 95 96 /* values in "offset" and "words" parameters are sized as words 97 * (16 bits) but ice_aq_read_nvm expects these values in bytes. 98 * So do this conversion while calling ice_aq_read_nvm. 99 */ 100 if (!status) 101 status = ice_aq_read_nvm(hw, 0, 2 * offset, 2 * words, data, 102 last_command, NULL); 103 104 return status; 105 } 106 107 /** 108 * ice_read_sr_word_aq - Reads Shadow RAM via AQ 109 * @hw: pointer to the HW structure 110 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 111 * @data: word read from the Shadow RAM 112 * 113 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_aq method. 114 */ 115 static enum ice_status 116 ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data) 117 { 118 enum ice_status status; 119 120 status = ice_read_sr_aq(hw, offset, 1, data, true); 121 if (!status) 122 *data = le16_to_cpu(*(__le16 *)data); 123 124 return status; 125 } 126 127 /** 128 * ice_read_sr_buf_aq - Reads Shadow RAM buf via AQ 129 * @hw: pointer to the HW structure 130 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 131 * @words: (in) number of words to read; (out) number of words actually read 132 * @data: words read from the Shadow RAM 133 * 134 * Reads 16 bit words (data buf) from the SR using the ice_read_sr_aq 135 * method. Ownership of the NVM is taken before reading the buffer and later 136 * released. 137 */ 138 static enum ice_status 139 ice_read_sr_buf_aq(struct ice_hw *hw, u16 offset, u16 *words, u16 *data) 140 { 141 enum ice_status status; 142 bool last_cmd = false; 143 u16 words_read = 0; 144 u16 i = 0; 145 146 do { 147 u16 read_size, off_w; 148 149 /* Calculate number of bytes we should read in this step. 150 * It's not allowed to read more than one page at a time or 151 * to cross page boundaries. 152 */ 153 off_w = offset % ICE_SR_SECTOR_SIZE_IN_WORDS; 154 read_size = off_w ? 155 min(*words, 156 (u16)(ICE_SR_SECTOR_SIZE_IN_WORDS - off_w)) : 157 min((*words - words_read), ICE_SR_SECTOR_SIZE_IN_WORDS); 158 159 /* Check if this is last command, if so set proper flag */ 160 if ((words_read + read_size) >= *words) 161 last_cmd = true; 162 163 status = ice_read_sr_aq(hw, offset, read_size, 164 data + words_read, last_cmd); 165 if (status) 166 goto read_nvm_buf_aq_exit; 167 168 /* Increment counter for words already read and move offset to 169 * new read location 170 */ 171 words_read += read_size; 172 offset += read_size; 173 } while (words_read < *words); 174 175 for (i = 0; i < *words; i++) 176 data[i] = le16_to_cpu(((__le16 *)data)[i]); 177 178 read_nvm_buf_aq_exit: 179 *words = words_read; 180 return status; 181 } 182 183 /** 184 * ice_acquire_nvm - Generic request for acquiring the NVM ownership 185 * @hw: pointer to the HW structure 186 * @access: NVM access type (read or write) 187 * 188 * This function will request NVM ownership. 189 */ 190 static enum ice_status 191 ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access) 192 { 193 if (hw->nvm.blank_nvm_mode) 194 return 0; 195 196 return ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT); 197 } 198 199 /** 200 * ice_release_nvm - Generic request for releasing the NVM ownership 201 * @hw: pointer to the HW structure 202 * 203 * This function will release NVM ownership. 204 */ 205 static void ice_release_nvm(struct ice_hw *hw) 206 { 207 if (hw->nvm.blank_nvm_mode) 208 return; 209 210 ice_release_res(hw, ICE_NVM_RES_ID); 211 } 212 213 /** 214 * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary 215 * @hw: pointer to the HW structure 216 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 217 * @data: word read from the Shadow RAM 218 * 219 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq. 220 */ 221 static enum ice_status 222 ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data) 223 { 224 enum ice_status status; 225 226 status = ice_acquire_nvm(hw, ICE_RES_READ); 227 if (!status) { 228 status = ice_read_sr_word_aq(hw, offset, data); 229 ice_release_nvm(hw); 230 } 231 232 return status; 233 } 234 235 /** 236 * ice_init_nvm - initializes NVM setting 237 * @hw: pointer to the hw struct 238 * 239 * This function reads and populates NVM settings such as Shadow RAM size, 240 * max_timeout, and blank_nvm_mode 241 */ 242 enum ice_status ice_init_nvm(struct ice_hw *hw) 243 { 244 struct ice_nvm_info *nvm = &hw->nvm; 245 u16 eetrack_lo, eetrack_hi; 246 enum ice_status status = 0; 247 u32 fla, gens_stat; 248 u8 sr_size; 249 250 /* The SR size is stored regardless of the nvm programming mode 251 * as the blank mode may be used in the factory line. 252 */ 253 gens_stat = rd32(hw, GLNVM_GENS); 254 sr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S; 255 256 /* Switching to words (sr_size contains power of 2) */ 257 nvm->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB; 258 259 /* Check if we are in the normal or blank NVM programming mode */ 260 fla = rd32(hw, GLNVM_FLA); 261 if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */ 262 nvm->blank_nvm_mode = false; 263 } else { /* Blank programming mode */ 264 nvm->blank_nvm_mode = true; 265 status = ICE_ERR_NVM_BLANK_MODE; 266 ice_debug(hw, ICE_DBG_NVM, 267 "NVM init error: unsupported blank mode.\n"); 268 return status; 269 } 270 271 status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &hw->nvm.ver); 272 if (status) { 273 ice_debug(hw, ICE_DBG_INIT, 274 "Failed to read DEV starter version.\n"); 275 return status; 276 } 277 278 status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_LO, &eetrack_lo); 279 if (status) { 280 ice_debug(hw, ICE_DBG_INIT, "Failed to read EETRACK lo.\n"); 281 return status; 282 } 283 status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_HI, &eetrack_hi); 284 if (status) { 285 ice_debug(hw, ICE_DBG_INIT, "Failed to read EETRACK hi.\n"); 286 return status; 287 } 288 289 hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo; 290 291 return status; 292 } 293 294 /** 295 * ice_read_sr_buf - Reads Shadow RAM buf and acquire lock if necessary 296 * @hw: pointer to the HW structure 297 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 298 * @words: (in) number of words to read; (out) number of words actually read 299 * @data: words read from the Shadow RAM 300 * 301 * Reads 16 bit words (data buf) from the SR using the ice_read_nvm_buf_aq 302 * method. The buf read is preceded by the NVM ownership take 303 * and followed by the release. 304 */ 305 enum ice_status 306 ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data) 307 { 308 enum ice_status status; 309 310 status = ice_acquire_nvm(hw, ICE_RES_READ); 311 if (!status) { 312 status = ice_read_sr_buf_aq(hw, offset, words, data); 313 ice_release_nvm(hw); 314 } 315 316 return status; 317 } 318