1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #include "ice_common.h" 5 6 /** 7 * ice_aq_read_nvm 8 * @hw: pointer to the hw struct 9 * @module_typeid: module pointer location in words from the NVM beginning 10 * @offset: byte offset from the module beginning 11 * @length: length of the section to be read (in bytes from the offset) 12 * @data: command buffer (size [bytes] = length) 13 * @last_command: tells if this is the last command in a series 14 * @cd: pointer to command details structure or NULL 15 * 16 * Read the NVM using the admin queue commands (0x0701) 17 */ 18 static enum ice_status 19 ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length, 20 void *data, bool last_command, struct ice_sq_cd *cd) 21 { 22 struct ice_aq_desc desc; 23 struct ice_aqc_nvm *cmd; 24 25 cmd = &desc.params.nvm; 26 27 /* In offset the highest byte must be zeroed. */ 28 if (offset & 0xFF000000) 29 return ICE_ERR_PARAM; 30 31 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read); 32 33 /* If this is the last command in a series, set the proper flag. */ 34 if (last_command) 35 cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD; 36 cmd->module_typeid = cpu_to_le16(module_typeid); 37 cmd->offset_low = cpu_to_le16(offset & 0xFFFF); 38 cmd->offset_high = (offset >> 16) & 0xFF; 39 cmd->length = cpu_to_le16(length); 40 41 return ice_aq_send_cmd(hw, &desc, data, length, cd); 42 } 43 44 /** 45 * ice_check_sr_access_params - verify params for Shadow RAM R/W operations. 46 * @hw: pointer to the HW structure 47 * @offset: offset in words from module start 48 * @words: number of words to access 49 */ 50 static enum ice_status 51 ice_check_sr_access_params(struct ice_hw *hw, u32 offset, u16 words) 52 { 53 if ((offset + words) > hw->nvm.sr_words) { 54 ice_debug(hw, ICE_DBG_NVM, 55 "NVM error: offset beyond SR lmt.\n"); 56 return ICE_ERR_PARAM; 57 } 58 59 if (words > ICE_SR_SECTOR_SIZE_IN_WORDS) { 60 /* We can access only up to 4KB (one sector), in one AQ write */ 61 ice_debug(hw, ICE_DBG_NVM, 62 "NVM error: tried to access %d words, limit is %d.\n", 63 words, ICE_SR_SECTOR_SIZE_IN_WORDS); 64 return ICE_ERR_PARAM; 65 } 66 67 if (((offset + (words - 1)) / ICE_SR_SECTOR_SIZE_IN_WORDS) != 68 (offset / ICE_SR_SECTOR_SIZE_IN_WORDS)) { 69 /* A single access cannot spread over two sectors */ 70 ice_debug(hw, ICE_DBG_NVM, 71 "NVM error: cannot spread over two sectors.\n"); 72 return ICE_ERR_PARAM; 73 } 74 75 return 0; 76 } 77 78 /** 79 * ice_read_sr_aq - Read Shadow RAM. 80 * @hw: pointer to the HW structure 81 * @offset: offset in words from module start 82 * @words: number of words to read 83 * @data: buffer for words reads from Shadow RAM 84 * @last_command: tells the AdminQ that this is the last command 85 * 86 * Reads 16-bit word buffers from the Shadow RAM using the admin command. 87 */ 88 static enum ice_status 89 ice_read_sr_aq(struct ice_hw *hw, u32 offset, u16 words, u16 *data, 90 bool last_command) 91 { 92 enum ice_status status; 93 94 status = ice_check_sr_access_params(hw, offset, words); 95 96 /* values in "offset" and "words" parameters are sized as words 97 * (16 bits) but ice_aq_read_nvm expects these values in bytes. 98 * So do this conversion while calling ice_aq_read_nvm. 99 */ 100 if (!status) 101 status = ice_aq_read_nvm(hw, 0, 2 * offset, 2 * words, data, 102 last_command, NULL); 103 104 return status; 105 } 106 107 /** 108 * ice_read_sr_word_aq - Reads Shadow RAM via AQ 109 * @hw: pointer to the HW structure 110 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 111 * @data: word read from the Shadow RAM 112 * 113 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_aq method. 114 */ 115 static enum ice_status 116 ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data) 117 { 118 enum ice_status status; 119 120 status = ice_read_sr_aq(hw, offset, 1, data, true); 121 if (!status) 122 *data = le16_to_cpu(*(__le16 *)data); 123 124 return status; 125 } 126 127 /** 128 * ice_acquire_nvm - Generic request for acquiring the NVM ownership 129 * @hw: pointer to the HW structure 130 * @access: NVM access type (read or write) 131 * 132 * This function will request NVM ownership. 133 */ 134 static enum 135 ice_status ice_acquire_nvm(struct ice_hw *hw, 136 enum ice_aq_res_access_type access) 137 { 138 if (hw->nvm.blank_nvm_mode) 139 return 0; 140 141 return ice_acquire_res(hw, ICE_NVM_RES_ID, access); 142 } 143 144 /** 145 * ice_release_nvm - Generic request for releasing the NVM ownership 146 * @hw: pointer to the HW structure 147 * 148 * This function will release NVM ownership. 149 */ 150 static void ice_release_nvm(struct ice_hw *hw) 151 { 152 if (hw->nvm.blank_nvm_mode) 153 return; 154 155 ice_release_res(hw, ICE_NVM_RES_ID); 156 } 157 158 /** 159 * ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary 160 * @hw: pointer to the HW structure 161 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF) 162 * @data: word read from the Shadow RAM 163 * 164 * Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq. 165 */ 166 static enum ice_status 167 ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data) 168 { 169 enum ice_status status; 170 171 status = ice_acquire_nvm(hw, ICE_RES_READ); 172 if (!status) { 173 status = ice_read_sr_word_aq(hw, offset, data); 174 ice_release_nvm(hw); 175 } 176 177 return status; 178 } 179 180 /** 181 * ice_init_nvm - initializes NVM setting 182 * @hw: pointer to the hw struct 183 * 184 * This function reads and populates NVM settings such as Shadow RAM size, 185 * max_timeout, and blank_nvm_mode 186 */ 187 enum ice_status ice_init_nvm(struct ice_hw *hw) 188 { 189 struct ice_nvm_info *nvm = &hw->nvm; 190 u16 eetrack_lo, eetrack_hi; 191 enum ice_status status = 0; 192 u32 fla, gens_stat; 193 u8 sr_size; 194 195 /* The SR size is stored regardless of the nvm programming mode 196 * as the blank mode may be used in the factory line. 197 */ 198 gens_stat = rd32(hw, GLNVM_GENS); 199 sr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S; 200 201 /* Switching to words (sr_size contains power of 2) */ 202 nvm->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB; 203 204 /* Check if we are in the normal or blank NVM programming mode */ 205 fla = rd32(hw, GLNVM_FLA); 206 if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */ 207 nvm->blank_nvm_mode = false; 208 } else { /* Blank programming mode */ 209 nvm->blank_nvm_mode = true; 210 status = ICE_ERR_NVM_BLANK_MODE; 211 ice_debug(hw, ICE_DBG_NVM, 212 "NVM init error: unsupported blank mode.\n"); 213 return status; 214 } 215 216 status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &hw->nvm.ver); 217 if (status) { 218 ice_debug(hw, ICE_DBG_INIT, 219 "Failed to read DEV starter version.\n"); 220 return status; 221 } 222 223 status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_LO, &eetrack_lo); 224 if (status) { 225 ice_debug(hw, ICE_DBG_INIT, "Failed to read EETRACK lo.\n"); 226 return status; 227 } 228 status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_HI, &eetrack_hi); 229 if (status) { 230 ice_debug(hw, ICE_DBG_INIT, "Failed to read EETRACK hi.\n"); 231 return status; 232 } 233 234 hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo; 235 236 return status; 237 } 238