1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018, Intel Corporation. */ 3 4 #ifndef _ICE_LAN_TX_RX_H_ 5 #define _ICE_LAN_TX_RX_H_ 6 7 union ice_32byte_rx_desc { 8 struct { 9 __le64 pkt_addr; /* Packet buffer address */ 10 __le64 hdr_addr; /* Header buffer address */ 11 /* bit 0 of hdr_addr is DD bit */ 12 __le64 rsvd1; 13 __le64 rsvd2; 14 } read; 15 struct { 16 struct { 17 struct { 18 __le16 mirroring_status; 19 __le16 l2tag1; 20 } lo_dword; 21 union { 22 __le32 rss; /* RSS Hash */ 23 __le32 fd_id; /* Flow Director filter ID */ 24 } hi_dword; 25 } qword0; 26 struct { 27 /* status/error/PTYPE/length */ 28 __le64 status_error_len; 29 } qword1; 30 struct { 31 __le16 ext_status; /* extended status */ 32 __le16 rsvd; 33 __le16 l2tag2_1; 34 __le16 l2tag2_2; 35 } qword2; 36 struct { 37 __le32 reserved; 38 __le32 fd_id; 39 } qword3; 40 } wb; /* writeback */ 41 }; 42 43 struct ice_fltr_desc { 44 __le64 qidx_compq_space_stat; 45 __le64 dtype_cmd_vsi_fdid; 46 }; 47 48 #define ICE_FXD_FLTR_QW0_QINDEX_S 0 49 #define ICE_FXD_FLTR_QW0_QINDEX_M (0x7FFULL << ICE_FXD_FLTR_QW0_QINDEX_S) 50 #define ICE_FXD_FLTR_QW0_COMP_Q_S 11 51 #define ICE_FXD_FLTR_QW0_COMP_Q_M BIT_ULL(ICE_FXD_FLTR_QW0_COMP_Q_S) 52 #define ICE_FXD_FLTR_QW0_COMP_Q_ZERO 0x0ULL 53 54 #define ICE_FXD_FLTR_QW0_COMP_REPORT_S 12 55 #define ICE_FXD_FLTR_QW0_COMP_REPORT_M \ 56 (0x3ULL << ICE_FXD_FLTR_QW0_COMP_REPORT_S) 57 #define ICE_FXD_FLTR_QW0_COMP_REPORT_SW_FAIL 0x1ULL 58 #define ICE_FXD_FLTR_QW0_COMP_REPORT_SW 0x2ULL 59 60 #define ICE_FXD_FLTR_QW0_FD_SPACE_S 14 61 #define ICE_FXD_FLTR_QW0_FD_SPACE_M (0x3ULL << ICE_FXD_FLTR_QW0_FD_SPACE_S) 62 #define ICE_FXD_FLTR_QW0_FD_SPACE_GUAR_BEST 0x2ULL 63 64 #define ICE_FXD_FLTR_QW0_STAT_CNT_S 16 65 #define ICE_FXD_FLTR_QW0_STAT_CNT_M \ 66 (0x1FFFULL << ICE_FXD_FLTR_QW0_STAT_CNT_S) 67 #define ICE_FXD_FLTR_QW0_STAT_ENA_S 29 68 #define ICE_FXD_FLTR_QW0_STAT_ENA_M (0x3ULL << ICE_FXD_FLTR_QW0_STAT_ENA_S) 69 #define ICE_FXD_FLTR_QW0_STAT_ENA_PKTS 0x1ULL 70 71 #define ICE_FXD_FLTR_QW0_EVICT_ENA_S 31 72 #define ICE_FXD_FLTR_QW0_EVICT_ENA_M BIT_ULL(ICE_FXD_FLTR_QW0_EVICT_ENA_S) 73 #define ICE_FXD_FLTR_QW0_EVICT_ENA_FALSE 0x0ULL 74 #define ICE_FXD_FLTR_QW0_EVICT_ENA_TRUE 0x1ULL 75 76 #define ICE_FXD_FLTR_QW0_TO_Q_S 32 77 #define ICE_FXD_FLTR_QW0_TO_Q_M (0x7ULL << ICE_FXD_FLTR_QW0_TO_Q_S) 78 #define ICE_FXD_FLTR_QW0_TO_Q_EQUALS_QINDEX 0x0ULL 79 80 #define ICE_FXD_FLTR_QW0_TO_Q_PRI_S 35 81 #define ICE_FXD_FLTR_QW0_TO_Q_PRI_M (0x7ULL << ICE_FXD_FLTR_QW0_TO_Q_PRI_S) 82 #define ICE_FXD_FLTR_QW0_TO_Q_PRIO1 0x1ULL 83 84 #define ICE_FXD_FLTR_QW0_DPU_RECIPE_S 38 85 #define ICE_FXD_FLTR_QW0_DPU_RECIPE_M \ 86 (0x3ULL << ICE_FXD_FLTR_QW0_DPU_RECIPE_S) 87 #define ICE_FXD_FLTR_QW0_DPU_RECIPE_DFLT 0x0ULL 88 89 #define ICE_FXD_FLTR_QW0_DROP_S 40 90 #define ICE_FXD_FLTR_QW0_DROP_M BIT_ULL(ICE_FXD_FLTR_QW0_DROP_S) 91 #define ICE_FXD_FLTR_QW0_DROP_NO 0x0ULL 92 #define ICE_FXD_FLTR_QW0_DROP_YES 0x1ULL 93 94 #define ICE_FXD_FLTR_QW0_FLEX_PRI_S 41 95 #define ICE_FXD_FLTR_QW0_FLEX_PRI_M (0x7ULL << ICE_FXD_FLTR_QW0_FLEX_PRI_S) 96 #define ICE_FXD_FLTR_QW0_FLEX_PRI_NONE 0x0ULL 97 98 #define ICE_FXD_FLTR_QW0_FLEX_MDID_S 44 99 #define ICE_FXD_FLTR_QW0_FLEX_MDID_M (0xFULL << ICE_FXD_FLTR_QW0_FLEX_MDID_S) 100 #define ICE_FXD_FLTR_QW0_FLEX_MDID0 0x0ULL 101 102 #define ICE_FXD_FLTR_QW0_FLEX_VAL_S 48 103 #define ICE_FXD_FLTR_QW0_FLEX_VAL_M \ 104 (0xFFFFULL << ICE_FXD_FLTR_QW0_FLEX_VAL_S) 105 #define ICE_FXD_FLTR_QW0_FLEX_VAL0 0x0ULL 106 107 #define ICE_FXD_FLTR_QW1_DTYPE_S 0 108 #define ICE_FXD_FLTR_QW1_DTYPE_M (0xFULL << ICE_FXD_FLTR_QW1_DTYPE_S) 109 #define ICE_FXD_FLTR_QW1_PCMD_S 4 110 #define ICE_FXD_FLTR_QW1_PCMD_M BIT_ULL(ICE_FXD_FLTR_QW1_PCMD_S) 111 #define ICE_FXD_FLTR_QW1_PCMD_ADD 0x0ULL 112 #define ICE_FXD_FLTR_QW1_PCMD_REMOVE 0x1ULL 113 114 #define ICE_FXD_FLTR_QW1_PROF_PRI_S 5 115 #define ICE_FXD_FLTR_QW1_PROF_PRI_M (0x7ULL << ICE_FXD_FLTR_QW1_PROF_PRI_S) 116 #define ICE_FXD_FLTR_QW1_PROF_PRIO_ZERO 0x0ULL 117 118 #define ICE_FXD_FLTR_QW1_PROF_S 8 119 #define ICE_FXD_FLTR_QW1_PROF_M (0x3FULL << ICE_FXD_FLTR_QW1_PROF_S) 120 #define ICE_FXD_FLTR_QW1_PROF_ZERO 0x0ULL 121 122 #define ICE_FXD_FLTR_QW1_FD_VSI_S 14 123 #define ICE_FXD_FLTR_QW1_FD_VSI_M (0x3FFULL << ICE_FXD_FLTR_QW1_FD_VSI_S) 124 #define ICE_FXD_FLTR_QW1_SWAP_S 24 125 #define ICE_FXD_FLTR_QW1_SWAP_M BIT_ULL(ICE_FXD_FLTR_QW1_SWAP_S) 126 #define ICE_FXD_FLTR_QW1_SWAP_NOT_SET 0x0ULL 127 #define ICE_FXD_FLTR_QW1_SWAP_SET 0x1ULL 128 129 #define ICE_FXD_FLTR_QW1_FDID_PRI_S 25 130 #define ICE_FXD_FLTR_QW1_FDID_PRI_M (0x7ULL << ICE_FXD_FLTR_QW1_FDID_PRI_S) 131 #define ICE_FXD_FLTR_QW1_FDID_PRI_ONE 0x1ULL 132 #define ICE_FXD_FLTR_QW1_FDID_PRI_THREE 0x3ULL 133 134 #define ICE_FXD_FLTR_QW1_FDID_MDID_S 28 135 #define ICE_FXD_FLTR_QW1_FDID_MDID_M (0xFULL << ICE_FXD_FLTR_QW1_FDID_MDID_S) 136 #define ICE_FXD_FLTR_QW1_FDID_MDID_FD 0x05ULL 137 138 #define ICE_FXD_FLTR_QW1_FDID_S 32 139 #define ICE_FXD_FLTR_QW1_FDID_M \ 140 (0xFFFFFFFFULL << ICE_FXD_FLTR_QW1_FDID_S) 141 #define ICE_FXD_FLTR_QW1_FDID_ZERO 0x0ULL 142 143 /* definition for FD filter programming status descriptor WB format */ 144 #define ICE_FXD_FLTR_WB_QW1_DD_S 0 145 #define ICE_FXD_FLTR_WB_QW1_DD_M (0x1ULL << ICE_FXD_FLTR_WB_QW1_DD_S) 146 #define ICE_FXD_FLTR_WB_QW1_DD_YES 0x1ULL 147 148 #define ICE_FXD_FLTR_WB_QW1_PROG_ID_S 1 149 #define ICE_FXD_FLTR_WB_QW1_PROG_ID_M \ 150 (0x3ULL << ICE_FXD_FLTR_WB_QW1_PROG_ID_S) 151 #define ICE_FXD_FLTR_WB_QW1_PROG_ADD 0x0ULL 152 #define ICE_FXD_FLTR_WB_QW1_PROG_DEL 0x1ULL 153 154 #define ICE_FXD_FLTR_WB_QW1_FAIL_S 4 155 #define ICE_FXD_FLTR_WB_QW1_FAIL_M (0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_S) 156 #define ICE_FXD_FLTR_WB_QW1_FAIL_YES 0x1ULL 157 158 #define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S 5 159 #define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_M \ 160 (0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S) 161 #define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_YES 0x1ULL 162 163 struct ice_rx_ptype_decoded { 164 u32 ptype:10; 165 u32 known:1; 166 u32 outer_ip:1; 167 u32 outer_ip_ver:2; 168 u32 outer_frag:1; 169 u32 tunnel_type:3; 170 u32 tunnel_end_prot:2; 171 u32 tunnel_end_frag:1; 172 u32 inner_prot:4; 173 u32 payload_layer:3; 174 }; 175 176 enum ice_rx_ptype_outer_ip { 177 ICE_RX_PTYPE_OUTER_L2 = 0, 178 ICE_RX_PTYPE_OUTER_IP = 1, 179 }; 180 181 enum ice_rx_ptype_outer_ip_ver { 182 ICE_RX_PTYPE_OUTER_NONE = 0, 183 ICE_RX_PTYPE_OUTER_IPV4 = 1, 184 ICE_RX_PTYPE_OUTER_IPV6 = 2, 185 }; 186 187 enum ice_rx_ptype_outer_fragmented { 188 ICE_RX_PTYPE_NOT_FRAG = 0, 189 ICE_RX_PTYPE_FRAG = 1, 190 }; 191 192 enum ice_rx_ptype_tunnel_type { 193 ICE_RX_PTYPE_TUNNEL_NONE = 0, 194 ICE_RX_PTYPE_TUNNEL_IP_IP = 1, 195 ICE_RX_PTYPE_TUNNEL_IP_GRENAT = 2, 196 ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3, 197 ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4, 198 }; 199 200 enum ice_rx_ptype_tunnel_end_prot { 201 ICE_RX_PTYPE_TUNNEL_END_NONE = 0, 202 ICE_RX_PTYPE_TUNNEL_END_IPV4 = 1, 203 ICE_RX_PTYPE_TUNNEL_END_IPV6 = 2, 204 }; 205 206 enum ice_rx_ptype_inner_prot { 207 ICE_RX_PTYPE_INNER_PROT_NONE = 0, 208 ICE_RX_PTYPE_INNER_PROT_UDP = 1, 209 ICE_RX_PTYPE_INNER_PROT_TCP = 2, 210 ICE_RX_PTYPE_INNER_PROT_SCTP = 3, 211 ICE_RX_PTYPE_INNER_PROT_ICMP = 4, 212 ICE_RX_PTYPE_INNER_PROT_TIMESYNC = 5, 213 }; 214 215 enum ice_rx_ptype_payload_layer { 216 ICE_RX_PTYPE_PAYLOAD_LAYER_NONE = 0, 217 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1, 218 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2, 219 ICE_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, 220 }; 221 222 /* Rx Flex Descriptor 223 * This descriptor is used instead of the legacy version descriptor when 224 * ice_rlan_ctx.adv_desc is set 225 */ 226 union ice_32b_rx_flex_desc { 227 struct { 228 __le64 pkt_addr; /* Packet buffer address */ 229 __le64 hdr_addr; /* Header buffer address */ 230 /* bit 0 of hdr_addr is DD bit */ 231 __le64 rsvd1; 232 __le64 rsvd2; 233 } read; 234 struct { 235 /* Qword 0 */ 236 u8 rxdid; /* descriptor builder profile ID */ 237 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */ 238 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */ 239 __le16 pkt_len; /* [15:14] are reserved */ 240 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */ 241 /* sph=[11:11] */ 242 /* ff1/ext=[15:12] */ 243 244 /* Qword 1 */ 245 __le16 status_error0; 246 __le16 l2tag1; 247 __le16 flex_meta0; 248 __le16 flex_meta1; 249 250 /* Qword 2 */ 251 __le16 status_error1; 252 u8 flex_flags2; 253 u8 time_stamp_low; 254 __le16 l2tag2_1st; 255 __le16 l2tag2_2nd; 256 257 /* Qword 3 */ 258 __le16 flex_meta2; 259 __le16 flex_meta3; 260 union { 261 struct { 262 __le16 flex_meta4; 263 __le16 flex_meta5; 264 } flex; 265 __le32 ts_high; 266 } flex_ts; 267 } wb; /* writeback */ 268 }; 269 270 /* Rx Flex Descriptor NIC Profile 271 * This descriptor corresponds to RxDID 2 which contains 272 * metadata fields for RSS, flow ID and timestamp info 273 */ 274 struct ice_32b_rx_flex_desc_nic { 275 /* Qword 0 */ 276 u8 rxdid; 277 u8 mir_id_umb_cast; 278 __le16 ptype_flexi_flags0; 279 __le16 pkt_len; 280 __le16 hdr_len_sph_flex_flags1; 281 282 /* Qword 1 */ 283 __le16 status_error0; 284 __le16 l2tag1; 285 __le32 rss_hash; 286 287 /* Qword 2 */ 288 __le16 status_error1; 289 u8 flexi_flags2; 290 u8 ts_low; 291 __le16 l2tag2_1st; 292 __le16 l2tag2_2nd; 293 294 /* Qword 3 */ 295 __le32 flow_id; 296 union { 297 struct { 298 __le16 vlan_id; 299 __le16 flow_id_ipv6; 300 } flex; 301 __le32 ts_high; 302 } flex_ts; 303 }; 304 305 /* Receive Flex Descriptor profile IDs: There are a total 306 * of 64 profiles where profile IDs 0/1 are for legacy; and 307 * profiles 2-63 are flex profiles that can be programmed 308 * with a specific metadata (profile 7 reserved for HW) 309 */ 310 enum ice_rxdid { 311 ICE_RXDID_LEGACY_0 = 0, 312 ICE_RXDID_LEGACY_1 = 1, 313 ICE_RXDID_FLEX_NIC = 2, 314 ICE_RXDID_FLEX_NIC_2 = 6, 315 ICE_RXDID_HW = 7, 316 ICE_RXDID_LAST = 63, 317 }; 318 319 /* Receive Flex Descriptor Rx opcode values */ 320 #define ICE_RX_OPC_MDID 0x01 321 322 /* Receive Descriptor MDID values that access packet flags */ 323 enum ice_flex_mdid_pkt_flags { 324 ICE_RX_MDID_PKT_FLAGS_15_0 = 20, 325 ICE_RX_MDID_PKT_FLAGS_31_16, 326 ICE_RX_MDID_PKT_FLAGS_47_32, 327 ICE_RX_MDID_PKT_FLAGS_63_48, 328 }; 329 330 /* Receive Descriptor MDID values */ 331 enum ice_flex_rx_mdid { 332 ICE_RX_MDID_FLOW_ID_LOWER = 5, 333 ICE_RX_MDID_FLOW_ID_HIGH, 334 ICE_RX_MDID_SRC_VSI = 19, 335 ICE_RX_MDID_HASH_LOW = 56, 336 ICE_RX_MDID_HASH_HIGH, 337 }; 338 339 /* Rx/Tx Flag64 packet flag bits */ 340 enum ice_flg64_bits { 341 ICE_FLG_PKT_DSI = 0, 342 ICE_FLG_EVLAN_x8100 = 14, 343 ICE_FLG_EVLAN_x9100, 344 ICE_FLG_VLAN_x8100, 345 ICE_FLG_TNL_MAC = 22, 346 ICE_FLG_TNL_VLAN, 347 ICE_FLG_PKT_FRG, 348 ICE_FLG_FIN = 32, 349 ICE_FLG_SYN, 350 ICE_FLG_RST, 351 ICE_FLG_TNL0 = 38, 352 ICE_FLG_TNL1, 353 ICE_FLG_TNL2, 354 ICE_FLG_UDP_GRE, 355 ICE_FLG_RSVD = 63 356 }; 357 358 /* for ice_32byte_rx_flex_desc.ptype_flexi_flags0 member */ 359 #define ICE_RX_FLEX_DESC_PTYPE_M (0x3FF) /* 10-bits */ 360 361 /* for ice_32byte_rx_flex_desc.pkt_length member */ 362 #define ICE_RX_FLX_DESC_PKT_LEN_M (0x3FFF) /* 14-bits */ 363 364 enum ice_rx_flex_desc_status_error_0_bits { 365 /* Note: These are predefined bit offsets */ 366 ICE_RX_FLEX_DESC_STATUS0_DD_S = 0, 367 ICE_RX_FLEX_DESC_STATUS0_EOF_S, 368 ICE_RX_FLEX_DESC_STATUS0_HBO_S, 369 ICE_RX_FLEX_DESC_STATUS0_L3L4P_S, 370 ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S, 371 ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S, 372 ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S, 373 ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S, 374 ICE_RX_FLEX_DESC_STATUS0_LPBK_S, 375 ICE_RX_FLEX_DESC_STATUS0_IPV6EXADD_S, 376 ICE_RX_FLEX_DESC_STATUS0_RXE_S, 377 ICE_RX_FLEX_DESC_STATUS0_CRCP_S, 378 ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S, 379 ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S, 380 ICE_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S, 381 ICE_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S, 382 ICE_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */ 383 }; 384 385 enum ice_rx_flex_desc_status_error_1_bits { 386 /* Note: These are predefined bit offsets */ 387 ICE_RX_FLEX_DESC_STATUS1_NAT_S = 4, 388 ICE_RX_FLEX_DESC_STATUS1_LAST /* this entry must be last!!! */ 389 }; 390 391 #define ICE_RXQ_CTX_SIZE_DWORDS 8 392 #define ICE_RXQ_CTX_SZ (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32)) 393 #define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS 22 394 #define ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS 5 395 #define GLTCLAN_CQ_CNTX(i, CQ) (GLTCLAN_CQ_CNTX0(CQ) + ((i) * 0x0800)) 396 397 /* RLAN Rx queue context data 398 * 399 * The sizes of the variables may be larger than needed due to crossing byte 400 * boundaries. If we do not have the width of the variable set to the correct 401 * size then we could end up shifting bits off the top of the variable when the 402 * variable is at the top of a byte and crosses over into the next byte. 403 */ 404 struct ice_rlan_ctx { 405 u16 head; 406 u16 cpuid; /* bigger than needed, see above for reason */ 407 #define ICE_RLAN_BASE_S 7 408 u64 base; 409 u16 qlen; 410 #define ICE_RLAN_CTX_DBUF_S 7 411 u16 dbuf; /* bigger than needed, see above for reason */ 412 #define ICE_RLAN_CTX_HBUF_S 6 413 u16 hbuf; /* bigger than needed, see above for reason */ 414 u8 dtype; 415 u8 dsize; 416 u8 crcstrip; 417 u8 l2tsel; 418 u8 hsplit_0; 419 u8 hsplit_1; 420 u8 showiv; 421 u32 rxmax; /* bigger than needed, see above for reason */ 422 u8 tphrdesc_ena; 423 u8 tphwdesc_ena; 424 u8 tphdata_ena; 425 u8 tphhead_ena; 426 u16 lrxqthresh; /* bigger than needed, see above for reason */ 427 u8 prefena; /* NOTE: normally must be set to 1 at init */ 428 }; 429 430 struct ice_ctx_ele { 431 u16 offset; 432 u16 size_of; 433 u16 width; 434 u16 lsb; 435 }; 436 437 #define ICE_CTX_STORE(_struct, _ele, _width, _lsb) { \ 438 .offset = offsetof(struct _struct, _ele), \ 439 .size_of = sizeof_field(struct _struct, _ele), \ 440 .width = _width, \ 441 .lsb = _lsb, \ 442 } 443 444 /* for hsplit_0 field of Rx RLAN context */ 445 enum ice_rlan_ctx_rx_hsplit_0 { 446 ICE_RLAN_RX_HSPLIT_0_NO_SPLIT = 0, 447 ICE_RLAN_RX_HSPLIT_0_SPLIT_L2 = 1, 448 ICE_RLAN_RX_HSPLIT_0_SPLIT_IP = 2, 449 ICE_RLAN_RX_HSPLIT_0_SPLIT_TCP_UDP = 4, 450 ICE_RLAN_RX_HSPLIT_0_SPLIT_SCTP = 8, 451 }; 452 453 /* for hsplit_1 field of Rx RLAN context */ 454 enum ice_rlan_ctx_rx_hsplit_1 { 455 ICE_RLAN_RX_HSPLIT_1_NO_SPLIT = 0, 456 ICE_RLAN_RX_HSPLIT_1_SPLIT_L2 = 1, 457 ICE_RLAN_RX_HSPLIT_1_SPLIT_ALWAYS = 2, 458 }; 459 460 /* Tx Descriptor */ 461 struct ice_tx_desc { 462 __le64 buf_addr; /* Address of descriptor's data buf */ 463 __le64 cmd_type_offset_bsz; 464 }; 465 466 enum ice_tx_desc_dtype_value { 467 ICE_TX_DESC_DTYPE_DATA = 0x0, 468 ICE_TX_DESC_DTYPE_CTX = 0x1, 469 ICE_TX_DESC_DTYPE_FLTR_PROG = 0x8, 470 /* DESC_DONE - HW has completed write-back of descriptor */ 471 ICE_TX_DESC_DTYPE_DESC_DONE = 0xF, 472 }; 473 474 #define ICE_TXD_QW1_CMD_S 4 475 #define ICE_TXD_QW1_CMD_M (0xFFFUL << ICE_TXD_QW1_CMD_S) 476 477 enum ice_tx_desc_cmd_bits { 478 ICE_TX_DESC_CMD_EOP = 0x0001, 479 ICE_TX_DESC_CMD_RS = 0x0002, 480 ICE_TX_DESC_CMD_IL2TAG1 = 0x0008, 481 ICE_TX_DESC_CMD_DUMMY = 0x0010, 482 ICE_TX_DESC_CMD_IIPT_IPV6 = 0x0020, 483 ICE_TX_DESC_CMD_IIPT_IPV4 = 0x0040, 484 ICE_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, 485 ICE_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, 486 ICE_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, 487 ICE_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, 488 ICE_TX_DESC_CMD_RE = 0x0400, 489 }; 490 491 #define ICE_TXD_QW1_OFFSET_S 16 492 #define ICE_TXD_QW1_OFFSET_M (0x3FFFFULL << ICE_TXD_QW1_OFFSET_S) 493 494 enum ice_tx_desc_len_fields { 495 /* Note: These are predefined bit offsets */ 496 ICE_TX_DESC_LEN_MACLEN_S = 0, /* 7 BITS */ 497 ICE_TX_DESC_LEN_IPLEN_S = 7, /* 7 BITS */ 498 ICE_TX_DESC_LEN_L4_LEN_S = 14 /* 4 BITS */ 499 }; 500 501 #define ICE_TXD_QW1_MACLEN_M (0x7FUL << ICE_TX_DESC_LEN_MACLEN_S) 502 #define ICE_TXD_QW1_IPLEN_M (0x7FUL << ICE_TX_DESC_LEN_IPLEN_S) 503 #define ICE_TXD_QW1_L4LEN_M (0xFUL << ICE_TX_DESC_LEN_L4_LEN_S) 504 505 /* Tx descriptor field limits in bytes */ 506 #define ICE_TXD_MACLEN_MAX ((ICE_TXD_QW1_MACLEN_M >> \ 507 ICE_TX_DESC_LEN_MACLEN_S) * ICE_BYTES_PER_WORD) 508 #define ICE_TXD_IPLEN_MAX ((ICE_TXD_QW1_IPLEN_M >> \ 509 ICE_TX_DESC_LEN_IPLEN_S) * ICE_BYTES_PER_DWORD) 510 #define ICE_TXD_L4LEN_MAX ((ICE_TXD_QW1_L4LEN_M >> \ 511 ICE_TX_DESC_LEN_L4_LEN_S) * ICE_BYTES_PER_DWORD) 512 513 #define ICE_TXD_QW1_TX_BUF_SZ_S 34 514 #define ICE_TXD_QW1_L2TAG1_S 48 515 516 /* Context descriptors */ 517 struct ice_tx_ctx_desc { 518 __le32 tunneling_params; 519 __le16 l2tag2; 520 __le16 rsvd; 521 __le64 qw1; 522 }; 523 524 #define ICE_TXD_CTX_QW1_CMD_S 4 525 #define ICE_TXD_CTX_QW1_CMD_M (0x7FUL << ICE_TXD_CTX_QW1_CMD_S) 526 527 #define ICE_TXD_CTX_QW1_TSO_LEN_S 30 528 #define ICE_TXD_CTX_QW1_TSO_LEN_M \ 529 (0x3FFFFULL << ICE_TXD_CTX_QW1_TSO_LEN_S) 530 531 #define ICE_TXD_CTX_QW1_MSS_S 50 532 533 enum ice_tx_ctx_desc_cmd_bits { 534 ICE_TX_CTX_DESC_TSO = 0x01, 535 ICE_TX_CTX_DESC_TSYN = 0x02, 536 ICE_TX_CTX_DESC_IL2TAG2 = 0x04, 537 ICE_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, 538 ICE_TX_CTX_DESC_SWTCH_NOTAG = 0x00, 539 ICE_TX_CTX_DESC_SWTCH_UPLINK = 0x10, 540 ICE_TX_CTX_DESC_SWTCH_LOCAL = 0x20, 541 ICE_TX_CTX_DESC_SWTCH_VSI = 0x30, 542 ICE_TX_CTX_DESC_RESERVED = 0x40 543 }; 544 545 enum ice_tx_ctx_desc_eipt_offload { 546 ICE_TX_CTX_EIPT_NONE = 0x0, 547 ICE_TX_CTX_EIPT_IPV6 = 0x1, 548 ICE_TX_CTX_EIPT_IPV4_NO_CSUM = 0x2, 549 ICE_TX_CTX_EIPT_IPV4 = 0x3 550 }; 551 552 #define ICE_TXD_CTX_QW0_EIPLEN_S 2 553 554 #define ICE_TXD_CTX_QW0_L4TUNT_S 9 555 556 #define ICE_TXD_CTX_UDP_TUNNELING BIT_ULL(ICE_TXD_CTX_QW0_L4TUNT_S) 557 #define ICE_TXD_CTX_GRE_TUNNELING (0x2ULL << ICE_TXD_CTX_QW0_L4TUNT_S) 558 559 #define ICE_TXD_CTX_QW0_NATLEN_S 12 560 561 #define ICE_TXD_CTX_QW0_L4T_CS_S 23 562 #define ICE_TXD_CTX_QW0_L4T_CS_M BIT_ULL(ICE_TXD_CTX_QW0_L4T_CS_S) 563 564 #define ICE_LAN_TXQ_MAX_QGRPS 127 565 #define ICE_LAN_TXQ_MAX_QDIS 1023 566 567 /* Tx queue context data 568 * 569 * The sizes of the variables may be larger than needed due to crossing byte 570 * boundaries. If we do not have the width of the variable set to the correct 571 * size then we could end up shifting bits off the top of the variable when the 572 * variable is at the top of a byte and crosses over into the next byte. 573 */ 574 struct ice_tlan_ctx { 575 #define ICE_TLAN_CTX_BASE_S 7 576 u64 base; /* base is defined in 128-byte units */ 577 u8 port_num; 578 u16 cgd_num; /* bigger than needed, see above for reason */ 579 u8 pf_num; 580 u16 vmvf_num; 581 u8 vmvf_type; 582 #define ICE_TLAN_CTX_VMVF_TYPE_VF 0 583 #define ICE_TLAN_CTX_VMVF_TYPE_VMQ 1 584 #define ICE_TLAN_CTX_VMVF_TYPE_PF 2 585 u16 src_vsi; 586 u8 tsyn_ena; 587 u8 internal_usage_flag; 588 u8 alt_vlan; 589 u16 cpuid; /* bigger than needed, see above for reason */ 590 u8 wb_mode; 591 u8 tphrd_desc; 592 u8 tphrd; 593 u8 tphwr_desc; 594 u16 cmpq_id; 595 u16 qnum_in_func; 596 u8 itr_notification_mode; 597 u8 adjust_prof_id; 598 u32 qlen; /* bigger than needed, see above for reason */ 599 u8 quanta_prof_idx; 600 u8 tso_ena; 601 u16 tso_qnum; 602 u8 legacy_int; 603 u8 drop_ena; 604 u8 cache_prof_idx; 605 u8 pkt_shaper_prof_idx; 606 u8 int_q_state; /* width not needed - internal - DO NOT WRITE!!! */ 607 }; 608 609 /* macro to make the table lines short */ 610 #define ICE_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\ 611 { PTYPE, \ 612 1, \ 613 ICE_RX_PTYPE_OUTER_##OUTER_IP, \ 614 ICE_RX_PTYPE_OUTER_##OUTER_IP_VER, \ 615 ICE_RX_PTYPE_##OUTER_FRAG, \ 616 ICE_RX_PTYPE_TUNNEL_##T, \ 617 ICE_RX_PTYPE_TUNNEL_END_##TE, \ 618 ICE_RX_PTYPE_##TEF, \ 619 ICE_RX_PTYPE_INNER_PROT_##I, \ 620 ICE_RX_PTYPE_PAYLOAD_LAYER_##PL } 621 622 #define ICE_PTT_UNUSED_ENTRY(PTYPE) { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 623 624 /* shorter macros makes the table fit but are terse */ 625 #define ICE_RX_PTYPE_NOF ICE_RX_PTYPE_NOT_FRAG 626 #define ICE_RX_PTYPE_FRG ICE_RX_PTYPE_FRAG 627 628 /* Lookup table mapping the HW PTYPE to the bit field for decoding */ 629 static const struct ice_rx_ptype_decoded ice_ptype_lkup[] = { 630 /* L2 Packet types */ 631 ICE_PTT_UNUSED_ENTRY(0), 632 ICE_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2), 633 ICE_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 634 ICE_PTT_UNUSED_ENTRY(3), 635 ICE_PTT_UNUSED_ENTRY(4), 636 ICE_PTT_UNUSED_ENTRY(5), 637 ICE_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 638 ICE_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 639 ICE_PTT_UNUSED_ENTRY(8), 640 ICE_PTT_UNUSED_ENTRY(9), 641 ICE_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 642 ICE_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE), 643 ICE_PTT_UNUSED_ENTRY(12), 644 ICE_PTT_UNUSED_ENTRY(13), 645 ICE_PTT_UNUSED_ENTRY(14), 646 ICE_PTT_UNUSED_ENTRY(15), 647 ICE_PTT_UNUSED_ENTRY(16), 648 ICE_PTT_UNUSED_ENTRY(17), 649 ICE_PTT_UNUSED_ENTRY(18), 650 ICE_PTT_UNUSED_ENTRY(19), 651 ICE_PTT_UNUSED_ENTRY(20), 652 ICE_PTT_UNUSED_ENTRY(21), 653 654 /* Non Tunneled IPv4 */ 655 ICE_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3), 656 ICE_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3), 657 ICE_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4), 658 ICE_PTT_UNUSED_ENTRY(25), 659 ICE_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4), 660 ICE_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4), 661 ICE_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4), 662 663 /* IPv4 --> IPv4 */ 664 ICE_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 665 ICE_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 666 ICE_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 667 ICE_PTT_UNUSED_ENTRY(32), 668 ICE_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 669 ICE_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 670 ICE_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 671 672 /* IPv4 --> IPv6 */ 673 ICE_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 674 ICE_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 675 ICE_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 676 ICE_PTT_UNUSED_ENTRY(39), 677 ICE_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 678 ICE_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 679 ICE_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 680 681 /* IPv4 --> GRE/NAT */ 682 ICE_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 683 684 /* IPv4 --> GRE/NAT --> IPv4 */ 685 ICE_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 686 ICE_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 687 ICE_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 688 ICE_PTT_UNUSED_ENTRY(47), 689 ICE_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 690 ICE_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 691 ICE_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 692 693 /* IPv4 --> GRE/NAT --> IPv6 */ 694 ICE_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 695 ICE_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 696 ICE_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 697 ICE_PTT_UNUSED_ENTRY(54), 698 ICE_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 699 ICE_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 700 ICE_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 701 702 /* IPv4 --> GRE/NAT --> MAC */ 703 ICE_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 704 705 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */ 706 ICE_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 707 ICE_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 708 ICE_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 709 ICE_PTT_UNUSED_ENTRY(62), 710 ICE_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 711 ICE_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 712 ICE_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 713 714 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */ 715 ICE_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 716 ICE_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 717 ICE_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 718 ICE_PTT_UNUSED_ENTRY(69), 719 ICE_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 720 ICE_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 721 ICE_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 722 723 /* IPv4 --> GRE/NAT --> MAC/VLAN */ 724 ICE_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 725 726 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */ 727 ICE_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 728 ICE_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 729 ICE_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 730 ICE_PTT_UNUSED_ENTRY(77), 731 ICE_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 732 ICE_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 733 ICE_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 734 735 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */ 736 ICE_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 737 ICE_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 738 ICE_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 739 ICE_PTT_UNUSED_ENTRY(84), 740 ICE_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 741 ICE_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 742 ICE_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 743 744 /* Non Tunneled IPv6 */ 745 ICE_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3), 746 ICE_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3), 747 ICE_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3), 748 ICE_PTT_UNUSED_ENTRY(91), 749 ICE_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4), 750 ICE_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4), 751 ICE_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4), 752 753 /* IPv6 --> IPv4 */ 754 ICE_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3), 755 ICE_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3), 756 ICE_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4), 757 ICE_PTT_UNUSED_ENTRY(98), 758 ICE_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4), 759 ICE_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4), 760 ICE_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4), 761 762 /* IPv6 --> IPv6 */ 763 ICE_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3), 764 ICE_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3), 765 ICE_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4), 766 ICE_PTT_UNUSED_ENTRY(105), 767 ICE_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4), 768 ICE_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4), 769 ICE_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4), 770 771 /* IPv6 --> GRE/NAT */ 772 ICE_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3), 773 774 /* IPv6 --> GRE/NAT -> IPv4 */ 775 ICE_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3), 776 ICE_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3), 777 ICE_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4), 778 ICE_PTT_UNUSED_ENTRY(113), 779 ICE_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4), 780 ICE_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4), 781 ICE_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4), 782 783 /* IPv6 --> GRE/NAT -> IPv6 */ 784 ICE_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3), 785 ICE_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3), 786 ICE_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4), 787 ICE_PTT_UNUSED_ENTRY(120), 788 ICE_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4), 789 ICE_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4), 790 ICE_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4), 791 792 /* IPv6 --> GRE/NAT -> MAC */ 793 ICE_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3), 794 795 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */ 796 ICE_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3), 797 ICE_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3), 798 ICE_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4), 799 ICE_PTT_UNUSED_ENTRY(128), 800 ICE_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4), 801 ICE_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4), 802 ICE_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4), 803 804 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */ 805 ICE_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3), 806 ICE_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3), 807 ICE_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4), 808 ICE_PTT_UNUSED_ENTRY(135), 809 ICE_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4), 810 ICE_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4), 811 ICE_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4), 812 813 /* IPv6 --> GRE/NAT -> MAC/VLAN */ 814 ICE_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3), 815 816 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */ 817 ICE_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3), 818 ICE_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3), 819 ICE_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4), 820 ICE_PTT_UNUSED_ENTRY(143), 821 ICE_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4), 822 ICE_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4), 823 ICE_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4), 824 825 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */ 826 ICE_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3), 827 ICE_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3), 828 ICE_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4), 829 ICE_PTT_UNUSED_ENTRY(150), 830 ICE_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4), 831 ICE_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4), 832 ICE_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4), 833 834 /* unused entries */ 835 ICE_PTT_UNUSED_ENTRY(154), 836 ICE_PTT_UNUSED_ENTRY(155), 837 ICE_PTT_UNUSED_ENTRY(156), 838 ICE_PTT_UNUSED_ENTRY(157), 839 ICE_PTT_UNUSED_ENTRY(158), 840 ICE_PTT_UNUSED_ENTRY(159), 841 842 ICE_PTT_UNUSED_ENTRY(160), 843 ICE_PTT_UNUSED_ENTRY(161), 844 ICE_PTT_UNUSED_ENTRY(162), 845 ICE_PTT_UNUSED_ENTRY(163), 846 ICE_PTT_UNUSED_ENTRY(164), 847 ICE_PTT_UNUSED_ENTRY(165), 848 ICE_PTT_UNUSED_ENTRY(166), 849 ICE_PTT_UNUSED_ENTRY(167), 850 ICE_PTT_UNUSED_ENTRY(168), 851 ICE_PTT_UNUSED_ENTRY(169), 852 853 ICE_PTT_UNUSED_ENTRY(170), 854 ICE_PTT_UNUSED_ENTRY(171), 855 ICE_PTT_UNUSED_ENTRY(172), 856 ICE_PTT_UNUSED_ENTRY(173), 857 ICE_PTT_UNUSED_ENTRY(174), 858 ICE_PTT_UNUSED_ENTRY(175), 859 ICE_PTT_UNUSED_ENTRY(176), 860 ICE_PTT_UNUSED_ENTRY(177), 861 ICE_PTT_UNUSED_ENTRY(178), 862 ICE_PTT_UNUSED_ENTRY(179), 863 864 ICE_PTT_UNUSED_ENTRY(180), 865 ICE_PTT_UNUSED_ENTRY(181), 866 ICE_PTT_UNUSED_ENTRY(182), 867 ICE_PTT_UNUSED_ENTRY(183), 868 ICE_PTT_UNUSED_ENTRY(184), 869 ICE_PTT_UNUSED_ENTRY(185), 870 ICE_PTT_UNUSED_ENTRY(186), 871 ICE_PTT_UNUSED_ENTRY(187), 872 ICE_PTT_UNUSED_ENTRY(188), 873 ICE_PTT_UNUSED_ENTRY(189), 874 875 ICE_PTT_UNUSED_ENTRY(190), 876 ICE_PTT_UNUSED_ENTRY(191), 877 ICE_PTT_UNUSED_ENTRY(192), 878 ICE_PTT_UNUSED_ENTRY(193), 879 ICE_PTT_UNUSED_ENTRY(194), 880 ICE_PTT_UNUSED_ENTRY(195), 881 ICE_PTT_UNUSED_ENTRY(196), 882 ICE_PTT_UNUSED_ENTRY(197), 883 ICE_PTT_UNUSED_ENTRY(198), 884 ICE_PTT_UNUSED_ENTRY(199), 885 886 ICE_PTT_UNUSED_ENTRY(200), 887 ICE_PTT_UNUSED_ENTRY(201), 888 ICE_PTT_UNUSED_ENTRY(202), 889 ICE_PTT_UNUSED_ENTRY(203), 890 ICE_PTT_UNUSED_ENTRY(204), 891 ICE_PTT_UNUSED_ENTRY(205), 892 ICE_PTT_UNUSED_ENTRY(206), 893 ICE_PTT_UNUSED_ENTRY(207), 894 ICE_PTT_UNUSED_ENTRY(208), 895 ICE_PTT_UNUSED_ENTRY(209), 896 897 ICE_PTT_UNUSED_ENTRY(210), 898 ICE_PTT_UNUSED_ENTRY(211), 899 ICE_PTT_UNUSED_ENTRY(212), 900 ICE_PTT_UNUSED_ENTRY(213), 901 ICE_PTT_UNUSED_ENTRY(214), 902 ICE_PTT_UNUSED_ENTRY(215), 903 ICE_PTT_UNUSED_ENTRY(216), 904 ICE_PTT_UNUSED_ENTRY(217), 905 ICE_PTT_UNUSED_ENTRY(218), 906 ICE_PTT_UNUSED_ENTRY(219), 907 908 ICE_PTT_UNUSED_ENTRY(220), 909 ICE_PTT_UNUSED_ENTRY(221), 910 ICE_PTT_UNUSED_ENTRY(222), 911 ICE_PTT_UNUSED_ENTRY(223), 912 ICE_PTT_UNUSED_ENTRY(224), 913 ICE_PTT_UNUSED_ENTRY(225), 914 ICE_PTT_UNUSED_ENTRY(226), 915 ICE_PTT_UNUSED_ENTRY(227), 916 ICE_PTT_UNUSED_ENTRY(228), 917 ICE_PTT_UNUSED_ENTRY(229), 918 919 ICE_PTT_UNUSED_ENTRY(230), 920 ICE_PTT_UNUSED_ENTRY(231), 921 ICE_PTT_UNUSED_ENTRY(232), 922 ICE_PTT_UNUSED_ENTRY(233), 923 ICE_PTT_UNUSED_ENTRY(234), 924 ICE_PTT_UNUSED_ENTRY(235), 925 ICE_PTT_UNUSED_ENTRY(236), 926 ICE_PTT_UNUSED_ENTRY(237), 927 ICE_PTT_UNUSED_ENTRY(238), 928 ICE_PTT_UNUSED_ENTRY(239), 929 930 ICE_PTT_UNUSED_ENTRY(240), 931 ICE_PTT_UNUSED_ENTRY(241), 932 ICE_PTT_UNUSED_ENTRY(242), 933 ICE_PTT_UNUSED_ENTRY(243), 934 ICE_PTT_UNUSED_ENTRY(244), 935 ICE_PTT_UNUSED_ENTRY(245), 936 ICE_PTT_UNUSED_ENTRY(246), 937 ICE_PTT_UNUSED_ENTRY(247), 938 ICE_PTT_UNUSED_ENTRY(248), 939 ICE_PTT_UNUSED_ENTRY(249), 940 941 ICE_PTT_UNUSED_ENTRY(250), 942 ICE_PTT_UNUSED_ENTRY(251), 943 ICE_PTT_UNUSED_ENTRY(252), 944 ICE_PTT_UNUSED_ENTRY(253), 945 ICE_PTT_UNUSED_ENTRY(254), 946 ICE_PTT_UNUSED_ENTRY(255), 947 }; 948 949 static inline struct ice_rx_ptype_decoded ice_decode_rx_desc_ptype(u16 ptype) 950 { 951 return ice_ptype_lkup[ptype]; 952 } 953 954 #define ICE_LINK_SPEED_UNKNOWN 0 955 #define ICE_LINK_SPEED_10MBPS 10 956 #define ICE_LINK_SPEED_100MBPS 100 957 #define ICE_LINK_SPEED_1000MBPS 1000 958 #define ICE_LINK_SPEED_2500MBPS 2500 959 #define ICE_LINK_SPEED_5000MBPS 5000 960 #define ICE_LINK_SPEED_10000MBPS 10000 961 #define ICE_LINK_SPEED_20000MBPS 20000 962 #define ICE_LINK_SPEED_25000MBPS 25000 963 #define ICE_LINK_SPEED_40000MBPS 40000 964 #define ICE_LINK_SPEED_50000MBPS 50000 965 #define ICE_LINK_SPEED_100000MBPS 100000 966 967 #endif /* _ICE_LAN_TX_RX_H_ */ 968